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1//===---------------------------------------------------------------------===//2 3Common register allocation / spilling problem:4 5 mul lr, r4, lr6 str lr, [sp, #+52]7 ldr lr, [r1, #+32]8 sxth r3, r39 ldr r4, [sp, #+52]10 mla r4, r3, lr, r411 12can be:13 14 mul lr, r4, lr15 mov r4, lr16 str lr, [sp, #+52]17 ldr lr, [r1, #+32]18 sxth r3, r319 mla r4, r3, lr, r420 21and then "merge" mul and mov:22 23 mul r4, r4, lr24 str r4, [sp, #+52]25 ldr lr, [r1, #+32]26 sxth r3, r327 mla r4, r3, lr, r428 29It also increase the likelihood the store may become dead.30 31//===---------------------------------------------------------------------===//32 33bb27 ...34 ...35 %reg1037 = ADDri %reg1039, 136 %reg1038 = ADDrs %reg1032, %reg1039, %noreg, 1037 Successors according to CFG: 0x8b03bf0 (#5)38 39bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):40 Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)41 %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>42 43Note ADDri is not a two-address instruction. However, its result %reg1037 is an44operand of the PHI node in bb76 and its operand %reg1039 is the result of the45PHI node. We should treat it as a two-address code and make sure the ADDri is46scheduled after any node that reads %reg1039.47 48//===---------------------------------------------------------------------===//49 50Use local info (i.e. register scavenger) to assign it a free register to allow51reuse:52 ldr r3, [sp, #+4]53 add r3, r3, #354 ldr r2, [sp, #+8]55 add r2, r2, #256 ldr r1, [sp, #+4] <==57 add r1, r1, #158 ldr r0, [sp, #+4]59 add r0, r0, #260 61//===---------------------------------------------------------------------===//62 63LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-64effects:65 66R1 = X + 467R2 = X + 768R3 = X + 1569 70loop:71load [i + R1]72...73load [i + R2]74...75load [i + R3]76 77Suppose there is high register pressure, R1, R2, R3, can be spilled. We need78to implement proper re-materialization to handle this:79 80R1 = X + 481R2 = X + 782R3 = X + 1583 84loop:85R1 = X + 4 @ re-materialized86load [i + R1]87...88R2 = X + 7 @ re-materialized89load [i + R2]90...91R3 = X + 15 @ re-materialized92load [i + R3]93 94Furthermore, with re-association, we can enable sharing:95 96R1 = X + 497R2 = X + 798R3 = X + 1599 100loop:101T = i + X102load [T + 4]103...104load [T + 7]105...106load [T + 15]107//===---------------------------------------------------------------------===//108 109It's not always a good idea to choose rematerialization over spilling. If all110the load / store instructions would be folded then spilling is cheaper because111it won't require new live intervals / registers. See 2003-05-31-LongShifts for112an example.113 114//===---------------------------------------------------------------------===//115 116With a copying garbage collector, derived pointers must not be retained across117collector safe points; the collector could move the objects and invalidate the118derived pointer. This is bad enough in the first place, but safe points can119crop up unpredictably. Consider:120 121 %array = load { i32, [0 x %obj] }** %array_addr122 %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n123 %old = load %obj** %nth_el124 %z = div i64 %x, %y125 store %obj* %new, %obj** %nth_el126 127If the i64 division is lowered to a libcall, then a safe point will (must)128appear for the call site. If a collection occurs, %array and %nth_el no longer129point into the correct object.130 131The fix for this is to copy address calculations so that dependent pointers132are never live across safe point boundaries. But the loads cannot be copied133like this if there was an intervening store, so may be hard to get right.134 135Only a concurrent mutator can trigger a collection at the libcall safe point.136So single-threaded programs do not have this requirement, even with a copying137collector. Still, LLVM optimizations would probably undo a front-end's careful138work.139 140//===---------------------------------------------------------------------===//141 142The ocaml frametable structure supports liveness information. It would be good143to support it.144 145//===---------------------------------------------------------------------===//146 147The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be148revisited. The check is there to work around a misuse of directives in inline149assembly.150 151//===---------------------------------------------------------------------===//152 153It would be good to detect collector/target compatibility instead of silently154doing the wrong thing.155 156//===---------------------------------------------------------------------===//157 158It would be really nice to be able to write patterns in .td files for copies,159which would eliminate a bunch of explicit predicates on them (e.g. no side160effects). Once this is in place, it would be even better to have tblgen161synthesize the various copy insertion/inspection methods in TargetInstrInfo.162 163//===---------------------------------------------------------------------===//164 165Stack coloring improvements:166 1671. Do proper LiveStacks analysis on all stack objects including those which are168 not spill slots.1692. Reorder objects to fill in gaps between objects.170 e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4171 172//===---------------------------------------------------------------------===//173 174The scheduler should be able to sort nearby instructions by their address. For175example, in an expanded memset sequence it's not uncommon to see code like this:176 177 movl $0, 4(%rdi)178 movl $0, 8(%rdi)179 movl $0, 12(%rdi)180 movl $0, 0(%rdi)181 182Each of the stores is independent, and the scheduler is currently making an183arbitrary decision about the order.184 185//===---------------------------------------------------------------------===//186 187Another opportunitiy in this code is that the $0 could be moved to a register:188 189 movl $0, 4(%rdi)190 movl $0, 8(%rdi)191 movl $0, 12(%rdi)192 movl $0, 0(%rdi)193 194This would save substantial code size, especially for longer sequences like195this. It would be easy to have a rule telling isel to avoid matching MOV32mi196if the immediate has more than some fixed number of uses. It's more involved197to teach the register allocator how to do late folding to recover from198excessive register pressure.199 200