716 lines · cpp
1//==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file implements the TargetRegisterInfo interface.10//11//===----------------------------------------------------------------------===//12 13#include "llvm/CodeGen/TargetRegisterInfo.h"14#include "llvm/ADT/ArrayRef.h"15#include "llvm/ADT/BitVector.h"16#include "llvm/ADT/STLExtras.h"17#include "llvm/ADT/SmallSet.h"18#include "llvm/ADT/StringExtras.h"19#include "llvm/BinaryFormat/Dwarf.h"20#include "llvm/CodeGen/LiveInterval.h"21#include "llvm/CodeGen/MachineFrameInfo.h"22#include "llvm/CodeGen/MachineFunction.h"23#include "llvm/CodeGen/MachineRegisterInfo.h"24#include "llvm/CodeGen/TargetFrameLowering.h"25#include "llvm/CodeGen/TargetInstrInfo.h"26#include "llvm/CodeGen/TargetSubtargetInfo.h"27#include "llvm/CodeGen/VirtRegMap.h"28#include "llvm/CodeGenTypes/MachineValueType.h"29#include "llvm/Config/llvm-config.h"30#include "llvm/IR/Attributes.h"31#include "llvm/IR/DebugInfoMetadata.h"32#include "llvm/IR/Function.h"33#include "llvm/MC/MCRegisterInfo.h"34#include "llvm/Support/CommandLine.h"35#include "llvm/Support/Compiler.h"36#include "llvm/Support/Debug.h"37#include "llvm/Support/Printable.h"38#include "llvm/Support/raw_ostream.h"39#include <cassert>40#include <utility>41 42#define DEBUG_TYPE "target-reg-info"43 44using namespace llvm;45 46static cl::opt<unsigned>47 HugeSizeForSplit("huge-size-for-split", cl::Hidden,48 cl::desc("A threshold of live range size which may cause "49 "high compile time cost in global splitting."),50 cl::init(5000));51 52TargetRegisterInfo::TargetRegisterInfo(53 const TargetRegisterInfoDesc *ID, regclass_iterator RCB,54 regclass_iterator RCE, const char *const *SRINames,55 const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks,56 LaneBitmask SRICoveringLanes, const RegClassInfo *const RCIs,57 const MVT::SimpleValueType *const RCVTLists, unsigned Mode)58 : InfoDesc(ID), SubRegIndexNames(SRINames), SubRegIdxRanges(SubIdxRanges),59 SubRegIndexLaneMasks(SRILaneMasks), RegClassBegin(RCB), RegClassEnd(RCE),60 CoveringLanes(SRICoveringLanes), RCInfos(RCIs), RCVTLists(RCVTLists),61 HwMode(Mode) {}62 63TargetRegisterInfo::~TargetRegisterInfo() = default;64 65bool TargetRegisterInfo::shouldRegionSplitForVirtReg(66 const MachineFunction &MF, const LiveInterval &VirtReg) const {67 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();68 const MachineRegisterInfo &MRI = MF.getRegInfo();69 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg());70 if (MI && TII->isTriviallyReMaterializable(*MI) &&71 VirtReg.size() > HugeSizeForSplit)72 return false;73 return true;74}75 76void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet,77 MCRegister Reg) const {78 for (MCPhysReg SR : superregs_inclusive(Reg))79 RegisterSet.set(SR);80}81 82bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,83 ArrayRef<MCPhysReg> Exceptions) const {84 // Check that all super registers of reserved regs are reserved as well.85 BitVector Checked(getNumRegs());86 for (unsigned Reg : RegisterSet.set_bits()) {87 if (Checked[Reg])88 continue;89 for (MCPhysReg SR : superregs(Reg)) {90 if (!RegisterSet[SR] && !is_contained(Exceptions, Reg)) {91 dbgs() << "Error: Super register " << printReg(SR, this)92 << " of reserved register " << printReg(Reg, this)93 << " is not reserved.\n";94 return false;95 }96 97 // We transitively check superregs. So we can remember this for later98 // to avoid compiletime explosion in deep register hierarchies.99 Checked.set(SR);100 }101 }102 return true;103}104 105Printable llvm::printReg(Register Reg, const TargetRegisterInfo *TRI,106 unsigned SubIdx, const MachineRegisterInfo *MRI) {107 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {108 if (!Reg)109 OS << "$noreg";110 else if (Reg.isStack())111 OS << "SS#" << Reg.stackSlotIndex();112 else if (Reg.isVirtual()) {113 StringRef Name = MRI ? MRI->getVRegName(Reg) : "";114 if (Name != "") {115 OS << '%' << Name;116 } else {117 OS << '%' << Reg.virtRegIndex();118 }119 } else if (!TRI)120 OS << '$' << "physreg" << Reg.id();121 else if (Reg < TRI->getNumRegs()) {122 OS << '$';123 printLowerCase(TRI->getName(Reg), OS);124 } else125 llvm_unreachable("Register kind is unsupported.");126 127 if (SubIdx) {128 if (TRI)129 OS << ':' << TRI->getSubRegIndexName(SubIdx);130 else131 OS << ":sub(" << SubIdx << ')';132 }133 });134}135 136Printable llvm::printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI) {137 return Printable([Unit, TRI](raw_ostream &OS) {138 // Generic printout when TRI is missing.139 if (!TRI) {140 OS << "Unit~" << static_cast<unsigned>(Unit);141 return;142 }143 144 // Check for invalid register units.145 if (static_cast<unsigned>(Unit) >= TRI->getNumRegUnits()) {146 OS << "BadUnit~" << static_cast<unsigned>(Unit);147 return;148 }149 150 // Normal units have at least one root.151 MCRegUnitRootIterator Roots(Unit, TRI);152 assert(Roots.isValid() && "Unit has no roots.");153 OS << TRI->getName(*Roots);154 for (++Roots; Roots.isValid(); ++Roots)155 OS << '~' << TRI->getName(*Roots);156 });157}158 159Printable llvm::printVRegOrUnit(VirtRegOrUnit VRegOrUnit,160 const TargetRegisterInfo *TRI) {161 return Printable([VRegOrUnit, TRI](raw_ostream &OS) {162 if (VRegOrUnit.isVirtualReg()) {163 OS << '%' << VRegOrUnit.asVirtualReg().virtRegIndex();164 } else {165 OS << printRegUnit(VRegOrUnit.asMCRegUnit(), TRI);166 }167 });168}169 170Printable llvm::printRegClassOrBank(Register Reg,171 const MachineRegisterInfo &RegInfo,172 const TargetRegisterInfo *TRI) {173 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {174 if (RegInfo.getRegClassOrNull(Reg))175 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();176 else if (RegInfo.getRegBankOrNull(Reg))177 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();178 else {179 OS << "_";180 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&181 "Generic registers must have a valid type");182 }183 });184}185 186/// getAllocatableClass - Return the maximal subclass of the given register187/// class that is alloctable, or NULL.188const TargetRegisterClass *189TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {190 if (!RC || RC->isAllocatable())191 return RC;192 193 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();194 ++It) {195 const TargetRegisterClass *SubRC = getRegClass(It.getID());196 if (SubRC->isAllocatable())197 return SubRC;198 }199 return nullptr;200}201 202template <typename TypeT>203static const TargetRegisterClass *204getMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg,205 TypeT Ty) {206 static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);207 assert(Reg.isPhysical() && "reg must be a physical register");208 209 bool IsDefault = [&]() {210 if constexpr (std::is_same_v<TypeT, MVT>)211 return Ty == MVT::Other;212 else213 return !Ty.isValid();214 }();215 216 // Pick the most sub register class of the right type that contains217 // this physreg.218 const TargetRegisterClass *BestRC = nullptr;219 for (const TargetRegisterClass *RC : TRI->regclasses()) {220 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) && RC->contains(Reg) &&221 (!BestRC || BestRC->hasSubClass(RC)))222 BestRC = RC;223 }224 225 if constexpr (std::is_same_v<TypeT, MVT>)226 assert(BestRC && "Couldn't find the register class");227 return BestRC;228}229 230template <typename TypeT>231static const TargetRegisterClass *232getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1,233 MCRegister Reg2, TypeT Ty) {234 static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);235 assert(Reg1.isPhysical() && Reg2.isPhysical() &&236 "Reg1/Reg2 must be a physical register");237 238 bool IsDefault = [&]() {239 if constexpr (std::is_same_v<TypeT, MVT>)240 return Ty == MVT::Other;241 else242 return !Ty.isValid();243 }();244 245 // Pick the most sub register class of the right type that contains246 // this physreg.247 const TargetRegisterClass *BestRC = nullptr;248 for (const TargetRegisterClass *RC : TRI->regclasses()) {249 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) &&250 RC->contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC)))251 BestRC = RC;252 }253 254 if constexpr (std::is_same_v<TypeT, MVT>)255 assert(BestRC && "Couldn't find the register class");256 return BestRC;257}258 259const TargetRegisterClass *260TargetRegisterInfo::getMinimalPhysRegClass(MCRegister Reg, MVT VT) const {261 return ::getMinimalPhysRegClass(this, Reg, VT);262}263 264const TargetRegisterClass *TargetRegisterInfo::getCommonMinimalPhysRegClass(265 MCRegister Reg1, MCRegister Reg2, MVT VT) const {266 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, VT);267}268 269const TargetRegisterClass *270TargetRegisterInfo::getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty) const {271 return ::getMinimalPhysRegClass(this, Reg, Ty);272}273 274const TargetRegisterClass *TargetRegisterInfo::getCommonMinimalPhysRegClassLLT(275 MCRegister Reg1, MCRegister Reg2, LLT Ty) const {276 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, Ty);277}278 279/// getAllocatableSetForRC - Toggle the bits that represent allocatable280/// registers for the specific register class.281static void getAllocatableSetForRC(const MachineFunction &MF,282 const TargetRegisterClass *RC, BitVector &R){283 assert(RC->isAllocatable() && "invalid for nonallocatable sets");284 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);285 for (MCPhysReg PR : Order)286 R.set(PR);287}288 289BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,290 const TargetRegisterClass *RC) const {291 BitVector Allocatable(getNumRegs());292 if (RC) {293 // A register class with no allocatable subclass returns an empty set.294 const TargetRegisterClass *SubClass = getAllocatableClass(RC);295 if (SubClass)296 getAllocatableSetForRC(MF, SubClass, Allocatable);297 } else {298 for (const TargetRegisterClass *C : regclasses())299 if (C->isAllocatable())300 getAllocatableSetForRC(MF, C, Allocatable);301 }302 303 // Mask out the reserved registers304 const MachineRegisterInfo &MRI = MF.getRegInfo();305 const BitVector &Reserved = MRI.getReservedRegs();306 Allocatable.reset(Reserved);307 308 return Allocatable;309}310 311static inline312const TargetRegisterClass *firstCommonClass(const uint32_t *A,313 const uint32_t *B,314 const TargetRegisterInfo *TRI) {315 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)316 if (unsigned Common = *A++ & *B++)317 return TRI->getRegClass(I + llvm::countr_zero(Common));318 return nullptr;319}320 321const TargetRegisterClass *322TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,323 const TargetRegisterClass *B) const {324 // First take care of the trivial cases.325 if (A == B)326 return A;327 if (!A || !B)328 return nullptr;329 330 // Register classes are ordered topologically, so the largest common331 // sub-class it the common sub-class with the smallest ID.332 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);333}334 335const TargetRegisterClass *336TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,337 const TargetRegisterClass *B,338 unsigned Idx) const {339 assert(A && B && "Missing register class");340 assert(Idx && "Bad sub-register index");341 342 // Find Idx in the list of super-register indices.343 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)344 if (RCI.getSubReg() == Idx)345 // The bit mask contains all register classes that are projected into B346 // by Idx. Find a class that is also a sub-class of A.347 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);348 return nullptr;349}350 351const TargetRegisterClass *TargetRegisterInfo::352getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,353 const TargetRegisterClass *RCB, unsigned SubB,354 unsigned &PreA, unsigned &PreB) const {355 assert(RCA && SubA && RCB && SubB && "Invalid arguments");356 357 // Search all pairs of sub-register indices that project into RCA and RCB358 // respectively. This is quadratic, but usually the sets are very small. On359 // most targets like X86, there will only be a single sub-register index360 // (e.g., sub_16bit projecting into GR16).361 //362 // The worst case is a register class like DPR on ARM.363 // We have indices dsub_0..dsub_7 projecting into that class.364 //365 // It is very common that one register class is a sub-register of the other.366 // Arrange for RCA to be the larger register so the answer will be found in367 // the first iteration. This makes the search linear for the most common368 // case.369 const TargetRegisterClass *BestRC = nullptr;370 unsigned *BestPreA = &PreA;371 unsigned *BestPreB = &PreB;372 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {373 std::swap(RCA, RCB);374 std::swap(SubA, SubB);375 std::swap(BestPreA, BestPreB);376 }377 378 // Also terminate the search one we have found a register class as small as379 // RCA.380 unsigned MinSize = getRegSizeInBits(*RCA);381 382 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {383 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);384 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {385 // Check if a common super-register class exists for this index pair.386 const TargetRegisterClass *RC =387 firstCommonClass(IA.getMask(), IB.getMask(), this);388 if (!RC || getRegSizeInBits(*RC) < MinSize)389 continue;390 391 // The indexes must compose identically: PreA+SubA == PreB+SubB.392 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);393 if (FinalA != FinalB)394 continue;395 396 // Is RC a better candidate than BestRC?397 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))398 continue;399 400 // Yes, RC is the smallest super-register seen so far.401 BestRC = RC;402 *BestPreA = IA.getSubReg();403 *BestPreB = IB.getSubReg();404 405 // Bail early if we reached MinSize. We won't find a better candidate.406 if (getRegSizeInBits(*BestRC) == MinSize)407 return BestRC;408 }409 }410 return BestRC;411}412 413const TargetRegisterClass *TargetRegisterInfo::findCommonRegClass(414 const TargetRegisterClass *DefRC, unsigned DefSubReg,415 const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const {416 // Same register class.417 //418 // When processing uncoalescable copies / bitcasts, it is possible we reach419 // here with the same register class, but mismatched subregister indices.420 if (DefRC == SrcRC && DefSubReg == SrcSubReg)421 return DefRC;422 423 // Both operands are sub registers. Check if they share a register class.424 unsigned SrcIdx, DefIdx;425 if (SrcSubReg && DefSubReg) {426 return getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, SrcIdx,427 DefIdx);428 }429 430 // At most one of the register is a sub register, make it Src to avoid431 // duplicating the test.432 if (!SrcSubReg) {433 std::swap(DefSubReg, SrcSubReg);434 std::swap(DefRC, SrcRC);435 }436 437 // One of the register is a sub register, check if we can get a superclass.438 if (SrcSubReg)439 return getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg);440 441 // Plain copy.442 return getCommonSubClass(DefRC, SrcRC);443}444 445float TargetRegisterInfo::getSpillWeightScaleFactor(446 const TargetRegisterClass *RC) const {447 return 1.0;448}449 450// Compute target-independent register allocator hints to help eliminate copies.451bool TargetRegisterInfo::getRegAllocationHints(452 Register VirtReg, ArrayRef<MCPhysReg> Order,453 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,454 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {455 const MachineRegisterInfo &MRI = MF.getRegInfo();456 const std::pair<unsigned, SmallVector<Register, 4>> *Hints_MRI =457 MRI.getRegAllocationHints(VirtReg);458 459 if (!Hints_MRI)460 return false;461 462 SmallSet<Register, 32> HintedRegs;463 // First hint may be a target hint.464 bool Skip = (Hints_MRI->first != 0);465 for (auto Reg : Hints_MRI->second) {466 if (Skip) {467 Skip = false;468 continue;469 }470 471 // Target-independent hints are either a physical or a virtual register.472 Register Phys = Reg;473 if (VRM && Phys.isVirtual())474 Phys = VRM->getPhys(Phys);475 476 // Don't add the same reg twice (Hints_MRI may contain multiple virtual477 // registers allocated to the same physreg).478 if (!HintedRegs.insert(Phys).second)479 continue;480 // Check that Phys is a valid hint in VirtReg's register class.481 if (!Phys.isPhysical())482 continue;483 if (MRI.isReserved(Phys))484 continue;485 // Check that Phys is in the allocation order. We shouldn't heed hints486 // from VirtReg's register class if they aren't in the allocation order. The487 // target probably has a reason for removing the register.488 if (!is_contained(Order, Phys))489 continue;490 491 // All clear, tell the register allocator to prefer this register.492 Hints.push_back(Phys.id());493 }494 return false;495}496 497bool TargetRegisterInfo::isCalleeSavedPhysReg(498 MCRegister PhysReg, const MachineFunction &MF) const {499 if (!PhysReg)500 return false;501 const uint32_t *callerPreservedRegs =502 getCallPreservedMask(MF, MF.getFunction().getCallingConv());503 if (callerPreservedRegs) {504 assert(PhysReg.isPhysical() && "Expected physical register");505 return (callerPreservedRegs[PhysReg.id() / 32] >> PhysReg.id() % 32) & 1;506 }507 return false;508}509 510bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {511 return MF.getFrameInfo().isStackRealignable();512}513 514bool TargetRegisterInfo::shouldRealignStack(const MachineFunction &MF) const {515 return MF.getFrameInfo().shouldRealignStack();516}517 518bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,519 const uint32_t *mask1) const {520 unsigned N = (getNumRegs()+31) / 32;521 for (unsigned I = 0; I < N; ++I)522 if ((mask0[I] & mask1[I]) != mask0[I])523 return false;524 return true;525}526 527TypeSize528TargetRegisterInfo::getRegSizeInBits(Register Reg,529 const MachineRegisterInfo &MRI) const {530 const TargetRegisterClass *RC{};531 if (Reg.isPhysical()) {532 // The size is not directly available for physical registers.533 // Instead, we need to access a register class that contains Reg and534 // get the size of that register class.535 RC = getMinimalPhysRegClass(Reg);536 assert(RC && "Unable to deduce the register class");537 return getRegSizeInBits(*RC);538 }539 LLT Ty = MRI.getType(Reg);540 if (Ty.isValid())541 return Ty.getSizeInBits();542 543 // Since Reg is not a generic register, it may have a register class.544 RC = MRI.getRegClass(Reg);545 assert(RC && "Unable to deduce the register class");546 return getRegSizeInBits(*RC);547}548 549bool TargetRegisterInfo::getCoveringSubRegIndexes(550 const TargetRegisterClass *RC, LaneBitmask LaneMask,551 SmallVectorImpl<unsigned> &NeededIndexes) const {552 SmallVector<unsigned, 8> PossibleIndexes;553 unsigned BestIdx = 0;554 unsigned BestCover = 0;555 556 for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {557 // Is this index even compatible with the given class?558 if (getSubClassWithSubReg(RC, Idx) != RC)559 continue;560 LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);561 // Early exit if we found a perfect match.562 if (SubRegMask == LaneMask) {563 BestIdx = Idx;564 break;565 }566 567 // The index must not cover any lanes outside \p LaneMask.568 if ((SubRegMask & ~LaneMask).any())569 continue;570 571 unsigned PopCount = SubRegMask.getNumLanes();572 PossibleIndexes.push_back(Idx);573 if (PopCount > BestCover) {574 BestCover = PopCount;575 BestIdx = Idx;576 }577 }578 579 // Abort if we cannot possibly implement the COPY with the given indexes.580 if (BestIdx == 0)581 return false;582 583 NeededIndexes.push_back(BestIdx);584 585 // Greedy heuristic: Keep iterating keeping the best covering subreg index586 // each time.587 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx);588 while (LanesLeft.any()) {589 unsigned BestIdx = 0;590 int BestCover = std::numeric_limits<int>::min();591 for (unsigned Idx : PossibleIndexes) {592 LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);593 // Early exit if we found a perfect match.594 if (SubRegMask == LanesLeft) {595 BestIdx = Idx;596 break;597 }598 599 // Do not cover already-covered lanes to avoid creating cycles600 // in copy bundles (= bundle contains copies that write to the601 // registers).602 if ((SubRegMask & ~LanesLeft).any())603 continue;604 605 // Try to cover as many of the remaining lanes as possible.606 const int Cover = (SubRegMask & LanesLeft).getNumLanes();607 if (Cover > BestCover) {608 BestCover = Cover;609 BestIdx = Idx;610 }611 }612 613 if (BestIdx == 0)614 return false; // Impossible to handle615 616 NeededIndexes.push_back(BestIdx);617 618 LanesLeft &= ~getSubRegIndexLaneMask(BestIdx);619 }620 621 return BestIdx;622}623 624unsigned TargetRegisterInfo::getSubRegIdxSize(unsigned Idx) const {625 assert(Idx && Idx < getNumSubRegIndices() &&626 "This is not a subregister index");627 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Size;628}629 630unsigned TargetRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {631 assert(Idx && Idx < getNumSubRegIndices() &&632 "This is not a subregister index");633 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Offset;634}635 636Register637TargetRegisterInfo::lookThruCopyLike(Register SrcReg,638 const MachineRegisterInfo *MRI) const {639 while (true) {640 const MachineInstr *MI = MRI->getVRegDef(SrcReg);641 if (!MI->isCopyLike())642 return SrcReg;643 644 Register CopySrcReg;645 if (MI->isCopy())646 CopySrcReg = MI->getOperand(1).getReg();647 else {648 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");649 CopySrcReg = MI->getOperand(2).getReg();650 }651 652 if (!CopySrcReg.isVirtual())653 return CopySrcReg;654 655 SrcReg = CopySrcReg;656 }657}658 659Register TargetRegisterInfo::lookThruSingleUseCopyChain(660 Register SrcReg, const MachineRegisterInfo *MRI) const {661 while (true) {662 const MachineInstr *MI = MRI->getVRegDef(SrcReg);663 // Found the real definition, return it if it has a single use.664 if (!MI->isCopyLike())665 return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg : Register();666 667 Register CopySrcReg;668 if (MI->isCopy())669 CopySrcReg = MI->getOperand(1).getReg();670 else {671 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");672 CopySrcReg = MI->getOperand(2).getReg();673 }674 675 // Continue only if the next definition in the chain is for a virtual676 // register that has a single use.677 if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(CopySrcReg))678 return Register();679 680 SrcReg = CopySrcReg;681 }682}683 684void TargetRegisterInfo::getOffsetOpcodes(685 const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {686 assert(!Offset.getScalable() && "Scalable offsets are not handled");687 DIExpression::appendOffset(Ops, Offset.getFixed());688}689 690DIExpression *691TargetRegisterInfo::prependOffsetExpression(const DIExpression *Expr,692 unsigned PrependFlags,693 const StackOffset &Offset) const {694 assert((PrependFlags &695 ~(DIExpression::DerefBefore | DIExpression::DerefAfter |696 DIExpression::StackValue | DIExpression::EntryValue)) == 0 &&697 "Unsupported prepend flag");698 SmallVector<uint64_t, 16> OffsetExpr;699 if (PrependFlags & DIExpression::DerefBefore)700 OffsetExpr.push_back(dwarf::DW_OP_deref);701 getOffsetOpcodes(Offset, OffsetExpr);702 if (PrependFlags & DIExpression::DerefAfter)703 OffsetExpr.push_back(dwarf::DW_OP_deref);704 return DIExpression::prependOpcodes(Expr, OffsetExpr,705 PrependFlags & DIExpression::StackValue,706 PrependFlags & DIExpression::EntryValue);707}708 709#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)710LLVM_DUMP_METHOD711void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,712 const TargetRegisterInfo *TRI) {713 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";714}715#endif716