62 lines · cpp
1//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9/// \file This file describes the general parts of a Subtarget.10//11//===----------------------------------------------------------------------===//12 13#include "llvm/CodeGen/TargetSubtargetInfo.h"14 15using namespace llvm;16 17TargetSubtargetInfo::TargetSubtargetInfo(18 const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,19 ArrayRef<StringRef> PN, ArrayRef<SubtargetFeatureKV> PF,20 ArrayRef<SubtargetSubTypeKV> PD, const MCWriteProcResEntry *WPR,21 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,22 const InstrStage *IS, const unsigned *OC, const unsigned *FP)23 : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, WPR, WL, RA, IS, OC,24 FP) {}25 26TargetSubtargetInfo::~TargetSubtargetInfo() = default;27 28bool TargetSubtargetInfo::enableAtomicExpand() const {29 return true;30}31 32bool TargetSubtargetInfo::enableIndirectBrExpand() const {33 return false;34}35 36bool TargetSubtargetInfo::enableMachineScheduler() const {37 return false;38}39 40bool TargetSubtargetInfo::enableJoinGlobalCopies() const {41 return enableMachineScheduler();42}43 44bool TargetSubtargetInfo::enableRALocalReassignment(45 CodeGenOptLevel OptLevel) const {46 return true;47}48 49bool TargetSubtargetInfo::enablePostRAScheduler() const {50 return getSchedModel().PostRAScheduler;51}52 53bool TargetSubtargetInfo::enablePostRAMachineScheduler() const {54 return enableMachineScheduler() && enablePostRAScheduler();55}56 57bool TargetSubtargetInfo::useAA() const {58 return false;59}60 61void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }62