265 lines · cpp
1//===--------------------- Instruction.cpp ----------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines abstractions used by the Pipeline to model register reads,10// register writes and instructions.11//12//===----------------------------------------------------------------------===//13 14#include "llvm/MCA/Instruction.h"15#include "llvm/Support/Debug.h"16#include "llvm/Support/raw_ostream.h"17 18namespace llvm {19namespace mca {20 21void WriteState::writeStartEvent(unsigned IID, MCPhysReg RegID,22 unsigned Cycles) {23 CRD.IID = IID;24 CRD.RegID = RegID;25 CRD.Cycles = Cycles;26 DependentWriteCyclesLeft = Cycles;27 DependentWrite = nullptr;28}29 30void ReadState::writeStartEvent(unsigned IID, MCPhysReg RegID,31 unsigned Cycles) {32 assert(DependentWrites);33 assert(CyclesLeft == UNKNOWN_CYCLES);34 35 // This read may be dependent on more than one write. This typically occurs36 // when a definition is the result of multiple writes where at least one37 // write does a partial register update.38 // The HW is forced to do some extra bookkeeping to track of all the39 // dependent writes, and implement a merging scheme for the partial writes.40 --DependentWrites;41 if (TotalCycles < Cycles) {42 CRD.IID = IID;43 CRD.RegID = RegID;44 CRD.Cycles = Cycles;45 TotalCycles = Cycles;46 }47 48 if (!DependentWrites) {49 CyclesLeft = TotalCycles;50 IsReady = !CyclesLeft;51 }52}53 54void WriteState::onInstructionIssued(unsigned IID) {55 assert(CyclesLeft == UNKNOWN_CYCLES);56 // Update the number of cycles left based on the WriteDescriptor info.57 CyclesLeft = getLatency();58 59 // Now that the time left before write-back is known, notify60 // all the users.61 for (const std::pair<ReadState *, int> &User : Users) {62 ReadState *RS = User.first;63 unsigned ReadCycles = std::max(0, CyclesLeft - User.second);64 RS->writeStartEvent(IID, RegisterID, ReadCycles);65 }66 67 // Notify any writes that are in a false dependency with this write.68 if (PartialWrite)69 PartialWrite->writeStartEvent(IID, RegisterID, CyclesLeft);70}71 72void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) {73 // If CyclesLeft is different than -1, then we don't need to74 // update the list of users. We can just notify the user with75 // the actual number of cycles left (which may be zero).76 if (CyclesLeft != UNKNOWN_CYCLES) {77 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance);78 User->writeStartEvent(IID, RegisterID, ReadCycles);79 return;80 }81 82 Users.emplace_back(User, ReadAdvance);83}84 85void WriteState::addUser(unsigned IID, WriteState *User) {86 if (CyclesLeft != UNKNOWN_CYCLES) {87 User->writeStartEvent(IID, RegisterID, std::max(0, CyclesLeft));88 return;89 }90 91 assert(!PartialWrite && "PartialWrite already set!");92 PartialWrite = User;93 User->setDependentWrite(this);94}95 96void WriteState::cycleEvent() {97 // Note: CyclesLeft can be a negative number. It is an error to98 // make it an unsigned quantity because users of this write may99 // specify a negative ReadAdvance.100 if (CyclesLeft != UNKNOWN_CYCLES)101 CyclesLeft--;102 103 if (DependentWriteCyclesLeft)104 DependentWriteCyclesLeft--;105}106 107void ReadState::cycleEvent() {108 // Update the total number of cycles.109 if (DependentWrites && TotalCycles) {110 --TotalCycles;111 return;112 }113 114 // Bail out immediately if we don't know how many cycles are left.115 if (CyclesLeft == UNKNOWN_CYCLES)116 return;117 118 if (CyclesLeft) {119 --CyclesLeft;120 IsReady = !CyclesLeft;121 }122}123 124#ifndef NDEBUG125void WriteState::dump() const {126 dbgs() << "{ OpIdx=" << WD->OpIndex << ", Lat=" << getLatency() << ", RegID "127 << getRegisterID() << ", Cycles Left=" << getCyclesLeft() << " }";128}129#endif130 131#ifndef NDEBUG132void ReadState::dump() const {133 dbgs() << "{ OpIdx=" << RD->OpIndex << ", RegID " << getRegisterID()134 << ", Cycles Left=" << CyclesLeft << " }";135}136#endif137 138const CriticalDependency &Instruction::computeCriticalRegDep() {139 if (CriticalRegDep.Cycles)140 return CriticalRegDep;141 142 unsigned MaxLatency = 0;143 for (const WriteState &WS : getDefs()) {144 const CriticalDependency &WriteCRD = WS.getCriticalRegDep();145 if (WriteCRD.Cycles > MaxLatency)146 CriticalRegDep = WriteCRD;147 }148 149 for (const ReadState &RS : getUses()) {150 const CriticalDependency &ReadCRD = RS.getCriticalRegDep();151 if (ReadCRD.Cycles > MaxLatency)152 CriticalRegDep = ReadCRD;153 }154 155 return CriticalRegDep;156}157 158void Instruction::reset() {159 // Note that this won't clear read/write descriptors160 // or other non-trivial fields161 Stage = IS_INVALID;162 CyclesLeft = UNKNOWN_CYCLES;163 clearOptimizableMove();164 RCUTokenID = 0;165 LSUTokenID = 0;166 CriticalResourceMask = 0;167 IsEliminated = false;168}169 170void Instruction::dispatch(unsigned RCUToken) {171 assert(Stage == IS_INVALID);172 Stage = IS_DISPATCHED;173 RCUTokenID = RCUToken;174 175 // Check if input operands are already available.176 if (updateDispatched())177 updatePending();178}179 180void Instruction::execute(unsigned IID) {181 assert(Stage == IS_READY);182 Stage = IS_EXECUTING;183 184 // Set the cycles left before the write-back stage.185 CyclesLeft = getLatency();186 187 for (WriteState &WS : getDefs())188 WS.onInstructionIssued(IID);189 190 // Transition to the "executed" stage if this is a zero-latency instruction.191 if (!CyclesLeft)192 Stage = IS_EXECUTED;193}194 195void Instruction::forceExecuted() {196 assert(Stage == IS_READY && "Invalid internal state!");197 CyclesLeft = 0;198 Stage = IS_EXECUTED;199}200 201bool Instruction::updatePending() {202 assert(isPending() && "Unexpected instruction stage found!");203 204 if (!all_of(getUses(), [](const ReadState &Use) { return Use.isReady(); }))205 return false;206 207 // A partial register write cannot complete before a dependent write.208 if (!all_of(getDefs(), [](const WriteState &Def) { return Def.isReady(); }))209 return false;210 211 Stage = IS_READY;212 return true;213}214 215bool Instruction::updateDispatched() {216 assert(isDispatched() && "Unexpected instruction stage found!");217 218 if (!all_of(getUses(), [](const ReadState &Use) {219 return Use.isPending() || Use.isReady();220 }))221 return false;222 223 // A partial register write cannot complete before a dependent write.224 if (!all_of(getDefs(),225 [](const WriteState &Def) { return !Def.getDependentWrite(); }))226 return false;227 228 Stage = IS_PENDING;229 return true;230}231 232void Instruction::update() {233 if (isDispatched())234 updateDispatched();235 if (isPending())236 updatePending();237}238 239void Instruction::cycleEvent() {240 if (isReady())241 return;242 243 if (isDispatched() || isPending()) {244 for (ReadState &Use : getUses())245 Use.cycleEvent();246 247 for (WriteState &Def : getDefs())248 Def.cycleEvent();249 250 update();251 return;252 }253 254 assert(isExecuting() && "Instruction not in-flight?");255 assert(CyclesLeft && "Instruction already executed?");256 for (WriteState &Def : getDefs())257 Def.cycleEvent();258 CyclesLeft--;259 if (!CyclesLeft)260 Stage = IS_EXECUTED;261}262 263} // namespace mca264} // namespace llvm265