197 lines · plain
1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9//10//===----------------------------------------------------------------------===//11 12//===----------------------------------------------------------------------===//13// Target-independent interfaces which we are implementing.14//===----------------------------------------------------------------------===//15 16include "llvm/Target/Target.td"17 18//===----------------------------------------------------------------------===//19// Subtarget features.20//===----------------------------------------------------------------------===//21include "AArch64Features.td"22include "AArch64FMV.td"23 24//===----------------------------------------------------------------------===//25// Register File Description26//===----------------------------------------------------------------------===//27 28include "AArch64RegisterInfo.td"29include "AArch64RegisterBanks.td"30include "AArch64CallingConvention.td"31 32//===----------------------------------------------------------------------===//33// Instruction Descriptions34//===----------------------------------------------------------------------===//35 36include "AArch64Schedule.td"37include "AArch64InstrInfo.td"38include "AArch64SchedPredicates.td"39include "AArch64SchedPredExynos.td"40include "AArch64SchedPredNeoverse.td"41include "AArch64Combine.td"42 43defm : RemapAllTargetPseudoPointerOperands<GPR64sp>;44 45def AArch64InstrInfo : InstrInfo;46 47//===----------------------------------------------------------------------===//48// Named operands for MRS/MSR/TLBI/...49//===----------------------------------------------------------------------===//50 51include "AArch64SystemOperands.td"52 53//===----------------------------------------------------------------------===//54// AArch64 Processors supported.55//56 57//===----------------------------------------------------------------------===//58// Unsupported features to disable for scheduling models59//===----------------------------------------------------------------------===//60 61class AArch64Unsupported { list<Predicate> F; }62 63let F = [HasSVE2p1, HasSVE2p1_or_SME2, HasSVE2p1_or_StreamingSME2, HasSVE2p1_or_SME2p1] in64def SVE2p1Unsupported : AArch64Unsupported;65 66def SVE2Unsupported : AArch64Unsupported {67 let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasNonStreamingSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,68 HasSMEF8F32, HasSVEAES, HasSVESHA3, HasSVESM4, HasSVEBitPerm,69 HasSVEB16B16],70 SVE2p1Unsupported.F);71}72 73def SVEUnsupported : AArch64Unsupported {74 let F = !listconcat([HasSVE, HasSVE_or_SME],75 SVE2Unsupported.F);76}77 78def SME2p3Unsupported : AArch64Unsupported {79 let F = [HasSVE2p3_or_SME2p3, HasSVE_B16MM];80}81 82def SME2p2Unsupported : AArch64Unsupported {83 let F = !listconcat([HasSME2p2, HasSVE2p2_or_SME2p2,84 HasNonStreamingSVE_or_SME2p2,85 HasNonStreamingSVE2p2_or_SME2p2],86 SME2p3Unsupported.F);87}88 89def SME2p1Unsupported : AArch64Unsupported {90 let F = !listconcat([HasSME2p1, HasSVE2p1_or_SME2p1,91 HasSME_MOP4, HasSME_TMOP, HasNonStreamingSVE_or_SSVE_FEXPA, 92 HasNonStreamingSVE_or_SSVE_BitPerm],93 SME2p2Unsupported.F);94}95 96def SME2Unsupported : AArch64Unsupported {97 let F = !listconcat([HasSME2, HasNonStreamingSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,98 HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16,99 HasNonStreamingSVE_or_SSVE_AES, HasSVE2p1_or_StreamingSME2],100 SME2p1Unsupported.F);101}102 103def SMEUnsupported : AArch64Unsupported {104 let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64, HasSMEFA64],105 SME2Unsupported.F);106}107 108def MTEUnsupported : AArch64Unsupported {109 let F = [HasMTE];110}111 112let F = [HasPAuth, HasPAuthLR] in113def PAUnsupported : AArch64Unsupported;114 115include "AArch64SchedA320.td"116include "AArch64SchedA53.td"117include "AArch64SchedA55.td"118include "AArch64SchedA510.td"119include "AArch64SchedA57.td"120include "AArch64SchedCyclone.td"121include "AArch64SchedFalkor.td"122include "AArch64SchedKryo.td"123include "AArch64SchedExynosM3.td"124include "AArch64SchedExynosM4.td"125include "AArch64SchedExynosM5.td"126include "AArch64SchedThunderX.td"127include "AArch64SchedThunderX2T99.td"128include "AArch64SchedA64FX.td"129include "AArch64SchedThunderX3T110.td"130include "AArch64SchedTSV110.td"131include "AArch64SchedAmpere1.td"132include "AArch64SchedAmpere1B.td"133include "AArch64SchedNeoverseN1.td"134include "AArch64SchedNeoverseN2.td"135include "AArch64SchedNeoverseN3.td"136include "AArch64SchedNeoverseV1.td"137include "AArch64SchedNeoverseV2.td"138include "AArch64SchedNeoverseV3.td"139include "AArch64SchedNeoverseV3AE.td"140include "AArch64SchedOryon.td"141 142include "AArch64Processors.td"143 144//===----------------------------------------------------------------------===//145// Assembly parser146//===----------------------------------------------------------------------===//147 148def GenericAsmParserVariant : AsmParserVariant {149 int Variant = 0;150 string Name = "generic";151 string BreakCharacters = ".";152 string TokenizingCharacters = "[]*!/";153}154 155def AppleAsmParserVariant : AsmParserVariant {156 int Variant = 1;157 string Name = "apple-neon";158 string BreakCharacters = ".";159 string TokenizingCharacters = "[]*!/";160}161 162//===----------------------------------------------------------------------===//163// Assembly printer164//===----------------------------------------------------------------------===//165// AArch64 Uses the MC printer for asm output, so make sure the TableGen166// AsmWriter bits get associated with the correct class.167def GenericAsmWriter : AsmWriter {168 string AsmWriterClassName = "InstPrinter";169 int PassSubtarget = 1;170 int Variant = 0;171 bit isMCAsmWriter = 1;172}173 174def AppleAsmWriter : AsmWriter {175 let AsmWriterClassName = "AppleInstPrinter";176 int PassSubtarget = 1;177 int Variant = 1;178 int isMCAsmWriter = 1;179}180 181//===----------------------------------------------------------------------===//182// Target Declaration183//===----------------------------------------------------------------------===//184 185def AArch64 : Target {186 let InstructionSet = AArch64InstrInfo;187 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];188 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];189 let AllowRegisterRenaming = 1;190}191 192//===----------------------------------------------------------------------===//193// Pfm Counters194//===----------------------------------------------------------------------===//195 196include "AArch64PfmCounters.td"197