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1//=- AArch64CallingConv.td - Calling Conventions for AArch64 -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This describes the calling conventions for AArch64 architecture.10//11//===----------------------------------------------------------------------===//12 13/// CCIfBigEndian - Match only if we're in big endian mode.14class CCIfBigEndian<CCAction A> :15 CCIf<"State.getMachineFunction().getDataLayout().isBigEndian()", A>;16 17class CCIfILP32<CCAction A> :18 CCIf<"State.getMachineFunction().getDataLayout().getPointerSize() == 4", A>;19 20/// CCIfSubtarget - Match if the current subtarget has a feature F.21class CCIfSubtarget<string F, CCAction A>22 : CCIf<!strconcat("State.getMachineFunction()"23 ".getSubtarget<AArch64Subtarget>().", F),24 A>;25 26//===----------------------------------------------------------------------===//27// ARM AAPCS64 Calling Convention28//===----------------------------------------------------------------------===//29 30defvar AArch64_Common = [31 // The 'nest' parameter, if any, is passed in X15.32 // The previous register used here (X18) is also defined to be unavailable33 // for this purpose, while all of X9-X15 were defined to be free for LLVM to34 // use for this, so use X15 (which LLVM often already clobbers anyways).35 CCIfNest<CCAssignToReg<[X15]>>,36 37 CCIfType<[iPTR], CCBitConvertToType<i64>>,38 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,39 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,40 41 // Big endian vectors must be passed as if they were 1-element vectors so that42 // their lanes are in a consistent order.43 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],44 CCBitConvertToType<f64>>>,45 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],46 CCBitConvertToType<f128>>>,47 48 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter.49 // However, on windows, in some circumstances, the SRet is passed in X0 or X150 // instead. The presence of the inreg attribute indicates that SRet is51 // passed in the alternative register (X0 or X1), not X8:52 // - X0 for non-instance methods.53 // - X1 for instance methods.54 55 // The "sret" attribute identifies indirect returns.56 // The "inreg" attribute identifies non-aggregate types.57 // The position of the "sret" attribute identifies instance/non-instance58 // methods.59 // "sret" on argument 0 means non-instance methods.60 // "sret" on argument 1 means instance methods.61 62 CCIfInReg<CCIfType<[i64],63 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X0, X1]>>>>>,64 65 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X8]>>>,66 67 // Put ByVal arguments directly on the stack. Minimum size and alignment of a68 // slot is 64-bit.69 CCIfByVal<CCPassByVal<8, 8>>,70 71 // Pass SwiftSelf in a callee saved register.72 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[X20]>>>,73 74 // A SwiftError is passed in X21.75 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X21]>>>,76 77 // Pass SwiftAsync in an otherwise callee saved register so that it will be78 // preserved for normal function calls.79 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[X22]>>>,80 81 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,82 83 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,84 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],85 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,86 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,87 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],88 CCPassIndirect<i64>>,89 90 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount],91 CCAssignToReg<[P0, P1, P2, P3]>>,92 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount],93 CCPassIndirect<i64>>,94 95 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,96 // up to eight each of GPR and FPR.97 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,98 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,99 // i128 is split to two i64s, we can't fit half to register X7.100 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6],101 [X0, X1, X3, X5]>>>,102 103 // i128 is split to two i64s, and its stack alignment is 16 bytes.104 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,105 106 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,107 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,108 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,109 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>,110 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,111 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],112 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,113 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],114 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,115 116 // If more than will fit in registers, pass them on the stack instead.117 CCIfType<[i1, i8, i16, f16, bf16], CCAssignToStack<8, 8>>,118 CCIfType<[i32, f32], CCAssignToStack<8, 8>>,119 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],120 CCAssignToStack<8, 8>>,121 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],122 CCAssignToStack<16, 16>>123];124 125let Entry = 1 in126def CC_AArch64_AAPCS : CallingConv<AArch64_Common>;127 128let Entry = 1 in129def RetCC_AArch64_AAPCS : CallingConv<[130 CCIfType<[iPTR], CCBitConvertToType<i64>>,131 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,132 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,133 134 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,135 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X21]>>>,136 137 // Big endian vectors must be passed as if they were 1-element vectors so that138 // their lanes are in a consistent order.139 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],140 CCBitConvertToType<f64>>>,141 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],142 CCBitConvertToType<f128>>>,143 144 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,145 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,146 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,147 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,148 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,149 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>,150 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,151 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],152 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,153 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],154 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,155 156 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,157 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],158 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,159 160 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount],161 CCAssignToReg<[P0, P1, P2, P3]>>162]>;163 164let Entry = 1 in165def CC_AArch64_Win64PCS : CallingConv<!listconcat(166 [167 // 'CFGuardTarget' is used for Arm64EC; it passes its parameter in X9.168 CCIfCFGuardTarget<CCAssignToReg<[X9]>>169 ],170 AArch64_Common)171>;172 173// Vararg functions on windows pass floats in integer registers174let Entry = 1 in175def CC_AArch64_Win64_VarArg : CallingConv<[176 CCIfType<[f16, bf16], CCBitConvertToType<i16>>,177 CCIfType<[f32], CCBitConvertToType<i32>>,178 CCIfType<[f64], CCBitConvertToType<i64>>,179 CCDelegateTo<CC_AArch64_Win64PCS>180]>;181 182// Vararg functions on Arm64EC ABI use a different convention, using183// a stack layout compatible with the x64 calling convention.184let Entry = 1 in185def CC_AArch64_Arm64EC_VarArg : CallingConv<[186 // 'CFGuardTarget' is used for Arm64EC; it passes its parameter in X9.187 CCIfCFGuardTarget<CCAssignToReg<[X9]>>,188 189 CCIfNest<CCAssignToReg<[X15]>>,190 191 // Convert small floating-point values to integer.192 CCIfType<[f16, bf16], CCBitConvertToType<i16>>,193 CCIfType<[f32], CCBitConvertToType<i32>>,194 CCIfType<[f64, v1f64, v1i64, v2f32, v2i32, v4i16, v4f16, v4bf16, v8i8, iPTR],195 CCBitConvertToType<i64>>,196 197 // Larger floating-point/vector values are passed indirectly.198 CCIfType<[f128, v2f64, v2i64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],199 CCPassIndirect<i64>>,200 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,201 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],202 CCPassIndirect<i64>>,203 CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1],204 CCPassIndirect<i64>>,205 206 // Handle SRet. See comment in CC_AArch64_AAPCS.207 CCIfInReg<CCIfType<[i64],208 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X0, X1]>>>>>,209 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X8]>>>,210 211 // Put ByVal arguments directly on the stack. Minimum size and alignment of a212 // slot is 64-bit. (Shouldn't normally come up; the Microsoft ABI doesn't213 // use byval.)214 CCIfByVal<CCPassByVal<8, 8>>,215 216 // Promote small integers to i32217 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,218 219 // Pass first four arguments in x0-x3.220 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3]>>,221 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3]>>,222 223 // Put remaining arguments on stack.224 CCIfType<[i32, i64], CCAssignToStack<8, 8>>,225]>;226 227// Arm64EC thunks use a calling convention that's precisely the x64 calling228// convention, except that the registers have different names, and the callee229// address is passed in X9.230let Entry = 1 in231def CC_AArch64_Arm64EC_Thunk : CallingConv<[232 // ARM64EC-specific: the InReg attribute can be used to access the x64 sp passed into entry thunks in x4 from the IR.233 CCIfInReg<CCIfType<[i64], CCAssignToReg<[X4]>>>,234 235 // Byval aggregates are passed by pointer236 CCIfByVal<CCPassIndirect<i64>>,237 238 // ARM64EC-specific: promote small integers to i32. (x86 only promotes i1,239 // but that would confuse ARM64 lowering code.)240 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,241 242 // The 'nest' parameter, if any, is passed in R10 (X4).243 CCIfNest<CCAssignToReg<[X4]>>,244 245 // A SwiftError is passed in R12 (X19).246 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X19]>>>,247 248 // Pass SwiftSelf in R13 (X20).249 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[X20]>>>,250 251 // Pass SwiftAsync in an otherwise callee saved register so that calls to252 // normal functions don't need to save it somewhere.253 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[X21]>>>,254 255 // The 'CFGuardTarget' parameter, if any, is passed in RAX (R8).256 CCIfCFGuardTarget<CCAssignToReg<[X8]>>,257 258 // 128 bit vectors are passed by pointer259 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect<i64>>,260 261 // 256 bit vectors are passed by pointer262 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], CCPassIndirect<i64>>,263 264 // 512 bit vectors are passed by pointer265 CCIfType<[v64i8, v32i16, v16i32, v32f16, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,266 267 // Long doubles are passed by pointer268 CCIfType<[f80], CCPassIndirect<i64>>,269 270 // The first 4 MMX vector arguments are passed in GPRs.271 CCIfType<[x86mmx], CCBitConvertToType<i64>>,272 273 // The first 4 FP/Vector arguments are passed in XMM registers.274 CCIfType<[f16],275 CCAssignToRegWithShadow<[H0, H1, H2, H3],276 [X0, X1, X2, X3]>>,277 CCIfType<[f32],278 CCAssignToRegWithShadow<[S0, S1, S2, S3],279 [X0, X1, X2, X3]>>,280 CCIfType<[f64],281 CCAssignToRegWithShadow<[D0, D1, D2, D3],282 [X0, X1, X2, X3]>>,283 284 // The first 4 integer arguments are passed in integer registers.285 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3],286 [Q0, Q1, Q2, Q3]>>,287 288 // Arm64EC thunks: the first argument is always a pointer to the destination289 // address, stored in x9.290 CCIfType<[i64], CCAssignToReg<[X9]>>,291 292 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3],293 [Q0, Q1, Q2, Q3]>>,294 295 // Integer/FP values get stored in stack slots that are 8 bytes in size and296 // 8-byte aligned if there are no more registers to hold them.297 CCIfType<[i8, i16, i32, i64, f16, f32, f64], CCAssignToStack<8, 8>>298]>;299 300// The native side of ARM64EC thunks301let Entry = 1 in302def CC_AArch64_Arm64EC_Thunk_Native : CallingConv<[303 CCIfType<[i64], CCAssignToReg<[X9]>>,304 CCDelegateTo<CC_AArch64_AAPCS>305]>;306 307let Entry = 1 in308def RetCC_AArch64_Arm64EC_Thunk : CallingConv<[309 // The X86-Win64 calling convention always returns __m64 values in RAX.310 CCIfType<[x86mmx], CCBitConvertToType<i64>>,311 312 // Otherwise, everything is the same as 'normal' X86-64 C CC.313 314 // The X86-64 calling convention always returns FP values in XMM0.315 CCIfType<[f16], CCAssignToReg<[H0, H1]>>,316 CCIfType<[f32], CCAssignToReg<[S0, S1]>>,317 CCIfType<[f64], CCAssignToReg<[D0, D1]>>,318 CCIfType<[f128], CCAssignToReg<[Q0, Q1]>>,319 320 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X19]>>>,321 322 // Scalar values are returned in AX first, then DX. For i8, the ABI323 // requires the values to be in AL and AH, however this code uses AL and DL324 // instead. This is because using AH for the second register conflicts with325 // the way LLVM does multiple return values -- a return of {i16,i8} would end326 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI327 // for functions that return two i8 values are currently expected to pack the328 // values into an i16 (which uses AX, and thus AL:AH).329 //330 // For code that doesn't care about the ABI, we allow returning more than two331 // integer values in registers.332 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,333 CCIfType<[i32], CCAssignToReg<[W8, W1, W0]>>,334 CCIfType<[i64], CCAssignToReg<[X8, X1, X0]>>,335 336 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3337 // can only be used by ABI non-compliant code. If the target doesn't have XMM338 // registers, it won't have vector types.339 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64],340 CCAssignToReg<[Q0, Q1, Q2, Q3]>>341]>;342 343// Windows Control Flow Guard checks take a single argument (the target function344// address) and have no return value.345let Entry = 1 in346def CC_AArch64_Win64_CFGuard_Check : CallingConv<[347 CCIfType<[i64], CCAssignToReg<[X15]>>348]>;349 350let Entry = 1 in351def CC_AArch64_Arm64EC_CFGuard_Check : CallingConv<[352 CCIfType<[i64], CCAssignToReg<[X11, X10, X9]>>353]>;354 355let Entry = 1 in356def RetCC_AArch64_Arm64EC_CFGuard_Check : CallingConv<[357 CCIfType<[i64], CCAssignToReg<[X11, X9]>>358]>;359 360 361// Darwin uses a calling convention which differs in only two ways362// from the standard one at this level:363// + i128s (i.e. split i64s) don't need even registers.364// + Stack slots are sized as needed rather than being at least 64-bit.365let Entry = 1 in366def CC_AArch64_DarwinPCS : CallingConv<[367 CCIfNest<CCAssignToReg<[X15]>>,368 369 CCIfType<[iPTR], CCBitConvertToType<i64>>,370 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,371 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,372 373 // An SRet is passed in X8, not X0 like a normal pointer parameter.374 CCIfSRet<CCIfType<[i64], CCAssignToReg<[X8]>>>,375 376 // Put ByVal arguments directly on the stack. Minimum size and alignment of a377 // slot is 64-bit.378 CCIfByVal<CCPassByVal<8, 8>>,379 380 // Pass SwiftSelf in a callee saved register.381 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[X20]>>>,382 383 // A SwiftError is passed in X21.384 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[X21]>>>,385 386 // Pass SwiftAsync in an otherwise callee saved register so that it will be387 // preserved for normal function calls.388 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[X22]>>>,389 390 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,391 392 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,393 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],394 CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,395 CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,396 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],397 CCPassIndirect<i64>>,398 399 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount],400 CCAssignToReg<[P0, P1, P2, P3]>>,401 CCIfType<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, aarch64svcount],402 CCPassIndirect<i64>>,403 404 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,405 // up to eight each of GPR and FPR.406 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,407 CCIfType<[i32], CCAssignToReg<[W0, W1, W2, W3, W4, W5, W6, W7]>>,408 // i128 is split to two i64s, we can't fit half to register X7.409 CCIfType<[i64],410 CCIfSplit<CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6]>>>,411 // i128 is split to two i64s, and its stack alignment is 16 bytes.412 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,413 414 CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,415 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,416 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,417 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>,418 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,419 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],420 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,421 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],422 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,423 424 // If more than will fit in registers, pass them on the stack instead.425 CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>,426 CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16",427 CCAssignToStack<2, 2>>,428 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,429 430 // Re-demote pointers to 32-bits so we don't end up storing 64-bit431 // values and clobbering neighbouring stack locations. Not very pretty.432 CCIfPtr<CCIfILP32<CCTruncToType<i32>>>,433 CCIfPtr<CCIfILP32<CCAssignToStack<4, 4>>>,434 435 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],436 CCAssignToStack<8, 8>>,437 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],438 CCAssignToStack<16, 16>>439]>;440 441let Entry = 1 in442def CC_AArch64_DarwinPCS_VarArg : CallingConv<[443 CCIfNest<CCAssignToReg<[X15]>>,444 445 CCIfType<[iPTR], CCBitConvertToType<i64>>,446 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,447 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,448 449 CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Stack_Block">>,450 451 // Handle all scalar types as either i64 or f64.452 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,453 CCIfType<[f16, bf16, f32], CCPromoteToType<f64>>,454 455 // Everything is on the stack.456 // i128 is split to two i64s, and its stack alignment is 16 bytes.457 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>,458 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],459 CCAssignToStack<8, 8>>,460 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],461 CCAssignToStack<16, 16>>462]>;463 464// In the ILP32 world, the minimum stack slot size is 4 bytes. Otherwise the465// same as the normal Darwin VarArgs handling.466let Entry = 1 in467def CC_AArch64_DarwinPCS_ILP32_VarArg : CallingConv<[468 CCIfNest<CCAssignToReg<[X15]>>,469 470 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,471 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,472 473 // Handle all scalar types as either i32 or f32.474 CCIfType<[i8, i16], CCPromoteToType<i32>>,475 CCIfType<[f16, bf16], CCPromoteToType<f32>>,476 477 // Everything is on the stack.478 // i128 is split to two i64s, and its stack alignment is 16 bytes.479 CCIfPtr<CCIfILP32<CCTruncToType<i32>>>,480 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,481 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>,482 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],483 CCAssignToStack<8, 8>>,484 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],485 CCAssignToStack<16, 16>>486]>;487 488//===----------------------------------------------------------------------===//489// ARM64 Calling Convention for GHC490//===----------------------------------------------------------------------===//491 492// This calling convention is specific to the Glasgow Haskell Compiler.493// The only documentation is the GHC source code, specifically the C header494// file:495//496// https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs.h497//498// which defines the registers for the Spineless Tagless G-Machine (STG) that499// GHC uses to implement lazy evaluation. The generic STG machine has a set of500// registers which are mapped to appropriate set of architecture specific501// registers for each CPU architecture.502//503// The STG Machine is documented here:504//505// https://ghc.haskell.org/trac/ghc/wiki/Commentary/Compiler/GeneratedCode506//507// The AArch64 register mapping is defined in the following header file:508//509// https://github.com/ghc/ghc/blob/master/rts/include/stg/MachRegs/arm64.h510//511 512let Entry = 1 in513def CC_AArch64_GHC : CallingConv<[514 CCIfNest<CCAssignToReg<[X15]>>,515 516 CCIfType<[iPTR], CCBitConvertToType<i64>>,517 518 // Handle all vector types as either f64 or v2f64.519 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,520 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>,521 522 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,523 CCIfType<[f32], CCAssignToReg<[S8, S9, S10, S11]>>,524 CCIfType<[f64], CCAssignToReg<[D12, D13, D14, D15]>>,525 526 // Promote i8/i16/i32 arguments to i64.527 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,528 529 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim530 CCIfType<[i64], CCAssignToReg<[X19, X20, X21, X22, X23, X24, X25, X26, X27, X28]>>531]>;532 533let Entry = 1 in534def CC_AArch64_Preserve_None : CallingConv<[535 // VarArgs are only supported using the C calling convention.536 // This handles the non-variadic parameter case. Variadic parameters537 // are handled in CCAssignFnForCall.538 CCIfVarArg<CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_AArch64_DarwinPCS>>>,539 CCIfVarArg<CCIfSubtarget<"isTargetWindows()", CCDelegateTo<CC_AArch64_Win64PCS>>>,540 CCIfVarArg<CCDelegateTo<CC_AArch64_AAPCS>>,541 542 // We can pass arguments in all general registers, except:543 // - X8, used for sret544 // - X15 (on Windows), used as a temporary register in the prologue when allocating call frames545 // - X16/X17, used by the linker as IP0/IP1546 // - X18, the platform register547 // - X19, the base pointer548 // - X29, the frame pointer549 // - X30, the link register550 // General registers are not preserved with the exception of551 // FP, LR, and X18552 // Non-volatile registers are used first, so functions may call553 // normal functions without saving and reloading arguments.554 // X9 is assigned last as it is used in FrameLowering as the first555 // choice for a scratch register.556 CCIfType<[i32], CCAssignToReg<[W20, W21, W22, W23,557 W24, W25, W26, W27, W28,558 W0, W1, W2, W3, W4, W5,559 W6, W7, W10, W11,560 W12, W13, W14, W9]>>,561 CCIfType<[i64], CCAssignToReg<[X20, X21, X22, X23,562 X24, X25, X26, X27, X28,563 X0, X1, X2, X3, X4, X5,564 X6, X7, X10, X11,565 X12, X13, X14, X9]>>,566 567 // Windows uses X15 for stack allocation568 CCIf<"!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()",569 CCIfType<[i32], CCAssignToReg<[W15]>>>,570 CCIf<"!State.getMachineFunction().getSubtarget<AArch64Subtarget>().isTargetWindows()",571 CCIfType<[i64], CCAssignToReg<[X15]>>>,572 573 CCDelegateTo<CC_AArch64_AAPCS>574]>;575 576// The order of the callee-saves in this file is important, because the577// FrameLowering code will use this order to determine the layout the578// callee-save area in the stack frame. As can be observed below, Darwin579// requires the frame-record (LR, FP) to be at the top the callee-save area,580// whereas for other platforms they are at the bottom.581 582// FIXME: LR is only callee-saved in the sense that *we* preserve it and are583// presumably a callee to someone. External functions may not do so, but this584// is currently safe since BL has LR as an implicit-def and what happens after a585// tail call doesn't matter.586//587// It would be better to model its preservation semantics properly (create a588// vreg on entry, use it in RET & tail call generation; make that vreg def if we589// end up saving LR as part of a call frame). Watch this space...590def CSR_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,591 X25, X26, X27, X28, LR, FP,592 D8, D9, D10, D11,593 D12, D13, D14, D15)>;594 595// A variant for treating X18 as callee saved, when interfacing with596// code that needs X18 to be preserved.597def CSR_AArch64_AAPCS_X18 : CalleeSavedRegs<(add X18, CSR_AArch64_AAPCS)>;598 599// Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x.600// We put FP before LR, so that frame lowering logic generates (FP,LR) pairs,601// and not (LR,FP) pairs.602def CSR_Win_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,603 X25, X26, X27, X28, FP, LR,604 D8, D9, D10, D11,605 D12, D13, D14, D15)>;606 607def CSR_Win_AArch64_AAPCS_SwiftError608 : CalleeSavedRegs<(sub CSR_Win_AArch64_AAPCS, X21)>;609 610def CSR_Win_AArch64_AAPCS_SwiftTail611 : CalleeSavedRegs<(sub CSR_Win_AArch64_AAPCS, X20, X22)>;612 613def CSR_Win_AArch64_RT_MostRegs614 : CalleeSavedRegs<(add CSR_Win_AArch64_AAPCS, (sequence "X%u", 9, 15))>;615 616def CSR_Win_AArch64_RT_AllRegs617 : CalleeSavedRegs<(add CSR_Win_AArch64_RT_MostRegs, (sequence "Q%u", 8, 31))>;618 619// The Control Flow Guard check call uses a custom calling convention that also620// preserves X0-X8 and Q0-Q7.621def CSR_Win_AArch64_CFGuard_Check : CalleeSavedRegs<(add CSR_Win_AArch64_AAPCS,622 (sequence "X%u", 0, 8),623 (sequence "Q%u", 0, 7))>;624 625// To match the x64 calling convention, Arm64EC thunks preserve q6-q15.626def CSR_Win_AArch64_Arm64EC_Thunk : CalleeSavedRegs<(add (sequence "Q%u", 6, 15),627 X19, X20, X21, X22, X23, X24,628 X25, X26, X27, X28, FP, LR)>;629 630// AArch64 PCS for vector functions (VPCS)631// must (additionally) preserve full Q8-Q23 registers632def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,633 X25, X26, X27, X28, LR, FP,634 (sequence "Q%u", 8, 23))>;635def CSR_Win_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,636 X25, X26, X27, X28, FP, LR,637 (sequence "Q%u", 8, 23))>;638 639// Functions taking SVE arguments or returning an SVE type640// must (additionally) preserve full Z8-Z23 and predicate registers P4-P15641def CSR_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23),642 (sequence "P%u", 4, 15),643 X19, X20, X21, X22, X23, X24,644 X25, X26, X27, X28, LR, FP)>;645 646def CSR_Darwin_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23),647 (sequence "P%u", 4, 15),648 LR, FP, X19, X20, X21, X22,649 X23, X24, X25, X26, X27, X28)>;650 651def CSR_Win_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "P%u", 4, 15),652 (sequence "Z%u", 8, 23),653 X19, X20, X21, X22, X23, X24,654 X25, X26, X27, X28, FP, LR)>;655 656// SME ABI support routines such as __arm_tpidr2_save/restore preserve most registers.657def CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0658 : CalleeSavedRegs<(add (sequence "Z%u", 0, 31),659 (sequence "P%u", 0, 15),660 (sequence "X%u", 0, 13),661 (sequence "X%u",19, 28),662 LR, FP)>;663 664// SME ABI support routines such as __arm_get_current_vg preserve most registers.665def CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X1666 : CalleeSavedRegs<(add (sequence "Z%u", 0, 31),667 (sequence "P%u", 0, 15),668 (sequence "X%u", 1, 15),669 (sequence "X%u",19, 28),670 LR, FP)>;671 672// SME ABI support routines __arm_sme_state preserves most registers.673def CSR_AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2674 : CalleeSavedRegs<(add (sequence "Z%u", 0, 31),675 (sequence "P%u", 0, 15),676 (sequence "X%u", 2, 15),677 (sequence "X%u",19, 28),678 LR, FP)>;679 680// The SMSTART/SMSTOP instructions preserve only GPR registers.681def CSR_AArch64_SMStartStop : CalleeSavedRegs<(add (sequence "X%u", 0, 28),682 LR, FP)>;683 684def CSR_AArch64_AAPCS_SwiftTail685 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X20, X22)>;686 687// Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since688// 'this' and the pointer return value are both passed in X0 in these cases,689// this can be partially modelled by treating X0 as a callee-saved register;690// only the resulting RegMask is used; the SaveList is ignored691//692// (For generic ARM 64-bit ABI code, clang will not generate constructors or693// destructors with 'this' returns, so this RegMask will not be used in that694// case)695def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>;696 697def CSR_AArch64_AAPCS_SwiftError698 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X21)>;699 700// The ELF stub used for TLS-descriptor access saves every feasible701// register. Only X0 and LR are clobbered.702def CSR_AArch64_TLS_ELF703 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP,704 (sequence "Q%u", 0, 31))>;705 706def CSR_AArch64_AllRegs707 : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP,708 (sequence "X%u", 0, 28), FP, LR, SP,709 (sequence "B%u", 0, 31), (sequence "H%u", 0, 31),710 (sequence "S%u", 0, 31), (sequence "D%u", 0, 31),711 (sequence "Q%u", 0, 31))>;712 713def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>;714 715def CSR_AArch64_NoneRegs : CalleeSavedRegs<(add LR, FP)>;716 717def CSR_AArch64_RT_MostRegs : CalleeSavedRegs<(add CSR_AArch64_AAPCS,718 (sequence "X%u", 9, 15))>;719 720def CSR_AArch64_RT_AllRegs : CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs,721 (sequence "Q%u", 8, 31))>;722 723def CSR_AArch64_StackProbe_Windows724 : CalleeSavedRegs<(add (sequence "X%u", 0, 15),725 (sequence "X%u", 18, 28), FP, SP,726 (sequence "Q%u", 0, 31))>;727 728// Darwin variants of AAPCS.729// Darwin puts the frame-record at the top of the callee-save area.730def CSR_Darwin_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,731 X23, X24, X25, X26, X27, X28,732 D8, D9, D10, D11,733 D12, D13, D14, D15)>;734 735def CSR_Darwin_AArch64_AAVPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21,736 X22, X23, X24, X25, X26, X27,737 X28, (sequence "Q%u", 8, 23))>;738 739// For Windows calling convention on a non-windows OS, where X18 is treated740// as reserved, back up X18 when entering non-windows code (marked with the741// Windows calling convention) and restore when returning regardless of742// whether the individual function uses it - it might call other functions743// that clobber it.744def CSR_Darwin_AArch64_AAPCS_Win64745 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, X18)>;746 747def CSR_Darwin_AArch64_AAPCS_ThisReturn748 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, X0)>;749 750def CSR_Darwin_AArch64_AAPCS_SwiftError751 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_AAPCS, X21)>;752 753def CSR_Darwin_AArch64_AAPCS_SwiftTail754 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_AAPCS, X20, X22)>;755 756// The function used by Darwin to obtain the address of a thread-local variable757// guarantees more than a normal AAPCS function. x16 and x17 are used on the758// fast path for calculation, but other registers except X0 (argument/return)759// and LR (it is a call, after all) are preserved.760def CSR_Darwin_AArch64_TLS761 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17),762 FP,763 (sequence "Q%u", 0, 31))>;764 765// We can only handle a register pair with adjacent registers, the register pair766// should belong to the same class as well. Since the access function on the767// fast path calls a function that follows CSR_Darwin_AArch64_TLS,768// CSR_Darwin_AArch64_CXX_TLS should be a subset of CSR_Darwin_AArch64_TLS.769def CSR_Darwin_AArch64_CXX_TLS770 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS,771 (sub (sequence "X%u", 1, 28), X9, X15, X16, X17, X18, X19),772 (sequence "D%u", 0, 31))>;773 774// CSRs that are handled by prologue, epilogue.775def CSR_Darwin_AArch64_CXX_TLS_PE776 : CalleeSavedRegs<(add LR, FP)>;777 778// CSRs that are handled explicitly via copies.779def CSR_Darwin_AArch64_CXX_TLS_ViaCopy780 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_CXX_TLS, LR, FP)>;781 782def CSR_Darwin_AArch64_RT_MostRegs783 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS, (sequence "X%u", 9, 15))>;784 785def CSR_Darwin_AArch64_RT_AllRegs786 : CalleeSavedRegs<(add CSR_Darwin_AArch64_RT_MostRegs, (sequence "Q%u", 8, 31))>;787 788// Variants of the standard calling conventions for shadow call stack.789// These all preserve x18 in addition to any other registers.790def CSR_AArch64_NoRegs_SCS791 : CalleeSavedRegs<(add CSR_AArch64_NoRegs, X18)>;792def CSR_AArch64_NoneRegs_SCS793 : CalleeSavedRegs<(add CSR_AArch64_NoneRegs, X18)>;794def CSR_AArch64_AllRegs_SCS795 : CalleeSavedRegs<(add CSR_AArch64_AllRegs, X18)>;796def CSR_AArch64_AAPCS_SwiftError_SCS797 : CalleeSavedRegs<(add CSR_AArch64_AAPCS_SwiftError, X18)>;798def CSR_AArch64_RT_MostRegs_SCS799 : CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, X18)>;800def CSR_AArch64_RT_AllRegs_SCS801 : CalleeSavedRegs<(add CSR_AArch64_RT_AllRegs, X18)>;802def CSR_AArch64_AAVPCS_SCS803 : CalleeSavedRegs<(add CSR_AArch64_AAVPCS, X18)>;804def CSR_AArch64_SVE_AAPCS_SCS805 : CalleeSavedRegs<(add CSR_AArch64_SVE_AAPCS, X18)>;806def CSR_AArch64_AAPCS_SCS807 : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X18)>;808