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1//=- AArch64Features.td - Describe AArch64 SubtargetFeatures -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9//10//===----------------------------------------------------------------------===//11 12// A SubtargetFeature that represents one or more Architecture Extensions, as13// defined by the Arm ARM and typically identified by a 'FEAT_*' name.14// Each Extension record defines an ExtensionInfo entry in the Target Parser15// with a corresponding 'AEK_*' entry in the ArchExtKind enum.16class Extension<17 string TargetFeatureName, // String used for -target-feature, unless overridden.18 string Spelling, // The XYZ in HasXYZ and AEK_XYZ.19 string ArchitectureFeatureName, // The extension's "FEAT_*"" name(s) defined by the architecture20 string Desc, // Description.21 list<SubtargetFeature> Implies = [] // List of dependent features.22> : SubtargetFeature<TargetFeatureName, "Has" # Spelling, "true", Desc, Implies>23{24 string ArchExtKindSpelling = "AEK_" # Spelling; // ArchExtKind enum name.25 26 string ArchFeatureName = ArchitectureFeatureName;27 28 // The user visible name used by -march/-mcpu modifiers and target attribute29 // values. Extensions are not available on these by default.30 string UserVisibleName = "";31 32 // An alias that can be used on the command line, if the extension has one.33 // Used for correcting historical names while remaining backwards compatible.34 string UserVisibleAlias = "";35}36 37// An Extension that can be toggled via a '-march'/'-mcpu' modifier or a target38// attribute, e.g. '+sm4".39class ExtensionWithMArch<40 string TargetFeatureName, // String used for -target-feature and -march, unless overridden.41 string Spelling, // The XYZ in HasXYZ and AEK_XYZ.42 string ArchitectureFeatureName, // The extension's "FEAT_*"" name(s) defined by the architecture43 string Desc, // Description.44 list<SubtargetFeature> Implies = [] // List of dependent features.45> : Extension<TargetFeatureName, Spelling, ArchitectureFeatureName, Desc, Implies> {46 // In general, the name written on the command line should match the name47 // used for -target-feature. However, there are exceptions. Therefore we48 // add a separate field for this, to allow overriding it. Strongly prefer49 // not doing so.50 let UserVisibleName = TargetFeatureName;51}52 53 54 55// Each SubtargetFeature which corresponds to an Arm Architecture feature should56// be annotated with the respective FEAT_ feature name from the Architecture57// Reference Manual. If a SubtargetFeature enables instructions from multiple58// Arm Architecture Features, it should list all the relevant features. Not all59// FEAT_ features have a corresponding SubtargetFeature.60 61 62//===----------------------------------------------------------------------===//63// Armv8.0 Architecture Extensions64//===----------------------------------------------------------------------===//65 66let ArchExtKindSpelling = "AEK_FP", UserVisibleName = "fp" in67def FeatureFPARMv8 : ExtensionWithMArch<"fp-armv8", "FPARMv8", "FEAT_FP",68 "Enable Armv8.0-A Floating Point Extensions">;69 70let ArchExtKindSpelling = "AEK_SIMD", UserVisibleName = "simd" in71def FeatureNEON : ExtensionWithMArch<"neon", "NEON", "FEAT_AdvSIMD",72 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;73 74def FeatureSHA2 : ExtensionWithMArch<"sha2", "SHA2", "FEAT_SHA1, FEAT_SHA256",75 "Enable SHA1 and SHA256 support", [FeatureNEON]>;76 77def FeatureAES : ExtensionWithMArch<"aes", "AES", "FEAT_AES, FEAT_PMULL",78 "Enable AES support", [FeatureNEON]>;79 80// Crypto has been split up and any combination is now valid (see the81// crypto definitions above). Also, crypto is now context sensitive:82// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.83// Therefore, we rely on Clang, the user interfacing tool, to pass on the84// appropriate crypto options. But here in the backend, crypto has very little85// meaning anymore. We kept the Crypto definition here for backward86// compatibility, and now imply features SHA2 and AES, which was the87// "traditional" meaning of Crypto.88def FeatureCrypto : ExtensionWithMArch<"crypto", "Crypto", "FEAT_Crypto",89 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;90 91def FeatureCRC : ExtensionWithMArch<"crc", "CRC", "FEAT_CRC32",92 "Enable Armv8.0-A CRC-32 checksum instructions">;93 94// This SubtargetFeature is special. It controls only whether codegen will turn95// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The96// `FEAT_PMUv3*` system registers are always available for assembly/disassembly.97let UserVisibleName = "pmuv3" in98def FeaturePerfMon : ExtensionWithMArch<"perfmon", "PerfMon", "FEAT_PMUv3",99 "Enable Armv8.0-A PMUv3 Performance Monitors extension">;100 101def FeatureSpecRestrict : Extension<"specrestrict", "SpecRestrict", "FEAT_CSV2_2",102 "Enable architectural speculation restriction">;103 104//===----------------------------------------------------------------------===//105// Armv8.1 Architecture Extensions106//===----------------------------------------------------------------------===//107 108def FeatureLSE : ExtensionWithMArch<"lse", "LSE", "FEAT_LSE",109 "Enable Armv8.1-A Large System Extension (LSE) atomic instructions">;110 111let UserVisibleAlias = "rdma" in112def FeatureRDM : ExtensionWithMArch<"rdm", "RDM", "FEAT_RDM",113 "Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions",114 [FeatureNEON]>;115 116def FeaturePAN : Extension<"pan", "PAN", "FEAT_PAN",117 "Enable Armv8.1-A Privileged Access-Never extension">;118 119def FeatureLOR : Extension<"lor", "LOR", "FEAT_LOR",120 "Enable Armv8.1-A Limited Ordering Regions extension">;121 122def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",123 "true", "Enable RW operand CONTEXTIDR_EL2">;124 125def FeatureVH : Extension<"vh", "VH", "FEAT_VHE",126 "Enable Armv8.1-A Virtual Host extension", [FeatureCONTEXTIDREL2]>;127 128//===----------------------------------------------------------------------===//129// Armv8.2 Architecture Extensions130//===----------------------------------------------------------------------===//131 132def FeatureSM4 : ExtensionWithMArch<"sm4", "SM4", "FEAT_SM4, FEAT_SM3",133 "Enable SM3 and SM4 support", [FeatureNEON]>;134 135def FeatureSHA3 : ExtensionWithMArch<"sha3", "SHA3", "FEAT_SHA3, FEAT_SHA512",136 "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;137 138def FeatureRAS : ExtensionWithMArch<"ras", "RAS", "FEAT_RAS, FEAT_RASv1p1",139 "Enable Armv8.0-A Reliability, Availability and Serviceability Extensions">;140 141let ArchExtKindSpelling = "AEK_FP16", UserVisibleName = "fp16" in142def FeatureFullFP16 : ExtensionWithMArch<"fullfp16", "FullFP16", "FEAT_FP16",143 "Enable half-precision floating-point data processing", [FeatureFPARMv8]>;144 145let ArchExtKindSpelling = "AEK_PROFILE", UserVisibleName = "profile" in146def FeatureSPE : ExtensionWithMArch<"spe", "SPE", "FEAT_SPE",147 "Enable Statistical Profiling extension">;148 149def FeaturePAN_RWV : Extension<"pan-rwv", "PAN_RWV", "FEAT_PAN2",150 "Enable Armv8.2-A PAN s1e1R and s1e1W Variants", [FeaturePAN]>;151 152def FeaturePsUAO : Extension<"uaops", "PsUAO", "FEAT_UAO",153 "Enable Armv8.2-A UAO PState">;154 155def FeatureCCPP : Extension<"ccpp", "CCPP", "FEAT_DPB",156 "Enable Armv8.2-A data Cache Clean to Point of Persistence">;157 158def FeatureSVE : ExtensionWithMArch<"sve", "SVE", "FEAT_SVE",159 "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>;160 161let ArchExtKindSpelling = "AEK_I8MM" in162def FeatureMatMulInt8 : ExtensionWithMArch<"i8mm", "MatMulInt8", "FEAT_I8MM",163 "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>;164 165let ArchExtKindSpelling = "AEK_F32MM" in166def FeatureMatMulFP32 : ExtensionWithMArch<"f32mm", "MatMulFP32", "FEAT_F32MM",167 "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>;168 169let ArchExtKindSpelling = "AEK_F64MM" in170def FeatureMatMulFP64 : ExtensionWithMArch<"f64mm", "MatMulFP64", "FEAT_F64MM",171 "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;172 173//===----------------------------------------------------------------------===//174// Armv8.3 Architecture Extensions175//===----------------------------------------------------------------------===//176 177def FeatureRCPC : ExtensionWithMArch<"rcpc", "RCPC", "FEAT_LRCPC",178 "Enable support for RCPC extension">;179 180def FeaturePAuth : ExtensionWithMArch<"pauth", "PAuth", "FEAT_PAuth",181 "Enable Armv8.3-A Pointer Authentication extension">;182 183let ArchExtKindSpelling = "AEK_JSCVT", UserVisibleName = "jscvt" in184def FeatureJS : ExtensionWithMArch<"jsconv", "JS", "FEAT_JSCVT",185 "Enable Armv8.3-A JavaScript FP conversion instructions",186 [FeatureFPARMv8]>;187 188def FeatureFPAC : Extension<"fpac", "FPAC", "FEAT_FPAC",189 "Enable Armv8.3-A Pointer Authentication Faulting enhancement">;190 191def FeatureCCIDX : Extension<"ccidx", "CCIDX", "FEAT_CCIDX",192 "Enable Armv8.3-A Extend of the CCSIDR number of sets">;193 194let ArchExtKindSpelling = "AEK_FCMA", UserVisibleName = "fcma" in195def FeatureComplxNum : ExtensionWithMArch<"complxnum", "ComplxNum", "FEAT_FCMA",196 "Enable Armv8.3-A Floating-point complex number support",197 [FeatureNEON]>;198 199def FeatureNV : Extension<"nv", "NV", "FEAT_NV, FEAT_NV2",200 "Enable Armv8.4-A Nested Virtualization Enchancement">;201 202//===----------------------------------------------------------------------===//203// Armv8.4 Architecture Extensions204//===----------------------------------------------------------------------===//205 206def FeatureLSE2 : Extension<"lse2", "LSE2", "FEAT_LSE2",207 "Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules">;208 209def FeatureFP16FML : ExtensionWithMArch<"fp16fml", "FP16FML", "FEAT_FHM",210 "Enable FP16 FML instructions", [FeatureFullFP16, FeatureNEON]>;211 212def FeatureDotProd : ExtensionWithMArch<"dotprod", "DotProd", "FEAT_DotProd",213 "Enable dot product support", [FeatureNEON]>;214 215def FeatureMPAM : Extension<"mpam", "MPAM", "FEAT_MPAM",216 "Enable Armv8.4-A Memory system Partitioning and Monitoring extension">;217 218def FeatureDIT : ExtensionWithMArch<"dit", "DIT", "FEAT_DIT",219 "Enable Armv8.4-A Data Independent Timing instructions">;220 221def FeatureTRACEV8_4 : Extension<"tracev8.4", "TRACEV8_4", "FEAT_TRF",222 "Enable Armv8.4-A Trace extension">;223 224def FeatureAM : Extension<"am", "AM", "FEAT_AMUv1",225 "Enable Armv8.4-A Activity Monitors extension">;226 227def FeatureSEL2 : Extension<"sel2", "SEL2", "FEAT_SEL2",228 "Enable Armv8.4-A Secure Exception Level 2 extension">;229 230def FeatureTLB_RMI : Extension<"tlb-rmi", "TLB_RMI",231 "FEAT_TLBIOS, FEAT_TLBIRANGE",232 "Enable Armv8.4-A TLB Range and Maintenance instructions">;233 234def FeatureFlagM : ExtensionWithMArch<"flagm", "FlagM", "FEAT_FlagM",235 "Enable Armv8.4-A Flag Manipulation instructions">;236 237def FeatureRCPC_IMMO : Extension<"rcpc-immo", "RCPC_IMMO", "FEAT_LRCPC2",238 "Enable Armv8.4-A RCPC instructions with Immediate Offsets",239 [FeatureRCPC]>;240 241//===----------------------------------------------------------------------===//242// Armv8.5 Architecture Extensions243//===----------------------------------------------------------------------===//244 245def FeatureAltFPCmp : Extension<"altnzcv", "AlternativeNZCV", "FEAT_FlagM2",246 "Enable alternative NZCV format for floating point comparisons", [FeatureFlagM]>;247 248def FeatureFRInt3264 : Extension<"fptoint", "FRInt3264", "FEAT_FRINTTS",249 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "250 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int",251 [FeatureFPARMv8]>;252 253def FeatureSB : ExtensionWithMArch<"sb", "SB", "FEAT_SB",254 "Enable Armv8.5-A Speculation Barrier">;255 256def FeatureSSBS : ExtensionWithMArch<"ssbs", "SSBS", "FEAT_SSBS, FEAT_SSBS2",257 "Enable Speculative Store Bypass Safe bit">;258 259def FeaturePredRes : ExtensionWithMArch<"predres", "PredRes", "FEAT_SPECRES",260 "Enable Armv8.5-A execution and data prediction invalidation instructions">;261 262def FeatureCacheDeepPersist : Extension<"ccdp", "CCDP", "FEAT_DPB2",263 "Enable Armv8.5-A Cache Clean to Point of Deep Persistence", [FeatureCCPP]>;264 265def FeatureBranchTargetId : ExtensionWithMArch<"bti", "BTI", "FEAT_BTI",266 "Enable Branch Target Identification">;267 268let ArchExtKindSpelling = "AEK_RAND", UserVisibleName = "rng" in269def FeatureRandGen : ExtensionWithMArch<"rand", "RandGen", "FEAT_RNG",270 "Enable Random Number generation instructions">;271 272// NOTE: "memtag" means FEAT_MTE + FEAT_MTE2 for -march or273// __attribute((target(...))), but only FEAT_MTE for FMV.274let UserVisibleName = "memtag" in275def FeatureMTE : ExtensionWithMArch<"mte", "MTE", "FEAT_MTE, FEAT_MTE2",276 "Enable Memory Tagging Extension">;277 278//===----------------------------------------------------------------------===//279// Armv8.6 Architecture Extensions280//===----------------------------------------------------------------------===//281 282def FeatureBF16 : ExtensionWithMArch<"bf16", "BF16", "FEAT_BF16",283 "Enable BFloat16 Extension", [FeatureNEON]>;284 285def FeatureAMVS : Extension<"amvs", "AMVS", "FEAT_AMUv1p1",286 "Enable Armv8.6-A Activity Monitors Virtualization support",287 [FeatureAM]>;288 289def FeatureFineGrainedTraps : Extension<"fgt", "FineGrainedTraps", "FEAT_FGT",290 "Enable fine grained virtualization traps extension">;291 292def FeatureEnhancedCounterVirtualization :293 Extension<"ecv", "EnhancedCounterVirtualization", "FEAT_ECV",294 "Enable enhanced counter virtualization extension">;295 296//===----------------------------------------------------------------------===//297// Armv8.7 Architecture Extensions298//===----------------------------------------------------------------------===//299 300def FeatureXS : Extension<"xs", "XS", "FEAT_XS",301 "Enable Armv8.7-A limited-TLB-maintenance instruction">;302 303def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT", "FEAT_WFxT",304 "Enable Armv8.7-A WFET and WFIT instruction">;305 306def FeatureHCX : Extension<"hcx", "HCX", "FEAT_HCX",307 "Enable Armv8.7-A HCRX_EL2 system register">;308 309def FeatureLS64 : ExtensionWithMArch<"ls64", "LS64",310 "FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA",311 "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;312 313def FeatureSPE_EEF : Extension<"spe-eef", "SPE_EEF", "FEAT_SPEv1p2",314 "Enable extra register in the Statistical Profiling Extension">;315 316//===----------------------------------------------------------------------===//317// Armv8.8 Architecture Extensions318//===----------------------------------------------------------------------===//319 320def FeatureHBC : ExtensionWithMArch<"hbc", "HBC", "FEAT_HBC",321 "Enable Armv8.8-A Hinted Conditional Branches Extension">;322 323def FeatureMOPS : ExtensionWithMArch<"mops", "MOPS", "FEAT_MOPS",324 "Enable Armv8.8-A memcpy and memset acceleration instructions">;325 326def FeatureNMI : Extension<"nmi", "NMI", "FEAT_NMI, FEAT_GICv3_NMI",327 "Enable Armv8.8-A Non-maskable Interrupts">;328 329//===----------------------------------------------------------------------===//330// Armv8.9 Architecture Extensions331//===----------------------------------------------------------------------===//332 333def FeatureRASv2 : ExtensionWithMArch<"rasv2", "RASv2", "FEAT_RASv2",334 "Enable Armv8.9-A Reliability, Availability and Serviceability Extensions",335 [FeatureRAS]>;336 337def FeatureCSSC : ExtensionWithMArch<"cssc", "CSSC", "FEAT_CSSC",338 "Enable Common Short Sequence Compression (CSSC) instructions">;339 340def FeatureCLRBHB : Extension<"clrbhb", "CLRBHB", "FEAT_CLRBHB",341 "Enable Clear BHB instruction">;342 343def FeaturePRFM_SLC : Extension<"prfm-slc-target", "PRFM_SLC", "FEAT_PRFMSLC",344 "Enable SLC target for PRFM instruction">;345 346let UserVisibleName = "predres2" in347def FeatureSPECRES2 : ExtensionWithMArch<"specres2", "SPECRES2", "FEAT_SPECRES2",348 "Enable Speculation Restriction Instruction",349 [FeaturePredRes]>;350 351def FeatureRCPC3 : ExtensionWithMArch<"rcpc3", "RCPC3", "FEAT_LRCPC3",352 "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set",353 [FeatureRCPC_IMMO]>;354 355def FeatureTHE : ExtensionWithMArch<"the", "THE", "FEAT_THE",356 "Enable Armv8.9-A Translation Hardening Extension">;357 358//===----------------------------------------------------------------------===//359// Armv9.0 Architecture Extensions360//===----------------------------------------------------------------------===//361 362def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2", "FEAT_SVE2",363 "Enable Scalable Vector Extension 2 (SVE2) instructions",364 [FeatureSVE]>;365 366def FeatureSVEAES : ExtensionWithMArch<"sve-aes", "SVEAES",367 "FEAT_SVE_AES, FEAT_SVE_PMULL128",368 "Enable SVE AES and quadword SVE polynomial multiply instructions", [FeatureAES]>;369 370def FeatureAliasSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",371 "", "Shorthand for +sve2+sve-aes", [FeatureSVE2, FeatureSVEAES]>;372 373def FeatureSVESM4 : ExtensionWithMArch<"sve-sm4", "SVESM4", "FEAT_SVE_SM4",374 "Enable SVE SM4 instructions", [FeatureSM4]>;375 376def FeatureAliasSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4",377 "", "Shorthand for +sve2+sve-sm4", [FeatureSVE2, FeatureSVESM4]>;378 379def FeatureSVESHA3 : ExtensionWithMArch<"sve-sha3", "SVESHA3", "FEAT_SVE_SHA3",380 "Enable SVE SHA3 instructions", [FeatureSHA3]>;381 382def FeatureAliasSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3",383 "", "Shorthand for +sve2+sve-sha3", [FeatureSVE2, FeatureSVESHA3]>;384 385def FeatureSVEBitPerm : ExtensionWithMArch<"sve-bitperm", "SVEBitPerm",386 "FEAT_SVE_BitPerm", "Enable bit permutation SVE2 instructions">;387 388def FeatureAliasSVE2BitPerm : ExtensionWithMArch<"sve2-bitperm", "SVE2BitPerm",389 "", "Shorthand for +sve2+sve-bitperm", [FeatureSVE2, FeatureSVEBitPerm]>;390 391def FeatureTRBE : Extension<"trbe", "TRBE", "FEAT_TRBE",392 "Enable Trace Buffer Extension">;393 394def FeatureETE : Extension<"ete", "ETE", "FEAT_ETE",395 "Enable Embedded Trace Extension", [FeatureTRBE]>;396 397//===----------------------------------------------------------------------===//398// Armv9.1 Architecture Extensions399//===----------------------------------------------------------------------===//400 401//===----------------------------------------------------------------------===//402// Armv9.2 Architecture Extensions403//===----------------------------------------------------------------------===//404 405def FeatureBRBE : ExtensionWithMArch<"brbe", "BRBE", "FEAT_BRBE",406 "Enable Branch Record Buffer Extension">;407 408def FeatureRME : Extension<"rme", "RME", "FEAT_RME",409 "Enable Realm Management Extension">;410 411def FeatureSME : ExtensionWithMArch<"sme", "SME", "FEAT_SME",412 "Enable Scalable Matrix Extension (SME)", [FeatureBF16, FeatureFullFP16]>;413 414def FeatureSMEF64F64 : ExtensionWithMArch<"sme-f64f64", "SMEF64F64", "FEAT_SME_F64F64",415 "Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>;416 417def FeatureSMEI16I64 : ExtensionWithMArch<"sme-i16i64", "SMEI16I64", "FEAT_SME_I16I64",418 "Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME]>;419 420def FeatureSMEFA64 : ExtensionWithMArch<"sme-fa64", "SMEFA64", "FEAT_SME_FA64",421 "Enable the full A64 instruction set in streaming SVE mode", [FeatureSME, FeatureSVE2]>;422 423//===----------------------------------------------------------------------===//424// Armv9.3 Architecture Extensions425//===----------------------------------------------------------------------===//426 427def FeatureSME2 : ExtensionWithMArch<"sme2", "SME2", "FEAT_SME2",428 "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>;429 430def FeatureMEC : Extension<"mec", "MEC", "FEAT_MEC",431 "Enable Memory Encryption Contexts Extension", [FeatureRME]>;432 433//===----------------------------------------------------------------------===//434// Armv9.4 Architecture Extensions435//===----------------------------------------------------------------------===//436 437def FeatureSVE2p1: ExtensionWithMArch<"sve2p1", "SVE2p1", "FEAT_SVE2p1",438 "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>;439 440def FeatureSVEB16B16: ExtensionWithMArch<"sve-b16b16", "SVEB16B16", "FEAT_SVE_B16B16",441 "Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions">;442 443def FeatureSMEB16B16 : ExtensionWithMArch<"sme-b16b16", "SMEB16B16", "FEAT_SME_B16B16",444 "Enable SME2.1 ZA-targeting non-widening BFloat16 instructions",445 [FeatureSME2, FeatureSVEB16B16]>;446 447def FeatureSMEF16F16 : ExtensionWithMArch<"sme-f16f16", "SMEF16F16", "FEAT_SME_F16F16",448 "Enable SME non-widening Float16 instructions", [FeatureSME2]>;449 450def FeatureSME2p1 : ExtensionWithMArch<"sme2p1", "SME2p1", "FEAT_SME2p1",451 "Enable Scalable Matrix Extension 2.1 instructions", [FeatureSME2]>;452 453def FeatureCHK : Extension<"chk", "CHK", "FEAT_CHK",454 "Enable Armv8.0-A Check Feature Status Extension">;455 456def FeatureGCS : ExtensionWithMArch<"gcs", "GCS", "FEAT_GCS",457 "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>;458 459def FeatureITE : ExtensionWithMArch<"ite", "ITE", "FEAT_ITE",460 "Enable Armv9.4-A Instrumentation Extension", [FeatureETE, FeatureTRBE]>;461 462def FeatureLSE128 : ExtensionWithMArch<"lse128", "LSE128", "FEAT_LSE128",463 "Enable Armv9.4-A 128-bit Atomic instructions",464 [FeatureLSE]>;465 466// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit.467// Therefore group them all under a single feature flag, d128:468def FeatureD128 : ExtensionWithMArch<"d128", "D128",469 "FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128",470 "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers "471 "and instructions",472 [FeatureLSE128]>;473 474//===----------------------------------------------------------------------===//475// Armv9.5 Architecture Extensions476//===----------------------------------------------------------------------===//477 478def FeatureFAMINMAX: ExtensionWithMArch<"faminmax", "FAMINMAX", "FEAT_FAMINMAX",479 "Enable FAMIN and FAMAX instructions", [FeatureNEON]>;480 481def FeatureLUT: ExtensionWithMArch<"lut", "LUT", "FEAT_LUT",482 "Enable Lookup Table instructions", [FeatureNEON]>;483 484def FeatureFP8 : ExtensionWithMArch<"fp8", "FP8", "FEAT_FP8",485 "Enable FP8 instructions", [FeatureNEON]>;486 487def FeatureFP8FMA : ExtensionWithMArch<"fp8fma", "FP8FMA", "FEAT_FP8FMA",488 "Enable Armv9.5-A FP8 multiply-add instructions", [FeatureFP8]>;489 490def FeatureSSVE_FP8FMA : ExtensionWithMArch<"ssve-fp8fma", "SSVE_FP8FMA", "FEAT_SSVE_FP8FMA",491 "Enable SVE2 FP8 multiply-add instructions", [FeatureSME2, FeatureFP8]>;492 493def FeatureFP8DOT4: ExtensionWithMArch<"fp8dot4", "FP8DOT4", "FEAT_FP8DOT4",494 "Enable FP8 4-way dot instructions", [FeatureFP8]>;495 496def FeatureFP8DOT2: ExtensionWithMArch<"fp8dot2", "FP8DOT2", "FEAT_FP8DOT2",497 "Enable FP8 2-way dot instructions", [FeatureFP8]>;498 499def FeatureSSVE_FP8DOT4 : ExtensionWithMArch<"ssve-fp8dot4", "SSVE_FP8DOT4", "FEAT_SSVE_FP8DOT4",500 "Enable SVE2 FP8 4-way dot product instructions", [FeatureSME2, FeatureFP8]>;501 502def FeatureSSVE_FP8DOT2 : ExtensionWithMArch<"ssve-fp8dot2", "SSVE_FP8DOT2", "FEAT_SSVE_FP8DOT2",503 "Enable SVE2 FP8 2-way dot product instructions", [FeatureSME2, FeatureFP8]>;504 505def FeatureSME_LUTv2 : ExtensionWithMArch<"sme-lutv2", "SME_LUTv2", "FEAT_SME_LUTv2",506 "Enable Scalable Matrix Extension (SME) LUTv2 instructions", [FeatureSME2]>;507 508def FeatureSMEF8F32 : ExtensionWithMArch<"sme-f8f32", "SMEF8F32", "FEAT_SME_F8F32",509 "Enable Scalable Matrix Extension (SME) F8F32 instructions", [FeatureSME2, FeatureFP8]>;510 511def FeatureSMEF8F16 : ExtensionWithMArch<"sme-f8f16", "SMEF8F16", "FEAT_SME_F8F16",512 "Enable Scalable Matrix Extension (SME) F8F16 instructions", [FeatureSME2, FeatureFP8]>;513 514def FeatureCPA : ExtensionWithMArch<"cpa", "CPA", "FEAT_CPA",515 "Enable Armv9.5-A Checked Pointer Arithmetic">;516 517def FeaturePAuthLR : ExtensionWithMArch<"pauth-lr", "PAuthLR", "FEAT_PAuth_LR",518 "Enable Armv9.5-A PAC enhancements">;519 520def FeatureTLBIW : ExtensionWithMArch<"tlbiw", "TLBIW", "FEAT_TLBIW",521 "Enable Armv9.5-A TLBI VMALL for Dirty State">;522 523//===----------------------------------------------------------------------===//524// Armv9.6 Architecture Extensions525//===----------------------------------------------------------------------===//526 527def FeatureCMPBR : ExtensionWithMArch<"cmpbr", "CMPBR", "FEAT_CMPBR",528 "Enable Armv9.6-A base compare and branch instructions">;529 530def FeatureF8F32MM: ExtensionWithMArch<"f8f32mm", "F8F32MM", "FEAT_F8F32MM",531 "Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication", [FeatureNEON, FeatureFP8]>;532 533def FeatureF8F16MM: ExtensionWithMArch<"f8f16mm", "F8F16MM", "FEAT_F8F16MM",534 "Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication", [FeatureNEON, FeatureFP8]>;535 536def FeatureFPRCVT: ExtensionWithMArch<"fprcvt", "FPRCVT", "FEAT_FPRCVT",537 "Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of"538 " different input and output sizes", [FeatureFPARMv8]>;539 540def FeatureLSFE : ExtensionWithMArch<"lsfe", "LSFE", "FEAT_LSFE",541 "Enable Armv9.6-A base Atomic floating-point in-memory instructions", [FeatureFPARMv8]>;542 543def FeatureSME2p2: ExtensionWithMArch<"sme2p2", "SME2p2", "FEAT_SME2p2",544 "Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions", [FeatureSME2p1]>;545 546def FeatureSSVE_AES : ExtensionWithMArch<"ssve-aes", "SSVE_AES", "FEAT_SSVE_AES",547 "Enable Armv9.6-A SVE AES support in streaming SVE mode", [FeatureSME2, FeatureSVEAES]>;548 549def FeatureSVE2p2 : ExtensionWithMArch<"sve2p2", "SVE2p2", "FEAT_SVE2p2",550 "Enable Armv9.6-A Scalable Vector Extension 2.2 instructions", [FeatureSVE2p1]>;551 552def FeatureSVEAES2: ExtensionWithMArch<"sve-aes2", "SVE_AES2", "FEAT_SVE_AES2",553 "Enable Armv9.6-A SVE multi-vector AES and multi-vector quadword polynomial multiply instructions">;554 555def FeatureSVEBFSCALE: ExtensionWithMArch<"sve-bfscale", "SVE_BFSCALE", "FEAT_SVE_BFSCALE",556 "Enable Armv9.6-A SVE BFloat16 scaling instructions">;557 558def FeatureSVE_F16F32MM: ExtensionWithMArch<"sve-f16f32mm", "SVE_F16F32MM", "FEAT_SVE_F16F32MM",559 "Enable Armv9.6-A FP16 to FP32 Matrix Multiply instructions", [FeatureSVE]>;560 561def FeatureLSUI: ExtensionWithMArch<"lsui", "LSUI", "FEAT_LSUI",562 "Enable Armv9.6-A unprivileged load/store instructions">;563 564def FeatureOCCMO: ExtensionWithMArch<"occmo", "OCCMO", "FEAT_OCCMO",565 "Enable Armv9.6-A Outer cacheable cache maintenance operations">;566 567def FeaturePCDPHINT: ExtensionWithMArch<"pcdphint", "PCDPHINT", "FEAT_PCDPHINT",568 "Enable Armv9.6-A Producer Consumer Data Placement hints">;569 570def FeaturePoPS: ExtensionWithMArch<"pops", "PoPS", "FEAT_PoPS",571 "Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions">;572 573def FeatureSSVE_BitPerm : ExtensionWithMArch<"ssve-bitperm", "SSVE_BitPerm", "FEAT_SSVE_BitPerm",574 "Enable Armv9.6-A SVE BitPerm support in streaming SVE mode", [FeatureSME2, FeatureSVEBitPerm]>;575 576def FeatureSME_MOP4: ExtensionWithMArch<"sme-mop4", "SME_MOP4", "FEAT_SME_MOP4",577 "Enable SME Quarter-tile outer product instructions", [FeatureSME2]>;578 579def FeatureSME_TMOP: ExtensionWithMArch<"sme-tmop", "SME_TMOP", "FEAT_SME_TMOP",580 "Enable SME Structured sparsity outer product instructions.", [FeatureSME2]>;581 582def FeatureSSVE_FEXPA : ExtensionWithMArch<"ssve-fexpa", "SSVE_FEXPA", "FEAT_SSVE_FEXPA",583 "Enable SVE FEXPA instruction in Streaming SVE mode", [FeatureSME2]>;584 585//===----------------------------------------------------------------------===//586// Armv9.7 Architecture Extensions587//===----------------------------------------------------------------------===//588 589def FeatureCMH : ExtensionWithMArch<"cmh", "CMH", "FEAT_CMH",590 "Enable Armv9.7-A Contention Management Hints">;591 592def FeatureLSCP : ExtensionWithMArch<"lscp", "LSCP", "FEAT_LSCP",593 "Enable Armv9.7-A Load-acquire and store-release pair extension">;594 595def FeatureTLBID: ExtensionWithMArch<"tlbid", "TLBID", "FEAT_TLBID",596 "Enable Armv9.7-A TLBI Domains extension">;597 598def FeatureMPAMv2: ExtensionWithMArch<"mpamv2", "MPAMv2", "FEAT_MPAMv2",599 "Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions">;600 601def FeatureMTETC: ExtensionWithMArch<"mtetc", "MTETC", "FEAT_MTETC",602 "Enable Virtual Memory Tagging Extension">;603 604def FeatureGCIE: ExtensionWithMArch<"gcie", "GCIE", "FEAT_GCIE",605 "Enable GICv5 (Generic Interrupt Controller) CPU Interface Extension">;606 607def FeatureSVE2p3 : ExtensionWithMArch<"sve2p3", "SVE2p3", "FEAT_SVE2p3",608 "Enable Armv9.7-A Scalable Vector Extension 2.3 instructions", [FeatureSVE2p2]>;609 610def FeatureSME2p3 : ExtensionWithMArch<"sme2p3", "SME2p3", "FEAT_SME2p3",611 "Enable Armv9.7-A Scalable Matrix Extension 2.3 instructions", [FeatureSME2p2]>;612 613def FeatureSVE_B16MM : ExtensionWithMArch<"sve-b16mm", "SVE_B16MM", "FEAT_SVE_B16MM",614 "Enable Armv9.7-A SVE non-widening BFloat16 matrix multiply-accumulate", [FeatureSVE]>;615 616def FeatureF16MM : ExtensionWithMArch<"f16mm", "F16MM", "FEAT_F16MM",617 "Enable Armv9.7-A non-widening half-precision matrix multiply-accumulate", [FeatureFullFP16]>;618 619def FeatureF16F32DOT : ExtensionWithMArch<"f16f32dot", "F16F32DOT", "FEAT_F16F32DOT",620 "Enable Armv9.7-A Advanced SIMD half-precision dot product accumulate to single-precision", [FeatureNEON, FeatureFullFP16]>;621 622def FeatureF16F32MM : ExtensionWithMArch<"f16f32mm", "F16F32MM", "FEAT_F16F32MM",623 "Enable Armv9.7-A Advanced SIMD half-precision matrix multiply-accumulate to single-precision", [FeatureNEON, FeatureFullFP16]>;624 625//===----------------------------------------------------------------------===//626// Future Architecture Technologies627//===----------------------------------------------------------------------===//628 629def FeatureMOPS_GO: ExtensionWithMArch<"mops-go", "MOPS_GO", "FEAT_MOPS_GO",630 "Enable memset acceleration granule only">;631 632def FeatureBTIE: ExtensionWithMArch<"btie", "BTIE", "FEAT_BTIE",633 "Enable Enhanced Branch Target Identification extension">;634 635def FeatureS1POE2: ExtensionWithMArch<"poe2", "POE2", "FEAT_S1POE2",636 "Enable Stage 1 Permission Overlays Extension 2 instructions">;637 638def FeatureTEV: ExtensionWithMArch<"tev", "TEV", "FEAT_TEV",639 "Enable TIndex Exception-like Vector instructions">;640 641//===----------------------------------------------------------------------===//642// Other Features643//===----------------------------------------------------------------------===//644 645def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",646 "Enable out of line atomics to support LSE instructions">;647 648def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true",649 "Enable Function Multi Versioning support.">;650 651// This flag is currently still labeled as Experimental, but when fully652// implemented this should tell the compiler to use the zeroing pseudos to653// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive654// lanes are known to be zero. The pseudos will then be expanded using the655// MOVPRFX instruction to zero the inactive lanes. This feature should only be656// enabled if MOVPRFX instructions are known to merge with the destructive657// operations they prefix.658//659// This feature could similarly be extended to support cheap merging of _any_660// value into the inactive lanes using the MOVPRFX instruction that uses661// merging-predication.662def FeatureExperimentalZeroingPseudos663 : SubtargetFeature<"use-experimental-zeroing-pseudos",664 "UseExperimentalZeroingPseudos", "true",665 "Hint to the compiler that the MOVPRFX instruction is "666 "merged with destructive operations",667 []>;668 669def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r",670 "NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">;671 672def FeatureZCRegMoveGPR64 : SubtargetFeature<"zcm-gpr64", "HasZeroCycleRegMoveGPR64", "true",673 "Has zero-cycle register moves for GPR64 registers">;674 675def FeatureZCRegMoveGPR32 : SubtargetFeature<"zcm-gpr32", "HasZeroCycleRegMoveGPR32", "true",676 "Has zero-cycle register moves for GPR32 registers">;677 678def FeatureZCRegMoveFPR128 : SubtargetFeature<"zcm-fpr128", "HasZeroCycleRegMoveFPR128", "true",679 "Has zero-cycle register moves for FPR128 registers">;680 681def FeatureZCRegMoveFPR64 : SubtargetFeature<"zcm-fpr64", "HasZeroCycleRegMoveFPR64", "true",682 "Has zero-cycle register moves for FPR64 registers">;683 684def FeatureZCRegMoveFPR32 : SubtargetFeature<"zcm-fpr32", "HasZeroCycleRegMoveFPR32", "true",685 "Has zero-cycle register moves for FPR32 registers">;686 687def FeatureZCZeroingGPR64 : SubtargetFeature<"zcz-gpr64", "HasZeroCycleZeroingGPR64", "true",688 "Has zero-cycle zeroing instructions for GPR64 registers">;689 690def FeatureZCZeroingGPR32 : SubtargetFeature<"zcz-gpr32", "HasZeroCycleZeroingGPR32", "true",691 "Has zero-cycle zeroing instructions for GPR32 registers">;692 693def FeatureZCZeroingFPR128 : SubtargetFeature<"zcz-fpr128", "HasZeroCycleZeroingFPR128", "true",694 "Has zero-cycle zeroing instructions for FPR128 registers">;695 696// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".697// as movi is more efficient across all cores. Newer cores can eliminate698// fmovs early and there is no difference with movi, but this not true for699// all implementations.700def FeatureNoZCZeroingFPR64 : SubtargetFeature<"no-zcz-fpr64", "HasZeroCycleZeroingFPR64", "false",701 "Has no zero-cycle zeroing instructions for FPR64 registers">;702 703/// ... but the floating-point version doesn't quite work in rare cases on older704/// CPUs.705def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",706 "HasZeroCycleZeroingFPWorkaround", "true",707 "The zero-cycle floating-point zeroing instruction has a bug">;708 709def FeatureStrictAlign : SubtargetFeature<"strict-align",710 "RequiresStrictAlign", "true",711 "Disallow all unaligned memory "712 "access">;713 714def FeatureExecuteOnly : SubtargetFeature<"execute-only",715 "GenExecuteOnly", "true",716 "Enable the generation of "717 "execute only code.">;718 719foreach i = {1-7,9-15,18,20-28} in720 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",721 "Reserve X"#i#", making it unavailable "722 "as a GPR">;723 724def FeatureReserveLRForRA : SubtargetFeature<"reserve-lr-for-ra",725 "ReserveLRForRA", "true",726 "Reserve LR for call use only">;727 728foreach i = {8-15,18} in729 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,730 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;731 732def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",733 "true",734 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;735 736def FeaturePredictableSelectIsExpensive : SubtargetFeature<737 "predictable-select-expensive", "PredictableSelectIsExpensive", "true",738 "Prefer likely predicted branches over selects">;739 740def FeatureEnableSelectOptimize : SubtargetFeature<741 "enable-select-opt", "EnableSelectOptimize", "true",742 "Enable the select optimize pass for select loop heuristics">;743 744def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",745 "HasExynosCheapAsMoveHandling", "true",746 "Use Exynos specific handling of cheap instructions">;747 748def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",749 "UsePostRAScheduler", "true", "Schedule again after register allocation">;750 751def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",752 "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">;753 754def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",755 "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">;756 757def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address",758 "IsStoreAddressAscend", "true",759 "Schedule vector stores by ascending address">;760 761def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow",762 "true", "STR of Q register with register offset is slow">;763 764def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<765 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",766 "true", "Use alternative pattern for sextload convert to f32">;767 768def FeatureArithmeticBccFusion : SubtargetFeature<769 "arith-bcc-fusion", "HasArithmeticBccFusion", "true",770 "CPU fuses arithmetic+bcc operations">;771 772def FeatureArithmeticCbzFusion : SubtargetFeature<773 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",774 "CPU fuses arithmetic + cbz/cbnz operations">;775 776def FeatureCmpBccFusion : SubtargetFeature<777 "cmp-bcc-fusion", "HasCmpBccFusion", "true",778 "CPU fuses cmp+bcc operations">;779 780def FeatureFuseAddress : SubtargetFeature<781 "fuse-address", "HasFuseAddress", "true",782 "CPU fuses address generation and memory operations">;783 784def FeatureFuseAES : SubtargetFeature<785 "fuse-aes", "HasFuseAES", "true",786 "CPU fuses AES crypto operations">;787 788def FeatureFuseArithmeticLogic : SubtargetFeature<789 "fuse-arith-logic", "HasFuseArithmeticLogic", "true",790 "CPU fuses arithmetic and logic operations">;791 792def FeatureFuseCmpCSel : SubtargetFeature<793 "fuse-csel", "HasFuseCmpCSel", "true",794 "CPU can fuse CMP and CSEL operations">;795 796def FeatureFuseCmpCSet : SubtargetFeature<797 "fuse-cset", "HasFuseCmpCSet", "true",798 "CPU can fuse CMP and CSET operations">;799 800def FeatureFuseCryptoEOR : SubtargetFeature<801 "fuse-crypto-eor", "HasFuseCryptoEOR", "true",802 "CPU fuses AES/PMULL and EOR operations">;803 804def FeatureFuseAdrpAdd : SubtargetFeature<805 "fuse-adrp-add", "HasFuseAdrpAdd", "true",806 "CPU fuses adrp+add operations">;807 808def FeatureFuseLiterals : SubtargetFeature<809 "fuse-literals", "HasFuseLiterals", "true",810 "CPU fuses literal generation operations">;811 812def FeatureFuseAddSub2RegAndConstOne : SubtargetFeature<813 "fuse-addsub-2reg-const1", "HasFuseAddSub2RegAndConstOne", "true",814 "CPU fuses (a + b + 1) and (a - b - 1)">;815 816def FeatureDisableLatencySchedHeuristic : SubtargetFeature<817 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",818 "Disable latency scheduling heuristic">;819 820def FeatureStorePairSuppress : SubtargetFeature<821 "store-pair-suppress", "EnableStorePairSuppress", "true",822 "Enable Store Pair Suppression heuristics">;823 824def FeatureForce32BitJumpTables825 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",826 "Force jump table entries to be 32-bits wide except at MinSize">;827 828def FeatureUseRSqrt : SubtargetFeature<829 "use-reciprocal-square-root", "UseRSqrt", "true",830 "Use the reciprocal square root approximation">;831 832def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",833 "NegativeImmediates", "false",834 "Convert immediates and instructions "835 "to their negated or complemented "836 "equivalent when the immediate does "837 "not fit in the encoding.">;838 839// Address operands with shift amount 2 or 3 are fast on all Arm chips except840// some old Apple cores (A7-A10?) which handle all shifts slowly. Cortex-A57841// and derived designs through Cortex-X1 take an extra micro-op for shifts842// of 1 or 4. Other Arm chips handle all shifted operands at the same speed843// as unshifted operands.844//845// We don't try to model the behavior of the old Apple cores because new code846// targeting A7 is very unlikely to actually run on an A7. The Cortex cores847// are modeled by FeatureAddrLSLSlow14.848def FeatureAddrLSLSlow14 : SubtargetFeature<849 "addr-lsl-slow-14", "HasAddrLSLSlow14", "true",850 "Address operands with shift amount of 1 or 4 are slow">;851 852def FeatureALULSLFast : SubtargetFeature<853 "alu-lsl-fast", "HasALULSLFast", "true",854 "Add/Sub operations with lsl shift <= 4 are cheap">;855 856def FeatureAggressiveFMA :857 SubtargetFeature<"aggressive-fma",858 "HasAggressiveFMA",859 "true",860 "Enable Aggressive FMA for floating-point.">;861 862def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",863 "AllowTaggedGlobals",864 "true", "Use an instruction sequence for taking the address of a global "865 "that allows a memory tag in the upper address bits">;866 867def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true",868 "Enable Exception Level 2 Virtual Memory System Architecture">;869 870def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true",871 "Enable Exception Level 3">;872 873def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769",874 "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">;875 876def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",877 "NoBTIAtReturnTwice", "true",878 "Don't place a BTI instruction "879 "after a return-twice">;880 881def FeatureDisableLdp : SubtargetFeature<"disable-ldp", "HasDisableLdp",882 "true", "Do not emit ldp">;883 884def FeatureDisableStp : SubtargetFeature<"disable-stp", "HasDisableStp",885 "true", "Do not emit stp">;886 887def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedOnly",888 "true", "In order to emit ldp, first check if the load will be aligned to 2 * element_size">;889 890def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly",891 "true", "In order to emit stp, first check if the store will be aligned to 2 * element_size">;892 893def FeatureUseFixedOverScalableIfEqualCost : SubtargetFeature<"use-fixed-over-scalable-if-equal-cost",894 "UseFixedOverScalableIfEqualCost", "true",895 "Prefer fixed width loop vectorization over scalable if the cost-model assigns equal costs">;896 897def FeatureDisableMaximizeScalableBandwidth : SubtargetFeature< "disable-maximize-scalable-bandwidth",898 "DisableMaximizeScalableBandwidth", "true",899 "Determine the maximum scalable vector length for a loop by the "900 "largest scalar type rather than the smallest">;901 902// For performance reasons we prefer to use ldapr to ldapur on certain cores.903def FeatureAvoidLDAPUR : SubtargetFeature<"avoid-ldapur", "AvoidLDAPUR", "true",904 "Prefer add+ldapr to offset ldapur">;905 906// Some INC/DEC forms have better latency and throughput than ADDVL.907def FeatureDisableFastIncVL : SubtargetFeature<"disable-fast-inc-vl",908 "HasDisableFastIncVL", "true",909 "Do not prefer INC/DEC, ALL, { 1, 2, 4 } over ADDVL">;910 911// On most processors we want to avoid moving from WZR to vector registers912// (relying on materializing 0 to a FPR and moving from there instead),913// but on some (in-order) cores it's preferable to avoid the extra instruction instead.914def FeatureUseWzrToVecMove : SubtargetFeature<"use-wzr-to-vec-move",915 "UseWzrToVecMove", "true",916 "Move from WZR to insert 0 into vector registers">;917 918//===----------------------------------------------------------------------===//919// Architectures.920//921class Architecture64<922 int major, int minor, string profile,923 string target_feature_name,924 list<SubtargetFeature> implied_features,925 list<Extension> default_extensions926> : SubtargetFeature<target_feature_name,927 "HasV" # major # "_" # minor # profile # "Ops", "true",928 "Support ARM " # target_feature_name # " architecture",929 implied_features930> {931 int Major = major;932 int Minor = minor;933 string Profile = profile;934 935 // Extensions enabled by default. Not the same as implied SubtargetFeatures.936 list<Extension> DefaultExts = default_extensions;937}938 939def HasV8_0aOps : Architecture64<8, 0, "a", "v8a",940 [FeatureEL2VMSA, FeatureEL3],941 [FeatureFPARMv8, FeatureNEON]>;942def HasV8_1aOps : Architecture64<8, 1, "a", "v8.1a",943 [HasV8_0aOps, FeatureCRC, FeatureLSE, FeatureRDM, FeaturePAN, FeatureLOR,944 FeatureVH],945 !listconcat(HasV8_0aOps.DefaultExts, [FeatureCRC, FeatureLSE, FeatureRDM])>;946def HasV8_2aOps : Architecture64<8, 2, "a", "v8.2a",947 [HasV8_1aOps, FeaturePsUAO, FeaturePAN_RWV, FeatureRAS, FeatureCCPP],948 !listconcat(HasV8_1aOps.DefaultExts, [FeatureRAS])>;949def HasV8_3aOps : Architecture64<8, 3, "a", "v8.3a",950 [HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureComplxNum],951 !listconcat(HasV8_2aOps.DefaultExts, [FeatureComplxNum, FeatureJS,952 FeaturePAuth, FeatureRCPC, FeatureCCIDX])>;953def HasV8_4aOps : Architecture64<8, 4, "a", "v8.4a",954 [HasV8_3aOps, FeatureDotProd, FeatureNV, FeatureMPAM, FeatureDIT,955 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, FeatureFlagM,956 FeatureRCPC_IMMO, FeatureLSE2],957 !listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd, FeatureDIT, FeatureFlagM])>;958def HasV8_5aOps : Architecture64<8, 5, "a", "v8.5a",959 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,960 FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,961 FeatureBranchTargetId],962 !listconcat(HasV8_4aOps.DefaultExts, [FeaturePredRes, FeatureSSBS, FeatureBranchTargetId, FeatureSB])>;963def HasV8_6aOps : Architecture64<8, 6, "a", "v8.6a",964 [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,965 FeatureEnhancedCounterVirtualization, FeatureMatMulInt8],966 !listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>;967def HasV8_7aOps : Architecture64<8, 7, "a", "v8.7a",968 [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX],969 !listconcat(HasV8_6aOps.DefaultExts, [FeatureWFxT, FeatureSPE_EEF])>;970def HasV8_8aOps : Architecture64<8, 8, "a", "v8.8a",971 [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI],972 !listconcat(HasV8_7aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;973def HasV8_9aOps : Architecture64<8, 9, "a", "v8.9a",974 [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2,975 FeatureCSSC, FeatureRASv2, FeatureCHK],976 !listconcat(HasV8_8aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC,977 FeatureRASv2])>;978def HasV9_0aOps : Architecture64<9, 0, "a", "v9a",979 [HasV8_5aOps],980 !listconcat(HasV8_5aOps.DefaultExts, [FeatureFullFP16, FeatureSVE,981 FeatureSVE2])>;982def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a",983 [HasV8_6aOps, HasV9_0aOps],984 !listconcat(HasV9_0aOps.DefaultExts, HasV8_6aOps.DefaultExts,985 [FeatureRME])>;986def HasV9_2aOps : Architecture64<9, 2, "a", "v9.2a",987 [HasV8_7aOps, HasV9_1aOps],988 !listconcat(HasV9_1aOps.DefaultExts, HasV8_7aOps.DefaultExts,989 [FeatureMEC])>;990def HasV9_3aOps : Architecture64<9, 3, "a", "v9.3a",991 [HasV8_8aOps, HasV9_2aOps],992 !listconcat(HasV9_2aOps.DefaultExts, HasV8_8aOps.DefaultExts, [])>;993def HasV9_4aOps : Architecture64<9, 4, "a", "v9.4a",994 [HasV8_9aOps, HasV9_3aOps],995 !listconcat(HasV9_3aOps.DefaultExts, HasV8_9aOps.DefaultExts,996 [FeatureSVE2p1])>;997def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a",998 [HasV9_4aOps, FeatureCPA],999 !listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA, FeatureLUT, FeatureFAMINMAX])>;1000def HasV9_6aOps : Architecture64<9, 6, "a", "v9.6a",1001 [HasV9_5aOps, FeatureCMPBR, FeatureLSUI, FeatureOCCMO],1002 !listconcat(HasV9_5aOps.DefaultExts, [FeatureCMPBR,1003 FeatureLSUI, FeatureOCCMO])>;1004def HasV9_7aOps : Architecture64<9, 7, "a", "v9.7a",1005 [HasV9_6aOps, FeatureSVE2p3, FeatureFPRCVT],1006 !listconcat(HasV9_6aOps.DefaultExts, [FeatureSVE2p3, FeatureFPRCVT])>;1007def HasV8_0rOps : Architecture64<8, 0, "r", "v8r",1008 [ //v8.11009 FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2,1010 //v8.21011 FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV,1012 //v8.31013 FeaturePAuth, FeatureRCPC,1014 //v8.41015 FeatureTRACEV8_4, FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2,1016 FeatureRCPC_IMMO,1017 // Not mandatory in v8.0-R, but included here on the grounds that it1018 // only enables names of system registers1019 FeatureSpecRestrict1020 ],1021 // For v8-R, we do not enable crypto and align with GCC that enables a more1022 // minimal set of optional architecture extensions.1023 !listconcat(1024 !listremove(HasV8_5aOps.DefaultExts, [FeatureBranchTargetId, FeaturePredRes]),1025 [FeatureSSBS, FeatureFullFP16, FeatureFP16FML, FeatureSB]1026 )>;1027 1028//===----------------------------------------------------------------------===//1029// Access to privileged registers1030//===----------------------------------------------------------------------===//1031 1032foreach i = 1-3 in1033def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",1034 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">;1035def FeatureUseROEL0ForTP : SubtargetFeature<"tpidrro-el0", "UseROEL0ForTP",1036 "true", "Permit use of TPIDRRO_EL0 for the TLS base">;1037 1038//===----------------------------------------------------------------------===//1039// Control codegen mitigation against Straight Line Speculation vulnerability.1040//===----------------------------------------------------------------------===//1041 1042def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",1043 "HardenSlsRetBr", "true",1044 "Harden against straight line speculation across RET and BR instructions">;1045def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",1046 "HardenSlsBlr", "true",1047 "Harden against straight line speculation across BLR instructions">;1048def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat",1049 "HardenSlsNoComdat", "true",1050 "Generate thunk code for SLS mitigation in the normal text section">;1051 1052 1053// Only intended to be used by disassemblers.1054def FeatureAll1055 : SubtargetFeature<"all", "IsAll", "true", "Enable all instructions">;1056