542 lines · plain
1//=----- AArch64InstrGISel.td - AArch64 GISel target pseudos -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// AArch64 GlobalISel target pseudo instruction definitions. This is kept10// separately from the other tablegen files for organizational purposes, but11// share the same infrastructure.12//13//===----------------------------------------------------------------------===//14 15 16class AArch64GenericInstruction : GenericInstruction {17 let Namespace = "AArch64";18}19 20// A pseudo to represent a relocatable add instruction as part of address21// computation.22def G_ADD_LOW : AArch64GenericInstruction {23 let OutOperandList = (outs type0:$dst);24 let InOperandList = (ins type1:$src, type2:$imm);25 let hasSideEffects = 0;26}27 28// Pseudo for a rev16 instruction. Produced post-legalization from29// G_SHUFFLE_VECTORs with appropriate masks.30def G_REV16 : AArch64GenericInstruction {31 let OutOperandList = (outs type0:$dst);32 let InOperandList = (ins type0:$src);33 let hasSideEffects = 0;34}35 36// Pseudo for a rev32 instruction. Produced post-legalization from37// G_SHUFFLE_VECTORs with appropriate masks.38def G_REV32 : AArch64GenericInstruction {39 let OutOperandList = (outs type0:$dst);40 let InOperandList = (ins type0:$src);41 let hasSideEffects = 0;42}43 44// Pseudo for a rev64 instruction. Produced post-legalization from45// G_SHUFFLE_VECTORs with appropriate masks.46def G_REV64 : AArch64GenericInstruction {47 let OutOperandList = (outs type0:$dst);48 let InOperandList = (ins type0:$src);49 let hasSideEffects = 0;50}51 52// Represents an uzp1 instruction. Produced post-legalization from53// G_SHUFFLE_VECTORs with appropriate masks.54def G_UZP1 : AArch64GenericInstruction {55 let OutOperandList = (outs type0:$dst);56 let InOperandList = (ins type0:$v1, type0:$v2);57 let hasSideEffects = 0;58}59 60// Represents an uzp2 instruction. Produced post-legalization from61// G_SHUFFLE_VECTORs with appropriate masks.62def G_UZP2 : AArch64GenericInstruction {63 let OutOperandList = (outs type0:$dst);64 let InOperandList = (ins type0:$v1, type0:$v2);65 let hasSideEffects = 0;66}67 68// Represents a zip1 instruction. Produced post-legalization from69// G_SHUFFLE_VECTORs with appropriate masks.70def G_ZIP1 : AArch64GenericInstruction {71 let OutOperandList = (outs type0:$dst);72 let InOperandList = (ins type0:$v1, type0:$v2);73 let hasSideEffects = 0;74}75 76// Represents a zip2 instruction. Produced post-legalization from77// G_SHUFFLE_VECTORs with appropriate masks.78def G_ZIP2 : AArch64GenericInstruction {79 let OutOperandList = (outs type0:$dst);80 let InOperandList = (ins type0:$v1, type0:$v2);81 let hasSideEffects = 0;82}83 84// Represents a dup instruction. Produced post-legalization from85// G_SHUFFLE_VECTORs with appropriate masks.86def G_DUP: AArch64GenericInstruction {87 let OutOperandList = (outs type0:$dst);88 let InOperandList = (ins type1:$lane);89 let hasSideEffects = 0;90}91 92// Represents a lane duplicate operation.93def G_DUPLANE8 : AArch64GenericInstruction {94 let OutOperandList = (outs type0:$dst);95 let InOperandList = (ins type0:$src, type1:$lane);96 let hasSideEffects = 0;97}98def G_DUPLANE16 : AArch64GenericInstruction {99 let OutOperandList = (outs type0:$dst);100 let InOperandList = (ins type0:$src, type1:$lane);101 let hasSideEffects = 0;102}103def G_DUPLANE32 : AArch64GenericInstruction {104 let OutOperandList = (outs type0:$dst);105 let InOperandList = (ins type0:$src, type1:$lane);106 let hasSideEffects = 0;107}108def G_DUPLANE64 : AArch64GenericInstruction {109 let OutOperandList = (outs type0:$dst);110 let InOperandList = (ins type0:$src, type1:$lane);111 let hasSideEffects = 0;112}113 114// Represents a trn1 instruction. Produced post-legalization from115// G_SHUFFLE_VECTORs with appropriate masks.116def G_TRN1 : AArch64GenericInstruction {117 let OutOperandList = (outs type0:$dst);118 let InOperandList = (ins type0:$v1, type0:$v2);119 let hasSideEffects = 0;120}121 122// Represents a trn2 instruction. Produced post-legalization from123// G_SHUFFLE_VECTORs with appropriate masks.124def G_TRN2 : AArch64GenericInstruction {125 let OutOperandList = (outs type0:$dst);126 let InOperandList = (ins type0:$v1, type0:$v2);127 let hasSideEffects = 0;128}129 130// Represents an ext instruction. Produced post-legalization from131// G_SHUFFLE_VECTORs with appropriate masks.132def G_EXT: AArch64GenericInstruction {133 let OutOperandList = (outs type0:$dst);134 let InOperandList = (ins type0:$v1, type0:$v2, untyped_imm_0:$imm);135 let hasSideEffects = 0;136}137 138// Represents a vector G_ASHR with an immediate.139def G_VASHR : AArch64GenericInstruction {140 let OutOperandList = (outs type0:$dst);141 let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);142 let hasSideEffects = 0;143}144 145// Represents a vector G_LSHR with an immediate.146def G_VLSHR : AArch64GenericInstruction {147 let OutOperandList = (outs type0:$dst);148 let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);149 let hasSideEffects = 0;150}151 152// Float truncation using round to odd153def G_FPTRUNC_ODD : AArch64GenericInstruction {154 let OutOperandList = (outs type0:$dst);155 let InOperandList = (ins type1:$src);156 let hasSideEffects = false;157}158 159// Represents an integer to FP conversion on the FPR bank.160def G_SITOF : AArch64GenericInstruction {161 let OutOperandList = (outs type0:$dst);162 let InOperandList = (ins type0:$src);163 let hasSideEffects = 0;164}165def G_UITOF : AArch64GenericInstruction {166 let OutOperandList = (outs type0:$dst);167 let InOperandList = (ins type0:$src);168 let hasSideEffects = 0;169}170 171def G_FCMEQ : AArch64GenericInstruction {172 let OutOperandList = (outs type0:$dst);173 let InOperandList = (ins type0:$src1, type1:$src2);174 let hasSideEffects = 0;175}176 177def G_FCMGE : AArch64GenericInstruction {178 let OutOperandList = (outs type0:$dst);179 let InOperandList = (ins type0:$src1, type1:$src2);180 let hasSideEffects = 0;181}182 183def G_FCMGT : AArch64GenericInstruction {184 let OutOperandList = (outs type0:$dst);185 let InOperandList = (ins type0:$src1, type1:$src2);186 let hasSideEffects = 0;187}188 189def G_AARCH64_PREFETCH : AArch64GenericInstruction {190 let OutOperandList = (outs);191 let InOperandList = (ins type0:$imm, ptype0:$src1);192 let hasSideEffects = 1;193}194 195def G_UMULL : AArch64GenericInstruction {196 let OutOperandList = (outs type0:$dst);197 let InOperandList = (ins type0:$src1, type0:$src2);198 let hasSideEffects = 0;199}200 201def G_SMULL : AArch64GenericInstruction {202 let OutOperandList = (outs type0:$dst);203 let InOperandList = (ins type0:$src1, type0:$src2);204 let hasSideEffects = 0;205}206 207def G_PMULL : AArch64GenericInstruction {208 let OutOperandList = (outs type0:$dst);209 let InOperandList = (ins type1:$src1, type1:$src2);210 let hasSideEffects = 0;211}212 213def G_UADDLP : AArch64GenericInstruction {214 let OutOperandList = (outs type0:$dst);215 let InOperandList = (ins type0:$src1);216 let hasSideEffects = 0;217}218 219def G_SADDLP : AArch64GenericInstruction {220 let OutOperandList = (outs type0:$dst);221 let InOperandList = (ins type0:$src1);222 let hasSideEffects = 0;223}224 225def G_UADDLV : AArch64GenericInstruction {226 let OutOperandList = (outs type0:$dst);227 let InOperandList = (ins type0:$src1);228 let hasSideEffects = 0;229}230 231def G_SADDLV : AArch64GenericInstruction {232 let OutOperandList = (outs type0:$dst);233 let InOperandList = (ins type0:$src1);234 let hasSideEffects = 0;235}236 237def G_UDOT : AArch64GenericInstruction {238 let OutOperandList = (outs type0:$dst);239 let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);240 let hasSideEffects = 0;241}242 243def G_SDOT : AArch64GenericInstruction {244 let OutOperandList = (outs type0:$dst);245 let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);246 let hasSideEffects = 0;247}248 249def G_USDOT : AArch64GenericInstruction {250 let OutOperandList = (outs type0:$dst);251 let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);252 let hasSideEffects = 0;253}254 255// Generic instruction for the BSP pseudo. It is expanded into BSP, which256// expands into BSL/BIT/BIF after register allocation.257def G_BSP : AArch64GenericInstruction {258 let OutOperandList = (outs type0:$dst);259 let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);260 let hasSideEffects = 0;261}262 263def : GINodeEquiv<G_REV16, AArch64rev16>;264def : GINodeEquiv<G_REV32, AArch64rev32>;265def : GINodeEquiv<G_REV64, AArch64rev64>;266def : GINodeEquiv<G_UZP1, AArch64uzp1>;267def : GINodeEquiv<G_UZP2, AArch64uzp2>;268def : GINodeEquiv<G_ZIP1, AArch64zip1>;269def : GINodeEquiv<G_ZIP2, AArch64zip2>;270def : GINodeEquiv<G_DUP, AArch64dup>;271def : GINodeEquiv<G_DUPLANE8, AArch64duplane8>;272def : GINodeEquiv<G_DUPLANE16, AArch64duplane16>;273def : GINodeEquiv<G_DUPLANE32, AArch64duplane32>;274def : GINodeEquiv<G_DUPLANE64, AArch64duplane64>;275def : GINodeEquiv<G_TRN1, AArch64trn1>;276def : GINodeEquiv<G_TRN2, AArch64trn2>;277def : GINodeEquiv<G_EXT, AArch64ext>;278def : GINodeEquiv<G_VASHR, AArch64vashr>;279def : GINodeEquiv<G_VLSHR, AArch64vlshr>;280def : GINodeEquiv<G_SITOF, AArch64sitof>;281def : GINodeEquiv<G_UITOF, AArch64uitof>;282 283def : GINodeEquiv<G_FCMEQ, AArch64fcmeq>;284def : GINodeEquiv<G_FCMGE, AArch64fcmge>;285def : GINodeEquiv<G_FCMGT, AArch64fcmgt>;286 287def : GINodeEquiv<G_BSP, AArch64bsp>;288 289def : GINodeEquiv<G_PMULL, AArch64pmull>;290def : GINodeEquiv<G_UMULL, AArch64umull>;291def : GINodeEquiv<G_SMULL, AArch64smull>;292 293def : GINodeEquiv<G_SADDLP, AArch64saddlp_n>;294def : GINodeEquiv<G_UADDLP, AArch64uaddlp_n>;295 296def : GINodeEquiv<G_SADDLV, AArch64saddlv>;297def : GINodeEquiv<G_UADDLV, AArch64uaddlv>;298 299def : GINodeEquiv<G_UDOT, AArch64udot>;300def : GINodeEquiv<G_SDOT, AArch64sdot>;301def : GINodeEquiv<G_USDOT, AArch64usdot>;302 303def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;304 305def : GINodeEquiv<G_AARCH64_PREFETCH, AArch64Prefetch>;306 307def : GINodeEquiv<G_FPTRUNC_ODD, AArch64fcvtxn_n>;308 309// These are patterns that we only use for GlobalISel via the importer.310def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),311 (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),312 (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;313 314let Predicates = [HasNoLSE] in {315def : Pat<(atomic_cmp_swap_i8 GPR64:$addr, GPR32:$desired, GPR32:$new),316 (CMP_SWAP_8 GPR64:$addr, GPR32:$desired, GPR32:$new)>;317 318def : Pat<(atomic_cmp_swap_i16 GPR64:$addr, GPR32:$desired, GPR32:$new),319 (CMP_SWAP_16 GPR64:$addr, GPR32:$desired, GPR32:$new)>;320 321def : Pat<(atomic_cmp_swap_i32 GPR64:$addr, GPR32:$desired, GPR32:$new),322 (CMP_SWAP_32 GPR64:$addr, GPR32:$desired, GPR32:$new)>;323 324def : Pat<(atomic_cmp_swap_i64 GPR64:$addr, GPR64:$desired, GPR64:$new),325 (CMP_SWAP_64 GPR64:$addr, GPR64:$desired, GPR64:$new)>;326}327 328def : Pat<(int_aarch64_stlxp GPR64:$lo, GPR64:$hi, GPR64:$addr),329 (STLXPX GPR64:$lo, GPR64:$hi, GPR64:$addr)>;330def : Pat<(int_aarch64_stxp GPR64:$lo, GPR64:$hi, GPR64:$addr),331 (STXPX GPR64:$lo, GPR64:$hi, GPR64:$addr)>;332 333let GIIgnoreCopies = 1 in334class PatIgnoreCopies<dag pattern, dag result> : Pat<pattern, result>, GISelFlags;335 336multiclass SIMDAcrossLanesSignedIntrinsicBHS<string baseOpc, Intrinsic intOp> {337 def : PatIgnoreCopies<(i32 (sext (i8 (intOp (v8i8 V64:$Rn))))),338 (i32 (SMOVvi8to32339 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),340 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),341 (i64 0)))>;342 def : Pat<(i8 (intOp (v8i8 V64:$Rn))),343 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn)>;344 345 def : PatIgnoreCopies<(i32 (sext (i8 (intOp (v16i8 V128:$Rn))))),346 (i32 (SMOVvi8to32347 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),348 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),349 (i64 0)))>;350 def : Pat<(i8 (intOp (v16i8 V128:$Rn))),351 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn)>;352 353 def : PatIgnoreCopies<(i32 (sext (i16 (intOp (v4i16 V64:$Rn))))),354 (i32 (SMOVvi16to32355 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),356 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),357 (i64 0)))>;358 def : Pat<(i16 (intOp (v4i16 V64:$Rn))),359 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn)>;360 361 def : PatIgnoreCopies<(i32 (sext (i16 (intOp (v8i16 V128:$Rn))))),362 (i32 (SMOVvi16to32363 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),364 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),365 (i64 0)))>;366 def : Pat<(i16 (intOp (v8i16 V128:$Rn))),367 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn)>;368 369 def : PatIgnoreCopies<(i32 (intOp (v4i32 V128:$Rn))),370 (i32 (EXTRACT_SUBREG371 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),372 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),373 ssub))>;374}375 376multiclass SIMDAcrossLanesUnsignedIntrinsicBHS<string baseOpc,377 Intrinsic intOp> {378 def : PatIgnoreCopies<(i32 (zext (i8 (intOp (v8i8 V64:$Rn))))),379 (COPY_TO_REGCLASS380 (i32 (EXTRACT_SUBREG381 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),382 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),383 ssub)),384 GPR32)>;385 def : Pat<(i8 (intOp (v8i8 V64:$Rn))),386 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn)>;387 388 def : PatIgnoreCopies<(i32 (zext (i8 (intOp (v16i8 V128:$Rn))))),389 (COPY_TO_REGCLASS390 (i32 (EXTRACT_SUBREG391 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),392 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),393 ssub)),394 GPR32)>;395 def : Pat<(i8 (intOp (v16i8 V128:$Rn))),396 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn)>;397 398 399 def : PatIgnoreCopies<(i32 (zext (i16 (intOp (v4i16 V64:$Rn))))),400 (COPY_TO_REGCLASS401 (i32 (EXTRACT_SUBREG402 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),403 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),404 ssub)),405 GPR32)>;406 def : Pat<(i16 (intOp (v4i16 V64:$Rn))),407 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn)>;408 409 def : PatIgnoreCopies<(i32 (zext (i16 (intOp (v8i16 V128:$Rn))))),410 (COPY_TO_REGCLASS411 (i32 (EXTRACT_SUBREG412 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),413 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),414 ssub)),415 GPR32)>;416 def : Pat<(i16 (intOp (v8i16 V128:$Rn))),417 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn)>;418 419 def : PatIgnoreCopies<(i32 (intOp (v4i32 V128:$Rn))),420 (i32 (EXTRACT_SUBREG421 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),422 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),423 ssub))>;424}425 426 427defm : SIMDAcrossLanesSignedIntrinsicBHS<"ADDV", int_aarch64_neon_saddv>;428// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm429def : Pat<(i32 (int_aarch64_neon_saddv (v2i32 V64:$Rn))),430 (i32 (EXTRACT_SUBREG431 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),432 (ADDPv2i32 V64:$Rn, V64:$Rn), dsub),433 ssub))>;434 435def : Pat<(i64 (int_aarch64_neon_saddv (v2i64 V128:$Rn))),436 (i64 (EXTRACT_SUBREG437 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),438 (ADDPv2i64p V128:$Rn), dsub),439 dsub))>;440 441defm : SIMDAcrossLanesUnsignedIntrinsicBHS<"ADDV", int_aarch64_neon_uaddv>;442def : Pat<(i32 (int_aarch64_neon_uaddv (v2i32 V64:$Rn))),443 (i32 (EXTRACT_SUBREG444 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),445 (ADDPv2i32 V64:$Rn, V64:$Rn), dsub),446 ssub))>;447def : Pat<(i64 (int_aarch64_neon_uaddv (v2i64 V128:$Rn))),448 (i64 (EXTRACT_SUBREG449 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),450 (ADDPv2i64p V128:$Rn), dsub),451 dsub))>;452 453defm : SIMDAcrossLanesSignedIntrinsicBHS<"SMAXV", int_aarch64_neon_smaxv>;454def : Pat<(i32 (int_aarch64_neon_smaxv (v2i32 V64:$Rn))),455 (i32 (EXTRACT_SUBREG456 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),457 (SMAXPv2i32 V64:$Rn, V64:$Rn), dsub),458 ssub))>;459 460defm : SIMDAcrossLanesSignedIntrinsicBHS<"SMINV", int_aarch64_neon_sminv>;461def : Pat<(i32 (int_aarch64_neon_sminv (v2i32 V64:$Rn))),462 (i32 (EXTRACT_SUBREG463 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),464 (SMINPv2i32 V64:$Rn, V64:$Rn), dsub),465 ssub))>;466 467defm : SIMDAcrossLanesUnsignedIntrinsicBHS<"UMAXV", int_aarch64_neon_umaxv>;468def : Pat<(i32 (int_aarch64_neon_umaxv (v2i32 V64:$Rn))),469 (i32 (EXTRACT_SUBREG470 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),471 (UMAXPv2i32 V64:$Rn, V64:$Rn), dsub),472 ssub))>;473 474defm : SIMDAcrossLanesUnsignedIntrinsicBHS<"UMINV", int_aarch64_neon_uminv>;475def : Pat<(i32 (int_aarch64_neon_uminv (v2i32 V64:$Rn))),476 (i32 (EXTRACT_SUBREG477 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),478 (UMINPv2i32 V64:$Rn, V64:$Rn), dsub),479 ssub))>;480 481// Match stores from lane 0 to the appropriate subreg's store.482multiclass VecStoreLane64_0Pat<ComplexPattern UIAddrMode, SDPatternOperator storeop,483 ValueType VTy, ValueType STy,484 SubRegIndex SubRegIdx, Operand IndexType,485 Instruction STR> {486 def : Pat<(storeop (STy (vector_extract (VTy VecListOne64:$Vt), (i64 0))),487 (UIAddrMode GPR64sp:$Rn, IndexType:$offset)),488 (STR (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),489 GPR64sp:$Rn, IndexType:$offset)>;490}491multiclass VecStoreULane64_0Pat<SDPatternOperator StoreOp,492 ValueType VTy, ValueType STy,493 SubRegIndex SubRegIdx, Instruction STR> {494 defm : VecStoreLane64_0Pat<am_unscaled64, StoreOp, VTy, STy, SubRegIdx, simm9, STR>;495}496 497multiclass VecROStoreLane64_0Pat<ROAddrMode ro, SDPatternOperator storeop,498 ValueType VecTy, ValueType STy,499 SubRegIndex SubRegIdx,500 Instruction STRW, Instruction STRX> {501 502 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne64:$Vt), (i64 0))),503 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),504 (STRW (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),505 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;506 507 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne64:$Vt), (i64 0))),508 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),509 (STRX (EXTRACT_SUBREG VecListOne64:$Vt, SubRegIdx),510 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;511}512 513let AddedComplexity = 19 in {514 def : St1Lane128Pat<store, VectorIndexB, v16i8, i8, ST1i8>;515 def : St1Lane64Pat<store, VectorIndexB, v8i8, i8, ST1i8>;516 517 defm : VecStoreLane64_0Pat<am_indexed16, store, v4i16, i16, hsub, uimm12s2, STRHui>;518 defm : VecStoreLane64_0Pat<am_indexed32, store, v2i32, i32, ssub, uimm12s4, STRSui>;519 520 defm : VecStoreULane64_0Pat<store, v4i16, i16, hsub, STURHi>;521 defm : VecStoreULane64_0Pat<store, v2i32, i32, ssub, STURSi>;522 defm : VecROStoreLane64_0Pat<ro16, store, v4i16, i16, hsub, STRHroW, STRHroX>;523 defm : VecROStoreLane64_0Pat<ro32, store, v2i32, i32, ssub, STRSroW, STRSroX>;524}525 526def : Pat<(v8i8 (AArch64dup (i8 (load GPR64sp:$Rn)))),527 (LD1Rv8b GPR64sp:$Rn)>;528def : Pat<(v16i8 (AArch64dup (i8 (load GPR64sp:$Rn)))),529 (LD1Rv16b GPR64sp:$Rn)>;530def : Pat<(v4i16 (AArch64dup (i16 (load GPR64sp:$Rn)))),531 (LD1Rv4h GPR64sp:$Rn)>;532def : Pat<(v8i16 (AArch64dup (i16 (load GPR64sp:$Rn)))),533 (LD1Rv8h GPR64sp:$Rn)>;534def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),535 (LD1Rv2s GPR64sp:$Rn)>;536def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),537 (LD1Rv4s GPR64sp:$Rn)>;538def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),539 (LD1Rv2d GPR64sp:$Rn)>;540def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),541 (LD1Rv1d GPR64sp:$Rn)>;542