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1//=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// AArch64 Instruction definitions.10//11//===----------------------------------------------------------------------===//12 13 14//===----------------------------------------------------------------------===//15// ARM Instruction Predicate Definitions.16//17 18class AssemblerPredicateWithAll<dag cond, string name="">19 : AssemblerPredicate<(any_of FeatureAll, cond), name>;20 21def HasV8_0a : Predicate<"Subtarget->hasV8_0aOps()">,22 AssemblerPredicate<(all_of HasV8_0aOps), "armv8.0a">;23def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,24 AssemblerPredicateWithAll<(all_of HasV8_1aOps), "armv8.1a">;25def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,26 AssemblerPredicateWithAll<(all_of HasV8_2aOps), "armv8.2a">;27def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">,28 AssemblerPredicateWithAll<(all_of HasV8_3aOps), "armv8.3a">;29def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">,30 AssemblerPredicateWithAll<(all_of HasV8_4aOps), "armv8.4a">;31def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">,32 AssemblerPredicateWithAll<(all_of HasV8_5aOps), "armv8.5a">;33def HasV8_6a : Predicate<"Subtarget->hasV8_6aOps()">,34 AssemblerPredicateWithAll<(all_of HasV8_6aOps), "armv8.6a">;35def HasV8_7a : Predicate<"Subtarget->hasV8_7aOps()">,36 AssemblerPredicateWithAll<(all_of HasV8_7aOps), "armv8.7a">;37def HasV8_8a : Predicate<"Subtarget->hasV8_8aOps()">,38 AssemblerPredicateWithAll<(all_of HasV8_8aOps), "armv8.8a">;39def HasV8_9a : Predicate<"Subtarget->hasV8_9aOps()">,40 AssemblerPredicateWithAll<(all_of HasV8_9aOps), "armv8.9a">;41def HasV9_0a : Predicate<"Subtarget->hasV9_0aOps()">,42 AssemblerPredicateWithAll<(all_of HasV9_0aOps), "armv9-a">;43def HasV9_1a : Predicate<"Subtarget->hasV9_1aOps()">,44 AssemblerPredicateWithAll<(all_of HasV9_1aOps), "armv9.1a">;45def HasV9_2a : Predicate<"Subtarget->hasV9_2aOps()">,46 AssemblerPredicateWithAll<(all_of HasV9_2aOps), "armv9.2a">;47def HasV9_3a : Predicate<"Subtarget->hasV9_3aOps()">,48 AssemblerPredicateWithAll<(all_of HasV9_3aOps), "armv9.3a">;49def HasV9_4a : Predicate<"Subtarget->hasV9_4aOps()">,50 AssemblerPredicateWithAll<(all_of HasV9_4aOps), "armv9.4a">;51def HasV8_0r : Predicate<"Subtarget->hasV8_0rOps()">,52 AssemblerPredicateWithAll<(all_of HasV8_0rOps), "armv8-r">;53def HasEL2VMSA : Predicate<"Subtarget->hasEL2VMSA()">,54 AssemblerPredicateWithAll<(all_of FeatureEL2VMSA), "el2vmsa">;55def HasEL3 : Predicate<"Subtarget->hasEL3()">,56 AssemblerPredicateWithAll<(all_of FeatureEL3), "el3">;57def HasVH : Predicate<"Subtarget->hasVH()">,58 AssemblerPredicateWithAll<(all_of FeatureVH), "vh">;59def HasLOR : Predicate<"Subtarget->hasLOR()">,60 AssemblerPredicateWithAll<(all_of FeatureLOR), "lor">;61def HasPAuth : Predicate<"Subtarget->hasPAuth()">,62 AssemblerPredicateWithAll<(all_of FeaturePAuth), "pauth">;63def HasPAuthLR : Predicate<"Subtarget->hasPAuthLR()">,64 AssemblerPredicateWithAll<(all_of FeaturePAuthLR), "pauth-lr">;65def HasJS : Predicate<"Subtarget->hasJS()">,66 AssemblerPredicateWithAll<(all_of FeatureJS), "jsconv">;67def HasCCIDX : Predicate<"Subtarget->hasCCIDX()">,68 AssemblerPredicateWithAll<(all_of FeatureCCIDX), "ccidx">;69def HasComplxNum : Predicate<"Subtarget->hasComplxNum()">,70 AssemblerPredicateWithAll<(all_of FeatureComplxNum), "complxnum">;71def HasNV : Predicate<"Subtarget->hasNV()">,72 AssemblerPredicateWithAll<(all_of FeatureNV), "nv">;73def HasMPAM : Predicate<"Subtarget->hasMPAM()">,74 AssemblerPredicateWithAll<(all_of FeatureMPAM), "mpam">;75def HasDIT : Predicate<"Subtarget->hasDIT()">,76 AssemblerPredicateWithAll<(all_of FeatureDIT), "dit">;77def HasTRACEV8_4 : Predicate<"Subtarget->hasTRACEV8_4()">,78 AssemblerPredicateWithAll<(all_of FeatureTRACEV8_4), "tracev8.4">;79def HasAM : Predicate<"Subtarget->hasAM()">,80 AssemblerPredicateWithAll<(all_of FeatureAM), "am">;81def HasSEL2 : Predicate<"Subtarget->hasSEL2()">,82 AssemblerPredicateWithAll<(all_of FeatureSEL2), "sel2">;83def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">,84 AssemblerPredicateWithAll<(all_of FeatureTLB_RMI), "tlb-rmi">;85def HasFlagM : Predicate<"Subtarget->hasFlagM()">,86 AssemblerPredicateWithAll<(all_of FeatureFlagM), "flagm">;87def HasRCPC_IMMO : Predicate<"Subtarget->hasRCPC_IMMO()">,88 AssemblerPredicateWithAll<(all_of FeatureRCPC_IMMO), "rcpc-immo">;89def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,90 AssemblerPredicateWithAll<(all_of FeatureFPARMv8), "fp-armv8">;91def HasNEON : Predicate<"Subtarget->isNeonAvailable()">,92 AssemblerPredicateWithAll<(all_of FeatureNEON), "neon">;93def HasSM4 : Predicate<"Subtarget->hasSM4()">,94 AssemblerPredicateWithAll<(all_of FeatureSM4), "sm4">;95def HasSHA3 : Predicate<"Subtarget->hasSHA3()">,96 AssemblerPredicateWithAll<(all_of FeatureSHA3), "sha3">;97def HasSHA2 : Predicate<"Subtarget->hasSHA2()">,98 AssemblerPredicateWithAll<(all_of FeatureSHA2), "sha2">;99def HasAES : Predicate<"Subtarget->hasAES()">,100 AssemblerPredicateWithAll<(all_of FeatureAES), "aes">;101def HasDotProd : Predicate<"Subtarget->hasDotProd()">,102 AssemblerPredicateWithAll<(all_of FeatureDotProd), "dotprod">;103def HasCRC : Predicate<"Subtarget->hasCRC()">,104 AssemblerPredicateWithAll<(all_of FeatureCRC), "crc">;105def HasCSSC : Predicate<"Subtarget->hasCSSC()">,106 AssemblerPredicateWithAll<(all_of FeatureCSSC), "cssc">;107def HasNoCSSC : Predicate<"!Subtarget->hasCSSC()">;108def HasLSE : Predicate<"Subtarget->hasLSE()">,109 AssemblerPredicateWithAll<(all_of FeatureLSE), "lse">;110def HasNoLSE : Predicate<"!Subtarget->hasLSE()">;111def HasRAS : Predicate<"Subtarget->hasRAS()">,112 AssemblerPredicateWithAll<(all_of FeatureRAS), "ras">;113def HasRDM : Predicate<"Subtarget->hasRDM()">,114 AssemblerPredicateWithAll<(all_of FeatureRDM), "rdm">;115def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,116 AssemblerPredicateWithAll<(all_of FeatureFullFP16), "fullfp16">;117def HasNoFullFP16 : Predicate<"!Subtarget->hasFullFP16()">;118def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">,119 AssemblerPredicateWithAll<(all_of FeatureFP16FML), "fp16fml">;120def HasSPE : Predicate<"Subtarget->hasSPE()">,121 AssemblerPredicateWithAll<(all_of FeatureSPE), "spe">;122def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">,123 AssemblerPredicateWithAll<(all_of FeatureFuseAES),124 "fuse-aes">;125def HasSVE : Predicate<"Subtarget->isSVEAvailable()">,126 AssemblerPredicateWithAll<(all_of FeatureSVE), "sve">;127def HasSVEB16B16 : Predicate<"Subtarget->hasSVEB16B16()">,128 AssemblerPredicateWithAll<(all_of FeatureSVEB16B16), "sve-b16b16">;129def HasSVE2 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2()">,130 AssemblerPredicateWithAll<(all_of FeatureSVE2), "sve2">;131def HasSVE2p1 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2p1()">,132 AssemblerPredicateWithAll<(all_of FeatureSVE2p1), "sve2p1">;133def HasSVEAES : Predicate<"Subtarget->hasSVEAES()">,134 AssemblerPredicateWithAll<(all_of FeatureSVEAES), "sve-aes">;135def HasSVESM4 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVESM4()">,136 AssemblerPredicateWithAll<(all_of FeatureSVESM4), "sve-sm4">;137def HasSVESHA3 : Predicate<"Subtarget->hasSVESHA3()">,138 AssemblerPredicateWithAll<(all_of FeatureSVESHA3), "sve-sha3">;139def HasSVEBitPerm : Predicate<"Subtarget->hasSVEBitPerm()">,140 AssemblerPredicateWithAll<(all_of FeatureSVEBitPerm), "sve-bitperm">;141def HasSMEandIsNonStreamingSafe142 : Predicate<"Subtarget->hasSME()">,143 AssemblerPredicateWithAll<(all_of FeatureSME), "sme">;144def HasSME : Predicate<"Subtarget->isStreaming() && Subtarget->hasSME()">,145 AssemblerPredicateWithAll<(all_of FeatureSME), "sme">;146def HasSMEF64F64 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEF64F64()">,147 AssemblerPredicateWithAll<(all_of FeatureSMEF64F64), "sme-f64f64">;148def HasSMEF16F16 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEF16F16()">,149 AssemblerPredicateWithAll<(all_of FeatureSMEF16F16), "sme-f16f16">;150def HasSMEFA64 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEFA64()">,151 AssemblerPredicateWithAll<(all_of FeatureSMEFA64), "sme-fa64">;152def HasSMEI16I64 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEI16I64()">,153 AssemblerPredicateWithAll<(all_of FeatureSMEI16I64), "sme-i16i64">;154def HasSMEB16B16 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEB16B16()">,155 AssemblerPredicateWithAll<(all_of FeatureSMEB16B16), "sme-b16b16">;156def HasSME2andIsNonStreamingSafe157 : Predicate<"Subtarget->hasSME2()">,158 AssemblerPredicateWithAll<(all_of FeatureSME2), "sme2">;159def HasSME2 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSME2()">,160 AssemblerPredicateWithAll<(all_of FeatureSME2), "sme2">;161def HasSME2p1 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSME2p1()">,162 AssemblerPredicateWithAll<(all_of FeatureSME2p1), "sme2p1">;163def HasFP8 : Predicate<"Subtarget->hasFP8()">,164 AssemblerPredicateWithAll<(all_of FeatureFP8), "fp8">;165def HasFAMINMAX : Predicate<"Subtarget->hasFAMINMAX()">,166 AssemblerPredicateWithAll<(all_of FeatureFAMINMAX), "faminmax">;167def HasFP8FMA : Predicate<"Subtarget->hasFP8FMA()">,168 AssemblerPredicateWithAll<(all_of FeatureFP8FMA), "fp8fma">;169def HasSSVE_FP8FMA : Predicate<"Subtarget->hasSSVE_FP8FMA() || "170 "(Subtarget->hasSVE2() && Subtarget->hasFP8FMA())">,171 AssemblerPredicateWithAll<(any_of FeatureSSVE_FP8FMA,172 (all_of FeatureSVE2, FeatureFP8FMA)),173 "ssve-fp8fma or (sve2 and fp8fma)">;174def HasFP8DOT2 : Predicate<"Subtarget->hasFP8DOT2()">,175 AssemblerPredicateWithAll<(all_of FeatureFP8DOT2), "fp8dot2">;176def HasSSVE_FP8DOT2 : Predicate<"Subtarget->hasSSVE_FP8DOT2() || "177 "(Subtarget->hasSVE2() && Subtarget->hasFP8DOT2())">,178 AssemblerPredicateWithAll<(any_of FeatureSSVE_FP8DOT2,179 (all_of FeatureSVE2, FeatureFP8DOT2)),180 "ssve-fp8dot2 or (sve2 and fp8dot2)">;181def HasFP8DOT4 : Predicate<"Subtarget->hasFP8DOT4()">,182 AssemblerPredicateWithAll<(all_of FeatureFP8DOT4), "fp8dot4">;183def HasSSVE_FP8DOT4 : Predicate<"Subtarget->hasSSVE_FP8DOT4() || "184 "(Subtarget->hasSVE2() && Subtarget->hasFP8DOT4())">,185 AssemblerPredicateWithAll<(any_of FeatureSSVE_FP8DOT4,186 (all_of FeatureSVE2, FeatureFP8DOT4)),187 "ssve-fp8dot4 or (sve2 and fp8dot4)">;188def HasLUT : Predicate<"Subtarget->hasLUT()">,189 AssemblerPredicateWithAll<(all_of FeatureLUT), "lut">;190def HasSME_LUTv2 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSME_LUTv2()">,191 AssemblerPredicateWithAll<(all_of FeatureSME_LUTv2), "sme-lutv2">;192def HasSMEF8F16 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEF8F16()">,193 AssemblerPredicateWithAll<(all_of FeatureSMEF8F16), "sme-f8f16">;194def HasSMEF8F32 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSMEF8F32()">,195 AssemblerPredicateWithAll<(all_of FeatureSMEF8F32), "sme-f8f32">;196def HasSME_MOP4 : Predicate<"(Subtarget->isStreaming() && Subtarget->hasSME_MOP4())">,197 AssemblerPredicateWithAll<(all_of FeatureSME_MOP4), "sme-mop4">;198def HasSME_TMOP : Predicate<"(Subtarget->isStreaming() && Subtarget->hasSME_TMOP())">,199 AssemblerPredicateWithAll<(all_of FeatureSME_TMOP), "sme-tmop">;200def HasCMPBR : Predicate<"Subtarget->hasCMPBR()">,201 AssemblerPredicateWithAll<(all_of FeatureCMPBR), "cmpbr">;202def HasF8F32MM : Predicate<"Subtarget->hasF8F32MM()">,203 AssemblerPredicateWithAll<(all_of FeatureF8F32MM), "f8f32mm">;204def HasF8F16MM : Predicate<"Subtarget->hasF8F16MM()">,205 AssemblerPredicateWithAll<(all_of FeatureF8F16MM), "f8f16mm">;206def HasFPRCVT : Predicate<"Subtarget->hasFPRCVT()">,207 AssemblerPredicateWithAll<(all_of FeatureFPRCVT), "fprcvt">;208def HasLSFE : Predicate<"Subtarget->hasLSFE()">,209 AssemblerPredicateWithAll<(all_of FeatureLSFE), "lsfe">;210def HasSME2p2 : Predicate<"Subtarget->isStreaming() && Subtarget->hasSME2p2()">,211 AssemblerPredicateWithAll<(all_of FeatureSME2p2), "sme2p2">;212def HasSVEAES2 : Predicate<"Subtarget->hasSVEAES2()">,213 AssemblerPredicateWithAll<(all_of FeatureSVEAES2), "sve-aes2">;214def HasSVEBFSCALE : Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSVEBFSCALE()">,215 AssemblerPredicateWithAll<(all_of FeatureSVEBFSCALE), "sve-bfscale">;216def HasSVE_F16F32MM : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE_F16F32MM()">,217 AssemblerPredicateWithAll<(all_of FeatureSVE_F16F32MM), "sve-f16f32mm">;218def HasPCDPHINT : Predicate<"Subtarget->hasPCDPHINT()">,219 AssemblerPredicateWithAll<(all_of FeaturePCDPHINT), "pcdphint">;220def HasLSUI : Predicate<"Subtarget->hasLSUI()">,221 AssemblerPredicateWithAll<(all_of FeatureLSUI), "lsui">;222def HasOCCMO : Predicate<"Subtarget->hasOCCMO()">,223 AssemblerPredicateWithAll<(all_of FeatureOCCMO), "occmo">;224def HasCMH : Predicate<"Subtarget->hasCMH()">,225 AssemblerPredicateWithAll<(all_of FeatureCMH), "cmh">;226def HasLSCP : Predicate<"Subtarget->hasLSCP()">,227 AssemblerPredicateWithAll<(all_of FeatureLSCP), "lscp">;228def HasSVE2p2 : Predicate<"Subtarget->hasSVE2p2()">,229 AssemblerPredicateWithAll<(all_of FeatureSVE2p2), "sve2p2">;230def HasSVE_B16MM : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE_B16MM()">,231 AssemblerPredicateWithAll<(all_of FeatureSVE_B16MM), "sve-b16mm">;232def HasF16MM : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasF16MM()">,233 AssemblerPredicateWithAll<(all_of FeatureF16MM), "f16mm">;234def HasSVE2p3 : Predicate<"Subtarget->hasSVE2p3()">,235 AssemblerPredicateWithAll<(all_of FeatureSVE2p3), "sve2p3">;236def HasSME2p3 : Predicate<"Subtarget->hasSME2p3()">,237 AssemblerPredicateWithAll<(all_of FeatureSME2p3), "sme2p3">;238def HasF16F32DOT : Predicate<"Subtarget->hasF16F32DOT()">,239 AssemblerPredicateWithAll<(all_of FeatureF16F32DOT), "f16f32dot">;240def HasF16F32MM : Predicate<"Subtarget->hasF16F32MM()">,241 AssemblerPredicateWithAll<(all_of FeatureF16F32MM), "f16f32mm">;242 243// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,244// they should be enabled if either has been specified.245def HasSVE_or_SME246 : Predicate<"Subtarget->isSVEorStreamingSVEAvailable()">,247 AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME),248 "sve or sme">;249def HasNonStreamingSVE_or_SME2250 : Predicate<"Subtarget->isNonStreamingSVEorSME2Available()">,251 AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2),252 "sve or sme2">;253def HasNonStreamingSVE_or_SME2p1254 : Predicate<"Subtarget->isSVEAvailable() ||"255 "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p1())">,256 AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p1),257 "sve or sme2p1">;258def HasNonStreamingSVE_or_SME2p2259 : Predicate<"Subtarget->isSVEAvailable() ||"260 "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,261 AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2),262 "sve or sme2p2">;263def HasNonStreamingSVE_or_SSVE_AES264 : Predicate<"Subtarget->isSVEAvailable() ||"265 "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">,266 AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_AES),267 "sve or ssve-aes">;268def HasNonStreamingSVE_or_SSVE_BitPerm269 : Predicate<"Subtarget->isSVEAvailable() ||"270 "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm())">,271 AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_BitPerm),272 "sve or ssve-bitperm">;273def HasNonStreamingSVE_or_SSVE_FEXPA274 : Predicate<"Subtarget->isSVEAvailable() ||"275 "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_FEXPA())">,276 AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_FEXPA),277 "sve or ssve-fexpa">;278 279def HasSVE2_or_SME280 : Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2() || Subtarget->hasSME())">,281 AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME),282 "sve2 or sme">;283def HasNonStreamingSVE2_or_SME2284 : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"285 "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2())">,286 AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME2),287 "sve2 or sme2">;288 289def HasSVE2p1_or_SME290 : Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME())">,291 AssemblerPredicateWithAll<(any_of FeatureSME, FeatureSVE2p1),292 "sme or sve2p1">;293def HasSVE2p1_or_SME2294 : Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME2())">,295 AssemblerPredicateWithAll<(any_of FeatureSME2, FeatureSVE2p1),296 "sme2 or sve2p1">;297def HasSVE2p1_or_SME2p1298 : Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME2p1())">,299 AssemblerPredicateWithAll<(any_of FeatureSME2p1, FeatureSVE2p1),300 "sme2p1 or sve2p1">;301def HasSVE2p1_or_StreamingSME2302 : Predicate<"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSVE2p1()) ||"303 "(Subtarget->isStreaming() && Subtarget->hasSME2())">,304 AssemblerPredicateWithAll<(any_of FeatureSME2, FeatureSVE2p1),305 "sme2 or sve2p1">;306 307def HasSVE2p2_or_SME2p2308 : Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p2() || Subtarget->hasSME2p2())">,309 AssemblerPredicateWithAll<(any_of FeatureSME2p2, FeatureSVE2p2),310 "sme2p2 or sve2p2">;311def HasSVE2p3_or_SME2p3312 : Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p3() || Subtarget->hasSME2p3())">,313 AssemblerPredicateWithAll<(any_of FeatureSME2p3, FeatureSVE2p3),314 "sme2p3 or sve2p3">;315def HasNonStreamingSVE2p2_or_SME2p2316 : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2p2()) ||"317 "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,318 AssemblerPredicateWithAll<(any_of FeatureSVE2p2, FeatureSME2p2),319 "sme2p2 or sve2p2">;320 321def HasSMEF16F16_or_SMEF8F16322 : Predicate<"Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16())">,323 AssemblerPredicateWithAll<(any_of FeatureSMEF16F16, FeatureSMEF8F16),324 "sme-f16f16 or sme-f8f16">;325 326// A subset of NEON instructions are legal in Streaming SVE execution mode,327// so don't need the additional check for 'isNeonAvailable'.328def HasNEONandIsStreamingSafe329 : Predicate<"Subtarget->hasNEON()">,330 AssemblerPredicateWithAll<(any_of FeatureNEON), "neon">;331// A subset of NEON instructions are legal in Streaming SVE mode only with +sme2p2.332def HasNEONandIsSME2p2StreamingSafe333 : Predicate<"Subtarget->isNeonAvailable() || (Subtarget->hasNEON() && Subtarget->hasSME2p2())">,334 AssemblerPredicateWithAll<(any_of FeatureNEON), "neon">;335def HasRCPC : Predicate<"Subtarget->hasRCPC()">,336 AssemblerPredicateWithAll<(all_of FeatureRCPC), "rcpc">;337def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">,338 AssemblerPredicateWithAll<(all_of FeatureAltFPCmp), "altnzcv">;339def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">,340 AssemblerPredicateWithAll<(all_of FeatureFRInt3264), "frint3264">;341def HasSB : Predicate<"Subtarget->hasSB()">,342 AssemblerPredicateWithAll<(all_of FeatureSB), "sb">;343def HasPredRes : Predicate<"Subtarget->hasPredRes()">,344 AssemblerPredicateWithAll<(all_of FeaturePredRes), "predres">;345def HasCCDP : Predicate<"Subtarget->hasCCDP()">,346 AssemblerPredicateWithAll<(all_of FeatureCacheDeepPersist), "ccdp">;347def HasBTI : Predicate<"Subtarget->hasBTI()">,348 AssemblerPredicateWithAll<(all_of FeatureBranchTargetId), "bti">;349def HasBTIE : Predicate<"Subtarget->hasBTIE()">,350 AssemblerPredicateWithAll<(all_of FeatureBTIE), "btie">;351def HasMTE : Predicate<"Subtarget->hasMTE()">,352 AssemblerPredicateWithAll<(all_of FeatureMTE), "mte">;353def HasETE : Predicate<"Subtarget->hasETE()">,354 AssemblerPredicateWithAll<(all_of FeatureETE), "ete">;355def HasTRBE : Predicate<"Subtarget->hasTRBE()">,356 AssemblerPredicateWithAll<(all_of FeatureTRBE), "trbe">;357def HasBF16 : Predicate<"Subtarget->hasBF16()">,358 AssemblerPredicateWithAll<(all_of FeatureBF16), "bf16">;359def HasNoBF16 : Predicate<"!Subtarget->hasBF16()">;360def HasMatMulInt8 : Predicate<"Subtarget->hasMatMulInt8()">,361 AssemblerPredicateWithAll<(all_of FeatureMatMulInt8), "i8mm">;362def HasMatMulFP32 : Predicate<"Subtarget->hasMatMulFP32()">,363 AssemblerPredicateWithAll<(all_of FeatureMatMulFP32), "f32mm">;364def HasMatMulFP64 : Predicate<"Subtarget->hasMatMulFP64()">,365 AssemblerPredicateWithAll<(all_of FeatureMatMulFP64), "f64mm">;366def HasXS : Predicate<"Subtarget->hasXS()">,367 AssemblerPredicateWithAll<(all_of FeatureXS), "xs">;368def HasWFxT : Predicate<"Subtarget->hasWFxT()">,369 AssemblerPredicateWithAll<(all_of FeatureWFxT), "wfxt">;370def HasLS64 : Predicate<"Subtarget->hasLS64()">,371 AssemblerPredicateWithAll<(all_of FeatureLS64), "ls64">;372def HasBRBE : Predicate<"Subtarget->hasBRBE()">,373 AssemblerPredicateWithAll<(all_of FeatureBRBE), "brbe">;374def HasSPE_EEF : Predicate<"Subtarget->hasSPE_EEF()">,375 AssemblerPredicateWithAll<(all_of FeatureSPE_EEF), "spe-eef">;376def HasHBC : Predicate<"Subtarget->hasHBC()">,377 AssemblerPredicateWithAll<(all_of FeatureHBC), "hbc">;378def HasMOPS : Predicate<"Subtarget->hasMOPS()">,379 AssemblerPredicateWithAll<(all_of FeatureMOPS), "mops">;380def HasCLRBHB : Predicate<"Subtarget->hasCLRBHB()">,381 AssemblerPredicateWithAll<(all_of FeatureCLRBHB), "clrbhb">;382def HasSPECRES2 : Predicate<"Subtarget->hasSPECRES2()">,383 AssemblerPredicateWithAll<(all_of FeatureSPECRES2), "specres2">;384def HasITE : Predicate<"Subtarget->hasITE()">,385 AssemblerPredicateWithAll<(all_of FeatureITE), "ite">;386def HasTHE : Predicate<"Subtarget->hasTHE()">,387 AssemblerPredicateWithAll<(all_of FeatureTHE), "the">;388def HasRCPC3 : Predicate<"Subtarget->hasRCPC3()">,389 AssemblerPredicateWithAll<(all_of FeatureRCPC3), "rcpc3">;390def HasLSE128 : Predicate<"Subtarget->hasLSE128()">,391 AssemblerPredicateWithAll<(all_of FeatureLSE128), "lse128">;392def HasD128 : Predicate<"Subtarget->hasD128()">,393 AssemblerPredicateWithAll<(all_of FeatureD128), "d128">;394def HasCHK : Predicate<"Subtarget->hasCHK()">,395 AssemblerPredicateWithAll<(all_of FeatureCHK), "chk">;396def HasGCS : Predicate<"Subtarget->hasGCS()">,397 AssemblerPredicateWithAll<(all_of FeatureGCS), "gcs">;398def HasCPA : Predicate<"Subtarget->hasCPA()">,399 AssemblerPredicateWithAll<(all_of FeatureCPA), "cpa">;400def HasTLBID : Predicate<"Subtarget->hasTLBID()">,401 AssemblerPredicateWithAll<(all_of FeatureTLBID), "tlbid">;402def HasMPAMv2 : Predicate<"Subtarget->hasMPAMv2()">,403 AssemblerPredicateWithAll<(all_of FeatureMPAMv2), "mpamv2">;404def HasMTETC : Predicate<"Subtarget->hasMTETC()">,405 AssemblerPredicateWithAll<(all_of FeatureMTETC), "mtetc">;406def HasGCIE : Predicate<"Subtarget->hasGCIE()">,407 AssemblerPredicateWithAll<(all_of FeatureGCIE), "gcie">;408def HasMOPS_GO : Predicate<"Subtarget->hasMOPS_GO()">,409 AssemblerPredicateWithAll<(all_of FeatureMOPS_GO), "mops-go">;410def HasS1POE2 : Predicate<"Subtarget->hasS1POE2()">,411 AssemblerPredicateWithAll<(all_of FeatureS1POE2), "poe2">;412def HasTEV : Predicate<"Subtarget->hasTEV()">,413 AssemblerPredicateWithAll<(all_of FeatureTEV), "tev">;414def IsLE : Predicate<"Subtarget->isLittleEndian()">;415def IsBE : Predicate<"!Subtarget->isLittleEndian()">;416def IsWindows : Predicate<"Subtarget->isTargetWindows()">;417def UseExperimentalZeroingPseudos418 : Predicate<"Subtarget->useExperimentalZeroingPseudos()">;419def UseAlternateSExtLoadCVTF32420 : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;421 422def UseNegativeImmediates423 : Predicate<"false">,424 AssemblerPredicate<(all_of (not FeatureNoNegativeImmediates)),425 "NegativeImmediates">;426 427def UseScalarIncVL : Predicate<"Subtarget->useScalarIncVL()">;428 429def NoUseScalarIncVL : Predicate<"!Subtarget->useScalarIncVL()">;430 431def HasFastIncVL : Predicate<"!Subtarget->hasDisableFastIncVL()">;432 433def UseSVEFPLD1R : Predicate<"!Subtarget->noSVEFPLD1R()">;434 435def UseLDAPUR : Predicate<"!Subtarget->avoidLDAPUR()">;436 437def AArch64LocalRecover : SDNode<"ISD::LOCAL_RECOVER",438 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,439 SDTCisInt<1>]>>;440 441def AllowMisalignedMemAccesses442 : Predicate<"!Subtarget->requiresStrictAlign()">;443 444def UseWzrToVecMove : Predicate<"Subtarget->useWzrToVecMove()">;445 446 447//===----------------------------------------------------------------------===//448// AArch64-specific DAG Nodes.449//450 451// SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS452def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,453 [SDTCisSameAs<0, 2>,454 SDTCisSameAs<0, 3>,455 SDTCisInt<0>,456 SDTCisVT<1, FlagsVT>]>;457 458// SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS459def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,460 [SDTCisSameAs<0, 1>,461 SDTCisSameAs<0, 2>,462 SDTCisInt<0>,463 SDTCisVT<3, FlagsVT>]>;464 465// SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS466def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,467 [SDTCisSameAs<0, 2>,468 SDTCisSameAs<0, 3>,469 SDTCisInt<0>,470 SDTCisVT<1, FlagsVT>,471 SDTCisVT<4, FlagsVT>]>;472 473// Value type used for condition codes.474// Should be kept in sync with its C++ counterpart.475defvar CondCodeVT = i32;476 477def SDT_AArch64Brcond : SDTypeProfile<0, 3,478 [SDTCisVT<0, OtherVT>,479 SDTCisVT<1, CondCodeVT>,480 SDTCisVT<2, FlagsVT>]>;481def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;482def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,483 SDTCisVT<2, OtherVT>]>;484 485def SDT_AArch64CSel : SDTypeProfile<1, 4,486 [SDTCisSameAs<0, 1>,487 SDTCisSameAs<0, 2>,488 SDTCisVT<3, CondCodeVT>,489 SDTCisVT<4, FlagsVT>]>;490def SDT_AArch64CCMP : SDTypeProfile<1, 5,491 [SDTCisVT<0, FlagsVT>,492 SDTCisInt<1>,493 SDTCisSameAs<1, 2>,494 SDTCisInt<3>,495 SDTCisVT<4, CondCodeVT>,496 SDTCisVT<5, FlagsVT>]>;497def SDT_AArch64FCCMP : SDTypeProfile<1, 5,498 [SDTCisVT<0, FlagsVT>,499 SDTCisFP<1>,500 SDTCisSameAs<1, 2>,501 SDTCisInt<3>,502 SDTCisVT<4, CondCodeVT>,503 SDTCisVT<5, FlagsVT>]>;504def SDT_AArch64FCmp : SDTypeProfile<1, 2, [SDTCisVT<0, FlagsVT>,505 SDTCisFP<1>,506 SDTCisSameAs<2, 1>]>;507def SDT_AArch64Rev : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>]>;508def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;509def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;510def SDT_AArch64Insr : SDTypeProfile<1, 2, [SDTCisVec<0>]>;511def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,512 SDTCisSameAs<0, 1>,513 SDTCisSameAs<0, 2>]>;514def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;515def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;516def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,517 SDTCisInt<2>, SDTCisInt<3>]>;518def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;519def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,520 SDTCisSameAs<0,2>, SDTCisInt<3>]>;521def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;522def SDT_AArch64Dot: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,523 SDTCisVec<2>, SDTCisSameAs<2,3>]>;524 525def SDT_AArch64vshiftinsert : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<3>,526 SDTCisSameAs<0,1>,527 SDTCisSameAs<0,2>]>;528 529def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;530def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;531def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;532def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,533 SDTCisSameAs<0,2>]>;534def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,535 SDTCisSameAs<0,2>,536 SDTCisSameAs<0,3>]>;537def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;538def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;539 540def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;541 542def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,543 SDTCisPtrTy<1>]>;544 545def SDT_AArch64uaddlp : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;546 547def SDT_AArch64ldp : SDTypeProfile<2, 1, [SDTCisVT<0, i64>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;548def SDT_AArch64ldiapp : SDTypeProfile<2, 1, [SDTCisVT<0, i64>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;549def SDT_AArch64ldnp : SDTypeProfile<2, 1, [SDTCisVT<0, v2i64>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;550def SDT_AArch64stp : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;551def SDT_AArch64stilp : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;552def SDT_AArch64stnp : SDTypeProfile<0, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;553 554// Generates the general dynamic sequences, i.e.555// adrp x0, :tlsdesc:var556// ldr x1, [x0, #:tlsdesc_lo12:var]557// add x0, x0, #:tlsdesc_lo12:var558// .tlsdesccall var559// blr x1560 561// (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)562// number of operands (the variable)563def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,564 [SDTCisPtrTy<0>]>;565 566def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,567 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,568 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,569 SDTCisSameAs<1, 4>]>;570 571def SDT_AArch64TBL : SDTypeProfile<1, 2, [572 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>573]>;574 575def SDT_AArch64cb : SDTypeProfile<0, 4,576 [SDTCisVT<0, CondCodeVT>,577 SDTCisInt<1>, SDTCisInt<2>,578 SDTCisVT<3, OtherVT>]>;579 580// non-extending masked load fragment.581def nonext_masked_load :582 PatFrag<(ops node:$ptr, node:$pred, node:$def),583 (masked_ld node:$ptr, undef, node:$pred, node:$def), [{584 return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD &&585 cast<MaskedLoadSDNode>(N)->isUnindexed() &&586 !cast<MaskedLoadSDNode>(N)->isNonTemporal();587}]>;588// Any/Zero extending masked load fragments.589def azext_masked_load :590 PatFrag<(ops node:$ptr, node:$pred, node:$def),591 (masked_ld node:$ptr, undef, node:$pred, node:$def),[{592 return (cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD ||593 cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD) &&594 cast<MaskedLoadSDNode>(N)->isUnindexed();595}]>;596def azext_masked_load_i8 :597 PatFrag<(ops node:$ptr, node:$pred, node:$def),598 (azext_masked_load node:$ptr, node:$pred, node:$def), [{599 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;600}]>;601def azext_masked_load_i16 :602 PatFrag<(ops node:$ptr, node:$pred, node:$def),603 (azext_masked_load node:$ptr, node:$pred, node:$def), [{604 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;605}]>;606def azext_masked_load_i32 :607 PatFrag<(ops node:$ptr, node:$pred, node:$def),608 (azext_masked_load node:$ptr, node:$pred, node:$def), [{609 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;610}]>;611// Sign extending masked load fragments.612def sext_masked_load :613 PatFrag<(ops node:$ptr, node:$pred, node:$def),614 (masked_ld node:$ptr, undef, node:$pred, node:$def), [{615 return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD &&616 cast<MaskedLoadSDNode>(N)->isUnindexed();617}]>;618def sext_masked_load_i8 :619 PatFrag<(ops node:$ptr, node:$pred, node:$def),620 (sext_masked_load node:$ptr, node:$pred, node:$def), [{621 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;622}]>;623def sext_masked_load_i16 :624 PatFrag<(ops node:$ptr, node:$pred, node:$def),625 (sext_masked_load node:$ptr, node:$pred, node:$def), [{626 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;627}]>;628def sext_masked_load_i32 :629 PatFrag<(ops node:$ptr, node:$pred, node:$def),630 (sext_masked_load node:$ptr, node:$pred, node:$def), [{631 return cast<MaskedLoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;632}]>;633 634def non_temporal_load :635 PatFrag<(ops node:$ptr, node:$pred, node:$def),636 (masked_ld node:$ptr, undef, node:$pred, node:$def), [{637 return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD &&638 cast<MaskedLoadSDNode>(N)->isUnindexed() &&639 cast<MaskedLoadSDNode>(N)->isNonTemporal();640}]>;641 642// non-truncating masked store fragment.643def nontrunc_masked_store :644 PatFrag<(ops node:$val, node:$ptr, node:$pred),645 (masked_st node:$val, node:$ptr, undef, node:$pred), [{646 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore() &&647 cast<MaskedStoreSDNode>(N)->isUnindexed() &&648 !cast<MaskedStoreSDNode>(N)->isNonTemporal() &&649 !cast<MaskedStoreSDNode>(N)->isCompressingStore();650}]>;651// truncating masked store fragments.652def trunc_masked_store :653 PatFrag<(ops node:$val, node:$ptr, node:$pred),654 (masked_st node:$val, node:$ptr, undef, node:$pred), [{655 return cast<MaskedStoreSDNode>(N)->isTruncatingStore() &&656 cast<MaskedStoreSDNode>(N)->isUnindexed() &&657 !cast<MaskedStoreSDNode>(N)->isCompressingStore();658}]>;659def trunc_masked_store_i8 :660 PatFrag<(ops node:$val, node:$ptr, node:$pred),661 (trunc_masked_store node:$val, node:$ptr, node:$pred), [{662 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8 &&663 !cast<MaskedStoreSDNode>(N)->isCompressingStore();664}]>;665def trunc_masked_store_i16 :666 PatFrag<(ops node:$val, node:$ptr, node:$pred),667 (trunc_masked_store node:$val, node:$ptr, node:$pred), [{668 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16 &&669 !cast<MaskedStoreSDNode>(N)->isCompressingStore();670}]>;671def trunc_masked_store_i32 :672 PatFrag<(ops node:$val, node:$ptr, node:$pred),673 (trunc_masked_store node:$val, node:$ptr, node:$pred), [{674 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32 &&675 !cast<MaskedStoreSDNode>(N)->isCompressingStore();676}]>;677 678def non_temporal_store :679 PatFrag<(ops node:$val, node:$ptr, node:$pred),680 (masked_st node:$val, node:$ptr, undef, node:$pred), [{681 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore() &&682 cast<MaskedStoreSDNode>(N)->isUnindexed() &&683 cast<MaskedStoreSDNode>(N)->isNonTemporal() &&684 !cast<MaskedStoreSDNode>(N)->isCompressingStore();685}]>;686 687multiclass masked_gather_scatter<PatFrags GatherScatterOp> {688 // offsets = (signed)Index << sizeof(elt)689 def NAME#_signed_scaled :690 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx),691 (GatherScatterOp node:$val, node:$pred, node:$ptr, node:$idx),[{692 auto MGS = cast<MaskedGatherScatterSDNode>(N);693 bool Signed = MGS->isIndexSigned() ||694 MGS->getIndex().getValueType().getVectorElementType() == MVT::i64;695 return Signed && MGS->isIndexScaled();696 }]>;697 // offsets = (signed)Index698 def NAME#_signed_unscaled :699 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx),700 (GatherScatterOp node:$val, node:$pred, node:$ptr, node:$idx),[{701 auto MGS = cast<MaskedGatherScatterSDNode>(N);702 bool Signed = MGS->isIndexSigned() ||703 MGS->getIndex().getValueType().getVectorElementType() == MVT::i64;704 return Signed && !MGS->isIndexScaled();705 }]>;706 // offsets = (unsigned)Index << sizeof(elt)707 def NAME#_unsigned_scaled :708 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx),709 (GatherScatterOp node:$val, node:$pred, node:$ptr, node:$idx),[{710 auto MGS = cast<MaskedGatherScatterSDNode>(N);711 bool Signed = MGS->isIndexSigned() ||712 MGS->getIndex().getValueType().getVectorElementType() == MVT::i64;713 return !Signed && MGS->isIndexScaled();714 }]>;715 // offsets = (unsigned)Index716 def NAME#_unsigned_unscaled :717 PatFrag<(ops node:$val, node:$pred, node:$ptr, node:$idx),718 (GatherScatterOp node:$val, node:$pred, node:$ptr, node:$idx),[{719 auto MGS = cast<MaskedGatherScatterSDNode>(N);720 bool Signed = MGS->isIndexSigned() ||721 MGS->getIndex().getValueType().getVectorElementType() == MVT::i64;722 return !Signed && !MGS->isIndexScaled();723 }]>;724}725 726defm nonext_masked_gather : masked_gather_scatter<nonext_masked_gather>;727defm azext_masked_gather_i8 : masked_gather_scatter<azext_masked_gather_i8>;728defm azext_masked_gather_i16 : masked_gather_scatter<azext_masked_gather_i16>;729defm azext_masked_gather_i32 : masked_gather_scatter<azext_masked_gather_i32>;730defm sext_masked_gather_i8 : masked_gather_scatter<sext_masked_gather_i8>;731defm sext_masked_gather_i16 : masked_gather_scatter<sext_masked_gather_i16>;732defm sext_masked_gather_i32 : masked_gather_scatter<sext_masked_gather_i32>;733 734defm nontrunc_masked_scatter : masked_gather_scatter<nontrunc_masked_scatter>;735defm trunc_masked_scatter_i8 : masked_gather_scatter<trunc_masked_scatter_i8>;736defm trunc_masked_scatter_i16 : masked_gather_scatter<trunc_masked_scatter_i16>;737defm trunc_masked_scatter_i32 : masked_gather_scatter<trunc_masked_scatter_i32>;738 739// top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise740def top16Zero: PatLeaf<(i32 GPR32:$src), [{741 return Op.getValueType() == MVT::i32 &&742 CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 16));743 }]> {744 let GISelLeafPredicateCode = [{745 return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 16)); }];746}747 748// top32Zero - answer true if the upper 32 bits of $src are 0, false otherwise749def top32Zero: PatLeaf<(i64 GPR64:$src), [{750 return Op.getValueType() == MVT::i64 &&751 CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(64, 32));752 }]> {753 let GISelLeafPredicateCode = [{ 754 return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 32)); }];755}756 757// topbitsallzero - Return true if all bits except the lowest bit are known zero758def topbitsallzero32: PatLeaf<(i32 GPR32:$src), [{759 return Op.getValueType() == MVT::i32 &&760 CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 31));761 }]> {762 let GISelLeafPredicateCode = [{ 763 return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 31)); }];764}765def topbitsallzero64: PatLeaf<(i64 GPR64:$src), [{766 return Op.getValueType() == MVT::i64 &&767 CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(64, 63));768 }]> {769 let GISelLeafPredicateCode = [{ 770 return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 63)); }];771}772 773// Node definitions.774// Compare-and-branch775def AArch64CB : SDNode<"AArch64ISD::CB", SDT_AArch64cb, [SDNPHasChain]>;776// Page address of a TargetGlobalAddress operand.777def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;778def AArch64adr : SDNode<"AArch64ISD::ADR", SDTIntUnaryOp, []>;779// Add the low 12 bits of a TargetGlobalAddress operand.780def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;781// Load from automatically generated descriptor (e.g. Global Offset Table, TLS782// record).783def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;784def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",785 SDCallSeqStart<[ SDTCisVT<0, i32>,786 SDTCisVT<1, i32> ]>,787 [SDNPHasChain, SDNPOutGlue]>;788def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",789 SDCallSeqEnd<[ SDTCisVT<0, i32>,790 SDTCisVT<1, i32> ]>,791 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;792def AArch64call : SDNode<"AArch64ISD::CALL",793 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,794 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,795 SDNPVariadic]>;796 797// Function call followed by a BTI instruction.798def AArch64call_bti : SDNode<"AArch64ISD::CALL_BTI",799 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,800 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,801 SDNPVariadic]>;802 803// Pseudo for a OBJC call that gets emitted together with a special `mov804// x29, x29` marker instruction.805def AArch64call_rvmarker: SDNode<"AArch64ISD::CALL_RVMARKER",806 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,807 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,808 SDNPVariadic]>;809 810// A call with the callee in x16, i.e. "blr x16".811def AArch64call_arm64ec_to_x64 : SDNode<"AArch64ISD::CALL_ARM64EC_TO_X64",812 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,813 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,814 SDNPVariadic]>;815 816// Function call, authenticating the callee value first:817// AUTH_CALL chain, callee, auth key #, int disc, addr disc, operands.818def AArch64authcall : SDNode<"AArch64ISD::AUTH_CALL",819 SDTypeProfile<0, -1, [SDTCisPtrTy<0>,820 SDTCisVT<1, i32>,821 SDTCisVT<2, i64>,822 SDTCisVT<3, i64>]>,823 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,824 SDNPVariadic]>;825 826// AUTH_TC_RETURN chain, callee, fpdiff, auth key #, int disc, addr disc,827// operands.828def AArch64authtcret: SDNode<"AArch64ISD::AUTH_TC_RETURN",829 SDTypeProfile<0, 5, [SDTCisPtrTy<0>,830 SDTCisVT<2, i32>,831 SDTCisVT<3, i64>,832 SDTCisVT<4, i64>]>,833 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;834 835// Authenticated variant of CALL_RVMARKER.836def AArch64authcall_rvmarker : SDNode<"AArch64ISD::AUTH_CALL_RVMARKER",837 SDTypeProfile<0, -1, [SDTCisPtrTy<0>,838 SDTCisVT<1, i32>,839 SDTCisPtrTy<2>,840 SDTCisVT<3, i32>,841 SDTCisVT<4, i64>,842 SDTCisVT<5, i64>]>,843 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,844 SDNPVariadic]>;845 846// Conditional branch instruction; "b.cond".847def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,848 [SDNPHasChain]>;849def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,850 [SDNPHasChain]>;851def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,852 [SDNPHasChain]>;853def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,854 [SDNPHasChain]>;855def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,856 [SDNPHasChain]>;857 858 859def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;860// Conditional select invert.861def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;862// Conditional select negate.863def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;864// Conditional select increment.865def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;866// Return with a glue operand. Operand 0 is the chain operand.867def AArch64retglue : SDNode<"AArch64ISD::RET_GLUE", SDTNone,868 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;869def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;870def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;871 872// Arithmetic instructions which write flags.873def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,874 [SDNPCommutative]>;875def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;876def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,877 [SDNPCommutative]>;878def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;879def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;880 881// Conditional compares. Operands: left,right,falsecc,cc,flags882def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>;883def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>;884def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;885 886// Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on887// ELF.888def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;889 890// Floating point comparison891def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;892 893let IsStrictFP = true in {894 // Strict (exception-raising) floating point comparison895 def AArch64strict_fcmp : SDNode<"AArch64ISD::STRICT_FCMP", SDT_AArch64FCmp,896 [SDNPHasChain]>;897 def AArch64strict_fcmpe : SDNode<"AArch64ISD::STRICT_FCMPE", SDT_AArch64FCmp,898 [SDNPHasChain]>;899}900 901def AArch64any_fcmp : PatFrags<(ops node:$lhs, node:$rhs),902 [(AArch64strict_fcmp node:$lhs, node:$rhs),903 (AArch64fcmp node:$lhs, node:$rhs)]>;904 905// Scalar-to-vector duplication906def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;907def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;908def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;909def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;910def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;911def AArch64duplane128 : SDNode<"AArch64ISD::DUPLANE128", SDT_AArch64DupLane>;912 913def AArch64insr : SDNode<"AArch64ISD::INSR", SDT_AArch64Insr>;914 915// Vector shuffles916def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;917def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;918def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;919def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;920def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;921def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;922 923// Vector immediate moves924def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;925def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;926def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;927def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;928def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;929def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;930def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;931 932def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64Rev>;933def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64Rev>;934def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64Rev>;935def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;936 937// Vector shift by scalar938def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;939def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;940def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;941 942def AArch64vashr_exact : PatFrag<(ops node:$lhs, node:$rhs),943 (AArch64vashr node:$lhs, node:$rhs), [{944 return N->getFlags().hasExact();945}]>;946 947// Vector shift by scalar (again)948def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;949def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;950def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;951def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;952def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;953 954def AArch64vsli : SDNode<"AArch64ISD::VSLI", SDT_AArch64vshiftinsert>;955def AArch64vsri : SDNode<"AArch64ISD::VSRI", SDT_AArch64vshiftinsert>;956 957// Vector bitwise select: similar to ISD::VSELECT but not all bits within an958// element must be identical.959def AArch64bsp: SDNode<"AArch64ISD::BSP", SDT_AArch64trivec>;960 961def AArch64cmeq : PatFrag<(ops node:$lhs, node:$rhs),962 (setcc node:$lhs, node:$rhs, SETEQ)>;963def AArch64cmge : PatFrag<(ops node:$lhs, node:$rhs),964 (setcc node:$lhs, node:$rhs, SETGE)>;965def AArch64cmgt : PatFrag<(ops node:$lhs, node:$rhs),966 (setcc node:$lhs, node:$rhs, SETGT)>;967def AArch64cmhi : PatFrag<(ops node:$lhs, node:$rhs),968 (setcc node:$lhs, node:$rhs, SETUGT)>;969def AArch64cmhs : PatFrag<(ops node:$lhs, node:$rhs),970 (setcc node:$lhs, node:$rhs, SETUGE)>;971 972// Vector comparisons973def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;974def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;975def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;976 977def AArch64cmeqz : PatFrag<(ops node:$lhs),978 (setcc node:$lhs, immAllZerosV, SETEQ)>;979def AArch64cmgez : PatFrags<(ops node:$lhs),980 [(setcc node:$lhs, immAllZerosV, SETGE),981 (setcc node:$lhs, immAllOnesV, SETGT)]>;982def AArch64cmgtz : PatFrag<(ops node:$lhs),983 (setcc node:$lhs, immAllZerosV, SETGT)>;984def AArch64cmlez : PatFrag<(ops node:$lhs),985 (setcc immAllZerosV, node:$lhs, SETGE)>;986def AArch64cmltz : PatFrag<(ops node:$lhs),987 (setcc immAllZerosV, node:$lhs, SETGT)>;988 989def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),990 (vnot (AArch64cmeqz (and node:$LHS, node:$RHS)))>;991 992def AArch64fcmeqz : PatFrag<(ops node:$lhs),993 (AArch64fcmeq node:$lhs, immAllZerosV)>;994 995def AArch64fcmgez : PatFrag<(ops node:$lhs),996 (AArch64fcmge node:$lhs, immAllZerosV)>;997 998def AArch64fcmgtz : PatFrag<(ops node:$lhs),999 (AArch64fcmgt node:$lhs, immAllZerosV)>;1000 1001def AArch64fcmlez : PatFrag<(ops node:$lhs),1002 (AArch64fcmge immAllZerosV, node:$lhs)>;1003 1004def AArch64fcmltz : PatFrag<(ops node:$lhs),1005 (AArch64fcmgt immAllZerosV, node:$lhs)>;1006 1007// Round wide FP to narrow FP with inexact results to odd.1008def AArch64fcvtxn_n: SDNode<"AArch64ISD::FCVTXN", SDTFPRoundOp>;1009def AArch64fcvtxnsdr: PatFrags<(ops node:$Rn),1010 [(f32 (int_aarch64_sisd_fcvtxn (f64 node:$Rn))),1011 (f32 (AArch64fcvtxn_n (f64 node:$Rn)))]>;1012def AArch64fcvtxnv: PatFrags<(ops node:$Rn),1013 [(int_aarch64_neon_fcvtxn node:$Rn),1014 (AArch64fcvtxn_n node:$Rn)]>;1015 1016def AArch64fcvtzs_half : SDNode<"AArch64ISD::FCVTZS_HALF", SDTFPExtendOp>;1017def AArch64fcvtzu_half : SDNode<"AArch64ISD::FCVTZU_HALF", SDTFPExtendOp>;1018def AArch64fcvtas_half : SDNode<"AArch64ISD::FCVTAS_HALF", SDTFPExtendOp>;1019def AArch64fcvtau_half : SDNode<"AArch64ISD::FCVTAU_HALF", SDTFPExtendOp>;1020def AArch64fcvtms_half : SDNode<"AArch64ISD::FCVTMS_HALF", SDTFPExtendOp>;1021def AArch64fcvtmu_half : SDNode<"AArch64ISD::FCVTMU_HALF", SDTFPExtendOp>;1022def AArch64fcvtns_half : SDNode<"AArch64ISD::FCVTNS_HALF", SDTFPExtendOp>;1023def AArch64fcvtnu_half : SDNode<"AArch64ISD::FCVTNU_HALF", SDTFPExtendOp>;1024def AArch64fcvtps_half : SDNode<"AArch64ISD::FCVTPS_HALF", SDTFPExtendOp>;1025def AArch64fcvtpu_half : SDNode<"AArch64ISD::FCVTPU_HALF", SDTFPExtendOp>;1026 1027//def Aarch64softf32tobf16v8: SDNode<"AArch64ISD::", SDTFPRoundOp>;1028 1029// Vector immediate ops1030def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;1031def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;1032 1033// Tail calls1034def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,1035 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;1036 1037// Custom prefetch handling1038def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,1039 [SDNPHasChain, SDNPSideEffect]>;1040 1041// {s|u}int to FP within a FP register.1042def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;1043def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;1044 1045// Produces the full sequence of instructions for getting the thread pointer1046// offset of a variable into X0, using the TLSDesc model.1047def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",1048 SDT_AArch64TLSDescCallSeq,1049 [SDNPOutGlue, SDNPOptInGlue, SDNPHasChain, SDNPVariadic]>;1050 1051def AArch64tlsdesc_auth_callseq : SDNode<"AArch64ISD::TLSDESC_AUTH_CALLSEQ",1052 SDT_AArch64TLSDescCallSeq,1053 [SDNPOutGlue, SDNPOptInGlue, SDNPHasChain, SDNPVariadic]>;1054 1055def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",1056 SDT_AArch64WrapperLarge>;1057 1058/// Natural vector cast. ISD::BITCAST is not natural in the big-endian1059/// world w.r.t vectors; which causes additional REV instructions to be1060/// generated to compensate for the byte-swapping. But sometimes we do1061/// need to re-interpret the data in SIMD vector registers in big-endian1062/// mode without emitting such REV instructions.1063def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;1064 1065def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,1066 SDTCisSameAs<1, 2>]>;1067def AArch64pmull : SDNode<"AArch64ISD::PMULL", SDT_AArch64mull,1068 [SDNPCommutative]>;1069def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull,1070 [SDNPCommutative]>;1071def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull,1072 [SDNPCommutative]>;1073def AArch64sqdmulh : SDNode<"AArch64ISD::SQDMULH", SDT_AArch64mull>;1074 1075// Reciprocal estimates and steps.1076def AArch64frecpe : SDNode<"AArch64ISD::FRECPE", SDTFPUnaryOp>;1077def AArch64frecps : SDNode<"AArch64ISD::FRECPS", SDTFPBinOp>;1078def AArch64frsqrte : SDNode<"AArch64ISD::FRSQRTE", SDTFPUnaryOp>;1079def AArch64frsqrts : SDNode<"AArch64ISD::FRSQRTS", SDTFPBinOp>;1080 1081// udot/sdot/usdot instructions1082def AArch64sdot : SDNode<"AArch64ISD::SDOT", SDT_AArch64Dot>;1083def AArch64udot : SDNode<"AArch64ISD::UDOT", SDT_AArch64Dot>;1084def AArch64usdot : SDNode<"AArch64ISD::USDOT", SDT_AArch64Dot>;1085 1086// Vector across-lanes addition1087// Only the lower result lane is defined.1088def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;1089def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;1090 1091// Vector across-lanes min/max1092// Only the lower result lane is defined.1093def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;1094def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;1095def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;1096def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;1097 1098// Unsigned sum Long across Vector1099def AArch64uaddlv : SDNode<"AArch64ISD::UADDLV", SDT_AArch64uaddlp>;1100def AArch64saddlv : SDNode<"AArch64ISD::SADDLV", SDT_AArch64uaddlp>;1101 1102// Add Pairwise of two vectors1103def AArch64addp_n : SDNode<"AArch64ISD::ADDP", SDT_AArch64Zip>;1104// Add Long Pairwise1105def AArch64uaddlp_n : SDNode<"AArch64ISD::UADDLP", SDT_AArch64uaddlp>;1106def AArch64saddlp_n : SDNode<"AArch64ISD::SADDLP", SDT_AArch64uaddlp>;1107def AArch64addp : PatFrags<(ops node:$Rn, node:$Rm),1108 [(AArch64addp_n node:$Rn, node:$Rm),1109 (int_aarch64_neon_addp node:$Rn, node:$Rm)]>;1110def AArch64uaddlp : PatFrags<(ops node:$src),1111 [(AArch64uaddlp_n node:$src),1112 (int_aarch64_neon_uaddlp node:$src)]>;1113def AArch64saddlp : PatFrags<(ops node:$src),1114 [(AArch64saddlp_n node:$src),1115 (int_aarch64_neon_saddlp node:$src)]>;1116def AArch64faddp : PatFrags<(ops node:$Rn, node:$Rm),1117 [(AArch64addp_n node:$Rn, node:$Rm),1118 (int_aarch64_neon_faddp node:$Rn, node:$Rm)]>;1119def AArch64roundingvlshr : ComplexPattern<vAny, 2, "SelectRoundingVLShr", [AArch64vlshr]>;1120def AArch64rshrn : PatFrags<(ops node:$LHS, node:$RHS),1121 [(trunc (AArch64roundingvlshr node:$LHS, node:$RHS)),1122 (int_aarch64_neon_rshrn node:$LHS, node:$RHS)]>;1123def AArch64facge : PatFrags<(ops node:$Rn, node:$Rm),1124 [(AArch64fcmge (fabs node:$Rn), (fabs node:$Rm)),1125 (int_aarch64_neon_facge node:$Rn, node:$Rm)]>;1126def AArch64facgt : PatFrags<(ops node:$Rn, node:$Rm),1127 [(AArch64fcmgt (fabs node:$Rn), (fabs node:$Rm)),1128 (int_aarch64_neon_facgt node:$Rn, node:$Rm)]>;1129 1130def AArch64fmaxnmv : PatFrags<(ops node:$Rn),1131 [(vecreduce_fmax node:$Rn),1132 (int_aarch64_neon_fmaxnmv node:$Rn)]>;1133def AArch64fminnmv : PatFrags<(ops node:$Rn),1134 [(vecreduce_fmin node:$Rn),1135 (int_aarch64_neon_fminnmv node:$Rn)]>;1136def AArch64fmaxv : PatFrags<(ops node:$Rn),1137 [(vecreduce_fmaximum node:$Rn),1138 (int_aarch64_neon_fmaxv node:$Rn)]>;1139def AArch64fminv : PatFrags<(ops node:$Rn),1140 [(vecreduce_fminimum node:$Rn),1141 (int_aarch64_neon_fminv node:$Rn)]>;1142 1143def SDT_AArch64SETTAG : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;1144def AArch64stg : SDNode<"AArch64ISD::STG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1145def AArch64stzg : SDNode<"AArch64ISD::STZG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1146def AArch64st2g : SDNode<"AArch64ISD::ST2G", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1147def AArch64stz2g : SDNode<"AArch64ISD::STZ2G", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1148 1149def SDT_AArch64unpk : SDTypeProfile<1, 1, [1150 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>1151]>;1152def AArch64sunpkhi : SDNode<"AArch64ISD::SUNPKHI", SDT_AArch64unpk>;1153def AArch64sunpklo : SDNode<"AArch64ISD::SUNPKLO", SDT_AArch64unpk>;1154def AArch64uunpkhi : SDNode<"AArch64ISD::UUNPKHI", SDT_AArch64unpk>;1155def AArch64uunpklo : SDNode<"AArch64ISD::UUNPKLO", SDT_AArch64unpk>;1156 1157def AArch64ldp : SDNode<"AArch64ISD::LDP", SDT_AArch64ldp, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1158def AArch64ldiapp : SDNode<"AArch64ISD::LDIAPP", SDT_AArch64ldiapp, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1159def AArch64ldnp : SDNode<"AArch64ISD::LDNP", SDT_AArch64ldnp, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1160def AArch64stp : SDNode<"AArch64ISD::STP", SDT_AArch64stp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1161def AArch64stilp : SDNode<"AArch64ISD::STILP", SDT_AArch64stilp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1162def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1163 1164def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;1165 1166// To avoid stack clash, allocation is performed by block and each block is1167// probed.1168def AArch64probedalloca1169 : SDNode<"AArch64ISD::PROBED_ALLOCA",1170 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,1171 [SDNPHasChain, SDNPMayStore]>;1172 1173// MRS, also sets the flags.1174def AArch64mrs : SDNode<"AArch64ISD::MRS",1175 SDTypeProfile<2, 1, [SDTCisVT<0, i64>,1176 SDTCisVT<1, FlagsVT>,1177 SDTCisVT<2, i32>]>,1178 [SDNPHasChain]>;1179 1180// 128-bit system register accesses1181// lo64, hi64, chain = MRRS(chain, sysregname)1182def AArch64mrrs : SDNode<"AArch64ISD::MRRS",1183 SDTypeProfile<2, 1, [SDTCisVT<0, i64>,1184 SDTCisVT<1, i64>]>,1185 [SDNPHasChain]>;1186 1187// chain = MSRR(chain, sysregname, lo64, hi64)1188def AArch64msrr : SDNode<"AArch64ISD::MSRR",1189 SDTypeProfile<0, 3, [SDTCisVT<1, i64>,1190 SDTCisVT<2, i64>]>,1191 [SDNPHasChain]>;1192 1193def SD_AArch64rshrnb : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i32>]>;1194// Vector narrowing shift by immediate (bottom)1195def AArch64rshrnb : SDNode<"AArch64ISD::RSHRNB_I", SD_AArch64rshrnb>;1196def AArch64rshrnb_pf : PatFrags<(ops node:$rs, node:$i),1197 [(AArch64rshrnb node:$rs, node:$i),1198 (int_aarch64_sve_rshrnb node:$rs, node:$i)]>;1199 1200def AArch64CttzElts : SDNode<"AArch64ISD::CTTZ_ELTS", SDTypeProfile<1, 1,1201 [SDTCisInt<0>, SDTCisVec<1>]>, []>;1202 1203// NEON Load/Store with post-increment base updates.1204// TODO: Complete SDTypeProfile constraints.1205def AArch64ld2post : SDNode<"AArch64ISD::LD2post", SDTypeProfile<3, 2, []>,1206 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1207def AArch64ld3post : SDNode<"AArch64ISD::LD3post", SDTypeProfile<4, 2, []>,1208 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1209def AArch64ld4post : SDNode<"AArch64ISD::LD4post", SDTypeProfile<5, 2, []>,1210 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1211def AArch64st2post : SDNode<"AArch64ISD::ST2post", SDTypeProfile<1, 4, []>,1212 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1213def AArch64st3post : SDNode<"AArch64ISD::ST3post", SDTypeProfile<1, 5, []>,1214 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1215def AArch64st4post : SDNode<"AArch64ISD::ST4post", SDTypeProfile<1, 6, []>,1216 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1217def AArch64ld1x2post : SDNode<"AArch64ISD::LD1x2post", SDTypeProfile<3, 2, []>,1218 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1219def AArch64ld1x3post : SDNode<"AArch64ISD::LD1x3post", SDTypeProfile<4, 2, []>,1220 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1221def AArch64ld1x4post : SDNode<"AArch64ISD::LD1x4post", SDTypeProfile<5, 2, []>,1222 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1223def AArch64st1x2post : SDNode<"AArch64ISD::ST1x2post", SDTypeProfile<1, 4, []>,1224 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1225def AArch64st1x3post : SDNode<"AArch64ISD::ST1x3post", SDTypeProfile<1, 5, []>,1226 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1227def AArch64st1x4post : SDNode<"AArch64ISD::ST1x4post", SDTypeProfile<1, 6, []>,1228 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1229def AArch64ld1duppost : SDNode<"AArch64ISD::LD1DUPpost", SDTypeProfile<2, 2, []>,1230 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1231def AArch64ld2duppost : SDNode<"AArch64ISD::LD2DUPpost", SDTypeProfile<3, 2, []>,1232 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1233def AArch64ld3duppost: SDNode<"AArch64ISD::LD3DUPpost", SDTypeProfile<4, 2, []>,1234 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1235def AArch64ld4duppost: SDNode<"AArch64ISD::LD4DUPpost", SDTypeProfile<5, 2, []>,1236 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1237def AArch64ld1lanepost: SDNode<"AArch64ISD::LD1LANEpost", SDTypeProfile<2, 4, []>,1238 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1239def AArch64ld2lanepost : SDNode<"AArch64ISD::LD2LANEpost", SDTypeProfile<3, 5, []>,1240 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1241def AArch64ld3lanepost: SDNode<"AArch64ISD::LD3LANEpost", SDTypeProfile<4, 6, []>,1242 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1243def AArch64ld4lanepost: SDNode<"AArch64ISD::LD4LANEpost", SDTypeProfile<5, 7, []>,1244 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1245def AArch64st2lanepost : SDNode<"AArch64ISD::ST2LANEpost", SDTypeProfile<1, 5, []>,1246 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1247def AArch64st3lanepost : SDNode<"AArch64ISD::ST3LANEpost", SDTypeProfile<1, 6, []>,1248 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1249def AArch64st4lanepost : SDNode<"AArch64ISD::ST4LANEpost", SDTypeProfile<1, 7, []>,1250 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1251 1252// Scatter store1253def AArch64sstnt1_index_pred1254 : SDNode<"AArch64ISD::SSTNT1_INDEX_PRED", SDTypeProfile<0, 5, []>,1255 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1256// Non-temporal scatter store1257def AArch64sst1q_index_pred1258 : SDNode<"AArch64ISD::SST1Q_INDEX_PRED", SDTypeProfile<0, 5, []>,1259 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;1260// Non-temporal gather loads1261def AArch64gldnt1_index_merge_zero1262 : SDNode<"AArch64ISD::GLDNT1_INDEX_MERGE_ZERO", SDTypeProfile<1, 4, []>,1263 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1264// Unsigned gather loads.1265def AArch64gld1q_index_merge_zero1266 : SDNode<"AArch64ISD::GLD1Q_INDEX_MERGE_ZERO", SDTypeProfile<1, 4, []>,1267 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;1268 1269// Match add node and also treat an 'or' node is as an 'add' if the or'ed operands1270// have no common bits.1271def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),1272 [(add node:$lhs, node:$rhs), (or node:$lhs, node:$rhs)],[{1273 if (Op.getOpcode() == ISD::ADD)1274 return true;1275 return CurDAG->isADDLike(Op);1276}]> {1277 let GISelPredicateCode = [{1278 return mi_match(MI, MRI, m_GAddLike(m_Reg(), m_Reg()));1279 }];1280}1281 1282// Match mul with enough sign-bits. Can be reduced to a smaller mul operand.1283def smullwithsignbits : PatFrag<(ops node:$l, node:$r), (mul node:$l, node:$r), [{1284 return CurDAG->ComputeNumSignBits(N->getOperand(0)) > 32 &&1285 CurDAG->ComputeNumSignBits(N->getOperand(1)) > 32;1286}]>;1287 1288// Match "nnan" flagged calls to fminnum and fmmaxnum. Then semantically equivalent1289// to fmaximum/fminimum.1290def fmaxnum_nnan : PatFrag<(ops node:$Rn, node:$Rm),1291 (fmaxnum node:$Rn, node:$Rm), [{1292 return N->getFlags().hasNoNaNs();1293 }]>;1294def fminnum_nnan : PatFrag<(ops node:$Rn, node:$Rm),1295 (fminnum node:$Rn, node:$Rm), [{1296 return N->getFlags().hasNoNaNs();1297 }]>;1298 1299//===----------------------------------------------------------------------===//1300 1301//===----------------------------------------------------------------------===//1302 1303// AArch64 Instruction Predicate Definitions.1304// We could compute these on a per-module basis but doing so requires accessing1305// the Function object through the <Target>Subtarget and objections were raised1306// to that (see post-commit review comments for r301750).1307let RecomputePerFunction = 1 in {1308 def ForCodeSize : Predicate<"shouldOptForSize(MF)">;1309 def NotForCodeSize : Predicate<"!shouldOptForSize(MF)">;1310 // Avoid generating STRQro if it is slow, unless we're optimizing for code size.1311 def UseSTRQro : Predicate<"!Subtarget->isSTRQroSlow() || shouldOptForSize(MF)">;1312 1313 // Register restrictions for indirect tail-calls:1314 // - If branch target enforcement is enabled, indirect calls must use x16 or1315 // x17, because these are the only registers which can target the BTI C1316 // instruction.1317 // - If PAuthLR is enabled, x16 is used in the epilogue to hold the address1318 // of the signing instruction. This can't be changed because it is used by a1319 // HINT instruction which only accepts x16. We can't load anything from the1320 // stack after this because the authentication instruction checks that SP is1321 // the same as it was at function entry, so we can't have anything on the1322 // stack.1323 1324 // BTI on, PAuthLR off: x16 or x171325 def TailCallX16X17 : Predicate<[{ MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && !MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() }]>;1326 // BTI on, PAuthLR on: x17 only1327 def TailCallX17 : Predicate<[{ MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() }]>;1328 // BTI off, PAuthLR on: Any non-callee-saved register except x161329 def TailCallNotX16 : Predicate<[{ !MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() }]>;1330 // BTI off, PAuthLR off: Any non-callee-saved register1331 def TailCallAny : Predicate<[{ !MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && !MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() }]>;1332 1333 def SLSBLRMitigation : Predicate<[{ MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() }]>;1334 def NoSLSBLRMitigation : Predicate<[{ !MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() }]>;1335 1336 // Toggles patterns which aren't beneficial in GlobalISel when we aren't1337 // optimizing. This allows us to selectively use patterns without impacting1338 // SelectionDAG's behaviour.1339 // FIXME: One day there will probably be a nicer way to check for this, but1340 // today is not that day.1341 def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasFailedISel() || !MF->getProperties().hasLegalized()">;1342}1343 1344include "AArch64InstrFormats.td"1345include "SVEInstrFormats.td"1346include "SMEInstrFormats.td"1347 1348//===----------------------------------------------------------------------===//1349 1350//===----------------------------------------------------------------------===//1351// Miscellaneous instructions.1352//===----------------------------------------------------------------------===//1353 1354let hasSideEffects = 1, isCodeGenOnly = 1 in {1355let Defs = [SP], Uses = [SP] in {1356// We set Sched to empty list because we expect these instructions to simply get1357// removed in most cases.1358def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),1359 [(AArch64callseq_start timm:$amt1, timm:$amt2)]>,1360 Sched<[]>;1361def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),1362 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>,1363 Sched<[]>;1364 1365}1366 1367let Defs = [SP, NZCV], Uses = [SP] in {1368// Probed stack allocation of a constant size, used in function prologues when1369// stack-clash protection is enabled.1370def PROBED_STACKALLOC : Pseudo<(outs GPR64:$scratch),1371 (ins i64imm:$stacksize, i64imm:$fixed_offset,1372 i64imm:$scalable_offset),1373 []>,1374 Sched<[]>;1375 1376// Probed stack allocation of a variable size, used in function prologues when1377// stack-clash protection is enabled.1378def PROBED_STACKALLOC_VAR : Pseudo<(outs),1379 (ins GPR64sp:$target),1380 []>,1381 Sched<[]>;1382 1383// Probed stack allocations of a variable size, used for allocas of unknown size1384// when stack-clash protection is enabled.1385let usesCustomInserter = 1 in1386def PROBED_STACKALLOC_DYN : Pseudo<(outs),1387 (ins GPR64common:$target),1388 [(AArch64probedalloca GPR64common:$target)]>,1389 Sched<[]>;1390 1391} // Defs = [SP, NZCV], Uses = [SP] in1392} // hasSideEffects = 1, isCodeGenOnly = 11393 1394let isReMaterializable = 1, isCodeGenOnly = 1 in {1395// FIXME: The following pseudo instructions are only needed because remat1396// cannot handle multiple instructions. When that changes, they can be1397// removed, along with the AArch64Wrapper node.1398 1399let AddedComplexity = 10 in1400def LOADgot : Pseudo<(outs GPR64common:$dst), (ins i64imm:$addr),1401 [(set GPR64common:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,1402 Sched<[WriteLDAdr]>;1403 1404// The MOVaddr instruction should match only when the add is not folded1405// into a load or store address.1406def MOVaddr1407 : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),1408 [(set GPR64common:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),1409 tglobaladdr:$low))]>,1410 Sched<[WriteAdrAdr]>;1411def MOVaddrJT1412 : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),1413 [(set GPR64common:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),1414 tjumptable:$low))]>,1415 Sched<[WriteAdrAdr]>;1416def MOVaddrCP1417 : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),1418 [(set GPR64common:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),1419 tconstpool:$low))]>,1420 Sched<[WriteAdrAdr]>;1421def MOVaddrBA1422 : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),1423 [(set GPR64common:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),1424 tblockaddress:$low))]>,1425 Sched<[WriteAdrAdr]>;1426def MOVaddrTLS1427 : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),1428 [(set GPR64common:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),1429 tglobaltlsaddr:$low))]>,1430 Sched<[WriteAdrAdr]>;1431def MOVaddrEXT1432 : Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),1433 [(set GPR64common:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),1434 texternalsym:$low))]>,1435 Sched<[WriteAdrAdr]>;1436// Normally AArch64addlow either gets folded into a following ldr/str,1437// or together with an adrp into MOVaddr above. For cases with TLS, it1438// might appear without either of them, so allow lowering it into a plain1439// add.1440def ADDlowTLS1441 : Pseudo<(outs GPR64sp:$dst), (ins GPR64sp:$src, i64imm:$low),1442 [(set GPR64sp:$dst, (AArch64addlow GPR64sp:$src,1443 tglobaltlsaddr:$low))]>,1444 Sched<[WriteAdr]>;1445 1446} // isReMaterializable, isCodeGenOnly1447 1448def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),1449 (LOADgot tglobaltlsaddr:$addr)>;1450 1451def : Pat<(AArch64LOADgot texternalsym:$addr),1452 (LOADgot texternalsym:$addr)>;1453 1454def : Pat<(AArch64LOADgot tconstpool:$addr),1455 (LOADgot tconstpool:$addr)>;1456 1457// In general these get lowered into a sequence of three 4-byte instructions.1458// 32-bit jump table destination is actually only 2 instructions since we can1459// use the table itself as a PC-relative base. But optimization occurs after1460// branch relaxation so be pessimistic.1461let Size = 12, Constraints = "@earlyclobber $dst,@earlyclobber $scratch",1462 isNotDuplicable = 1 in {1463def JumpTableDest32 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch),1464 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,1465 Sched<[]>;1466def JumpTableDest16 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch),1467 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,1468 Sched<[]>;1469def JumpTableDest8 : Pseudo<(outs GPR64:$dst, GPR64sp:$scratch),1470 (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,1471 Sched<[]>;1472}1473 1474// A hardened but more expensive version of jump-table dispatch.1475// This combines the target address computation (otherwise done using the1476// JumpTableDest pseudos above) with the branch itself (otherwise done using1477// a plain BR) in a single non-attackable sequence.1478//1479// We take the final entry index as an operand to allow isel freedom. This does1480// mean that the index can be attacker-controlled. To address that, we also do1481// limited checking of the offset, mainly ensuring it still points within the1482// jump-table array. When it doesn't, this branches to the first entry.1483// We might want to trap instead.1484//1485// This is intended for use in conjunction with ptrauth for other code pointers,1486// to avoid signing jump-table entries and turning them into pointers.1487//1488// Entry index is passed in x16. Clobbers x16/x17/nzcv.1489let isNotDuplicable = 1 in1490def BR_JumpTable : Pseudo<(outs), (ins i32imm:$jti), []>, Sched<[]> {1491 let isBranch = 1;1492 let isTerminator = 1;1493 let isIndirectBranch = 1;1494 let isBarrier = 1;1495 let isNotDuplicable = 1;1496 let Defs = [X16,X17,NZCV];1497 let Uses = [X16];1498 let Size = 44; // 28 fixed + 16 variable, for table size materialization1499}1500 1501// Space-consuming pseudo to aid testing of placement and reachability1502// algorithms. Immediate operand is the number of bytes this "instruction"1503// occupies; register operands can be used to enforce dependency and constrain1504// the scheduler.1505let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in1506def SPACE : Pseudo<(outs GPR64:$Rd), (ins i32imm:$size, GPR64:$Rn),1507 [(set GPR64:$Rd, (int_aarch64_space imm:$size, GPR64:$Rn))]>,1508 Sched<[]>;1509 1510let hasSideEffects = 1, isCodeGenOnly = 1 in {1511 def SpeculationSafeValueX1512 : Pseudo<(outs GPR64:$dst), (ins GPR64:$src), []>, Sched<[]>;1513 def SpeculationSafeValueW1514 : Pseudo<(outs GPR32:$dst), (ins GPR32:$src), []>, Sched<[]>;1515}1516 1517// SpeculationBarrierEndBB must only be used after an unconditional control1518// flow, i.e. after a terminator for which isBarrier is True.1519let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in {1520 // This gets lowered to a pair of 4-byte instructions.1521 let Size = 8 in1522 def SpeculationBarrierISBDSBEndBB1523 : Pseudo<(outs), (ins), []>, Sched<[]>;1524 // This gets lowered to a 4-byte instruction.1525 let Size = 4 in1526 def SpeculationBarrierSBEndBB1527 : Pseudo<(outs), (ins), []>, Sched<[]>;1528}1529 1530//===----------------------------------------------------------------------===//1531// System instructions.1532//===----------------------------------------------------------------------===//1533 1534def HINT : HintI<"hint">;1535def : InstAlias<"nop", (HINT 0b000)>;1536def : InstAlias<"yield",(HINT 0b001)>;1537def : InstAlias<"wfe", (HINT 0b010)>;1538def : InstAlias<"wfi", (HINT 0b011)>;1539def : InstAlias<"sev", (HINT 0b100)>;1540def : InstAlias<"sevl", (HINT 0b101)>;1541def : InstAlias<"dgh", (HINT 0b110)>;1542def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>;1543def : InstAlias<"csdb", (HINT 20)>;1544 1545let Predicates = [HasPCDPHINT] in {1546 def STSHH: STSHHI;1547}1548 1549// In order to be able to write readable assembly, LLVM should accept assembly1550// inputs that use Branch Target Identification mnemonics, even with BTI disabled.1551// However, in order to be compatible with other assemblers (e.g. GAS), LLVM1552// should not emit these mnemonics unless BTI is enabled.1553def : InstAlias<"bti", (HINT 32), 0>;1554def : InstAlias<"bti $op", (HINT btihint_op:$op), 0>;1555def : InstAlias<"bti r", (HINT 32)>, Requires<[HasBTIE]>;1556def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>;1557def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>;1558 1559// v8.2a Statistical Profiling extension1560def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;1561 1562// As far as LLVM is concerned this writes to the system's exclusive monitors.1563let mayLoad = 1, mayStore = 1 in1564def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;1565 1566// NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot1567// model patterns with sufficiently fine granularity.1568let mayLoad = ?, mayStore = ? in {1569def DMB : CRmSystemI<barrier_op, 0b101, "dmb",1570 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;1571 1572def DSB : CRmSystemI<barrier_op, 0b100, "dsb",1573 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;1574 1575def ISB : CRmSystemI<barrier_op, 0b110, "isb",1576 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;1577 1578def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> {1579 let CRm = 0b0010;1580 let Inst{12} = 0;1581 let Predicates = [HasTRACEV8_4];1582}1583 1584def DSBnXS : CRmSystemI<barrier_nxs_op, 0b001, "dsb"> {1585 let CRm{1-0} = 0b11;1586 let Inst{9-8} = 0b10;1587 let Predicates = [HasXS];1588}1589 1590let Predicates = [HasWFxT] in {1591def WFET : RegInputSystemI<0b0000, 0b000, "wfet">;1592def WFIT : RegInputSystemI<0b0000, 0b001, "wfit">;1593}1594 1595// Branch Record Buffer two-word mnemonic instructions1596class BRBEI<bits<3> op2, string keyword>1597 : SimpleSystemI<0, (ins), "brb", keyword>, Sched<[WriteSys]> {1598 let Inst{31-8} = 0b110101010000100101110010;1599 let Inst{7-5} = op2;1600 let Predicates = [HasBRBE];1601}1602def BRB_IALL: BRBEI<0b100, "\tiall">;1603def BRB_INJ: BRBEI<0b101, "\tinj">;1604 1605}1606 1607// Allow uppercase and lowercase keyword arguments for BRB IALL and BRB INJ1608def : TokenAlias<"INJ", "inj">;1609def : TokenAlias<"IALL", "iall">;1610 1611 1612// ARMv9.4-A Guarded Control Stack1613class GCSNoOp<bits<3> op2, string mnemonic>1614 : SimpleSystemI<0, (ins), mnemonic, "">, Sched<[]> {1615 let Inst{20-8} = 0b0100001110111;1616 let Inst{7-5} = op2;1617 let Predicates = [HasGCS];1618}1619def GCSPUSHX : GCSNoOp<0b100, "gcspushx">;1620def GCSPOPCX : GCSNoOp<0b101, "gcspopcx">;1621def GCSPOPX : GCSNoOp<0b110, "gcspopx">;1622 1623class GCSRtIn<bits<3> op1, bits<3> op2, string mnemonic,1624 list<dag> pattern = []>1625 : RtSystemI<0, (outs), (ins GPR64:$Rt), mnemonic, "\t$Rt", pattern> {1626 let Inst{20-19} = 0b01;1627 let Inst{18-16} = op1;1628 let Inst{15-8} = 0b01110111;1629 let Inst{7-5} = op2;1630 let Predicates = [HasGCS];1631 let hasSideEffects = 1;1632}1633 1634let mayStore = 1, mayLoad = 1 in1635def GCSSS1 : GCSRtIn<0b011, 0b010, "gcsss1">;1636let mayStore = 1 in1637def GCSPUSHM : GCSRtIn<0b011, 0b000, "gcspushm">;1638 1639class GCSRtOut<bits<3> op1, bits<3> op2, string mnemonic,1640 list<dag> pattern = []>1641 : RtSystemI<1, (outs GPR64:$Rt), (ins GPR64:$src), mnemonic, "\t$Rt", pattern> {1642 let Inst{20-19} = 0b01;1643 let Inst{18-16} = op1;1644 let Inst{15-8} = 0b01110111;1645 let Inst{7-5} = op2;1646 let Predicates = [HasGCS];1647 let hasSideEffects = 1;1648 // The input register is unchanged when GCS is disabled, so we need it as1649 // both an input and output operand.1650 let Constraints = "$src = $Rt";1651}1652 1653let mayStore = 1, mayLoad = 1 in1654def GCSSS2 : GCSRtOut<0b011, 0b011, "gcsss2">;1655// FIXME: mayStore = 1 only needed to match the intrinsic definition1656let mayStore = 1, mayLoad = 1 in1657def GCSPOPM : GCSRtOut<0b011, 0b001, "gcspopm",1658 [(set GPR64:$Rt, (int_aarch64_gcspopm GPR64:$src))]>;1659def GCSPOPM_NoOp : InstAlias<"gcspopm", (GCSPOPM XZR)>, Requires<[HasGCS]>; // Rt defaults to XZR if absent1660 1661def GCSB_DSYNC_disable : InstAlias<"gcsb\tdsync", (HINT 19), 0>;1662def GCSB_DSYNC : InstAlias<"gcsb\tdsync", (HINT 19), 1>, Requires<[HasGCS]>;1663 1664def : TokenAlias<"DSYNC", "dsync">;1665 1666let Uses = [X16], Defs = [X16], CRm = 0b0101 in {1667 def CHKFEAT : SystemNoOperands<0b000, "hint\t#40",1668 [(set X16, (int_aarch64_chkfeat X16))]>;1669}1670def : InstAlias<"chkfeat\tx16", (CHKFEAT), 0>;1671def : InstAlias<"chkfeat\tx16", (CHKFEAT), 1>, Requires<[HasCHK]>;1672 1673class GCSSt<string mnemonic, bits<3> op>1674 : I<(outs), (ins GPR64:$Rt, GPR64sp:$Rn), mnemonic, "\t$Rt, [$Rn]", "", []>, Sched<[]> {1675 bits<5> Rt;1676 bits<5> Rn;1677 let Inst{31-15} = 0b11011001000111110;1678 let Inst{14-12} = op;1679 let Inst{11-10} = 0b11;1680 let Inst{9-5} = Rn;1681 let Inst{4-0} = Rt;1682 let Predicates = [HasGCS];1683}1684def GCSSTR : GCSSt<"gcsstr", 0b000>;1685def GCSSTTR : GCSSt<"gcssttr", 0b001>;1686 1687// ARMv8.2-A Dot Product1688let Predicates = [HasDotProd] in {1689defm SDOT : SIMDThreeSameVectorDot<0, 0, "sdot", AArch64sdot>;1690defm UDOT : SIMDThreeSameVectorDot<1, 0, "udot", AArch64udot>;1691defm SDOTlane : SIMDThreeSameVectorDotIndex<0, 0, 0b10, "sdot", AArch64sdot>;1692defm UDOTlane : SIMDThreeSameVectorDotIndex<1, 0, 0b10, "udot", AArch64udot>;1693}1694 1695let Predicates = [HasNEON, HasDotProd] in {1696 def : Pat<(v4i32 (partial_reduce_umla (v4i32 V128:$Acc), (v16i8 V128:$MulLHS), (v16i8 V128:$MulRHS))),1697 (v4i32 (UDOTv16i8 V128:$Acc, V128:$MulLHS, V128:$MulRHS))>;1698 def : Pat<(v4i32 (partial_reduce_smla (v4i32 V128:$Acc), (v16i8 V128:$MulLHS), (v16i8 V128:$MulRHS))),1699 (v4i32 (SDOTv16i8 V128:$Acc, V128:$MulLHS, V128:$MulRHS))>;1700 def : Pat<(v2i32 (partial_reduce_umla (v2i32 V64:$Acc), (v8i8 V64:$MulLHS), (v8i8 V64:$MulRHS))),1701 (v2i32 (UDOTv8i8 V64:$Acc, V64:$MulLHS, V64:$MulRHS))>;1702 def : Pat<(v2i32 (partial_reduce_smla (v2i32 V64:$Acc), (v8i8 V64:$MulLHS), (v8i8 V64:$MulRHS))),1703 (v2i32 (SDOTv8i8 V64:$Acc, V64:$MulLHS, V64:$MulRHS))>; 1704} // End HasNEON, HasDotProd1705 1706// ARMv8.6-A BFloat1707let Predicates = [HasNEON, HasBF16] in {1708defm BFDOT : SIMDThreeSameVectorBFDot<1, "bfdot">;1709defm BF16DOTlane : SIMDThreeSameVectorBF16DotI<0, "bfdot">;1710def BFMMLA : SIMDThreeSameVectorBF16MatrixMul<"bfmmla">;1711def BFMLALB : SIMDBF16MLAL<0, "bfmlalb", int_aarch64_neon_bfmlalb>;1712def BFMLALT : SIMDBF16MLAL<1, "bfmlalt", int_aarch64_neon_bfmlalt>;1713def BFMLALBIdx : SIMDBF16MLALIndex<0, "bfmlalb", int_aarch64_neon_bfmlalb>;1714def BFMLALTIdx : SIMDBF16MLALIndex<1, "bfmlalt", int_aarch64_neon_bfmlalt>;1715def BFCVTN : SIMD_BFCVTN;1716def BFCVTN2 : SIMD_BFCVTN2;1717 1718def : Pat<(concat_vectors (v4bf16 V64:$Rd), (any_fpround (v4f32 V128:$Rn))),1719 (BFCVTN2 (v8bf16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub)), V128:$Rn)>;1720 1721// Vector-scalar BFDOT:1722// The second source operand of the 64-bit variant of BF16DOTlane is a 128-bit1723// register (the instruction uses a single 32-bit lane from it), so the pattern1724// is a bit tricky.1725def : Pat<(v2f32 (int_aarch64_neon_bfdot1726 (v2f32 V64:$Rd), (v4bf16 V64:$Rn),1727 (v4bf16 (bitconvert1728 (v2i32 (AArch64duplane321729 (v4i32 (bitconvert1730 (v8bf16 (insert_subvector undef,1731 (v4bf16 V64:$Rm),1732 (i64 0))))),1733 VectorIndexS:$idx)))))),1734 (BF16DOTlanev4bf16 (v2f32 V64:$Rd), (v4bf16 V64:$Rn),1735 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),1736 VectorIndexS:$idx)>;1737}1738 1739let Predicates = [HasNEONandIsStreamingSafe, HasBF16] in {1740def BFCVT : BF16ToSinglePrecision<"bfcvt">;1741}1742 1743// ARMv8.6A AArch64 matrix multiplication1744let Predicates = [HasMatMulInt8] in {1745def SMMLA : SIMDThreeSameVectorMatMul<0, 0, "smmla", int_aarch64_neon_smmla>;1746def UMMLA : SIMDThreeSameVectorMatMul<0, 1, "ummla", int_aarch64_neon_ummla>;1747def USMMLA : SIMDThreeSameVectorMatMul<1, 0, "usmmla", int_aarch64_neon_usmmla>;1748defm USDOT : SIMDThreeSameVectorDot<0, 1, "usdot", AArch64usdot>;1749defm USDOTlane : SIMDThreeSameVectorDotIndex<0, 1, 0b10, "usdot", AArch64usdot>;1750 1751// sudot lane has a pattern where usdot is expected (there is no sudot).1752// The second operand is used in the dup operation to repeat the indexed1753// element.1754class BaseSIMDSUDOTIndex<bit Q, string dst_kind, string lhs_kind,1755 string rhs_kind, RegisterOperand RegType,1756 ValueType AccumType, ValueType InputType>1757 : BaseSIMDThreeSameVectorIndexS<Q, 0, 0b00, 0b1111, "sudot", dst_kind,1758 lhs_kind, rhs_kind, RegType, AccumType,1759 InputType, VectorIndexS, null_frag> {1760 let Pattern = [(set (AccumType RegType:$dst),1761 (AccumType (AArch64usdot (AccumType RegType:$Rd),1762 (InputType (bitconvert (AccumType1763 (AArch64duplane32 (v4i32 V128:$Rm),1764 VectorIndexS:$idx)))),1765 (InputType RegType:$Rn))))];1766}1767 1768multiclass SIMDSUDOTIndex {1769 def v8i8 : BaseSIMDSUDOTIndex<0, ".2s", ".8b", ".4b", V64, v2i32, v8i8>;1770 def v16i8 : BaseSIMDSUDOTIndex<1, ".4s", ".16b", ".4b", V128, v4i32, v16i8>;1771}1772 1773defm SUDOTlane : SIMDSUDOTIndex;1774 1775def : Pat<(v2i32 (partial_reduce_sumla v2i32:$Acc, v8i8:$LHS, v8i8:$RHS)),1776 (USDOTv8i8 $Acc, $RHS, $LHS)>;1777def : Pat<(v4i32 (partial_reduce_sumla v4i32:$Acc, v16i8:$LHS, v16i8:$RHS)),1778 (USDOTv16i8 $Acc, $RHS, $LHS)>;1779 1780}1781 1782// ARMv8.2-A FP16 Fused Multiply-Add Long1783let Predicates = [HasNEON, HasFP16FML] in {1784defm FMLAL : SIMDThreeSameVectorFML<0, 1, 0b001, "fmlal", int_aarch64_neon_fmlal>;1785defm FMLSL : SIMDThreeSameVectorFML<0, 1, 0b101, "fmlsl", int_aarch64_neon_fmlsl>;1786defm FMLAL2 : SIMDThreeSameVectorFML<1, 0, 0b001, "fmlal2", int_aarch64_neon_fmlal2>;1787defm FMLSL2 : SIMDThreeSameVectorFML<1, 0, 0b101, "fmlsl2", int_aarch64_neon_fmlsl2>;1788defm FMLALlane : SIMDThreeSameVectorFMLIndex<0, 0b0000, "fmlal", int_aarch64_neon_fmlal>;1789defm FMLSLlane : SIMDThreeSameVectorFMLIndex<0, 0b0100, "fmlsl", int_aarch64_neon_fmlsl>;1790defm FMLAL2lane : SIMDThreeSameVectorFMLIndex<1, 0b1000, "fmlal2", int_aarch64_neon_fmlal2>;1791defm FMLSL2lane : SIMDThreeSameVectorFMLIndex<1, 0b1100, "fmlsl2", int_aarch64_neon_fmlsl2>;1792}1793 1794// Armv8.2-A Crypto extensions1795let Predicates = [HasSHA3] in {1796def SHA512H : CryptoRRRTied<0b0, 0b00, "sha512h">;1797def SHA512H2 : CryptoRRRTied<0b0, 0b01, "sha512h2">;1798def SHA512SU0 : CryptoRRTied_2D<0b0, 0b00, "sha512su0">;1799def SHA512SU1 : CryptoRRRTied_2D<0b0, 0b10, "sha512su1">;1800def RAX1 : CryptoRRR_2D<0b0,0b11, "rax1">;1801def EOR3 : CryptoRRRR_16B<0b00, "eor3">;1802def BCAX : CryptoRRRR_16B<0b01, "bcax">;1803def XAR : CryptoRRRi6<"xar">;1804 1805class SHA3_pattern<Instruction INST, Intrinsic OpNode, ValueType VecTy>1806 : Pat<(VecTy (OpNode (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))),1807 (INST (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))>;1808 1809def : Pat<(v2i64 (int_aarch64_crypto_sha512su0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),1810 (SHA512SU0 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;1811 1812def : SHA3_pattern<SHA512H, int_aarch64_crypto_sha512h, v2i64>;1813def : SHA3_pattern<SHA512H2, int_aarch64_crypto_sha512h2, v2i64>;1814def : SHA3_pattern<SHA512SU1, int_aarch64_crypto_sha512su1, v2i64>;1815 1816def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v16i8>;1817def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v8i16>;1818def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v4i32>;1819def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v2i64>;1820 1821multiclass EOR3_pattern<ValueType Vec128Ty, ValueType Vec64Ty>{1822 def : Pat<(xor (xor (Vec128Ty V128:$Vn), (Vec128Ty V128:$Vm)), (Vec128Ty V128:$Va)),1823 (EOR3 (Vec128Ty V128:$Vn), (Vec128Ty V128:$Vm), (Vec128Ty V128:$Va))>;1824 def : Pat<(xor (xor (Vec64Ty V64:$Vn), (Vec64Ty V64:$Vm)), (Vec64Ty V64:$Va)),1825 (EXTRACT_SUBREG1826 (EOR31827 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vn, dsub),1828 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vm, dsub),1829 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Va, dsub)),1830 dsub)>;1831}1832 1833defm : EOR3_pattern<v16i8, v8i8>;1834defm : EOR3_pattern<v8i16, v4i16>;1835defm : EOR3_pattern<v4i32, v2i32>;1836defm : EOR3_pattern<v2i64, v1i64>;1837 1838class BCAX_pattern<ValueType VecTy>1839 : Pat<(xor (VecTy V128:$Vn), (and (VecTy V128:$Vm), (vnot (VecTy V128:$Va)))),1840 (BCAX (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;1841 1842def : BCAX_pattern<v16i8>;1843def : BCAX_pattern<v8i16>;1844def : BCAX_pattern<v4i32>;1845def : BCAX_pattern<v2i64>;1846 1847def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v16i8>;1848def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v8i16>;1849def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v4i32>;1850def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v2i64>;1851 1852def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v16i8>;1853def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v8i16>;1854def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v4i32>;1855def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v2i64>;1856 1857def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v16i8>;1858def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v8i16>;1859def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v4i32>;1860def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v2i64>;1861 1862def : Pat<(v2i64 (int_aarch64_crypto_rax1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),1863 (RAX1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;1864 1865def : Pat<(v2i64 (int_aarch64_crypto_xar (v2i64 V128:$Vn), (v2i64 V128:$Vm), (i64 timm0_63:$imm))),1866 (XAR (v2i64 V128:$Vn), (v2i64 V128:$Vm), (timm0_63:$imm))>;1867 1868def : Pat<(xor (v2i64 V128:$Vn), (or (AArch64vlshr (v2i64 V128:$Vm), (i32 63)), (AArch64vshl (v2i64 V128:$Vm), (i32 1)))),1869 (RAX1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;1870 1871} // HasSHA31872 1873let Predicates = [HasSM4] in {1874def SM3TT1A : CryptoRRRi2Tied<0b0, 0b00, "sm3tt1a">;1875def SM3TT1B : CryptoRRRi2Tied<0b0, 0b01, "sm3tt1b">;1876def SM3TT2A : CryptoRRRi2Tied<0b0, 0b10, "sm3tt2a">;1877def SM3TT2B : CryptoRRRi2Tied<0b0, 0b11, "sm3tt2b">;1878def SM3SS1 : CryptoRRRR_4S<0b10, "sm3ss1">;1879def SM3PARTW1 : CryptoRRRTied_4S<0b1, 0b00, "sm3partw1">;1880def SM3PARTW2 : CryptoRRRTied_4S<0b1, 0b01, "sm3partw2">;1881def SM4ENCKEY : CryptoRRR_4S<0b1, 0b10, "sm4ekey">;1882def SM4E : CryptoRRTied_4S<0b0, 0b01, "sm4e">;1883 1884def : Pat<(v4i32 (int_aarch64_crypto_sm3ss1 (v4i32 V128:$Vn), (v4i32 V128:$Vm), (v4i32 V128:$Va))),1885 (SM3SS1 (v4i32 V128:$Vn), (v4i32 V128:$Vm), (v4i32 V128:$Va))>;1886 1887class SM3PARTW_pattern<Instruction INST, Intrinsic OpNode>1888 : Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))),1889 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))>;1890 1891class SM3TT_pattern<Instruction INST, Intrinsic OpNode>1892 : Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (i64 VectorIndexS_timm:$imm) )),1893 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (VectorIndexS_timm:$imm))>;1894 1895class SM4_pattern<Instruction INST, Intrinsic OpNode>1896 : Pat<(v4i32 (OpNode (v4i32 V128:$Vn), (v4i32 V128:$Vm))),1897 (INST (v4i32 V128:$Vn), (v4i32 V128:$Vm))>;1898 1899def : SM3PARTW_pattern<SM3PARTW1, int_aarch64_crypto_sm3partw1>;1900def : SM3PARTW_pattern<SM3PARTW2, int_aarch64_crypto_sm3partw2>;1901 1902def : SM3TT_pattern<SM3TT1A, int_aarch64_crypto_sm3tt1a>;1903def : SM3TT_pattern<SM3TT1B, int_aarch64_crypto_sm3tt1b>;1904def : SM3TT_pattern<SM3TT2A, int_aarch64_crypto_sm3tt2a>;1905def : SM3TT_pattern<SM3TT2B, int_aarch64_crypto_sm3tt2b>;1906 1907def : SM4_pattern<SM4ENCKEY, int_aarch64_crypto_sm4ekey>;1908def : SM4_pattern<SM4E, int_aarch64_crypto_sm4e>;1909} // HasSM41910 1911let Predicates = [HasRCPC] in {1912 // v8.3 Release Consistent Processor Consistent support, optional in v8.2.1913 def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>;1914 def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>;1915 def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>;1916 def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>;1917}1918 1919// v8.3a complex add and multiply-accumulate. No predicate here, that is done1920// inside the multiclass as the FP16 versions need different predicates.1921defm FCMLA : SIMDThreeSameVectorTiedComplexHSD<1, 0b110, complexrotateop,1922 "fcmla", null_frag>;1923defm FCADD : SIMDThreeSameVectorComplexHSD<1, 0b111, complexrotateopodd,1924 "fcadd", null_frag>;1925defm FCMLA : SIMDIndexedTiedComplexHSD<0, 1, complexrotateop, "fcmla">;1926 1927let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {1928 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot90 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),1929 (FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 0))>;1930 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot270 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),1931 (FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 1))>;1932 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot90 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),1933 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 0))>;1934 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot270 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),1935 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 1))>;1936}1937 1938let Predicates = [HasComplxNum, HasNEON] in {1939 def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot90 (v2f32 V64:$Rn), (v2f32 V64:$Rm))),1940 (FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 0))>;1941 def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot270 (v2f32 V64:$Rn), (v2f32 V64:$Rm))),1942 (FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 1))>;1943 foreach Ty = [v4f32, v2f64] in {1944 def : Pat<(Ty (int_aarch64_neon_vcadd_rot90 (Ty V128:$Rn), (Ty V128:$Rm))),1945 (!cast<Instruction>("FCADD"#Ty) (Ty V128:$Rn), (Ty V128:$Rm), (i32 0))>;1946 def : Pat<(Ty (int_aarch64_neon_vcadd_rot270 (Ty V128:$Rn), (Ty V128:$Rm))),1947 (!cast<Instruction>("FCADD"#Ty) (Ty V128:$Rn), (Ty V128:$Rm), (i32 1))>;1948 }1949}1950 1951multiclass FCMLA_PATS<ValueType ty, DAGOperand Reg> {1952 def : Pat<(ty (int_aarch64_neon_vcmla_rot0 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))),1953 (!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 0)>;1954 def : Pat<(ty (int_aarch64_neon_vcmla_rot90 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))),1955 (!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 1)>;1956 def : Pat<(ty (int_aarch64_neon_vcmla_rot180 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))),1957 (!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 2)>;1958 def : Pat<(ty (int_aarch64_neon_vcmla_rot270 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))),1959 (!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 3)>;1960}1961 1962multiclass FCMLA_LANE_PATS<ValueType ty, DAGOperand Reg, dag RHSDup> {1963 def : Pat<(ty (int_aarch64_neon_vcmla_rot0 (ty Reg:$Rd), (ty Reg:$Rn), RHSDup)),1964 (!cast<Instruction>("FCMLA" # ty # "_indexed") $Rd, $Rn, $Rm, VectorIndexS:$idx, 0)>;1965 def : Pat<(ty (int_aarch64_neon_vcmla_rot90 (ty Reg:$Rd), (ty Reg:$Rn), RHSDup)),1966 (!cast<Instruction>("FCMLA" # ty # "_indexed") $Rd, $Rn, $Rm, VectorIndexS:$idx, 1)>;1967 def : Pat<(ty (int_aarch64_neon_vcmla_rot180 (ty Reg:$Rd), (ty Reg:$Rn), RHSDup)),1968 (!cast<Instruction>("FCMLA" # ty # "_indexed") $Rd, $Rn, $Rm, VectorIndexS:$idx, 2)>;1969 def : Pat<(ty (int_aarch64_neon_vcmla_rot270 (ty Reg:$Rd), (ty Reg:$Rn), RHSDup)),1970 (!cast<Instruction>("FCMLA" # ty # "_indexed") $Rd, $Rn, $Rm, VectorIndexS:$idx, 3)>;1971}1972 1973 1974let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {1975 defm : FCMLA_PATS<v4f16, V64>;1976 defm : FCMLA_PATS<v8f16, V128>;1977 1978 defm : FCMLA_LANE_PATS<v4f16, V64,1979 (v4f16 (bitconvert (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexD:$idx))))>;1980 defm : FCMLA_LANE_PATS<v8f16, V128,1981 (v8f16 (bitconvert (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))>;1982}1983let Predicates = [HasComplxNum, HasNEON] in {1984 defm : FCMLA_PATS<v2f32, V64>;1985 defm : FCMLA_PATS<v4f32, V128>;1986 defm : FCMLA_PATS<v2f64, V128>;1987 1988 defm : FCMLA_LANE_PATS<v4f32, V128,1989 (v4f32 (bitconvert (v2i64 (AArch64duplane64 (v2i64 V128:$Rm), VectorIndexD:$idx))))>;1990}1991 1992// v8.3a Pointer Authentication1993// These instructions inhabit part of the hint space and so can be used for1994// armv8 targets. Keeping the old HINT mnemonic when compiling without PA is1995// important for compatibility with other assemblers (e.g. GAS) when building1996// software compatible with both CPUs that do or don't implement PA.1997let Uses = [LR], Defs = [LR] in {1998 def PACIAZ : SystemNoOperands<0b000, "hint\t#24">;1999 def PACIBZ : SystemNoOperands<0b010, "hint\t#26">;2000 let isAuthenticated = 1 in {2001 def AUTIAZ : SystemNoOperands<0b100, "hint\t#28">;2002 def AUTIBZ : SystemNoOperands<0b110, "hint\t#30">;2003 }2004}2005let Uses = [LR, SP], Defs = [LR] in {2006 def PACIASP : SystemNoOperands<0b001, "hint\t#25">;2007 def PACIBSP : SystemNoOperands<0b011, "hint\t#27">;2008 let isAuthenticated = 1 in {2009 def AUTIASP : SystemNoOperands<0b101, "hint\t#29">;2010 def AUTIBSP : SystemNoOperands<0b111, "hint\t#31">;2011 }2012}2013let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in {2014 def PACIA1716 : SystemNoOperands<0b000, "hint\t#8">;2015 def PACIB1716 : SystemNoOperands<0b010, "hint\t#10">;2016 let isAuthenticated = 1 in {2017 def AUTIA1716 : SystemNoOperands<0b100, "hint\t#12">;2018 def AUTIB1716 : SystemNoOperands<0b110, "hint\t#14">;2019 }2020}2021 2022let Uses = [LR], Defs = [LR], CRm = 0b0000 in {2023 def XPACLRI : SystemNoOperands<0b111, "hint\t#7">;2024}2025 2026// In order to be able to write readable assembly, LLVM should accept assembly2027// inputs that use pointer authentication mnemonics, even with PA disabled.2028// However, in order to be compatible with other assemblers (e.g. GAS), LLVM2029// should not emit these mnemonics unless PA is enabled.2030def : InstAlias<"paciaz", (PACIAZ), 0>;2031def : InstAlias<"pacibz", (PACIBZ), 0>;2032def : InstAlias<"autiaz", (AUTIAZ), 0>;2033def : InstAlias<"autibz", (AUTIBZ), 0>;2034def : InstAlias<"paciasp", (PACIASP), 0>;2035def : InstAlias<"pacibsp", (PACIBSP), 0>;2036def : InstAlias<"autiasp", (AUTIASP), 0>;2037def : InstAlias<"autibsp", (AUTIBSP), 0>;2038def : InstAlias<"pacia1716", (PACIA1716), 0>;2039def : InstAlias<"pacib1716", (PACIB1716), 0>;2040def : InstAlias<"autia1716", (AUTIA1716), 0>;2041def : InstAlias<"autib1716", (AUTIB1716), 0>;2042def : InstAlias<"xpaclri", (XPACLRI), 0>;2043 2044// Pseudos2045 2046let Uses = [LR, SP], Defs = [LR] in {2047// Insertion point of LR signing code.2048def PAUTH_PROLOGUE : Pseudo<(outs), (ins), []>, Sched<[]> {2049 // When using PAuthLR, the address of one of the instructions this expands2050 // into is used as an input to the signature calculation, so this must not be2051 // duplicated.2052 let isNotDuplicable = 1;2053}2054// Insertion point of LR authentication code.2055// The RET terminator of the containing machine basic block may be replaced2056// with a combined RETA(A|B) instruction when rewriting this Pseudo.2057def PAUTH_EPILOGUE : Pseudo<(outs), (ins), []>, Sched<[]>;2058}2059 2060// These pointer authentication instructions require armv8.3a2061let Predicates = [HasPAuth] in {2062 2063 // When PA is enabled, a better mnemonic should be emitted.2064 def : InstAlias<"paciaz", (PACIAZ), 1>;2065 def : InstAlias<"pacibz", (PACIBZ), 1>;2066 def : InstAlias<"autiaz", (AUTIAZ), 1>;2067 def : InstAlias<"autibz", (AUTIBZ), 1>;2068 def : InstAlias<"paciasp", (PACIASP), 1>;2069 def : InstAlias<"pacibsp", (PACIBSP), 1>;2070 def : InstAlias<"autiasp", (AUTIASP), 1>;2071 def : InstAlias<"autibsp", (AUTIBSP), 1>;2072 def : InstAlias<"pacia1716", (PACIA1716), 1>;2073 def : InstAlias<"pacib1716", (PACIB1716), 1>;2074 def : InstAlias<"autia1716", (AUTIA1716), 1>;2075 def : InstAlias<"autib1716", (AUTIB1716), 1>;2076 def : InstAlias<"xpaclri", (XPACLRI), 1>;2077 2078 multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm,2079 SDPatternOperator op> {2080 def IA : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia"), op>;2081 def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib"), op>;2082 def DA : SignAuthOneData<prefix, 0b10, !strconcat(asm, "da"), op>;2083 def DB : SignAuthOneData<prefix, 0b11, !strconcat(asm, "db"), op>;2084 def IZA : SignAuthZero<prefix_z, 0b00, !strconcat(asm, "iza"), op>;2085 def DZA : SignAuthZero<prefix_z, 0b10, !strconcat(asm, "dza"), op>;2086 def IZB : SignAuthZero<prefix_z, 0b01, !strconcat(asm, "izb"), op>;2087 def DZB : SignAuthZero<prefix_z, 0b11, !strconcat(asm, "dzb"), op>;2088 }2089 2090 defm PAC : SignAuth<0b000, 0b010, "pac", null_frag>;2091 defm AUT : SignAuth<0b001, 0b011, "aut", null_frag>;2092 2093 def XPACI : ClearAuth<0, "xpaci">;2094 def : Pat<(int_ptrauth_strip GPR64:$Rd, 0), (XPACI GPR64:$Rd)>;2095 def : Pat<(int_ptrauth_strip GPR64:$Rd, 1), (XPACI GPR64:$Rd)>;2096 2097 def XPACD : ClearAuth<1, "xpacd">;2098 def : Pat<(int_ptrauth_strip GPR64:$Rd, 2), (XPACD GPR64:$Rd)>;2099 def : Pat<(int_ptrauth_strip GPR64:$Rd, 3), (XPACD GPR64:$Rd)>;2100 2101 def PACGA : SignAuthTwoOperand<0b1100, "pacga", int_ptrauth_sign_generic>;2102 2103 // Combined Instructions2104 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {2105 def BRAA : AuthBranchTwoOperands<0, 0, "braa">;2106 def BRAB : AuthBranchTwoOperands<0, 1, "brab">;2107 }2108 let isCall = 1, Defs = [LR], Uses = [SP] in {2109 def BLRAA : AuthBranchTwoOperands<1, 0, "blraa">;2110 def BLRAB : AuthBranchTwoOperands<1, 1, "blrab">;2111 }2112 2113 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {2114 def BRAAZ : AuthOneOperand<0b000, 0, "braaz">;2115 def BRABZ : AuthOneOperand<0b000, 1, "brabz">;2116 }2117 let isCall = 1, Defs = [LR], Uses = [SP] in {2118 def BLRAAZ : AuthOneOperand<0b001, 0, "blraaz">;2119 def BLRABZ : AuthOneOperand<0b001, 1, "blrabz">;2120 }2121 2122 // BLRA pseudo, a generalized version of BLRAA/BLRAB/Z.2123 // This directly manipulates x16/x17 to materialize the discriminator.2124 // x16/x17 are generally used as the safe registers for sensitive ptrauth2125 // operations (such as raw address manipulation or discriminator2126 // materialization here), in part because they're handled in a safer way by2127 // the kernel, notably on Darwin.2128 def BLRA : Pseudo<(outs), (ins GPR64noip:$Rn, i32imm:$Key, i64imm:$Disc,2129 GPR64:$AddrDisc),2130 [(AArch64authcall GPR64noip:$Rn, timm:$Key, timm:$Disc,2131 GPR64:$AddrDisc)]>, Sched<[]> {2132 let isCodeGenOnly = 1;2133 let hasSideEffects = 1;2134 let mayStore = 0;2135 let mayLoad = 0;2136 let isCall = 1;2137 let Size = 12; // 4 fixed + 8 variable, to compute discriminator.2138 let Defs = [X16,X17,LR];2139 let Uses = [SP];2140 }2141 2142 def BLRA_RVMARKER : Pseudo<2143 (outs), (ins i64imm:$rvfunc, i32imm:$withmarker, GPR64noip:$Rn,2144 i32imm:$Key, i64imm:$Disc, GPR64:$AddrDisc),2145 [(AArch64authcall_rvmarker tglobaladdr:$rvfunc, timm:$withmarker,2146 GPR64noip:$Rn, timm:$Key, timm:$Disc,2147 GPR64:$AddrDisc)]>, Sched<[]> {2148 let isCodeGenOnly = 1;2149 let isCall = 1;2150 let Defs = [X16,X17,LR];2151 let Uses = [SP];2152 }2153 2154 // BRA pseudo, generalized version of BRAA/BRAB/Z.2155 // This directly manipulates x16/x17, which are the only registers the OS2156 // guarantees are safe to use for sensitive operations.2157 def BRA : Pseudo<(outs), (ins GPR64noip:$Rn, i32imm:$Key, i64imm:$Disc,2158 GPR64noip:$AddrDisc), []>, Sched<[]> {2159 let isCodeGenOnly = 1;2160 let hasNoSchedulingInfo = 1;2161 let hasSideEffects = 1;2162 let mayStore = 0;2163 let mayLoad = 0;2164 let isBranch = 1;2165 let isTerminator = 1;2166 let isBarrier = 1;2167 let isIndirectBranch = 1;2168 let Size = 12; // 4 fixed + 8 variable, to compute discriminator.2169 let Defs = [X17];2170 }2171 2172 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {2173 def RETAA : AuthReturn<0b010, 0, "retaa">;2174 def RETAB : AuthReturn<0b010, 1, "retab">;2175 def ERETAA : AuthReturn<0b100, 0, "eretaa">;2176 def ERETAB : AuthReturn<0b100, 1, "eretab">;2177 }2178 2179 defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>;2180 defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>;2181 2182 // AUT pseudo.2183 // This directly manipulates x16/x17, which are the only registers that2184 // certain OSs guarantee are safe to use for sensitive operations.2185 def AUTx16x17 : Pseudo<(outs), (ins i32imm:$Key, i64imm:$Disc,2186 GPR64noip:$AddrDisc),2187 []>, Sched<[WriteI, ReadI]> {2188 let isCodeGenOnly = 1;2189 let hasSideEffects = 1;2190 let mayStore = 0;2191 let mayLoad = 0;2192 let Size = 32;2193 let Defs = [X16,X17,NZCV];2194 let Uses = [X16];2195 }2196 2197 def AUTxMxN : Pseudo<(outs GPR64:$AuthVal, GPR64common:$Scratch),2198 (ins GPR64:$Val, i32imm:$Key,2199 i64imm:$Disc, GPR64:$AddrDisc),2200 [], "$AuthVal = $Val">, Sched<[WriteI, ReadI]> {2201 let isCodeGenOnly = 1;2202 let hasSideEffects = 1;2203 let mayStore = 0;2204 let mayLoad = 0;2205 let Size = 32;2206 let Defs = [NZCV];2207 let Uses = [];2208 }2209 2210 // PAC pseudo instruction. In AsmPrinter, it is expanded into an actual PAC*2211 // instruction immediately preceded by the discriminator computation.2212 // This enforces the expected immediate modifier is used for signing, even2213 // if an attacker is able to substitute AddrDisc.2214 def PAC : Pseudo<(outs GPR64:$SignedVal),2215 (ins GPR64:$Val, i32imm:$Key, i64imm:$Disc, GPR64noip:$AddrDisc),2216 [], "$SignedVal = $Val">, Sched<[WriteI, ReadI]> {2217 let isCodeGenOnly = 1;2218 let hasSideEffects = 0;2219 let mayStore = 0;2220 let mayLoad = 0;2221 let Size = 12;2222 let Defs = [X16, X17];2223 let usesCustomInserter = 1;2224 let supportsDeactivationSymbol = true;2225 }2226 2227 // A standalone pattern is used, so that literal 0 can be passed as $Disc.2228 def : Pat<(int_ptrauth_sign GPR64:$Val, timm:$Key, GPR64noip:$AddrDisc),2229 (PAC GPR64:$Val, $Key, 0, GPR64noip:$AddrDisc)>;2230 2231 // AUT and re-PAC a value, using different keys/data.2232 // This directly manipulates x16/x17, which are the only registers that2233 // certain OSs guarantee are safe to use for sensitive operations.2234 def AUTPAC2235 : Pseudo<(outs),2236 (ins i32imm:$AUTKey, i64imm:$AUTDisc, GPR64noip:$AUTAddrDisc,2237 i32imm:$PACKey, i64imm:$PACDisc, GPR64noip:$PACAddrDisc),2238 []>, Sched<[WriteI, ReadI]> {2239 let isCodeGenOnly = 1;2240 let hasSideEffects = 1;2241 let mayStore = 0;2242 let mayLoad = 0;2243 let Size = 48;2244 let Defs = [X16,X17,NZCV];2245 let Uses = [X16];2246 }2247 2248 // Materialize a signed global address, with adrp+add and PAC.2249 def MOVaddrPAC : Pseudo<(outs),2250 (ins i64imm:$Addr, i32imm:$Key,2251 GPR64noip:$AddrDisc, i64imm:$Disc), []>,2252 Sched<[WriteI, ReadI]> {2253 let isReMaterializable = 1;2254 let isCodeGenOnly = 1;2255 let Size = 40; // 12 fixed + 28 variable, for pointer offset, and discriminator2256 let Defs = [X16,X17];2257 }2258 2259 // Materialize a signed global address, using a GOT load and PAC.2260 def LOADgotPAC : Pseudo<(outs),2261 (ins i64imm:$Addr, i32imm:$Key,2262 GPR64noip:$AddrDisc, i64imm:$Disc), []>,2263 Sched<[WriteI, ReadI]> {2264 let isReMaterializable = 1;2265 let isCodeGenOnly = 1;2266 let Size = 68; // 12 fixed + 56 variable, for pointer offset, discriminator and2267 // ELF signed GOT signed pointer authentication (if no FPAC)2268 let Defs = [X16,X17,NZCV];2269 }2270 2271 def LOADgotAUTH : Pseudo<(outs GPR64common:$dst), (ins i64imm:$addr), []>,2272 Sched<[WriteI, ReadI]> {2273 let Defs = [X16,X17,NZCV];2274 let Size = 44;2275 }2276 2277 // Load a signed global address from a special $auth_ptr$ stub slot.2278 def LOADauthptrstatic : Pseudo<(outs GPR64:$dst),2279 (ins i64imm:$Addr, i32imm:$Key,2280 i64imm:$Disc), []>,2281 Sched<[WriteI, ReadI]> {2282 let isReMaterializable = 1;2283 let isCodeGenOnly = 1;2284 let Size = 8;2285 }2286 2287 // Size 16: 4 fixed + 8 variable, to compute discriminator.2288 // The size returned by getInstSizeInBytes() is incremented according2289 // to the variant of LR check.2290 // As the check requires either x16 or x17 as a scratch register and2291 // authenticated tail call instructions have two register operands,2292 // make sure at least one register is usable as a scratch one - for that2293 // purpose, use tcGPRnotx16x17 register class for one of the operands.2294 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Size = 16,2295 Defs = [X16,X17], Uses = [SP] in {2296 def AUTH_TCRETURN2297 : Pseudo<(outs), (ins tcGPRnotx16x17:$dst, i32imm:$FPDiff, i32imm:$Key,2298 i64imm:$Disc, tcGPR64:$AddrDisc),2299 []>, Sched<[WriteBrReg]>;2300 def AUTH_TCRETURN_BTI2301 : Pseudo<(outs), (ins tcGPRx16x17:$dst, i32imm:$FPDiff, i32imm:$Key,2302 i64imm:$Disc, tcGPRnotx16x17:$AddrDisc),2303 []>, Sched<[WriteBrReg]>;2304 }2305 2306 let Predicates = [TailCallAny] in2307 def : Pat<(AArch64authtcret tcGPRnotx16x17:$dst, (i32 timm:$FPDiff), (i32 timm:$Key),2308 (i64 timm:$Disc), tcGPR64:$AddrDisc),2309 (AUTH_TCRETURN tcGPRnotx16x17:$dst, imm:$FPDiff, imm:$Key, imm:$Disc,2310 tcGPR64:$AddrDisc)>;2311 2312 let Predicates = [TailCallX16X17] in2313 def : Pat<(AArch64authtcret tcGPRx16x17:$dst, (i32 timm:$FPDiff),2314 (i32 timm:$Key), (i64 timm:$Disc),2315 tcGPRnotx16x17:$AddrDisc),2316 (AUTH_TCRETURN_BTI tcGPRx16x17:$dst, imm:$FPDiff, imm:$Key,2317 imm:$Disc, tcGPRnotx16x17:$AddrDisc)>;2318}2319 2320// v9.5-A pointer authentication extensions2321 2322// Always accept "pacm" as an alias for "hint #39", but don't emit it when2323// disassembling if we don't have the pauth-lr feature.2324let CRm = 0b0100 in {2325 def PACM : SystemNoOperands<0b111, "hint\t#39">;2326}2327def : InstAlias<"pacm", (PACM), 0>;2328 2329let Predicates = [HasPAuthLR] in {2330 let Defs = [LR], Uses = [LR, SP] in {2331 // opcode2, opcode, asm2332 def PACIASPPC : SignAuthFixedRegs<0b00001, 0b101000, "paciasppc">;2333 def PACIBSPPC : SignAuthFixedRegs<0b00001, 0b101001, "pacibsppc">;2334 def PACNBIASPPC : SignAuthFixedRegs<0b00001, 0b100000, "pacnbiasppc">;2335 def PACNBIBSPPC : SignAuthFixedRegs<0b00001, 0b100001, "pacnbibsppc">;2336 // opc, asm2337 def AUTIASPPCi : SignAuthPCRel<0b00, "autiasppc">;2338 def AUTIBSPPCi : SignAuthPCRel<0b01, "autibsppc">;2339 // opcode2, opcode, asm2340 def AUTIASPPCr : SignAuthOneReg<0b00001, 0b100100, "autiasppcr">;2341 def AUTIBSPPCr : SignAuthOneReg<0b00001, 0b100101, "autibsppcr">;2342 }2343 let Defs = [X17], Uses = [X15, X16, X17] in {2344 // opcode2, opcode, asm2345 def PACIA171615 : SignAuthFixedRegs<0b00001, 0b100010, "pacia171615">;2346 def PACIB171615 : SignAuthFixedRegs<0b00001, 0b100011, "pacib171615">;2347 def AUTIA171615 : SignAuthFixedRegs<0b00001, 0b101110, "autia171615">;2348 def AUTIB171615 : SignAuthFixedRegs<0b00001, 0b101111, "autib171615">;2349 }2350 2351 let Uses = [LR, SP], isReturn = 1, isTerminator = 1, isBarrier = 1 in {2352 // opc, op2, asm2353 def RETAASPPCi : SignAuthReturnPCRel<0b000, 0b11111, "retaasppc">;2354 def RETABSPPCi : SignAuthReturnPCRel<0b001, 0b11111, "retabsppc">;2355 // op3, asm2356 def RETAASPPCr : SignAuthReturnReg<0b000010, "retaasppcr">;2357 def RETABSPPCr : SignAuthReturnReg<0b000011, "retabsppcr">;2358 }2359 def : InstAlias<"pacm", (PACM), 1>;2360}2361 2362 2363// v8.3a floating point conversion for javascript2364let Predicates = [HasJS, HasFPARMv8], Defs = [NZCV] in2365def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,2366 "fjcvtzs",2367 [(set GPR32:$Rd,2368 (int_aarch64_fjcvtzs FPR64:$Rn))]> {2369 let Inst{31} = 0;2370} // HasJS, HasFPARMv82371 2372// v8.4 Flag manipulation instructions2373let Predicates = [HasFlagM], Defs = [NZCV], Uses = [NZCV] in {2374def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {2375 let Inst{20-5} = 0b0000001000000000;2376 let Unpredictable{11-8} = 0b1111;2377}2378def SETF8 : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">;2379def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">;2380def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif",2381 "{\t$Rn, $imm, $mask}">;2382} // HasFlagM2383 2384// v8.5 flag manipulation instructions2385let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in {2386 2387def XAFLAG : PstateWriteSimple<(ins), "xaflag", "">, Sched<[WriteSys]> {2388 let Inst{18-16} = 0b000;2389 let Inst{11-8} = 0b0000;2390 let Unpredictable{11-8} = 0b1111;2391 let Inst{7-5} = 0b001;2392}2393 2394def AXFLAG : PstateWriteSimple<(ins), "axflag", "">, Sched<[WriteSys]> {2395 let Inst{18-16} = 0b000;2396 let Inst{11-8} = 0b0000;2397 let Unpredictable{11-8} = 0b1111;2398 let Inst{7-5} = 0b010;2399}2400} // HasAltNZCV2401 2402 2403// Armv8.5-A speculation barrier2404def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> {2405 let Inst{20-5} = 0b0001100110000111;2406 let Unpredictable{11-8} = 0b1111;2407 let Predicates = [HasSB];2408 let hasSideEffects = 1;2409}2410 2411def : InstAlias<"clrex", (CLREX 0xf)>;2412def : InstAlias<"isb", (ISB 0xf)>;2413def : InstAlias<"ssbb", (DSB 0)>;2414def : InstAlias<"pssbb", (DSB 4)>;2415def : InstAlias<"dfb", (DSB 0b1100)>, Requires<[HasV8_0r]>;2416 2417def MRS : MRSI;2418def MSR : MSRI;2419def MSRpstateImm1 : MSRpstateImm0_1;2420def MSRpstateImm4 : MSRpstateImm0_15;2421 2422def : Pat<(AArch64mrs imm:$id),2423 (MRS imm:$id)>;2424 2425// The thread pointer (on Linux, at least, where this has been implemented) is2426// TPIDR_EL0.2427def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins),2428 [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>;2429 2430// This gets lowered into a 24-byte instruction sequence2431let Defs = [ X9, X16, X17, NZCV ], Size = 24 in {2432def KCFI_CHECK : Pseudo<2433 (outs), (ins GPR64:$ptr, i32imm:$type), []>, Sched<[]>;2434}2435 2436let Uses = [ X9 ], Defs = [ X16, X17, LR, NZCV ] in {2437def HWASAN_CHECK_MEMACCESS : Pseudo<2438 (outs), (ins GPR64noip:$ptr, i32imm:$accessinfo),2439 [(int_hwasan_check_memaccess X9, GPR64noip:$ptr, (i32 timm:$accessinfo))]>,2440 Sched<[]>;2441}2442 2443let Uses = [ X20 ], Defs = [ X16, X17, LR, NZCV ] in {2444def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo<2445 (outs), (ins GPR64noip:$ptr, i32imm:$accessinfo),2446 [(int_hwasan_check_memaccess_shortgranules X20, GPR64noip:$ptr, (i32 timm:$accessinfo))]>,2447 Sched<[]>;2448}2449 2450let Defs = [ X16, X17, LR, NZCV ] in {2451def HWASAN_CHECK_MEMACCESS_FIXEDSHADOW : Pseudo<2452 (outs), (ins GPR64noip:$ptr, i32imm:$accessinfo, i64imm:$fixed_shadow),2453 [(int_hwasan_check_memaccess_fixedshadow GPR64noip:$ptr, (i32 timm:$accessinfo), (i64 timm:$fixed_shadow))]>,2454 Sched<[]>;2455}2456 2457let Defs = [ X16, X17, LR, NZCV ] in {2458def HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW : Pseudo<2459 (outs), (ins GPR64noip:$ptr, i32imm:$accessinfo, i64imm:$fixed_shadow),2460 [(int_hwasan_check_memaccess_shortgranules_fixedshadow GPR64noip:$ptr, (i32 timm:$accessinfo), (i64 timm:$fixed_shadow))]>,2461 Sched<[]>;2462}2463 2464// The virtual cycle counter register is CNTVCT_EL0.2465def : Pat<(readcyclecounter), (MRS 0xdf02)>;2466 2467// FPCR and FPSR registers.2468let Uses = [FPCR] in2469def MRS_FPCR : Pseudo<(outs GPR64:$dst), (ins),2470 [(set GPR64:$dst, (int_aarch64_get_fpcr))]>,2471 PseudoInstExpansion<(MRS GPR64:$dst, 0xda20)>,2472 Sched<[WriteSys]>;2473let Defs = [FPCR] in2474def MSR_FPCR : Pseudo<(outs), (ins GPR64:$val),2475 [(int_aarch64_set_fpcr i64:$val)]>,2476 PseudoInstExpansion<(MSR 0xda20, GPR64:$val)>,2477 Sched<[WriteSys]>;2478 2479let Uses = [FPSR] in2480def MRS_FPSR : Pseudo<(outs GPR64:$dst), (ins),2481 [(set GPR64:$dst, (int_aarch64_get_fpsr))]>,2482 PseudoInstExpansion<(MRS GPR64:$dst, 0xda21)>,2483 Sched<[WriteSys]>;2484let Defs = [FPSR] in2485def MSR_FPSR : Pseudo<(outs), (ins GPR64:$val),2486 [(int_aarch64_set_fpsr i64:$val)]>,2487 PseudoInstExpansion<(MSR 0xda21, GPR64:$val)>,2488 Sched<[WriteSys]>;2489 2490let Defs = [FPMR] in2491def MSR_FPMR : Pseudo<(outs), (ins GPR64:$val),2492 [(int_aarch64_set_fpmr i64:$val)]>,2493 PseudoInstExpansion<(MSR 0xda22, GPR64:$val)>,2494 Sched<[WriteSys]>;2495 2496// Generic system instructions2497def SYSxt : SystemXtI<0, "sys">;2498def SYSLxt : SystemLXtI<1, "sysl">;2499 2500def : InstAlias<"sys $op1, $Cn, $Cm, $op2",2501 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,2502 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;2503 2504 2505//===----------------------------------------------------------------------===//2506// Move immediate instructions.2507//===----------------------------------------------------------------------===//2508 2509defm MOVK : InsertImmediate<0b11, "movk">;2510defm MOVN : MoveImmediate<0b00, "movn">;2511 2512let PostEncoderMethod = "fixMOVZ" in2513defm MOVZ : MoveImmediate<0b10, "movz">;2514 2515// First group of aliases covers an implicit "lsl #0".2516def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, timm32_0_65535:$imm, 0), 0>;2517def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, timm32_0_65535:$imm, 0), 0>;2518def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, timm32_0_65535:$imm, 0)>;2519def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, timm32_0_65535:$imm, 0)>;2520def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, timm32_0_65535:$imm, 0)>;2521def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, timm32_0_65535:$imm, 0)>;2522 2523// Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.2524def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g3:$sym, 48)>;2525def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g2:$sym, 32)>;2526def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g1:$sym, 16)>;2527def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g0:$sym, 0)>;2528 2529def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g3:$sym, 48)>;2530def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g2:$sym, 32)>;2531def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g1:$sym, 16)>;2532def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g0:$sym, 0)>;2533 2534def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g3:$sym, 48), 0>;2535def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g2:$sym, 32), 0>;2536def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g1:$sym, 16), 0>;2537def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movw_symbol_g0:$sym, 0), 0>;2538 2539def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movw_symbol_g1:$sym, 16)>;2540def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movw_symbol_g0:$sym, 0)>;2541 2542def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movw_symbol_g1:$sym, 16)>;2543def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movw_symbol_g0:$sym, 0)>;2544 2545def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movw_symbol_g1:$sym, 16), 0>;2546def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movw_symbol_g0:$sym, 0), 0>;2547 2548// Final group of aliases covers true "mov $Rd, $imm" cases.2549multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,2550 int width, int shift> {2551 def _asmoperand : AsmOperandClass {2552 let Name = basename # width # "_lsl" # shift # "MovAlias";2553 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "2554 # shift # ">";2555 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";2556 }2557 2558 def _movimm : Operand<i32> {2559 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");2560 }2561 2562 def : InstAlias<"mov $Rd, $imm",2563 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;2564}2565 2566defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;2567defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;2568 2569defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;2570defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;2571defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;2572defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;2573 2574defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;2575defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;2576 2577defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;2578defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;2579defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;2580defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;2581 2582let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,2583 isAsCheapAsAMove = 1 in {2584// FIXME: The following pseudo instructions are only needed because remat2585// cannot handle multiple instructions. When that changes, we can select2586// directly to the real instructions and get rid of these pseudos.2587 2588def MOVi32imm2589 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),2590 [(set GPR32:$dst, imm:$src)]>,2591 Sched<[WriteImm]>;2592def MOVi64imm2593 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),2594 [(set GPR64:$dst, imm:$src)]>,2595 Sched<[WriteImm]>;2596} // isReMaterializable, isCodeGenOnly2597 2598// If possible, we want to use MOVi32imm even for 64-bit moves. This gives the2599// eventual expansion code fewer bits to worry about getting right. Marshalling2600// the types is a little tricky though:2601def i64imm_32bit : ImmLeaf<i64, [{2602 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);2603}]>;2604 2605def s64imm_32bit : ImmLeaf<i64, [{2606 int64_t Imm64 = static_cast<int64_t>(Imm);2607 return Imm64 >= std::numeric_limits<int32_t>::min() &&2608 Imm64 <= std::numeric_limits<int32_t>::max();2609}]>;2610 2611def trunc_imm : SDNodeXForm<imm, [{2612 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue(), SDLoc(N), MVT::i32);2613}]>;2614 2615def gi_trunc_imm : GICustomOperandRenderer<"renderTruncImm">,2616 GISDNodeXFormEquiv<trunc_imm>;2617 2618let Predicates = [OptimizedGISelOrOtherSelector] in {2619// The SUBREG_TO_REG isn't eliminated at -O0, which can result in pointless2620// copies.2621def : Pat<(i64 i64imm_32bit:$src),2622 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;2623}2624 2625// Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).2626def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{2627return CurDAG->getTargetConstant(2628 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);2629}]>;2630 2631def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{2632return CurDAG->getTargetConstant(2633 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);2634}]>;2635 2636 2637def : Pat<(f32 fpimm:$in),2638 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;2639def : Pat<(f64 fpimm:$in),2640 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;2641 2642 2643// Deal with the various forms of (ELF) large addressing with MOVZ/MOVK2644// sequences.2645def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,2646 tglobaladdr:$g1, tglobaladdr:$g0),2647 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0),2648 tglobaladdr:$g1, 16),2649 tglobaladdr:$g2, 32),2650 tglobaladdr:$g3, 48)>;2651 2652def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,2653 tblockaddress:$g1, tblockaddress:$g0),2654 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g0, 0),2655 tblockaddress:$g1, 16),2656 tblockaddress:$g2, 32),2657 tblockaddress:$g3, 48)>;2658 2659def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,2660 tconstpool:$g1, tconstpool:$g0),2661 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g0, 0),2662 tconstpool:$g1, 16),2663 tconstpool:$g2, 32),2664 tconstpool:$g3, 48)>;2665 2666def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,2667 tjumptable:$g1, tjumptable:$g0),2668 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g0, 0),2669 tjumptable:$g1, 16),2670 tjumptable:$g2, 32),2671 tjumptable:$g3, 48)>;2672 2673 2674//===----------------------------------------------------------------------===//2675// Arithmetic instructions.2676//===----------------------------------------------------------------------===//2677 2678// Add/subtract with carry.2679defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;2680defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;2681 2682def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;2683def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;2684def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;2685def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;2686 2687// Add/subtract2688defm ADD : AddSub<0, "add", "sub", add>;2689defm SUB : AddSub<1, "sub", "add">;2690 2691def : InstAlias<"mov $dst, $src",2692 (ADDWri GPR32sponly:$dst, GPR32sp:$src,2693 (addsub_shifted_imm32 0, 0))>;2694def : InstAlias<"mov $dst, $src",2695 (ADDWri GPR32sp:$dst, GPR32sponly:$src,2696 (addsub_shifted_imm32 0, 0))>;2697def : InstAlias<"mov $dst, $src",2698 (ADDXri GPR64sponly:$dst, GPR64sp:$src,2699 (addsub_shifted_imm64 0, 0))>;2700def : InstAlias<"mov $dst, $src",2701 (ADDXri GPR64sp:$dst, GPR64sponly:$src,2702 (addsub_shifted_imm64 0, 0))>;2703 2704defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;2705defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;2706 2707def copyFromSP: PatLeaf<(i64 GPR64:$src), [{2708 return N->getOpcode() == ISD::CopyFromReg &&2709 cast<RegisterSDNode>(N->getOperand(1))->getReg() == AArch64::SP;2710}]>;2711 2712// Use SUBS instead of SUB to enable CSE between SUBS and SUB.2713def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),2714 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;2715def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),2716 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;2717def : Pat<(sub GPR32:$Rn, GPR32:$Rm),2718 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;2719def : Pat<(sub GPR64:$Rn, GPR64:$Rm),2720 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;2721def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),2722 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;2723def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),2724 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;2725let AddedComplexity = 1 in {2726def : Pat<(sub GPR32sp:$R2, arith_extended_reg32_i32:$R3),2727 (SUBSWrx GPR32sp:$R2, arith_extended_reg32_i32:$R3)>;2728def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64_i64:$R3),2729 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64_i64:$R3)>;2730def : Pat<(sub copyFromSP:$R2, (arith_uxtx GPR64:$R3, arith_extendlsl64:$imm)),2731 (SUBXrx64 GPR64sp:$R2, GPR64:$R3, arith_extendlsl64:$imm)>;2732}2733 2734// Because of the immediate format for add/sub-imm instructions, the2735// expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).2736// These patterns capture that transformation.2737let AddedComplexity = 1 in {2738def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),2739 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;2740def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),2741 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;2742def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),2743 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;2744def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),2745 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;2746}2747 2748// Because of the immediate format for add/sub-imm instructions, the2749// expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).2750// These patterns capture that transformation.2751let AddedComplexity = 1 in {2752def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),2753 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;2754def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),2755 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;2756def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),2757 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;2758def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),2759 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;2760}2761 2762 2763def trunc_isWorthFoldingALU : PatFrag<(ops node:$src), (trunc $src)> {2764 let PredicateCode = [{ return isWorthFoldingALU(SDValue(N, 0)); }];2765 let GISelPredicateCode = [{ return isWorthFoldingIntoExtendedReg(MI, MRI, false); }];2766}2767 2768// Patterns for (add X, trunc(shift(Y))), for which we can generate 64bit instructions.2769def : Pat<(add GPR32:$Rn, (trunc_isWorthFoldingALU arith_shifted_reg64:$Rm)),2770 (EXTRACT_SUBREG (ADDXrs (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32),2771 arith_shifted_reg64:$Rm), sub_32)>;2772def : Pat<(sub GPR32:$Rn, (trunc_isWorthFoldingALU arith_shifted_reg64:$Rm)),2773 (EXTRACT_SUBREG (SUBXrs (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32),2774 arith_shifted_reg64:$Rm), sub_32)>;2775 2776def : InstAlias<"neg $dst, $src",2777 (SUBWrs GPR32:$dst, WZR,2778 (arith_shifted_reg32 GPR32:$src, 0)), 3>;2779def : InstAlias<"neg $dst, $src",2780 (SUBXrs GPR64:$dst, XZR,2781 (arith_shifted_reg64 GPR64:$src, 0)), 3>;2782def : InstAlias<"neg $dst, $src$shift",2783 (SUBWrs GPR32:$dst, WZR,2784 (arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)), 2>;2785def : InstAlias<"neg $dst, $src$shift",2786 (SUBXrs GPR64:$dst, XZR,2787 (arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)), 2>;2788 2789def : InstAlias<"negs $dst, $src",2790 (SUBSWrs GPR32:$dst, WZR,2791 (arith_shifted_reg32 GPR32:$src, 0)), 3>;2792def : InstAlias<"negs $dst, $src",2793 (SUBSXrs GPR64:$dst, XZR,2794 (arith_shifted_reg64 GPR64:$src, 0)), 3>;2795def : InstAlias<"negs $dst, $src$shift",2796 (SUBSWrs GPR32:$dst, WZR,2797 (arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)), 2>;2798def : InstAlias<"negs $dst, $src$shift",2799 (SUBSXrs GPR64:$dst, XZR,2800 (arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)), 2>;2801 2802 2803// Unsigned/Signed divide2804defm UDIV : Div<0, "udiv", udiv>;2805defm SDIV : Div<1, "sdiv", sdiv>;2806 2807def : Pat<(int_aarch64_udiv GPR32:$Rn, GPR32:$Rm), (UDIVWr GPR32:$Rn, GPR32:$Rm)>;2808def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr GPR64:$Rn, GPR64:$Rm)>;2809def : Pat<(int_aarch64_sdiv GPR32:$Rn, GPR32:$Rm), (SDIVWr GPR32:$Rn, GPR32:$Rm)>;2810def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr GPR64:$Rn, GPR64:$Rm)>;2811 2812// Variable shift2813defm ASRV : Shift<0b10, "asr", sra>;2814defm LSLV : Shift<0b00, "lsl", shl>;2815defm LSRV : Shift<0b01, "lsr", srl>;2816defm RORV : Shift<0b11, "ror", rotr>;2817 2818def : ShiftAlias<"asrv", ASRVWr, GPR32>;2819def : ShiftAlias<"asrv", ASRVXr, GPR64>;2820def : ShiftAlias<"lslv", LSLVWr, GPR32>;2821def : ShiftAlias<"lslv", LSLVXr, GPR64>;2822def : ShiftAlias<"lsrv", LSRVWr, GPR32>;2823def : ShiftAlias<"lsrv", LSRVXr, GPR64>;2824def : ShiftAlias<"rorv", RORVWr, GPR32>;2825def : ShiftAlias<"rorv", RORVXr, GPR64>;2826 2827// Multiply-add2828let AddedComplexity = 5 in {2829defm MADD : MulAccum<0, "madd">;2830defm MSUB : MulAccum<1, "msub">;2831 2832def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),2833 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;2834def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),2835 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;2836 2837def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),2838 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;2839def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),2840 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;2841def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),2842 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;2843def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),2844 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;2845} // AddedComplexity = 52846 2847let AddedComplexity = 5 in {2848def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;2849def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;2850def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;2851def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;2852 2853def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (sext_inreg GPR64:$Rm, i32))),2854 (SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;2855def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (sext GPR32:$Rm))),2856 (SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;2857def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),2858 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;2859def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (and GPR64:$Rm, 0xFFFFFFFF))),2860 (UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;2861def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (zext GPR32:$Rm))),2862 (UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;2863def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),2864 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;2865 2866def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),2867 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;2868def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),2869 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;2870 2871def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))),2872 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;2873def : Pat<(i64 (mul (zext GPR32:$Rn), (i64imm_32bit:$C))),2874 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;2875def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C))),2876 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),2877 (MOVi32imm (trunc_imm imm:$C)), XZR)>;2878 2879def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),2880 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;2881def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),2882 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;2883def : Pat<(i64 (ineg (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)))),2884 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),2885 (MOVi32imm (trunc_imm imm:$C)), XZR)>;2886 2887def : Pat<(i64 (add (mul (sext GPR32:$Rn), (s64imm_32bit:$C)), GPR64:$Ra)),2888 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;2889def : Pat<(i64 (add (mul (zext GPR32:$Rn), (i64imm_32bit:$C)), GPR64:$Ra)),2890 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;2891def : Pat<(i64 (add (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)),2892 GPR64:$Ra)),2893 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),2894 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;2895 2896def : Pat<(i64 (sub GPR64:$Ra, (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),2897 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;2898def : Pat<(i64 (sub GPR64:$Ra, (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),2899 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;2900def : Pat<(i64 (sub GPR64:$Ra, (mul (sext_inreg GPR64:$Rn, i32),2901 (s64imm_32bit:$C)))),2902 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),2903 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;2904 2905def : Pat<(i64 (smullwithsignbits GPR64:$Rn, GPR64:$Rm)),2906 (SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;2907def : Pat<(i64 (smullwithsignbits GPR64:$Rn, (sext GPR32:$Rm))),2908 (SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;2909 2910def : Pat<(i64 (add (smullwithsignbits GPR64:$Rn, GPR64:$Rm), GPR64:$Ra)),2911 (SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), GPR64:$Ra)>;2912def : Pat<(i64 (add (smullwithsignbits GPR64:$Rn, (sext GPR32:$Rm)), GPR64:$Ra)),2913 (SMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, GPR64:$Ra)>;2914 2915def : Pat<(i64 (ineg (smullwithsignbits GPR64:$Rn, GPR64:$Rm))),2916 (SMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;2917def : Pat<(i64 (ineg (smullwithsignbits GPR64:$Rn, (sext GPR32:$Rm)))),2918 (SMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;2919 2920def : Pat<(i64 (sub GPR64:$Ra, (smullwithsignbits GPR64:$Rn, GPR64:$Rm))),2921 (SMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), GPR64:$Ra)>;2922def : Pat<(i64 (sub GPR64:$Ra, (smullwithsignbits GPR64:$Rn, (sext GPR32:$Rm)))),2923 (SMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, GPR64:$Ra)>;2924 2925def : Pat<(i64 (mul top32Zero:$Rn, top32Zero:$Rm)),2926 (UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;2927def : Pat<(i64 (mul top32Zero:$Rn, (zext GPR32:$Rm))),2928 (UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;2929 2930def : Pat<(i64 (add (mul top32Zero:$Rn, top32Zero:$Rm), GPR64:$Ra)),2931 (UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), GPR64:$Ra)>;2932def : Pat<(i64 (add (mul top32Zero:$Rn, (zext GPR32:$Rm)), GPR64:$Ra)),2933 (UMADDLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, GPR64:$Ra)>;2934 2935def : Pat<(i64 (ineg (mul top32Zero:$Rn, top32Zero:$Rm))),2936 (UMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), XZR)>;2937def : Pat<(i64 (ineg (mul top32Zero:$Rn, (zext GPR32:$Rm)))),2938 (UMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, XZR)>;2939 2940def : Pat<(i64 (sub GPR64:$Ra, (mul top32Zero:$Rn, top32Zero:$Rm))),2941 (UMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), (EXTRACT_SUBREG GPR64:$Rm, sub_32), GPR64:$Ra)>;2942def : Pat<(i64 (sub GPR64:$Ra, (mul top32Zero:$Rn, (zext GPR32:$Rm)))),2943 (UMSUBLrrr (EXTRACT_SUBREG GPR64:$Rn, sub_32), $Rm, GPR64:$Ra)>;2944} // AddedComplexity = 52945 2946def : MulAccumWAlias<"mul", MADDWrrr>;2947def : MulAccumXAlias<"mul", MADDXrrr>;2948def : MulAccumWAlias<"mneg", MSUBWrrr>;2949def : MulAccumXAlias<"mneg", MSUBXrrr>;2950def : WideMulAccumAlias<"smull", SMADDLrrr>;2951def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;2952def : WideMulAccumAlias<"umull", UMADDLrrr>;2953def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;2954 2955// Multiply-high2956def SMULHrr : MulHi<0b010, "smulh", mulhs>;2957def UMULHrr : MulHi<0b110, "umulh", mulhu>;2958 2959// CRC322960def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;2961def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;2962def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;2963def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;2964 2965def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;2966def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;2967def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;2968def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;2969 2970// v8.1 atomic CAS2971defm CAS : CompareAndSwap<0, 0, "">;2972defm CASA : CompareAndSwap<1, 0, "a">;2973defm CASL : CompareAndSwap<0, 1, "l">;2974defm CASAL : CompareAndSwap<1, 1, "al">;2975 2976// v8.1 atomic CASP2977defm CASP : CompareAndSwapPair<0, 0, "">;2978defm CASPA : CompareAndSwapPair<1, 0, "a">;2979defm CASPL : CompareAndSwapPair<0, 1, "l">;2980defm CASPAL : CompareAndSwapPair<1, 1, "al">;2981 2982// v9.6-a atomic CAST2983let Predicates = [HasLSUI] in {2984defm CAST : CompareAndSwapUnprivileged<0b11, 0, 0, "">;2985defm CASLT : CompareAndSwapUnprivileged<0b11, 0, 1, "l">;2986defm CASAT : CompareAndSwapUnprivileged<0b11, 1, 0, "a">;2987defm CASALT : CompareAndSwapUnprivileged<0b11, 1, 1, "al">;2988 2989// v9.6-a atomic CASPT2990defm CASPT : CompareAndSwapPairUnprivileged<0b01, 0, 0, "">;2991defm CASPLT : CompareAndSwapPairUnprivileged<0b01, 0, 1, "l">;2992defm CASPAT : CompareAndSwapPairUnprivileged<0b01, 1, 0, "a">;2993defm CASPALT : CompareAndSwapPairUnprivileged<0b01, 1, 1, "al">;2994}2995 2996// v8.1 atomic SWP2997defm SWP : Swap<0, 0, "">;2998defm SWPA : Swap<1, 0, "a">;2999defm SWPL : Swap<0, 1, "l">;3000defm SWPAL : Swap<1, 1, "al">;3001 3002// v9.6a atomic swap (FEAT_LSUI)3003let Predicates = [HasLSUI] in {3004 defm SWPT : SwapLSUI<0, 0, "">;3005 defm SWPTA : SwapLSUI<1, 0, "a">;3006 defm SWPTL : SwapLSUI<0, 1, "l">;3007 defm SWPTAL : SwapLSUI<1, 1, "al">;3008}3009 3010// v9.6-a unprivileged atomic LD<OP> (FEAT_LSUI)3011let Predicates = [HasLSUI] in {3012 defm LDTADD : LDOPregisterLSUI<0b000, "add", 0, 0, "">;3013 defm LDTADDA : LDOPregisterLSUI<0b000, "add", 1, 0, "a">;3014 defm LDTADDL : LDOPregisterLSUI<0b000, "add", 0, 1, "l">;3015 defm LDTADDAL : LDOPregisterLSUI<0b000, "add", 1, 1, "al">;3016 3017 defm LDTCLR : LDOPregisterLSUI<0b001, "clr", 0, 0, "">;3018 defm LDTCLRA : LDOPregisterLSUI<0b001, "clr", 1, 0, "a">;3019 defm LDTCLRL : LDOPregisterLSUI<0b001, "clr", 0, 1, "l">;3020 defm LDTCLRAL : LDOPregisterLSUI<0b001, "clr", 1, 1, "al">;3021 3022 defm LDTSET : LDOPregisterLSUI<0b011, "set", 0, 0, "">;3023 defm LDTSETA : LDOPregisterLSUI<0b011, "set", 1, 0, "a">;3024 defm LDTSETL : LDOPregisterLSUI<0b011, "set", 0, 1, "l">;3025 defm LDTSETAL : LDOPregisterLSUI<0b011, "set", 1, 1, "al">;3026 3027 defm : STOPregisterLSUI<"sttadd","LDTADD">; // STTADDx3028 defm : STOPregisterLSUI<"sttclr","LDTCLR">; // STTCLRx3029 defm : STOPregisterLSUI<"sttset","LDTSET">; // STTSETx3030}3031 3032// v9.6-a FEAT_RME_GPC33033def APAS : APASI;3034 3035// v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)3036defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;3037defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;3038defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;3039defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;3040 3041defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;3042defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;3043defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;3044defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;3045 3046defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;3047defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;3048defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;3049defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;3050 3051defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;3052defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;3053defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;3054defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;3055 3056defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;3057defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;3058defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;3059defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;3060 3061defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;3062defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;3063defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;3064defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;3065 3066defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;3067defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;3068defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;3069defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;3070 3071defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;3072defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;3073defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;3074defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;3075 3076// v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"3077defm : STOPregister<"stadd","LDADD">; // STADDx3078defm : STOPregister<"stclr","LDCLR">; // STCLRx3079defm : STOPregister<"steor","LDEOR">; // STEORx3080defm : STOPregister<"stset","LDSET">; // STSETx3081defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx3082defm : STOPregister<"stsmin","LDSMIN">;// STSMINx3083defm : STOPregister<"stumax","LDUMAX">;// STUMAXx3084defm : STOPregister<"stumin","LDUMIN">;// STUMINx3085 3086// v8.5 Memory Tagging Extension3087let Predicates = [HasMTE] in {3088 3089def IRG : BaseTwoOperandRegReg<0b1, 0b0, 0b000100, GPR64sp, "irg",3090 int_aarch64_irg, GPR64sp, GPR64>, Sched<[]>;3091 3092def GMI : BaseTwoOperandRegReg<0b1, 0b0, 0b000101, GPR64, "gmi",3093 int_aarch64_gmi, GPR64sp>, Sched<[]> {3094 let isNotDuplicable = 1;3095}3096def ADDG : AddSubG<0, "addg", null_frag>;3097def SUBG : AddSubG<1, "subg", null_frag>;3098 3099def : InstAlias<"irg $dst, $src", (IRG GPR64sp:$dst, GPR64sp:$src, XZR), 1>;3100 3101def SUBP : SUBP<0, "subp", int_aarch64_subp>, Sched<[]>;3102def SUBPS : SUBP<1, "subps", null_frag>, Sched<[]>{3103 let Defs = [NZCV];3104}3105 3106def : InstAlias<"cmpp $lhs, $rhs", (SUBPS XZR, GPR64sp:$lhs, GPR64sp:$rhs), 0>;3107 3108def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">;3109 3110def : Pat<(int_aarch64_addg (am_indexedu6s128 GPR64sp:$Rn, uimm6s16:$imm6), imm0_15:$imm4),3111 (ADDG GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4)>;3112def : Pat<(int_aarch64_ldg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$offset)),3113 (LDG GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;3114 3115def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;3116 3117let mayLoad = 1 in3118def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",3119 (outs GPR64:$Rt), (ins GPR64sp:$Rn)>;3120let mayStore = 1 in {3121def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",3122 (outs), (ins GPR64:$Rt, GPR64sp:$Rn)>;3123def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]",3124 (outs), (ins GPR64:$Rt, GPR64sp:$Rn)> {3125 let Inst{23} = 0;3126}3127} // mayStore = 13128 3129defm STG : MemTagStore<0b00, "stg">;3130defm STZG : MemTagStore<0b01, "stzg">;3131defm ST2G : MemTagStore<0b10, "st2g">;3132defm STZ2G : MemTagStore<0b11, "stz2g">;3133 3134def : Pat<(AArch64stg GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)),3135 (STGi $Rn, $Rm, $imm)>;3136def : Pat<(AArch64stzg GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)),3137 (STZGi $Rn, $Rm, $imm)>;3138def : Pat<(AArch64st2g GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)),3139 (ST2Gi $Rn, $Rm, $imm)>;3140def : Pat<(AArch64stz2g GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)),3141 (STZ2Gi $Rn, $Rm, $imm)>;3142 3143defm STGP : StorePairOffset <0b01, 0, GPR64z, simm7s16, "stgp">;3144def STGPpre : StorePairPreIdx <0b01, 0, GPR64z, simm7s16, "stgp">;3145def STGPpost : StorePairPostIdx<0b01, 0, GPR64z, simm7s16, "stgp">;3146 3147def : Pat<(int_aarch64_stg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$offset)),3148 (STGi GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;3149 3150def : Pat<(int_aarch64_stgp (am_indexed7s128 GPR64sp:$Rn, simm7s16:$imm), GPR64:$Rt, GPR64:$Rt2),3151 (STGPi $Rt, $Rt2, $Rn, $imm)>;3152 3153def IRGstack3154 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rsp, GPR64:$Rm), []>,3155 Sched<[]>;3156def TAGPstack3157 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, uimm6s16:$imm6, GPR64sp:$Rm, imm0_15:$imm4), []>,3158 Sched<[]>;3159 3160// Explicit SP in the first operand prevents ShrinkWrap optimization3161// from leaving this instruction out of the stack frame. When IRGstack3162// is transformed into IRG, this operand is replaced with the actual3163// register / expression for the tagged base pointer of the current function.3164def : Pat<(int_aarch64_irg_sp i64:$Rm), (IRGstack SP, i64:$Rm)>;3165 3166// Large STG to be expanded into a loop. $sz is the size, $Rn is start address.3167// $Rn_wback is one past the end of the range. $Rm is the loop counter.3168let isCodeGenOnly=1, mayStore=1, Defs=[NZCV] in {3169def STGloop_wback3170 : Pseudo<(outs GPR64common:$Rm, GPR64sp:$Rn_wback), (ins i64imm:$sz, GPR64sp:$Rn),3171 [], "$Rn = $Rn_wback,@earlyclobber $Rn_wback,@earlyclobber $Rm" >,3172 Sched<[WriteAdr, WriteST]>;3173 3174def STZGloop_wback3175 : Pseudo<(outs GPR64common:$Rm, GPR64sp:$Rn_wback), (ins i64imm:$sz, GPR64sp:$Rn),3176 [], "$Rn = $Rn_wback,@earlyclobber $Rn_wback,@earlyclobber $Rm" >,3177 Sched<[WriteAdr, WriteST]>;3178 3179// A variant of the above where $Rn2 is an independent register not tied to the input register $Rn.3180// Their purpose is to use a FrameIndex operand as $Rn (which of course can not be written back).3181def STGloop3182 : Pseudo<(outs GPR64common:$Rm, GPR64sp:$Rn2), (ins i64imm:$sz, GPR64sp:$Rn),3183 [], "@earlyclobber $Rn2,@earlyclobber $Rm" >,3184 Sched<[WriteAdr, WriteST]>;3185 3186def STZGloop3187 : Pseudo<(outs GPR64common:$Rm, GPR64sp:$Rn2), (ins i64imm:$sz, GPR64sp:$Rn),3188 [], "@earlyclobber $Rn2,@earlyclobber $Rm" >,3189 Sched<[WriteAdr, WriteST]>;3190}3191 3192} // Predicates = [HasMTE]3193 3194//===----------------------------------------------------------------------===//3195// Logical instructions.3196//===----------------------------------------------------------------------===//3197 3198// (immediate)3199defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;3200defm AND : LogicalImm<0b00, "and", and, "bic">;3201defm EOR : LogicalImm<0b10, "eor", xor, "eon">;3202defm ORR : LogicalImm<0b01, "orr", or, "orn">;3203 3204// FIXME: these aliases *are* canonical sometimes (when movz can't be3205// used). Actually, it seems to be working right now, but putting logical_immXX3206// here is a bit dodgy on the AsmParser side too.3207def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,3208 logical_imm32:$imm), 0>;3209def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,3210 logical_imm64:$imm), 0>;3211 3212 3213// (register)3214defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;3215defm BICS : LogicalRegS<0b11, 1, "bics",3216 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;3217defm AND : LogicalReg<0b00, 0, "and", and>;3218defm BIC : LogicalReg<0b00, 1, "bic",3219 BinOpFrag<(and node:$LHS, (not node:$RHS))>, 3>;3220defm EON : LogicalReg<0b10, 1, "eon",3221 BinOpFrag<(not (xor_like node:$LHS, node:$RHS))>>;3222defm EOR : LogicalReg<0b10, 0, "eor", xor>;3223defm ORN : LogicalReg<0b01, 1, "orn",3224 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;3225defm ORR : LogicalReg<0b01, 0, "orr", or>;3226 3227def : InstAlias<"mov $dst, $src",3228 (ORRWrs GPR32:$dst, WZR,3229 (logical_shifted_reg32 GPR32:$src, 0)), 2>;3230def : InstAlias<"mov $dst, $src", 3231 (ORRXrs GPR64:$dst, XZR,3232 (logical_shifted_reg64 GPR64:$src, 0)), 2>;3233 3234def : InstAlias<"mvn $Wd, $Wm",3235 (ORNWrs GPR32:$Wd, WZR,3236 (logical_shifted_reg32 GPR32:$Wm, 0)), 3>;3237def : InstAlias<"mvn $Xd, $Xm",3238 (ORNXrs GPR64:$Xd, XZR,3239 (logical_shifted_reg64 GPR64:$Xm, 0)), 3>;3240 3241def : InstAlias<"mvn $Wd, $Wm$sh",3242 (ORNWrs GPR32:$Wd, WZR,3243 (logical_shifted_reg32 GPR32:$Wm, logical_shift32:$sh)), 2>;3244def : InstAlias<"mvn $Xd, $Xm$sh",3245 (ORNXrs GPR64:$Xd, XZR,3246 (logical_shifted_reg64 GPR64:$Xm, logical_shift64:$sh)), 2>;3247 3248def : InstAlias<"tst $src1, $src2",3249 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;3250def : InstAlias<"tst $src1, $src2",3251 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;3252 3253def : InstAlias<"tst $src1, $src2",3254 (ANDSWrs WZR, GPR32:$src1,3255 (logical_shifted_reg32 GPR32:$src2, 0)), 3>;3256def : InstAlias<"tst $src1, $src2",3257 (ANDSXrs XZR, GPR64:$src1,3258 (logical_shifted_reg64 GPR64:$src2, 0)), 3>;3259 3260def : InstAlias<"tst $src1, $src2$sh",3261 (ANDSWrs WZR, GPR32:$src1,3262 (logical_shifted_reg32 GPR32:$src2, logical_shift32:$sh)), 2>;3263def : InstAlias<"tst $src1, $src2$sh",3264 (ANDSXrs XZR, GPR64:$src1,3265 (logical_shifted_reg64 GPR64:$src2, logical_shift64:$sh)), 2>;3266 3267 3268def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;3269def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;3270 3271// Emit (and 0xFFFFFFFF) as a ORRWrr move which may be eliminated.3272let AddedComplexity = 6 in3273def : Pat<(i64 (and GPR64:$Rn, 0xffffffff)),3274 (SUBREG_TO_REG (i64 0), (ORRWrr WZR, (EXTRACT_SUBREG GPR64:$Rn, sub_32)), sub_32)>;3275 3276 3277//===----------------------------------------------------------------------===//3278// One operand data processing instructions.3279//===----------------------------------------------------------------------===//3280 3281defm CLS : OneOperandData<0b000101, "cls">;3282defm CLZ : OneOperandData<0b000100, "clz", ctlz>;3283defm RBIT : OneOperandData<0b000000, "rbit", bitreverse>;3284 3285def REV16Wr : OneWRegData<0b000001, "rev16",3286 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;3287def REV16Xr : OneXRegData<0b000001, "rev16", null_frag>;3288 3289def : Pat<(cttz GPR32:$Rn),3290 (CLZWr (RBITWr GPR32:$Rn))>;3291def : Pat<(cttz GPR64:$Rn),3292 (CLZXr (RBITXr GPR64:$Rn))>;3293def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),3294 (i32 1))),3295 (CLSWr GPR32:$Rn)>;3296def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),3297 (i64 1))),3298 (CLSXr GPR64:$Rn)>;3299def : Pat<(int_aarch64_cls GPR32:$Rn), (CLSWr GPR32:$Rn)>;3300def : Pat<(int_aarch64_cls64 GPR64:$Rm), (EXTRACT_SUBREG (CLSXr GPR64:$Rm), sub_32)>;3301 3302// Unlike the other one operand instructions, the instructions with the "rev"3303// mnemonic do *not* just different in the size bit, but actually use different3304// opcode bits for the different sizes.3305def REVWr : OneWRegData<0b000010, "rev", bswap>;3306def REVXr : OneXRegData<0b000011, "rev", bswap>;3307def REV32Xr : OneXRegData<0b000010, "rev32",3308 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;3309 3310def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;3311 3312// The bswap commutes with the rotr so we want a pattern for both possible3313// orders.3314def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;3315def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;3316 3317// Match (srl (bswap x), C) -> revC if the upper bswap bits are known zero.3318def : Pat<(srl (bswap top16Zero:$Rn), (i64 16)), (REV16Wr GPR32:$Rn)>;3319def : Pat<(srl (bswap top32Zero:$Rn), (i64 32)), (REV32Xr GPR64:$Rn)>;3320 3321def : Pat<(AArch64rev16 GPR32:$Rn), (REV16Wr GPR32:$Rn)>;3322def : Pat<(AArch64rev16 GPR64:$Rn), (REV16Xr GPR64:$Rn)>;3323 3324def : Pat<(or (and (srl GPR64:$Rn, (i64 8)), (i64 0x00ff00ff00ff00ff)),3325 (and (shl GPR64:$Rn, (i64 8)), (i64 0xff00ff00ff00ff00))),3326 (REV16Xr GPR64:$Rn)>;3327 3328//===----------------------------------------------------------------------===//3329// Bitfield immediate extraction instruction.3330//===----------------------------------------------------------------------===//3331let hasSideEffects = 0 in3332defm EXTR : ExtractImm<"extr">;3333def : InstAlias<"ror $dst, $src, $shift",3334 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;3335def : InstAlias<"ror $dst, $src, $shift",3336 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;3337 3338def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),3339 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;3340def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),3341 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;3342 3343//===----------------------------------------------------------------------===//3344// Other bitfield immediate instructions.3345//===----------------------------------------------------------------------===//3346let hasSideEffects = 0 in {3347defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;3348defm SBFM : BitfieldImm<0b00, "sbfm">;3349defm UBFM : BitfieldImm<0b10, "ubfm">;3350}3351 3352def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{3353 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;3354 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);3355}]>;3356 3357def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{3358 uint64_t enc = 31 - N->getZExtValue();3359 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);3360}]>;3361 3362// min(7, 31 - shift_amt)3363def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{3364 uint64_t enc = 31 - N->getZExtValue();3365 enc = enc > 7 ? 7 : enc;3366 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);3367}]>;3368 3369// min(15, 31 - shift_amt)3370def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{3371 uint64_t enc = 31 - N->getZExtValue();3372 enc = enc > 15 ? 15 : enc;3373 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);3374}]>;3375 3376def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{3377 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;3378 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);3379}]>;3380 3381def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{3382 uint64_t enc = 63 - N->getZExtValue();3383 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);3384}]>;3385 3386// min(7, 63 - shift_amt)3387def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{3388 uint64_t enc = 63 - N->getZExtValue();3389 enc = enc > 7 ? 7 : enc;3390 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);3391}]>;3392 3393// min(15, 63 - shift_amt)3394def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{3395 uint64_t enc = 63 - N->getZExtValue();3396 enc = enc > 15 ? 15 : enc;3397 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);3398}]>;3399 3400// min(31, 63 - shift_amt)3401def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{3402 uint64_t enc = 63 - N->getZExtValue();3403 enc = enc > 31 ? 31 : enc;3404 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);3405}]>;3406 3407def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),3408 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),3409 (i64 (i32shift_b imm0_31:$imm)))>;3410def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),3411 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),3412 (i64 (i64shift_b imm0_63:$imm)))>;3413 3414let AddedComplexity = 10 in {3415def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),3416 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;3417def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),3418 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;3419}3420 3421def : InstAlias<"asr $dst, $src, $shift",3422 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;3423def : InstAlias<"asr $dst, $src, $shift",3424 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;3425def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;3426def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;3427def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;3428def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;3429def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;3430 3431def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),3432 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;3433def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),3434 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;3435 3436def : InstAlias<"lsr $dst, $src, $shift",3437 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;3438def : InstAlias<"lsr $dst, $src, $shift",3439 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;3440def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;3441def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;3442def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;3443def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;3444def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;3445 3446//===----------------------------------------------------------------------===//3447// Conditional comparison instructions.3448//===----------------------------------------------------------------------===//3449defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>;3450defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>;3451 3452//===----------------------------------------------------------------------===//3453// Conditional select instructions.3454//===----------------------------------------------------------------------===//3455defm CSEL : CondSelect<0, 0b00, "csel">;3456 3457def inc : PatFrag<(ops node:$in), (add_and_or_is_add node:$in, 1)>;3458defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;3459defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;3460defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;3461 3462def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),3463 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;3464def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),3465 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;3466def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),3467 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;3468def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),3469 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;3470def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),3471 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;3472def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),3473 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;3474 3475def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),3476 (CSINCWr WZR, WZR, (i32 imm:$cc))>;3477def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),3478 (CSINCXr XZR, XZR, (i32 imm:$cc))>;3479def : Pat<(AArch64csel GPR32:$tval, (i32 1), (i32 imm:$cc), NZCV),3480 (CSINCWr GPR32:$tval, WZR, (i32 imm:$cc))>;3481def : Pat<(AArch64csel GPR64:$tval, (i64 1), (i32 imm:$cc), NZCV),3482 (CSINCXr GPR64:$tval, XZR, (i32 imm:$cc))>;3483def : Pat<(AArch64csel (i32 1), GPR32:$fval, (i32 imm:$cc), NZCV),3484 (CSINCWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>;3485def : Pat<(AArch64csel (i64 1), GPR64:$fval, (i32 imm:$cc), NZCV),3486 (CSINCXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>;3487def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),3488 (CSINVWr WZR, WZR, (i32 imm:$cc))>;3489def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),3490 (CSINVXr XZR, XZR, (i32 imm:$cc))>;3491def : Pat<(AArch64csel GPR32:$tval, (i32 -1), (i32 imm:$cc), NZCV),3492 (CSINVWr GPR32:$tval, WZR, (i32 imm:$cc))>;3493def : Pat<(AArch64csel GPR64:$tval, (i64 -1), (i32 imm:$cc), NZCV),3494 (CSINVXr GPR64:$tval, XZR, (i32 imm:$cc))>;3495def : Pat<(AArch64csel (i32 -1), GPR32:$fval, (i32 imm:$cc), NZCV),3496 (CSINVWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>;3497def : Pat<(AArch64csel (i64 -1), GPR64:$fval, (i32 imm:$cc), NZCV),3498 (CSINVXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>;3499 3500def : Pat<(add_and_or_is_add GPR32:$val, (AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV)),3501 (CSINCWr GPR32:$val, GPR32:$val, (i32 imm:$cc))>;3502def : Pat<(add_and_or_is_add GPR64:$val, (zext (AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV))),3503 (CSINCXr GPR64:$val, GPR64:$val, (i32 imm:$cc))>;3504 3505def : Pat<(or (topbitsallzero32:$val), (AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV)),3506 (CSINCWr GPR32:$val, WZR, imm:$cc)>;3507def : Pat<(or (topbitsallzero64:$val), (AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV)),3508 (CSINCXr GPR64:$val, XZR, imm:$cc)>;3509def : Pat<(or (topbitsallzero64:$val), (zext (AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV))),3510 (CSINCXr GPR64:$val, XZR, imm:$cc)>;3511 3512def : Pat<(and (topbitsallzero32:$val), (AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV)),3513 (CSELWr WZR, GPR32:$val, imm:$cc)>;3514def : Pat<(and (topbitsallzero64:$val), (AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV)),3515 (CSELXr XZR, GPR64:$val, imm:$cc)>;3516def : Pat<(and (topbitsallzero64:$val), (zext (AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV))),3517 (CSELXr XZR, GPR64:$val, imm:$cc)>;3518 3519// The inverse of the condition code from the alias instruction is what is used3520// in the aliased instruction. The parser all ready inverts the condition code3521// for these aliases.3522def : InstAlias<"cset $dst, $cc",3523 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;3524def : InstAlias<"cset $dst, $cc",3525 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;3526 3527def : InstAlias<"csetm $dst, $cc",3528 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;3529def : InstAlias<"csetm $dst, $cc",3530 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;3531 3532def : InstAlias<"cinc $dst, $src, $cc",3533 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;3534def : InstAlias<"cinc $dst, $src, $cc",3535 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;3536 3537def : InstAlias<"cinv $dst, $src, $cc",3538 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;3539def : InstAlias<"cinv $dst, $src, $cc",3540 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;3541 3542def : InstAlias<"cneg $dst, $src, $cc",3543 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;3544def : InstAlias<"cneg $dst, $src, $cc",3545 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;3546 3547//===----------------------------------------------------------------------===//3548// PC-relative instructions.3549//===----------------------------------------------------------------------===//3550let isReMaterializable = 1 in {3551let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {3552def ADR : ADRI<0, "adr", adrlabel,3553 [(set GPR64:$Xd, (AArch64adr tglobaladdr:$label))]>;3554} // hasSideEffects = 03555 3556def ADRP : ADRI<1, "adrp", adrplabel,3557 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;3558} // isReMaterializable = 13559 3560// page address of a constant pool entry, block address3561def : Pat<(AArch64adr tconstpool:$cp), (ADR tconstpool:$cp)>;3562def : Pat<(AArch64adr tblockaddress:$cp), (ADR tblockaddress:$cp)>;3563def : Pat<(AArch64adr texternalsym:$sym), (ADR texternalsym:$sym)>;3564def : Pat<(AArch64adr tjumptable:$sym), (ADR tjumptable:$sym)>;3565def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;3566def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;3567def : Pat<(AArch64adrp texternalsym:$sym), (ADRP texternalsym:$sym)>;3568 3569//===----------------------------------------------------------------------===//3570// Unconditional branch (register) instructions.3571//===----------------------------------------------------------------------===//3572 3573let isReturn = 1, isTerminator = 1, isBarrier = 1 in {3574def RET : BranchReg<0b0010, "ret", []>;3575def DRPS : SpecialReturn<0b0101, "drps">;3576def ERET : SpecialReturn<0b0100, "eret">;3577} // isReturn = 1, isTerminator = 1, isBarrier = 13578 3579// Default to the LR register.3580def : InstAlias<"ret", (RET LR)>;3581 3582let isCall = 1, Defs = [LR], Uses = [SP] in {3583 def BLR : BranchReg<0b0001, "blr", []>;3584 def BLRNoIP : Pseudo<(outs), (ins GPR64noip:$Rn), []>,3585 Sched<[WriteBrReg]>,3586 PseudoInstExpansion<(BLR GPR64:$Rn)>;3587 def BLR_RVMARKER : Pseudo<(outs), (ins variable_ops), []>,3588 Sched<[WriteBrReg]>;3589 def BLR_BTI : Pseudo<(outs), (ins variable_ops), []>,3590 Sched<[WriteBrReg]>;3591 let Uses = [X16, SP] in3592 def BLR_X16 : Pseudo<(outs), (ins), [(AArch64call_arm64ec_to_x64 X16)]>,3593 Sched<[WriteBrReg]>,3594 PseudoInstExpansion<(BLR X16)>;3595} // isCall3596 3597def : Pat<(AArch64call GPR64:$Rn),3598 (BLR GPR64:$Rn)>,3599 Requires<[NoSLSBLRMitigation]>;3600def : Pat<(AArch64call GPR64noip:$Rn),3601 (BLRNoIP GPR64noip:$Rn)>,3602 Requires<[SLSBLRMitigation]>;3603 3604def : Pat<(AArch64call_rvmarker (i64 tglobaladdr:$rvfunc),3605 (i32 timm:$withmarker), GPR64:$Rn),3606 (BLR_RVMARKER tglobaladdr:$rvfunc, timm:$withmarker, GPR64:$Rn)>,3607 Requires<[NoSLSBLRMitigation]>;3608 3609def : Pat<(AArch64call_bti GPR64:$Rn),3610 (BLR_BTI GPR64:$Rn)>,3611 Requires<[NoSLSBLRMitigation]>;3612def : Pat<(AArch64call_bti GPR64noip:$Rn),3613 (BLR_BTI GPR64noip:$Rn)>,3614 Requires<[SLSBLRMitigation]>;3615 3616let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {3617def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;3618} // isBranch, isTerminator, isBarrier, isIndirectBranch3619 3620// Create a separate pseudo-instruction for codegen to use so that we don't3621// flag lr as used in every function. It'll be restored before the RET by the3622// epilogue if it's legitimately used.3623def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retglue)]>,3624 Sched<[WriteBrReg]> {3625 let isTerminator = 1;3626 let isBarrier = 1;3627 let isReturn = 1;3628}3629 3630// This is a directive-like pseudo-instruction. The purpose is to insert an3631// R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction3632// (which in the usual case is a BLR).3633let hasSideEffects = 1 in3634def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []>, Sched<[]> {3635 let AsmString = ".tlsdesccall $sym";3636}3637 3638// Pseudo instruction to tell the streamer to emit a 'B' character into the3639// augmentation string.3640def EMITBKEY : Pseudo<(outs), (ins), []>, Sched<[]> {}3641 3642// Pseudo instruction to tell the streamer to emit a 'G' character into the3643// augmentation string.3644def EMITMTETAGGED : Pseudo<(outs), (ins), []>, Sched<[]> {}3645 3646// FIXME: maybe the scratch register used shouldn't be fixed to X1?3647// FIXME: can "hasSideEffects be dropped?3648// This gets lowered to an instruction sequence which takes 16 bytes3649let isCall = 1, Defs = [NZCV, LR, X0, X1], hasSideEffects = 1, Size = 16,3650 isCodeGenOnly = 1 in3651def TLSDESC_CALLSEQ3652 : Pseudo<(outs), (ins i64imm:$sym),3653 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>,3654 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;3655let isCall = 1, Defs = [NZCV, LR, X0, X16], hasSideEffects = 1, Size = 16,3656 isCodeGenOnly = 1 in3657def TLSDESC_AUTH_CALLSEQ3658 : Pseudo<(outs), (ins i64imm:$sym),3659 [(AArch64tlsdesc_auth_callseq tglobaltlsaddr:$sym)]>,3660 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;3661def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),3662 (TLSDESC_CALLSEQ texternalsym:$sym)>;3663def : Pat<(AArch64tlsdesc_auth_callseq texternalsym:$sym),3664 (TLSDESC_AUTH_CALLSEQ texternalsym:$sym)>;3665 3666//===----------------------------------------------------------------------===//3667// Conditional branch (immediate) instruction.3668//===----------------------------------------------------------------------===//3669def Bcc : BranchCond<0, "b">;3670 3671// Armv8.8-A variant form which hints to the branch predictor that3672// this branch is very likely to go the same way nearly all the time3673// (even though it is not known at compile time _which_ way that is).3674def BCcc : BranchCond<1, "bc">, Requires<[HasHBC]>;3675 3676//===----------------------------------------------------------------------===//3677// Compare-and-branch instructions.3678//===----------------------------------------------------------------------===//3679defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;3680defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;3681 3682//===----------------------------------------------------------------------===//3683// Test-bit-and-branch instructions.3684//===----------------------------------------------------------------------===//3685defm TBZ : TestBranch<0, "tbz", AArch64tbz>;3686defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;3687 3688//===----------------------------------------------------------------------===//3689// Unconditional branch (immediate) instructions.3690//===----------------------------------------------------------------------===//3691let isBranch = 1, isTerminator = 1, isBarrier = 1 in {3692def B : BranchImm<0, "b", [(br bb:$addr)]>;3693} // isBranch, isTerminator, isBarrier3694 3695let isCall = 1, Defs = [LR], Uses = [SP] in {3696def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;3697} // isCall3698def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;3699 3700//===----------------------------------------------------------------------===//3701// Exception generation instructions.3702//===----------------------------------------------------------------------===//3703let isTrap = 1 in {3704def BRK : ExceptionGeneration<0b001, 0b00, "brk",3705 [(int_aarch64_break timm32_0_65535:$imm)]>;3706}3707def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;3708def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;3709def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">, Requires<[HasEL3]>;3710def HLT : ExceptionGeneration<0b010, 0b00, "hlt",3711 [(int_aarch64_hlt timm32_0_65535:$imm)]>;3712def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;3713def SMC : ExceptionGeneration<0b000, 0b11, "smc">, Requires<[HasEL3]>;3714def SVC : ExceptionGeneration<0b000, 0b01, "svc">;3715 3716// DCPSn defaults to an immediate operand of zero if unspecified.3717def : InstAlias<"dcps1", (DCPS1 0)>;3718def : InstAlias<"dcps2", (DCPS2 0)>;3719def : InstAlias<"dcps3", (DCPS3 0)>, Requires<[HasEL3]>;3720 3721def UDF : UDFType<0, "udf">;3722 3723//===----------------------------------------------------------------------===//3724// Load instructions.3725//===----------------------------------------------------------------------===//3726 3727let Predicates = [HasLSCP] in {3728defm LDAP : LoadAcquirePairOffset<0b0101, "ldap">;3729defm LDAPP : LoadAcquirePairOffset<0b0111, "ldapp">;3730defm STLP : StoreAcquirePairOffset<0b0101, "stlp">;3731}3732 3733// Pair (indexed, offset)3734defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">;3735defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">;3736let Predicates = [HasFPARMv8] in {3737defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">;3738defm LDPD : LoadPairOffset<0b01, 1, FPR64Op, simm7s8, "ldp">;3739defm LDPQ : LoadPairOffset<0b10, 1, FPR128Op, simm7s16, "ldp">;3740}3741 3742defm LDPSW : LoadPairOffset<0b01, 0, GPR64z, simm7s4, "ldpsw">;3743 3744// Pair (pre-indexed)3745def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32z, simm7s4, "ldp">;3746def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64z, simm7s8, "ldp">;3747let Predicates = [HasFPARMv8] in {3748def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32Op, simm7s4, "ldp">;3749def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64Op, simm7s8, "ldp">;3750def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128Op, simm7s16, "ldp">;3751}3752 3753def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">;3754 3755// Pair (post-indexed)3756def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32z, simm7s4, "ldp">;3757def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64z, simm7s8, "ldp">;3758let Predicates = [HasFPARMv8] in {3759def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32Op, simm7s4, "ldp">;3760def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64Op, simm7s8, "ldp">;3761def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128Op, simm7s16, "ldp">;3762}3763 3764def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">;3765 3766 3767// Pair (no allocate)3768defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32z, simm7s4, "ldnp">;3769defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64z, simm7s8, "ldnp">;3770let Predicates = [HasFPARMv8] in {3771defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32Op, simm7s4, "ldnp">;3772defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64Op, simm7s8, "ldnp">;3773defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128Op, simm7s16, "ldnp">;3774}3775 3776def : Pat<(AArch64ldp (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),3777 (LDPXi GPR64sp:$Rn, simm7s8:$offset)>;3778 3779def : Pat<(AArch64ldnp (am_indexed7s128 GPR64sp:$Rn, simm7s16:$offset)),3780 (LDNPQi GPR64sp:$Rn, simm7s16:$offset)>;3781//---3782// (register offset)3783//---3784 3785// Integer3786defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;3787defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;3788defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;3789defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;3790 3791// Floating-point3792let Predicates = [HasFPARMv8] in {3793defm LDRB : Load8RO<0b00, 1, 0b01, FPR8Op, "ldr", i8, load>;3794defm LDRH : Load16RO<0b01, 1, 0b01, FPR16Op, "ldr", f16, load>;3795defm LDRS : Load32RO<0b10, 1, 0b01, FPR32Op, "ldr", f32, load>;3796defm LDRD : Load64RO<0b11, 1, 0b01, FPR64Op, "ldr", f64, load>;3797defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128Op, "ldr", f128, load>;3798}3799 3800// Load sign-extended half-word3801defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;3802defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;3803 3804// Load sign-extended byte3805defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;3806defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;3807 3808// Load sign-extended word3809defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;3810 3811// Pre-fetch.3812defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;3813 3814// Match all load 64 bits width whose type is compatible with FPR643815multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,3816 Instruction LOADW, Instruction LOADX> {3817 3818 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),3819 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;3820 3821 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),3822 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;3823}3824 3825let AddedComplexity = 10 in {3826let Predicates = [IsLE] in {3827 // We must do vector loads with LD1 in big-endian.3828 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;3829 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;3830 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;3831 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;3832 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;3833 defm : VecROLoadPat<ro64, v4bf16, LDRDroW, LDRDroX>;3834}3835 3836defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;3837defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;3838 3839// Match all load 128 bits width whose type is compatible with FPR1283840let Predicates = [IsLE] in {3841 // We must do vector loads with LD1 in big-endian.3842 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;3843 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;3844 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;3845 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;3846 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;3847 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;3848 defm : VecROLoadPat<ro128, v8bf16, LDRQroW, LDRQroX>;3849 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;3850}3851} // AddedComplexity = 103852 3853// zextload -> i643854multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,3855 Instruction INSTW, Instruction INSTX> {3856 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),3857 (SUBREG_TO_REG (i64 0),3858 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),3859 sub_32)>;3860 3861 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),3862 (SUBREG_TO_REG (i64 0),3863 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),3864 sub_32)>;3865}3866 3867let AddedComplexity = 10 in {3868 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;3869 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;3870 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;3871 3872 // zextloadi1 -> zextloadi83873 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;3874 3875 // extload -> zextload3876 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;3877 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;3878 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;3879 3880 // extloadi1 -> zextloadi83881 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;3882}3883 3884 3885// zextload -> i323886multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,3887 Instruction INSTW, Instruction INSTX> {3888 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),3889 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;3890 3891 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),3892 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;3893}3894 3895let AddedComplexity = 10 in {3896 // extload -> zextload3897 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;3898 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;3899 3900 // zextloadi1 -> zextloadi83901 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;3902}3903 3904//---3905// (unsigned immediate)3906//---3907defm LDRX : LoadUI<0b11, 0, 0b01, GPR64z, uimm12s8, "ldr",3908 [(set GPR64z:$Rt,3909 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;3910defm LDRW : LoadUI<0b10, 0, 0b01, GPR32z, uimm12s4, "ldr",3911 [(set GPR32z:$Rt,3912 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;3913let Predicates = [HasFPARMv8] in {3914defm LDRB : LoadUI<0b00, 1, 0b01, FPR8Op, uimm12s1, "ldr",3915 [(set (i8 FPR8Op:$Rt),3916 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;3917defm LDRH : LoadUI<0b01, 1, 0b01, FPR16Op, uimm12s2, "ldr",3918 [(set (f16 FPR16Op:$Rt),3919 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;3920defm LDRS : LoadUI<0b10, 1, 0b01, FPR32Op, uimm12s4, "ldr",3921 [(set (f32 FPR32Op:$Rt),3922 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;3923defm LDRD : LoadUI<0b11, 1, 0b01, FPR64Op, uimm12s8, "ldr",3924 [(set (f64 FPR64Op:$Rt),3925 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;3926defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128Op, uimm12s16, "ldr",3927 [(set (f128 FPR128Op:$Rt),3928 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;3929}3930 3931// bf16 load pattern3932def : Pat <(bf16 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),3933 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;3934 3935// Match all load 64 bits width whose type is compatible with FPR643936let Predicates = [IsLE] in {3937 // We must use LD1 to perform vector loads in big-endian.3938 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),3939 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;3940 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),3941 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;3942 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),3943 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;3944 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),3945 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;3946 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),3947 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;3948 def : Pat<(v4bf16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),3949 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;3950}3951def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),3952 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;3953def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),3954 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;3955 3956// Match all load 128 bits width whose type is compatible with FPR1283957let Predicates = [IsLE] in {3958 // We must use LD1 to perform vector loads in big-endian.3959 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),3960 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;3961 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),3962 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;3963 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),3964 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;3965 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),3966 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;3967 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),3968 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;3969 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),3970 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;3971 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),3972 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;3973 def : Pat<(v8bf16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),3974 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;3975}3976def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),3977 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;3978 3979defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",3980 [(set GPR32:$Rt,3981 (zextloadi16 (am_indexed16 GPR64sp:$Rn,3982 uimm12s2:$offset)))]>;3983defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",3984 [(set GPR32:$Rt,3985 (zextloadi8 (am_indexed8 GPR64sp:$Rn,3986 uimm12s1:$offset)))]>;3987// zextload -> i643988def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),3989 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;3990def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),3991 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;3992 3993// zextloadi1 -> zextloadi83994def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),3995 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;3996def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),3997 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;3998 3999// extload -> zextload4000def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),4001 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;4002def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),4003 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;4004def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),4005 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;4006def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),4007 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;4008def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),4009 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;4010def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),4011 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;4012def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),4013 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;4014 4015// load sign-extended half-word4016defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",4017 [(set GPR32:$Rt,4018 (sextloadi16 (am_indexed16 GPR64sp:$Rn,4019 uimm12s2:$offset)))]>;4020defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",4021 [(set GPR64:$Rt,4022 (sextloadi16 (am_indexed16 GPR64sp:$Rn,4023 uimm12s2:$offset)))]>;4024 4025// load sign-extended byte4026defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",4027 [(set GPR32:$Rt,4028 (sextloadi8 (am_indexed8 GPR64sp:$Rn,4029 uimm12s1:$offset)))]>;4030defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",4031 [(set GPR64:$Rt,4032 (sextloadi8 (am_indexed8 GPR64sp:$Rn,4033 uimm12s1:$offset)))]>;4034 4035// load sign-extended word4036defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",4037 [(set GPR64:$Rt,4038 (sextloadi32 (am_indexed32 GPR64sp:$Rn,4039 uimm12s4:$offset)))]>;4040 4041// load zero-extended word4042def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),4043 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;4044 4045// Pre-fetch.4046def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",4047 [(AArch64Prefetch timm:$Rt,4048 (am_indexed64 GPR64sp:$Rn,4049 uimm12s8:$offset))]>;4050 4051def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;4052 4053//---4054// (literal)4055 4056def alignedglobal : PatLeaf<(iPTR iPTR:$label), [{4057 if (auto *G = dyn_cast<GlobalAddressSDNode>(N)) {4058 const DataLayout &DL = MF->getDataLayout();4059 Align Align = G->getGlobal()->getPointerAlignment(DL);4060 return Align >= 4 && G->getOffset() % 4 == 0;4061 }4062 if (auto *C = dyn_cast<ConstantPoolSDNode>(N))4063 return C->getAlign() >= 4 && C->getOffset() % 4 == 0;4064 return false;4065}]>;4066 4067def LDRWl : LoadLiteral<0b00, 0, GPR32z, "ldr",4068 [(set GPR32z:$Rt, (load (AArch64adr alignedglobal:$label)))]>;4069def LDRXl : LoadLiteral<0b01, 0, GPR64z, "ldr",4070 [(set GPR64z:$Rt, (load (AArch64adr alignedglobal:$label)))]>;4071let Predicates = [HasFPARMv8] in {4072def LDRSl : LoadLiteral<0b00, 1, FPR32Op, "ldr",4073 [(set (f32 FPR32Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>;4074def LDRDl : LoadLiteral<0b01, 1, FPR64Op, "ldr",4075 [(set (f64 FPR64Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>;4076def LDRQl : LoadLiteral<0b10, 1, FPR128Op, "ldr",4077 [(set (f128 FPR128Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>;4078}4079 4080// load sign-extended word4081def LDRSWl : LoadLiteral<0b10, 0, GPR64z, "ldrsw",4082 [(set GPR64z:$Rt, (sextloadi32 (AArch64adr alignedglobal:$label)))]>;4083 4084let AddedComplexity = 20 in {4085def : Pat<(i64 (zextloadi32 (AArch64adr alignedglobal:$label))),4086 (SUBREG_TO_REG (i64 0), (LDRWl $label), sub_32)>;4087}4088 4089// prefetch4090def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;4091// [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;4092 4093//---4094// (unscaled immediate)4095defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64z, "ldur",4096 [(set GPR64z:$Rt,4097 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;4098defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32z, "ldur",4099 [(set GPR32z:$Rt,4100 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;4101let Predicates = [HasFPARMv8] in {4102defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8Op, "ldur",4103 [(set (i8 FPR8Op:$Rt),4104 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;4105defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16Op, "ldur",4106 [(set (f16 FPR16Op:$Rt),4107 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;4108defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32Op, "ldur",4109 [(set (f32 FPR32Op:$Rt),4110 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;4111defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64Op, "ldur",4112 [(set (f64 FPR64Op:$Rt),4113 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;4114defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128Op, "ldur",4115 [(set (f128 FPR128Op:$Rt),4116 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;4117}4118 4119defm LDURHH4120 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",4121 [(set GPR32:$Rt,4122 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;4123defm LDURBB4124 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",4125 [(set GPR32:$Rt,4126 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;4127 4128// bf16 load pattern4129def : Pat <(bf16 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),4130 (LDURHi GPR64sp:$Rn, simm9:$offset)>;4131 4132// Match all load 64 bits width whose type is compatible with FPR644133let Predicates = [IsLE] in {4134 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),4135 (LDURDi GPR64sp:$Rn, simm9:$offset)>;4136 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),4137 (LDURDi GPR64sp:$Rn, simm9:$offset)>;4138 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),4139 (LDURDi GPR64sp:$Rn, simm9:$offset)>;4140 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),4141 (LDURDi GPR64sp:$Rn, simm9:$offset)>;4142 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),4143 (LDURDi GPR64sp:$Rn, simm9:$offset)>;4144}4145def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),4146 (LDURDi GPR64sp:$Rn, simm9:$offset)>;4147def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),4148 (LDURDi GPR64sp:$Rn, simm9:$offset)>;4149 4150// Match all load 128 bits width whose type is compatible with FPR1284151let Predicates = [IsLE] in {4152 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),4153 (LDURQi GPR64sp:$Rn, simm9:$offset)>;4154 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),4155 (LDURQi GPR64sp:$Rn, simm9:$offset)>;4156 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),4157 (LDURQi GPR64sp:$Rn, simm9:$offset)>;4158 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),4159 (LDURQi GPR64sp:$Rn, simm9:$offset)>;4160 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),4161 (LDURQi GPR64sp:$Rn, simm9:$offset)>;4162 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),4163 (LDURQi GPR64sp:$Rn, simm9:$offset)>;4164 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),4165 (LDURQi GPR64sp:$Rn, simm9:$offset)>;4166}4167 4168// anyext -> zext4169def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),4170 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;4171def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),4172 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;4173def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),4174 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;4175def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),4176 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;4177def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),4178 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;4179def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),4180 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;4181def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),4182 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;4183// unscaled zext4184def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),4185 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;4186def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),4187 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;4188def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),4189 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;4190def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),4191 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;4192def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),4193 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;4194def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),4195 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;4196def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),4197 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;4198 4199 4200//---4201// LDR mnemonics fall back to LDUR for negative or unaligned offsets.4202 4203// Define new assembler match classes as we want to only match these when4204// the don't otherwise match the scaled addressing mode for LDR/STR. Don't4205// associate a DiagnosticType either, as we want the diagnostic for the4206// canonical form (the scaled operand) to take precedence.4207class SImm9OffsetOperand<int Width> : AsmOperandClass {4208 let Name = "SImm9OffsetFB" # Width;4209 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";4210 let RenderMethod = "addImmOperands";4211}4212 4213def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;4214def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;4215def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;4216def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;4217def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;4218 4219def simm9_offset_fb8 : Operand<i64> {4220 let ParserMatchClass = SImm9OffsetFB8Operand;4221}4222def simm9_offset_fb16 : Operand<i64> {4223 let ParserMatchClass = SImm9OffsetFB16Operand;4224}4225def simm9_offset_fb32 : Operand<i64> {4226 let ParserMatchClass = SImm9OffsetFB32Operand;4227}4228def simm9_offset_fb64 : Operand<i64> {4229 let ParserMatchClass = SImm9OffsetFB64Operand;4230}4231def simm9_offset_fb128 : Operand<i64> {4232 let ParserMatchClass = SImm9OffsetFB128Operand;4233}4234 4235def : InstAlias<"ldr $Rt, [$Rn, $offset]",4236 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;4237def : InstAlias<"ldr $Rt, [$Rn, $offset]",4238 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;4239let Predicates = [HasFPARMv8] in {4240def : InstAlias<"ldr $Rt, [$Rn, $offset]",4241 (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;4242def : InstAlias<"ldr $Rt, [$Rn, $offset]",4243 (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;4244def : InstAlias<"ldr $Rt, [$Rn, $offset]",4245 (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;4246def : InstAlias<"ldr $Rt, [$Rn, $offset]",4247 (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;4248def : InstAlias<"ldr $Rt, [$Rn, $offset]",4249 (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;4250}4251 4252// zextload -> i644253def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),4254 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;4255def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),4256 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;4257 4258// load sign-extended half-word4259defm LDURSHW4260 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",4261 [(set GPR32:$Rt,4262 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;4263defm LDURSHX4264 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",4265 [(set GPR64:$Rt,4266 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;4267 4268// load sign-extended byte4269defm LDURSBW4270 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",4271 [(set GPR32:$Rt,4272 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;4273defm LDURSBX4274 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",4275 [(set GPR64:$Rt,4276 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;4277 4278// load sign-extended word4279defm LDURSW4280 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",4281 [(set GPR64:$Rt,4282 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;4283 4284// zero and sign extending aliases from generic LDR* mnemonics to LDUR*.4285def : InstAlias<"ldrb $Rt, [$Rn, $offset]",4286 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;4287def : InstAlias<"ldrh $Rt, [$Rn, $offset]",4288 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;4289def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",4290 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;4291def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",4292 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;4293def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",4294 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;4295def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",4296 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;4297def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",4298 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;4299 4300// A LDR will implicitly zero the rest of the vector, so vector_insert(zeros, load, 0)4301// can use a single load. Same for scalar_to_vector(load) or insert(undef, load, 0).4302multiclass LoadInsertVTPatterns<SDPatternOperator LoadOp, ValueType VT, ValueType ScalarVT,4303 Instruction LoadInst, Instruction UnscaledLoadInst,4304 Instruction ROWLoadInst, Instruction ROXLoadInst,4305 ROAddrMode ro, ComplexPattern Addr, ComplexPattern UnscaledAddr,4306 Operand AddrImm, SubRegIndex SubReg> {4307 // Scaled4308 def : Pat <(vector_insert (VT immAllZerosV),4309 (ScalarVT (LoadOp (Addr GPR64sp:$Rn, AddrImm:$offset))), (i64 0)),4310 (SUBREG_TO_REG (i64 0), (LoadInst GPR64sp:$Rn, AddrImm:$offset), SubReg)>;4311 // Unscaled4312 def : Pat <(vector_insert (VT immAllZerosV),4313 (ScalarVT (LoadOp (UnscaledAddr GPR64sp:$Rn, simm9:$offset))), (i64 0)),4314 (SUBREG_TO_REG (i64 0), (UnscaledLoadInst GPR64sp:$Rn, simm9:$offset), SubReg)>;4315 // roW4316 def : Pat <(vector_insert (VT immAllZerosV),4317 (ScalarVT (LoadOp (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), (i64 0)),4318 (SUBREG_TO_REG (i64 0), (ROWLoadInst GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), SubReg)>;4319 // roX4320 def : Pat <(vector_insert (VT immAllZerosV),4321 (ScalarVT (LoadOp (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), (i64 0)),4322 (SUBREG_TO_REG (i64 0), (ROXLoadInst GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), SubReg)>;4323 4324 // Undef equivalents of the patterns above.4325 def : Pat <(VT (vec_ins_or_scal_vec4326 (ScalarVT (LoadOp (Addr GPR64sp:$Rn, AddrImm:$offset))))),4327 (SUBREG_TO_REG (i64 0), (LoadInst GPR64sp:$Rn, AddrImm:$offset), SubReg)>;4328 def : Pat <(VT (vec_ins_or_scal_vec4329 (ScalarVT (LoadOp (UnscaledAddr GPR64sp:$Rn, simm9:$offset))))),4330 (SUBREG_TO_REG (i64 0), (UnscaledLoadInst GPR64sp:$Rn, simm9:$offset), SubReg)>;4331 def : Pat <(VT (vec_ins_or_scal_vec4332 (ScalarVT (LoadOp (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))))),4333 (SUBREG_TO_REG (i64 0), (ROWLoadInst GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), SubReg)>;4334 def : Pat <(VT (vec_ins_or_scal_vec4335 (ScalarVT (LoadOp (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))))),4336 (SUBREG_TO_REG (i64 0), (ROXLoadInst GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), SubReg)>;4337}4338 4339multiclass LoadInsertPatterns<SDPatternOperator LoadOp, ValueType VT, ValueType HVT, ValueType SVT,4340 ValueType ScalarVT, Instruction LoadInst, Instruction UnscaledLoadInst,4341 Instruction ROWLoadInst, Instruction ROXLoadInst,4342 ROAddrMode ro, ComplexPattern Addr, ComplexPattern UnscaledAddr,4343 Operand AddrImm, SubRegIndex SubReg> {4344 defm : LoadInsertVTPatterns<LoadOp, VT, ScalarVT, LoadInst, UnscaledLoadInst, ROWLoadInst,4345 ROXLoadInst, ro, Addr, UnscaledAddr, AddrImm, SubReg>;4346 defm : LoadInsertVTPatterns<LoadOp, HVT, ScalarVT, LoadInst, UnscaledLoadInst, ROWLoadInst,4347 ROXLoadInst, ro, Addr, UnscaledAddr, AddrImm, SubReg>;4348 defm : LoadInsertVTPatterns<LoadOp, SVT, ScalarVT, LoadInst, UnscaledLoadInst, ROWLoadInst,4349 ROXLoadInst, ro, Addr, UnscaledAddr, AddrImm, SubReg>;4350}4351 4352// Accept i8 scalar argument in GlobalISel.4353defm : LoadInsertPatterns<load, v16i8, v8i8, nxv16i8, i8,4354 LDRBui, LDURBi, LDRBroW, LDRBroX,4355 ro8, am_indexed8, am_unscaled8, uimm12s1, bsub>;4356defm : LoadInsertPatterns<extloadi8, v16i8, v8i8, nxv16i8, i32,4357 LDRBui, LDURBi, LDRBroW, LDRBroX,4358 ro8, am_indexed8, am_unscaled8, uimm12s1, bsub>;4359defm : LoadInsertPatterns<extloadi16, v8i16, v4i16, nxv8i16, i32,4360 LDRHui, LDURHi, LDRHroW, LDRHroX,4361 ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;4362defm : LoadInsertPatterns<load, v4i32, v2i32, nxv4i32, i32,4363 LDRSui, LDURSi, LDRSroW, LDRSroX,4364 ro32, am_indexed32, am_unscaled32, uimm12s4, ssub>;4365defm : LoadInsertPatterns<load, v2i64, isVoid, nxv2i64, i64,4366 LDRDui, LDURDi, LDRDroW, LDRDroX,4367 ro64, am_indexed64, am_unscaled64, uimm12s8, dsub>;4368defm : LoadInsertPatterns<load, v8f16, v4f16, nxv8f16, f16,4369 LDRHui, LDURHi, LDRHroW, LDRHroX,4370 ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;4371defm : LoadInsertPatterns<load, v8bf16, v4bf16, nxv8bf16, bf16,4372 LDRHui, LDURHi, LDRHroW, LDRHroX,4373 ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;4374defm : LoadInsertPatterns<load, v4f32, v2f32, nxv4f32, f32,4375 LDRSui, LDURSi, LDRSroW, LDRSroX,4376 ro32, am_indexed32, am_unscaled32, uimm12s4, ssub>;4377defm : LoadInsertPatterns<load, v2f64, isVoid, nxv2f64, f64,4378 LDRDui, LDURDi, LDRDroW, LDRDroX,4379 ro64, am_indexed64, am_unscaled64, uimm12s8, dsub>;4380 4381// Extra patterns for v1f64 scalar_to_vector(load), which need to avoid the4382// SUBREG_TO_REG used above.4383def : Pat <(v1i64 (scalar_to_vector (i644384 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),4385 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;4386def : Pat <(v1i64 (scalar_to_vector (i644387 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))))),4388 (LDURDi GPR64sp:$Rn, simm9:$offset)>;4389def : Pat <(v1i64 (scalar_to_vector (i644390 (load (ro64.Wpat GPR64sp:$Rn, GPR32:$Rm, ro64.Wext:$extend))))),4391 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro64.Wext:$extend)>;4392def : Pat <(v1i64 (scalar_to_vector (i644393 (load (ro64.Xpat GPR64sp:$Rn, GPR64:$Rm, ro64.Xext:$extend))))),4394 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro64.Xext:$extend)>;4395 4396// Patterns for bitconvert or scalar_to_vector of load operations.4397// Enables direct SIMD register loads for small integer types (i8/i16) that are4398// naturally zero-extended to i32/i64.4399multiclass ExtLoad8_16AllModes<ValueType OutTy, ValueType InnerTy,4400 SDPatternOperator OuterOp,4401 PatFrags LoadOp8, PatFrags LoadOp16> {4402 // 8-bit loads.4403 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),4404 (SUBREG_TO_REG (i64 0), (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;4405 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),4406 (SUBREG_TO_REG (i64 0), (LDURBi GPR64sp:$Rn, simm9:$offset), bsub)>;4407 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$extend))))),4408 (SUBREG_TO_REG (i64 0), (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$extend), bsub)>;4409 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$extend))))),4410 (SUBREG_TO_REG (i64 0), (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$extend), bsub)>;4411 4412 // 16-bit loads.4413 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),4414 (SUBREG_TO_REG (i64 0), (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;4415 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),4416 (SUBREG_TO_REG (i64 0), (LDURHi GPR64sp:$Rn, simm9:$offset), hsub)>;4417 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$extend))))),4418 (SUBREG_TO_REG (i64 0), (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$extend), hsub)>;4419 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$extend))))),4420 (SUBREG_TO_REG (i64 0), (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$extend), hsub)>;4421}4422 4423// Extended multiclass that includes 32-bit loads in addition to 8-bit and 16-bit.4424multiclass ExtLoad8_16_32AllModes<ValueType OutTy, ValueType InnerTy,4425 SDPatternOperator OuterOp,4426 PatFrags LoadOp8, PatFrags LoadOp16, PatFrags LoadOp32> {4427 defm : ExtLoad8_16AllModes<OutTy, InnerTy, OuterOp, LoadOp8, LoadOp16>;4428 4429 // 32-bit loads.4430 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),4431 (SUBREG_TO_REG (i64 0), (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;4432 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),4433 (SUBREG_TO_REG (i64 0), (LDURSi GPR64sp:$Rn, simm9:$offset), ssub)>;4434 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp32 (ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$extend))))),4435 (SUBREG_TO_REG (i64 0), (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$extend), ssub)>;4436 def : Pat<(OutTy (OuterOp (InnerTy (LoadOp32 (ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$extend))))),4437 (SUBREG_TO_REG (i64 0), (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$extend), ssub)>;4438}4439 4440// Instantiate bitconvert patterns for floating-point types.4441defm : ExtLoad8_16AllModes<f32, i32, bitconvert, zextloadi8, zextloadi16>;4442defm : ExtLoad8_16_32AllModes<f64, i64, bitconvert, zextloadi8, zextloadi16, zextloadi32>;4443 4444// Instantiate scalar_to_vector patterns for all vector types.4445defm : ExtLoad8_16AllModes<v16i8, i32, scalar_to_vector, zextloadi8, zextloadi16>;4446defm : ExtLoad8_16AllModes<v16i8, i32, scalar_to_vector, extloadi8, extloadi16>;4447defm : ExtLoad8_16AllModes<v8i16, i32, scalar_to_vector, zextloadi8, zextloadi16>;4448defm : ExtLoad8_16AllModes<v8i16, i32, scalar_to_vector, extloadi8, extloadi16>;4449defm : ExtLoad8_16AllModes<v4i32, i32, scalar_to_vector, zextloadi8, zextloadi16>;4450defm : ExtLoad8_16AllModes<v4i32, i32, scalar_to_vector, extloadi8, extloadi16>;4451defm : ExtLoad8_16_32AllModes<v2i64, i64, scalar_to_vector, zextloadi8, zextloadi16, zextloadi32>;4452defm : ExtLoad8_16_32AllModes<v2i64, i64, scalar_to_vector, extloadi8, extloadi16, extloadi32>;4453 4454// Pre-fetch.4455defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",4456 [(AArch64Prefetch timm:$Rt,4457 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;4458 4459// PRFM falls back to PRFUM for negative or unaligned offsets (not a multiple4460// of 8).4461def : InstAlias<"prfm $Rt, [$Rn, $offset]",4462 (PRFUMi prfop:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;4463 4464//---4465// (unscaled immediate, unprivileged)4466defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;4467defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;4468 4469defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;4470defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;4471 4472// load sign-extended half-word4473defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;4474defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;4475 4476// load sign-extended byte4477defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;4478defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;4479 4480// load sign-extended word4481defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;4482 4483//---4484// (immediate pre-indexed)4485def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32z, "ldr">;4486def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64z, "ldr">;4487let Predicates = [HasFPARMv8] in {4488def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8Op, "ldr">;4489def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16Op, "ldr">;4490def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32Op, "ldr">;4491def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64Op, "ldr">;4492def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128Op, "ldr">;4493}4494 4495// load sign-extended half-word4496def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32z, "ldrsh">;4497def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64z, "ldrsh">;4498 4499// load sign-extended byte4500def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32z, "ldrsb">;4501def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64z, "ldrsb">;4502 4503// load zero-extended byte4504def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32z, "ldrb">;4505def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32z, "ldrh">;4506 4507// load sign-extended word4508def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64z, "ldrsw">;4509 4510//---4511// (immediate post-indexed)4512def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32z, "ldr">;4513def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64z, "ldr">;4514let Predicates = [HasFPARMv8] in {4515def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8Op, "ldr">;4516def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16Op, "ldr">;4517def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32Op, "ldr">;4518def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64Op, "ldr">;4519def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128Op, "ldr">;4520}4521 4522// load sign-extended half-word4523def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32z, "ldrsh">;4524def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64z, "ldrsh">;4525 4526// load sign-extended byte4527def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32z, "ldrsb">;4528def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64z, "ldrsb">;4529 4530// load zero-extended byte4531def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32z, "ldrb">;4532def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32z, "ldrh">;4533 4534// load sign-extended word4535def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64z, "ldrsw">;4536 4537//===----------------------------------------------------------------------===//4538// Store instructions.4539//===----------------------------------------------------------------------===//4540 4541// Pair (indexed, offset)4542// FIXME: Use dedicated range-checked addressing mode operand here.4543defm STPW : StorePairOffset<0b00, 0, GPR32z, simm7s4, "stp">;4544defm STPX : StorePairOffset<0b10, 0, GPR64z, simm7s8, "stp">;4545let Predicates = [HasFPARMv8] in {4546defm STPS : StorePairOffset<0b00, 1, FPR32Op, simm7s4, "stp">;4547defm STPD : StorePairOffset<0b01, 1, FPR64Op, simm7s8, "stp">;4548defm STPQ : StorePairOffset<0b10, 1, FPR128Op, simm7s16, "stp">;4549}4550 4551// Pair (pre-indexed)4552def STPWpre : StorePairPreIdx<0b00, 0, GPR32z, simm7s4, "stp">;4553def STPXpre : StorePairPreIdx<0b10, 0, GPR64z, simm7s8, "stp">;4554let Predicates = [HasFPARMv8] in {4555def STPSpre : StorePairPreIdx<0b00, 1, FPR32Op, simm7s4, "stp">;4556def STPDpre : StorePairPreIdx<0b01, 1, FPR64Op, simm7s8, "stp">;4557def STPQpre : StorePairPreIdx<0b10, 1, FPR128Op, simm7s16, "stp">;4558}4559 4560// Pair (post-indexed)4561def STPWpost : StorePairPostIdx<0b00, 0, GPR32z, simm7s4, "stp">;4562def STPXpost : StorePairPostIdx<0b10, 0, GPR64z, simm7s8, "stp">;4563let Predicates = [HasFPARMv8] in {4564def STPSpost : StorePairPostIdx<0b00, 1, FPR32Op, simm7s4, "stp">;4565def STPDpost : StorePairPostIdx<0b01, 1, FPR64Op, simm7s8, "stp">;4566def STPQpost : StorePairPostIdx<0b10, 1, FPR128Op, simm7s16, "stp">;4567}4568 4569// Pair (no allocate)4570defm STNPW : StorePairNoAlloc<0b00, 0, GPR32z, simm7s4, "stnp">;4571defm STNPX : StorePairNoAlloc<0b10, 0, GPR64z, simm7s8, "stnp">;4572let Predicates = [HasFPARMv8] in {4573defm STNPS : StorePairNoAlloc<0b00, 1, FPR32Op, simm7s4, "stnp">;4574defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, "stnp">;4575defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">;4576}4577 4578// Armv9.6-a Load/store pair (FEAT_LSUI)4579let Predicates = [HasLSUI] in {4580 defm LDTP : LoadPairOffset<0b11, 0, GPR64z, simm7s8, "ldtp">;4581 def LDTPpre : LoadPairPreIdx<0b11, 0, GPR64z, simm7s8, "ldtp">;4582 def LDTPpost : LoadPairPostIdx<0b11, 0, GPR64z, simm7s8, "ldtp">;4583 4584 defm STTNPX : StorePairNoAllocLSUI<0b11, 0, GPR64z, simm7s8, "sttnp">;4585 defm LDTNPX : LoadPairNoAllocLSUI<0b11, 0, GPR64z, simm7s8, "ldtnp">;4586 4587 defm STTP : StorePairOffset<0b11, 0, GPR64z, simm7s8, "sttp">;4588 def STTPpre : StorePairPreIdx<0b11, 0, GPR64z, simm7s8, "sttp">;4589 def STTPpost : StorePairPostIdx<0b11, 0, GPR64z, simm7s8, "sttp">;4590}4591 4592let Predicates = [HasLSUI, HasNEON] in {4593 defm LDTPQ : LoadPairOffset<0b11, 1, FPR128Op, simm7s16, "ldtp">;4594 def LDTPQpre : LoadPairPreIdx<0b11, 1, FPR128Op, simm7s16, "ldtp">;4595 def LDTPQpost : LoadPairPostIdx<0b11, 1, FPR128Op, simm7s16, "ldtp">;4596 4597 defm STTNPQ : StorePairNoAllocLSUI<0b11, 1, FPR128Op, simm7s16, "sttnp">;4598 defm LDTNPQ : LoadPairNoAllocLSUI<0b11, 1, FPR128Op, simm7s16, "ldtnp">;4599 4600 defm STTPQ : StorePairOffset<0b11, 1, FPR128Op, simm7s16, "sttp">;4601 def STTPQpre : StorePairPreIdx<0b11, 1, FPR128Op, simm7s16, "sttp">;4602 def STTPQpost : StorePairPostIdx<0b11, 1, FPR128Op, simm7s16, "sttp">;4603}4604 4605def : Pat<(AArch64stp GPR64z:$Rt, GPR64z:$Rt2, (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),4606 (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, simm7s8:$offset)>;4607 4608def : Pat<(AArch64stnp FPR128:$Rt, FPR128:$Rt2, (am_indexed7s128 GPR64sp:$Rn, simm7s16:$offset)),4609 (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, simm7s16:$offset)>;4610 4611 4612//---4613// (Register offset)4614 4615// Integer4616defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;4617defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;4618defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;4619defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;4620 4621 4622// Floating-point4623let Predicates = [HasFPARMv8] in {4624defm STRB : Store8RO< 0b00, 1, 0b00, FPR8Op, "str", i8, store>;4625defm STRH : Store16RO<0b01, 1, 0b00, FPR16Op, "str", f16, store>;4626defm STRS : Store32RO<0b10, 1, 0b00, FPR32Op, "str", f32, store>;4627defm STRD : Store64RO<0b11, 1, 0b00, FPR64Op, "str", f64, store>;4628defm STRQ : Store128RO<0b00, 1, 0b10, FPR128Op, "str">;4629}4630 4631let Predicates = [UseSTRQro], AddedComplexity = 10 in {4632 def : Pat<(store (f128 FPR128:$Rt),4633 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,4634 ro_Wextend128:$extend)),4635 (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>;4636 def : Pat<(store (f128 FPR128:$Rt),4637 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,4638 ro_Xextend128:$extend)),4639 (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>;4640}4641 4642multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,4643 Instruction STRW, Instruction STRX> {4644 4645 def : Pat<(storeop GPR64:$Rt,4646 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),4647 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),4648 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;4649 4650 def : Pat<(storeop GPR64:$Rt,4651 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),4652 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),4653 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;4654}4655 4656let AddedComplexity = 10 in {4657 // truncstore i644658 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;4659 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;4660 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;4661}4662 4663multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,4664 Instruction STRW, Instruction STRX> {4665 def : Pat<(store (VecTy FPR:$Rt),4666 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),4667 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;4668 4669 def : Pat<(store (VecTy FPR:$Rt),4670 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),4671 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;4672}4673 4674let AddedComplexity = 10 in {4675// Match all store 64 bits width whose type is compatible with FPR644676let Predicates = [IsLE] in {4677 // We must use ST1 to store vectors in big-endian.4678 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;4679 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;4680 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;4681 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;4682 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;4683 defm : VecROStorePat<ro64, v4bf16, FPR64, STRDroW, STRDroX>;4684}4685 4686defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;4687defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;4688 4689// Match all store 128 bits width whose type is compatible with FPR1284690let Predicates = [IsLE, UseSTRQro] in {4691 // We must use ST1 to store vectors in big-endian.4692 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;4693 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;4694 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;4695 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;4696 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;4697 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;4698 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;4699 defm : VecROStorePat<ro128, v8bf16, FPR128, STRQroW, STRQroX>;4700}4701} // AddedComplexity = 104702 4703// Match stores from lane 0 to the appropriate subreg's store.4704multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,4705 ValueType VecTy, ValueType STy,4706 ValueType SubRegTy,4707 SubRegIndex SubRegIdx,4708 Instruction STRW, Instruction STRX> {4709 4710 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), (i64 0))),4711 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),4712 (STRW (SubRegTy (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx)),4713 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;4714 4715 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), (i64 0))),4716 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),4717 (STRX (SubRegTy (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx)),4718 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;4719}4720 4721let AddedComplexity = 19 in {4722 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, f16, hsub, STRHroW, STRHroX>;4723 defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, f16, hsub, STRHroW, STRHroX>;4724 defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, i32, ssub, STRSroW, STRSroX>;4725 defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, i32, ssub, STRSroW, STRSroX>;4726 defm : VecROStoreLane0Pat<ro64, store, v2i64, i64, i64, dsub, STRDroW, STRDroX>;4727 defm : VecROStoreLane0Pat<ro64, store, v2f64, f64, i64, dsub, STRDroW, STRDroX>;4728}4729 4730//---4731// (unsigned immediate)4732defm STRX : StoreUIz<0b11, 0, 0b00, GPR64z, uimm12s8, "str",4733 [(store GPR64z:$Rt,4734 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;4735defm STRW : StoreUIz<0b10, 0, 0b00, GPR32z, uimm12s4, "str",4736 [(store GPR32z:$Rt,4737 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;4738let Predicates = [HasFPARMv8] in {4739defm STRB : StoreUI<0b00, 1, 0b00, FPR8Op, uimm12s1, "str",4740 [(store (i8 FPR8Op:$Rt),4741 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;4742defm STRH : StoreUI<0b01, 1, 0b00, FPR16Op, uimm12s2, "str",4743 [(store (f16 FPR16Op:$Rt),4744 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;4745defm STRS : StoreUI<0b10, 1, 0b00, FPR32Op, uimm12s4, "str",4746 [(store (f32 FPR32Op:$Rt),4747 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;4748defm STRD : StoreUI<0b11, 1, 0b00, FPR64Op, uimm12s8, "str",4749 [(store (f64 FPR64Op:$Rt),4750 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;4751defm STRQ : StoreUI<0b00, 1, 0b10, FPR128Op, uimm12s16, "str", []>;4752}4753 4754defm STRHH : StoreUIz<0b01, 0, 0b00, GPR32z, uimm12s2, "strh",4755 [(truncstorei16 GPR32z:$Rt,4756 (am_indexed16 GPR64sp:$Rn,4757 uimm12s2:$offset))]>;4758defm STRBB : StoreUIz<0b00, 0, 0b00, GPR32z, uimm12s1, "strb",4759 [(truncstorei8 GPR32z:$Rt,4760 (am_indexed8 GPR64sp:$Rn,4761 uimm12s1:$offset))]>;4762 4763// bf16 store pattern4764def : Pat<(store (bf16 FPR16Op:$Rt),4765 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),4766 (STRHui FPR16:$Rt, GPR64sp:$Rn, uimm12s2:$offset)>;4767 4768let AddedComplexity = 10 in {4769 4770// Match all store 64 bits width whose type is compatible with FPR644771def : Pat<(store (v1i64 FPR64:$Rt),4772 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),4773 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;4774def : Pat<(store (v1f64 FPR64:$Rt),4775 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),4776 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;4777 4778let Predicates = [IsLE] in {4779 // We must use ST1 to store vectors in big-endian.4780 def : Pat<(store (v2f32 FPR64:$Rt),4781 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),4782 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;4783 def : Pat<(store (v8i8 FPR64:$Rt),4784 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),4785 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;4786 def : Pat<(store (v4i16 FPR64:$Rt),4787 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),4788 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;4789 def : Pat<(store (v2i32 FPR64:$Rt),4790 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),4791 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;4792 def : Pat<(store (v4f16 FPR64:$Rt),4793 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),4794 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;4795 def : Pat<(store (v4bf16 FPR64:$Rt),4796 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),4797 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;4798}4799 4800// Match all store 128 bits width whose type is compatible with FPR1284801def : Pat<(store (f128 FPR128:$Rt),4802 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),4803 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;4804 4805let Predicates = [IsLE] in {4806 // We must use ST1 to store vectors in big-endian.4807 def : Pat<(store (v4f32 FPR128:$Rt),4808 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),4809 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;4810 def : Pat<(store (v2f64 FPR128:$Rt),4811 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),4812 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;4813 def : Pat<(store (v16i8 FPR128:$Rt),4814 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),4815 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;4816 def : Pat<(store (v8i16 FPR128:$Rt),4817 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),4818 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;4819 def : Pat<(store (v4i32 FPR128:$Rt),4820 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),4821 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;4822 def : Pat<(store (v2i64 FPR128:$Rt),4823 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),4824 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;4825 def : Pat<(store (v8f16 FPR128:$Rt),4826 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),4827 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;4828 def : Pat<(store (v8bf16 FPR128:$Rt),4829 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),4830 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;4831}4832 4833// truncstorei32 of f64 bitcasted to i644834def : Pat<(truncstorei32 (i64 (bitconvert (f64 FPR64:$Rt))), (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),4835 (STRSui (EXTRACT_SUBREG FPR64:$Rt, ssub), GPR64sp:$Rn, uimm12s4:$offset)>;4836 4837// truncstorei16 of f64 bitcasted to i644838def : Pat<(truncstorei16 (i64 (bitconvert (f64 FPR64:$Rt))), (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),4839 (STRHui (f16 (EXTRACT_SUBREG FPR64:$Rt, hsub)), GPR64sp:$Rn, uimm12s2:$offset)>; 4840 4841 // truncstorei16 of f32 bitcasted to i324842def : Pat<(truncstorei16 (i32 (bitconvert (f32 FPR32:$Rt))), (am_indexed16 GPR64sp:$Rn, uimm12s2:$off)),4843 (STRHui (f16 (EXTRACT_SUBREG FPR32:$Rt, hsub)), GPR64sp:$Rn, uimm12s2:$off)>;4844 4845 // truncstorei8 of f64 bitcasted to i644846def : Pat<(truncstorei8 (i64 (bitconvert (f64 FPR64:$Rt))), (am_indexed8 GPR64sp:$Rn, uimm12s1:$off)),4847 (STRBui (aarch64mfp8 (EXTRACT_SUBREG FPR64:$Rt, bsub)), GPR64sp:$Rn, uimm12s1:$off)>;4848 4849 // truncstorei8 of f32 bitcasted to i324850def : Pat<(truncstorei8 (i32 (bitconvert (f32 FPR32:$Rt))), (am_indexed8 GPR64sp:$Rn, uimm12s1:$off)),4851 (STRBui (aarch64mfp8 (EXTRACT_SUBREG FPR32:$Rt, bsub)), GPR64sp:$Rn, uimm12s1:$off)>;4852 4853// truncstore i644854def : Pat<(truncstorei32 GPR64:$Rt,4855 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),4856 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;4857def : Pat<(truncstorei16 GPR64:$Rt,4858 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),4859 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;4860def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),4861 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;4862 4863} // AddedComplexity = 104864 4865// Match stores from lane 0 to the appropriate subreg's store.4866multiclass VecStoreLane0Pat<ComplexPattern UIAddrMode, SDPatternOperator storeop,4867 ValueType VTy, ValueType STy,4868 ValueType SubRegTy,4869 SubRegIndex SubRegIdx, Operand IndexType,4870 Instruction STR> {4871 def : Pat<(storeop (STy (vector_extract (VTy VecListOne128:$Vt), (i64 0))),4872 (UIAddrMode GPR64sp:$Rn, IndexType:$offset)),4873 (STR (SubRegTy (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx)),4874 GPR64sp:$Rn, IndexType:$offset)>;4875}4876 4877let AddedComplexity = 19 in {4878 defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, f16, hsub, uimm12s2, STRHui>;4879 defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, f16, hsub, uimm12s2, STRHui>;4880 defm : VecStoreLane0Pat<am_indexed32, store, v4i32, i32, i32, ssub, uimm12s4, STRSui>;4881 defm : VecStoreLane0Pat<am_indexed32, store, v4f32, f32, i32, ssub, uimm12s4, STRSui>;4882 defm : VecStoreLane0Pat<am_indexed64, store, v2i64, i64, i64, dsub, uimm12s8, STRDui>;4883 defm : VecStoreLane0Pat<am_indexed64, store, v2f64, f64, i64, dsub, uimm12s8, STRDui>;4884}4885 4886//---4887// (unscaled immediate)4888defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64z, "stur",4889 [(store GPR64z:$Rt,4890 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;4891defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32z, "stur",4892 [(store GPR32z:$Rt,4893 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;4894let Predicates = [HasFPARMv8] in {4895defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8Op, "stur",4896 [(store (i8 FPR8Op:$Rt),4897 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;4898defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16Op, "stur",4899 [(store (f16 FPR16Op:$Rt),4900 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;4901defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32Op, "stur",4902 [(store (f32 FPR32Op:$Rt),4903 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;4904defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64Op, "stur",4905 [(store (f64 FPR64Op:$Rt),4906 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;4907defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128Op, "stur",4908 [(store (f128 FPR128Op:$Rt),4909 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;4910}4911defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32z, "sturh",4912 [(truncstorei16 GPR32z:$Rt,4913 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;4914defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb",4915 [(truncstorei8 GPR32z:$Rt,4916 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;4917 4918// bf16 store pattern4919def : Pat<(store (bf16 FPR16Op:$Rt),4920 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),4921 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9:$offset)>;4922 4923// Armv8.4 Weaker Release Consistency enhancements4924// LDAPR & STLR with Immediate Offset instructions4925let Predicates = [HasRCPC_IMMO] in {4926defm STLURB : BaseStoreUnscaleV84<"stlurb", 0b00, 0b00, GPR32>;4927defm STLURH : BaseStoreUnscaleV84<"stlurh", 0b01, 0b00, GPR32>;4928defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>;4929defm STLURX : BaseStoreUnscaleV84<"stlur", 0b11, 0b00, GPR64>;4930defm LDAPURB : BaseLoadUnscaleV84<"ldapurb", 0b00, 0b01, GPR32>;4931defm LDAPURSBW : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>;4932defm LDAPURSBX : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>;4933defm LDAPURH : BaseLoadUnscaleV84<"ldapurh", 0b01, 0b01, GPR32>;4934defm LDAPURSHW : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>;4935defm LDAPURSHX : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>;4936defm LDAPUR : BaseLoadUnscaleV84<"ldapur", 0b10, 0b01, GPR32>;4937defm LDAPURSW : BaseLoadUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>;4938defm LDAPURX : BaseLoadUnscaleV84<"ldapur", 0b11, 0b01, GPR64>;4939}4940 4941// Match all store 64 bits width whose type is compatible with FPR644942def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),4943 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;4944def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),4945 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;4946 4947let AddedComplexity = 10 in {4948 4949let Predicates = [IsLE] in {4950 // We must use ST1 to store vectors in big-endian.4951 def : Pat<(store (v2f32 FPR64:$Rt),4952 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),4953 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;4954 def : Pat<(store (v8i8 FPR64:$Rt),4955 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),4956 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;4957 def : Pat<(store (v4i16 FPR64:$Rt),4958 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),4959 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;4960 def : Pat<(store (v2i32 FPR64:$Rt),4961 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),4962 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;4963 def : Pat<(store (v4f16 FPR64:$Rt),4964 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),4965 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;4966 def : Pat<(store (v4bf16 FPR64:$Rt),4967 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),4968 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;4969}4970 4971// Match all store 128 bits width whose type is compatible with FPR1284972def : Pat<(store (f128 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),4973 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;4974 4975let Predicates = [IsLE] in {4976 // We must use ST1 to store vectors in big-endian.4977 def : Pat<(store (v4f32 FPR128:$Rt),4978 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),4979 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;4980 def : Pat<(store (v2f64 FPR128:$Rt),4981 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),4982 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;4983 def : Pat<(store (v16i8 FPR128:$Rt),4984 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),4985 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;4986 def : Pat<(store (v8i16 FPR128:$Rt),4987 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),4988 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;4989 def : Pat<(store (v4i32 FPR128:$Rt),4990 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),4991 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;4992 def : Pat<(store (v2i64 FPR128:$Rt),4993 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),4994 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;4995 def : Pat<(store (v2f64 FPR128:$Rt),4996 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),4997 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;4998 def : Pat<(store (v8f16 FPR128:$Rt),4999 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),5000 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;5001 def : Pat<(store (v8bf16 FPR128:$Rt),5002 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),5003 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;5004}5005 5006} // AddedComplexity = 105007 5008// unscaled i64 truncating stores5009def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),5010 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;5011def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),5012 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;5013def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),5014 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;5015 5016// aarch64mfp8 (bsub) stores5017def : Pat<(store aarch64mfp8:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),5018 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9:$offset)>;5019def : Pat<(store aarch64mfp8:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),5020 (STRBui FPR8:$Rt, GPR64sp:$Rn, uimm12s1:$offset)>;5021 5022// Match stores from lane 0 to the appropriate subreg's store.5023multiclass VecStoreULane0Pat<SDPatternOperator StoreOp,5024 ValueType VTy, ValueType STy,5025 ValueType SubRegTy,5026 SubRegIndex SubRegIdx, Instruction STR> {5027 defm : VecStoreLane0Pat<am_unscaled128, StoreOp, VTy, STy, SubRegTy, SubRegIdx, simm9, STR>;5028}5029 5030let AddedComplexity = 19 in {5031 defm : VecStoreULane0Pat<truncstorei16, v8i16, i32, f16, hsub, STURHi>;5032 defm : VecStoreULane0Pat<store, v8f16, f16, f16, hsub, STURHi>;5033 defm : VecStoreULane0Pat<store, v4i32, i32, i32, ssub, STURSi>;5034 defm : VecStoreULane0Pat<store, v4f32, f32, i32, ssub, STURSi>;5035 defm : VecStoreULane0Pat<store, v2i64, i64, i64, dsub, STURDi>;5036 defm : VecStoreULane0Pat<store, v2f64, f64, i64, dsub, STURDi>;5037}5038 5039//---5040// STR mnemonics fall back to STUR for negative or unaligned offsets.5041def : InstAlias<"str $Rt, [$Rn, $offset]",5042 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;5043def : InstAlias<"str $Rt, [$Rn, $offset]",5044 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;5045let Predicates = [HasFPARMv8] in {5046def : InstAlias<"str $Rt, [$Rn, $offset]",5047 (STURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;5048def : InstAlias<"str $Rt, [$Rn, $offset]",5049 (STURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;5050def : InstAlias<"str $Rt, [$Rn, $offset]",5051 (STURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;5052def : InstAlias<"str $Rt, [$Rn, $offset]",5053 (STURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;5054def : InstAlias<"str $Rt, [$Rn, $offset]",5055 (STURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;5056}5057 5058def : InstAlias<"strb $Rt, [$Rn, $offset]",5059 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;5060def : InstAlias<"strh $Rt, [$Rn, $offset]",5061 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;5062 5063//---5064// (unscaled immediate, unprivileged)5065defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;5066defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;5067 5068defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;5069defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;5070 5071//---5072// (immediate pre-indexed)5073def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32z, "str", pre_store, i32>;5074def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64z, "str", pre_store, i64>;5075let Predicates = [HasFPARMv8] in {5076def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8Op, "str", pre_store, i8>;5077def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16Op, "str", pre_store, f16>;5078def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32Op, "str", pre_store, f32>;5079def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64Op, "str", pre_store, f64>;5080def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128Op, "str", pre_store, f128>;5081}5082 5083def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32z, "strb", pre_truncsti8, i32>;5084def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32z, "strh", pre_truncsti16, i32>;5085 5086// bf16 pre-index store5087def : Pat<(pre_store (bf16 FPR16:$Rt), GPR64sp:$addr, simm9:$off),5088 (STRHpre FPR16:$Rt, GPR64sp:$addr, simm9:$off)>;5089 5090// truncstore i645091def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),5092 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,5093 simm9:$off)>;5094def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),5095 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,5096 simm9:$off)>;5097def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),5098 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,5099 simm9:$off)>;5100 5101def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5102 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5103def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5104 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5105def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5106 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5107def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5108 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5109def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5110 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5111def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5112 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5113def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5114 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5115def : Pat<(pre_store (v4bf16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5116 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5117 5118def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5119 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5120def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5121 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5122def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5123 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5124def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5125 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5126def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5127 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5128def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5129 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5130def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5131 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5132def : Pat<(pre_store (v8bf16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5133 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5134 5135//---5136// (immediate post-indexed)5137def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32z, "str", post_store, i32>;5138def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64z, "str", post_store, i64>;5139let Predicates = [HasFPARMv8] in {5140def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8Op, "str", post_store, i8>;5141def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16Op, "str", post_store, f16>;5142def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32Op, "str", post_store, f32>;5143def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64Op, "str", post_store, f64>;5144def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128Op, "str", post_store, f128>;5145}5146 5147def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32z, "strb", post_truncsti8, i32>;5148def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32z, "strh", post_truncsti16, i32>;5149 5150// truncstore i645151def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),5152 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,5153 simm9:$off)>;5154def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),5155 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,5156 simm9:$off)>;5157def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),5158 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,5159 simm9:$off)>;5160 5161def : Pat<(post_store (bf16 FPR16:$Rt), GPR64sp:$addr, simm9:$off),5162 (STRHpost FPR16:$Rt, GPR64sp:$addr, simm9:$off)>;5163 5164let Predicates = [IsLE] in {5165 // We must use ST1 to store vectors in big-endian.5166 def : Pat<(post_store(v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5167 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5168 def : Pat<(post_store(v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5169 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5170 def : Pat<(post_store(v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5171 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5172 def : Pat<(post_store(v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5173 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5174 def : Pat<(post_store(v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5175 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5176 def : Pat<(post_store(v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5177 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5178 def : Pat<(post_store(v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5179 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5180 def : Pat<(post_store(v4bf16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),5181 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;5182 5183 def : Pat<(post_store(v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5184 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5185 def : Pat<(post_store(v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5186 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5187 def : Pat<(post_store(v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5188 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5189 def : Pat<(post_store(v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5190 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5191 def : Pat<(post_store(v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5192 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5193 def : Pat<(post_store(v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5194 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5195 def : Pat<(post_store(v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5196 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5197 def : Pat<(post_store(v8bf16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),5198 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;5199}5200 5201//===----------------------------------------------------------------------===//5202// Load/store exclusive instructions.5203//===----------------------------------------------------------------------===//5204 5205def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;5206def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;5207def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;5208def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;5209 5210def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;5211def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;5212def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;5213def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;5214 5215def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;5216def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;5217def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;5218def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;5219 5220def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;5221def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;5222def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;5223def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;5224 5225/*5226Aliases for when offset=0. Note that in contrast to LoadAcquire which has a $Rn5227of type GPR64sp0, we deliberately choose to make $Rn of type GPR64sp and add an5228alias for the case of immediate #0. This is because new STLR versions (from5229LRCPC3 extension) do have a non-zero immediate value, so GPR64sp0 is not5230appropriate anymore (it parses and discards the optional zero). This is not the5231case for LoadAcquire because the new LRCPC3 LDAR instructions are post-indexed,5232and the immediate values are not inside the [] brackets and thus not accepted5233by GPR64sp0 parser.5234*/5235def STLRW0 : InstAlias<"stlr\t$Rt, [$Rn, #0]" , (STLRW GPR32: $Rt, GPR64sp:$Rn)>;5236def STLRX0 : InstAlias<"stlr\t$Rt, [$Rn, #0]" , (STLRX GPR64: $Rt, GPR64sp:$Rn)>;5237def STLRB0 : InstAlias<"stlrb\t$Rt, [$Rn, #0]", (STLRB GPR32: $Rt, GPR64sp:$Rn)>;5238def STLRH0 : InstAlias<"stlrh\t$Rt, [$Rn, #0]", (STLRH GPR32: $Rt, GPR64sp:$Rn)>;5239 5240def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;5241def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;5242def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;5243def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;5244 5245def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;5246def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;5247def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;5248def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;5249 5250def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;5251def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;5252 5253def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;5254def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;5255 5256def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;5257def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;5258 5259def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;5260def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;5261 5262let Predicates = [HasLOR] in {5263 // v8.1a "Limited Order Region" extension load-acquire instructions5264 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;5265 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;5266 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;5267 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;5268 5269 // v8.1a "Limited Order Region" extension store-release instructions5270 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;5271 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;5272 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;5273 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;5274 5275 // Aliases for when offset=05276 def STLLRW0 : InstAlias<"stllr\t$Rt, [$Rn, #0]", (STLLRW GPR32: $Rt, GPR64sp:$Rn)>;5277 def STLLRX0 : InstAlias<"stllr\t$Rt, [$Rn, #0]", (STLLRX GPR64: $Rt, GPR64sp:$Rn)>;5278 def STLLRB0 : InstAlias<"stllrb\t$Rt, [$Rn, #0]", (STLLRB GPR32: $Rt, GPR64sp:$Rn)>;5279 def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]", (STLLRH GPR32: $Rt, GPR64sp:$Rn)>;5280}5281 5282// v9.6-a Unprivileged load store operations5283let Predicates = [HasLSUI] in {5284defm LDTXRW : LoadUnprivilegedLSUI<0b10, GPR32, "ldtxr">;5285defm LDTXRX : LoadUnprivilegedLSUI<0b11, GPR64, "ldtxr">;5286 5287def LDATXRW : LoadExclusiveLSUI <0b10, 1, 1, GPR32, "ldatxr">;5288def LDATXRX : LoadExclusiveLSUI <0b11, 1, 1, GPR64, "ldatxr">;5289 5290defm STTXRW : StoreUnprivilegedLSUI<0b10, GPR32, "sttxr">;5291defm STTXRX : StoreUnprivilegedLSUI<0b11, GPR64, "sttxr">;5292 5293def STLTXRW : StoreExclusiveLSUI<0b10, 0, 1, GPR32, "stltxr">;5294def STLTXRX : StoreExclusiveLSUI<0b11, 0, 1, GPR64, "stltxr">;5295}5296 5297//===----------------------------------------------------------------------===//5298// Scaled floating point to integer conversion instructions.5299//===----------------------------------------------------------------------===//5300 5301defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;5302defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;5303defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;5304defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;5305defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;5306defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;5307defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;5308defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;5309defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;5310defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;5311defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;5312defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;5313 5314let Predicates = [HasNEON, HasFPRCVT] in{5315 defm FCVTAS : FPToIntegerSIMDScalar<0b11, 0b010, "fcvtas", int_aarch64_neon_fcvtas>;5316 defm FCVTAU : FPToIntegerSIMDScalar<0b11, 0b011, "fcvtau", int_aarch64_neon_fcvtau>;5317 defm FCVTMS : FPToIntegerSIMDScalar<0b10, 0b100, "fcvtms", int_aarch64_neon_fcvtms>;5318 defm FCVTMU : FPToIntegerSIMDScalar<0b10, 0b101, "fcvtmu", int_aarch64_neon_fcvtmu>;5319 defm FCVTNS : FPToIntegerSIMDScalar<0b01, 0b010, "fcvtns", int_aarch64_neon_fcvtns>;5320 defm FCVTNU : FPToIntegerSIMDScalar<0b01, 0b011, "fcvtnu", int_aarch64_neon_fcvtnu>;5321 defm FCVTPS : FPToIntegerSIMDScalar<0b10, 0b010, "fcvtps", int_aarch64_neon_fcvtps>;5322 defm FCVTPU : FPToIntegerSIMDScalar<0b10, 0b011, "fcvtpu", int_aarch64_neon_fcvtpu>;5323 defm FCVTZS : FPToIntegerSIMDScalar<0b10, 0b110, "fcvtzs", any_fp_to_sint>;5324 defm FCVTZU : FPToIntegerSIMDScalar<0b10, 0b111, "fcvtzu", any_fp_to_uint>;5325}5326 5327 5328 5329let Predicates = [HasFullFP16] in {5330 def : Pat<(i32 (any_lround f16:$Rn)),5331 (FCVTASUWHr f16:$Rn)>;5332 def : Pat<(i64 (any_lround f16:$Rn)),5333 (FCVTASUXHr f16:$Rn)>;5334 def : Pat<(i64 (any_llround f16:$Rn)),5335 (FCVTASUXHr f16:$Rn)>;5336}5337def : Pat<(i32 (any_lround f32:$Rn)),5338 (FCVTASUWSr f32:$Rn)>;5339def : Pat<(i32 (any_lround f64:$Rn)),5340 (FCVTASUWDr f64:$Rn)>;5341def : Pat<(i64 (any_lround f32:$Rn)),5342 (FCVTASUXSr f32:$Rn)>;5343def : Pat<(i64 (any_lround f64:$Rn)),5344 (FCVTASUXDr f64:$Rn)>;5345def : Pat<(i64 (any_llround f32:$Rn)),5346 (FCVTASUXSr f32:$Rn)>;5347def : Pat<(i64 (any_llround f64:$Rn)),5348 (FCVTASUXDr f64:$Rn)>;5349 5350//===----------------------------------------------------------------------===//5351// Scaled integer to floating point conversion instructions.5352//===----------------------------------------------------------------------===//5353 5354defm SCVTF : IntegerToFP<0b00, 0b010, "scvtf", any_sint_to_fp>;5355defm UCVTF : IntegerToFP<0b00, 0b011, "ucvtf", any_uint_to_fp>;5356 5357let Predicates = [HasNEON, HasFPRCVT] in {5358 defm SCVTF : IntegerToFPSIMDScalar<0b11, 0b100, "scvtf", any_sint_to_fp>;5359 defm UCVTF : IntegerToFPSIMDScalar<0b11, 0b101, "ucvtf", any_uint_to_fp>;5360 5361 def : Pat<(v1f64 (extract_subvector (v2f64 (sint_to_fp (v2i64 (sext (v2i32 V64:$Rn))))), (i64 0))),5362 (SCVTFDSr (EXTRACT_SUBREG V64:$Rn, ssub))>;5363 def : Pat<(v1f64 (extract_subvector (v2f64 (uint_to_fp (v2i64 (zext (v2i32 V64:$Rn))))), (i64 0))),5364 (UCVTFDSr (EXTRACT_SUBREG V64:$Rn, ssub))>;5365}5366 5367def : Pat<(f16 (fdiv (f16 (any_sint_to_fp (i32 GPR32:$Rn))), fixedpoint_f16_i32:$scale)),5368 (SCVTFSWHri GPR32:$Rn, fixedpoint_f16_i32:$scale)>;5369def : Pat<(f32 (fdiv (f32 (any_sint_to_fp (i32 GPR32:$Rn))), fixedpoint_f32_i32:$scale)),5370 (SCVTFSWSri GPR32:$Rn, fixedpoint_f32_i32:$scale)>;5371def : Pat<(f64 (fdiv (f64 (any_sint_to_fp (i32 GPR32:$Rn))), fixedpoint_f64_i32:$scale)),5372 (SCVTFSWDri GPR32:$Rn, fixedpoint_f64_i32:$scale)>;5373 5374def : Pat<(f16 (fdiv (f16 (any_sint_to_fp (i64 GPR64:$Rn))), fixedpoint_f16_i64:$scale)),5375 (SCVTFSXHri GPR64:$Rn, fixedpoint_f16_i64:$scale)>;5376def : Pat<(f32 (fdiv (f32 (any_sint_to_fp (i64 GPR64:$Rn))), fixedpoint_f32_i64:$scale)),5377 (SCVTFSXSri GPR64:$Rn, fixedpoint_f32_i64:$scale)>;5378def : Pat<(f64 (fdiv (f64 (any_sint_to_fp (i64 GPR64:$Rn))), fixedpoint_f64_i64:$scale)),5379 (SCVTFSXDri GPR64:$Rn, fixedpoint_f64_i64:$scale)>;5380 5381def : Pat<(f16 (fdiv (f16 (any_uint_to_fp (i64 GPR64:$Rn))), fixedpoint_f16_i64:$scale)),5382 (UCVTFSXHri GPR64:$Rn, fixedpoint_f16_i64:$scale)>;5383def : Pat<(f32 (fdiv (f32 (any_uint_to_fp (i64 GPR64:$Rn))), fixedpoint_f32_i64:$scale)),5384 (UCVTFSXSri GPR64:$Rn, fixedpoint_f32_i64:$scale)>;5385def : Pat<(f64 (fdiv (f64 (any_uint_to_fp (i64 GPR64:$Rn))), fixedpoint_f64_i64:$scale)),5386 (UCVTFSXDri GPR64:$Rn, fixedpoint_f64_i64:$scale)>;5387 5388def : Pat<(f16 (fdiv (f16 (any_uint_to_fp (i32 GPR32:$Rn))), fixedpoint_f16_i32:$scale)),5389 (UCVTFSWHri GPR32:$Rn, fixedpoint_f16_i32:$scale)>;5390def : Pat<(f32 (fdiv (f32 (any_uint_to_fp (i32 GPR32:$Rn))), fixedpoint_f32_i32:$scale)),5391 (UCVTFSWSri GPR32:$Rn, fixedpoint_f32_i32:$scale)>;5392def : Pat<(f64 (fdiv (f64 (any_uint_to_fp (i32 GPR32:$Rn))), fixedpoint_f64_i32:$scale)),5393 (UCVTFSWDri GPR32:$Rn, fixedpoint_f64_i32:$scale)>;5394 5395//===----------------------------------------------------------------------===//5396// Unscaled integer to floating point conversion instruction.5397//===----------------------------------------------------------------------===//5398 5399defm FMOV : UnscaledConversion<"fmov">;5400 5401// Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable5402let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1,5403 Predicates = [HasFPARMv8] in {5404def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>,5405 Sched<[WriteF]>;5406def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,5407 Sched<[WriteF]>;5408def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,5409 Sched<[WriteF]>;5410}5411 5412// Similarly add aliases5413def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>,5414 Requires<[HasFullFP16]>;5415let Predicates = [HasFPARMv8] in {5416def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>;5417def : InstAlias<"fmov $Rd, #0.0", (FMOVXDr FPR64:$Rd, XZR), 0>;5418}5419 5420def : Pat<(bf16 fpimm0),5421 (FMOVH0)>;5422 5423// Pattern for FP16 and BF16 immediates5424let Predicates = [HasFullFP16] in {5425 def : Pat<(f16 fpimm:$in),5426 (FMOVWHr (MOVi32imm (bitcast_fpimm_to_i32 f16:$in)))>;5427 5428 def : Pat<(bf16 fpimm:$in),5429 (FMOVWHr (MOVi32imm (bitcast_fpimm_to_i32 bf16:$in)))>;5430}5431 5432//===----------------------------------------------------------------------===//5433// Floating point conversion instruction.5434//===----------------------------------------------------------------------===//5435 5436defm FCVT : FPConversion<"fcvt">;5437 5438//===----------------------------------------------------------------------===//5439// Floating point single operand instructions.5440//===----------------------------------------------------------------------===//5441 5442defm FABS : SingleOperandFPDataNoException<0b0001, "fabs", fabs>;5443defm FMOV : SingleOperandFPDataNoException<0b0000, "fmov">;5444defm FNEG : SingleOperandFPDataNoException<0b0010, "fneg", fneg>;5445defm FRINTA : SingleOperandFPData<0b1100, "frinta", any_fround>;5446defm FRINTI : SingleOperandFPData<0b1111, "frinti", any_fnearbyint>;5447defm FRINTM : SingleOperandFPData<0b1010, "frintm", any_ffloor>;5448defm FRINTN : SingleOperandFPData<0b1000, "frintn", any_froundeven>;5449defm FRINTP : SingleOperandFPData<0b1001, "frintp", any_fceil>;5450 5451defm FRINTX : SingleOperandFPData<0b1110, "frintx", any_frint>;5452defm FRINTZ : SingleOperandFPData<0b1011, "frintz", any_ftrunc>;5453 5454let SchedRW = [WriteFDiv] in {5455defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", any_fsqrt>;5456}5457 5458let Predicates = [HasFRInt3264] in {5459 defm FRINT32Z : FRIntNNT<0b00, "frint32z", int_aarch64_frint32z>;5460 defm FRINT64Z : FRIntNNT<0b10, "frint64z", int_aarch64_frint64z>;5461 defm FRINT32X : FRIntNNT<0b01, "frint32x", int_aarch64_frint32x>;5462 defm FRINT64X : FRIntNNT<0b11, "frint64x", int_aarch64_frint64x>;5463} // HasFRInt32645464 5465// Pattern to convert 1x64 vector intrinsics to equivalent scalar instructions5466def : Pat<(v1f64 (int_aarch64_neon_frint32z (v1f64 FPR64:$Rn))),5467 (FRINT32ZDr FPR64:$Rn)>;5468def : Pat<(v1f64 (int_aarch64_neon_frint64z (v1f64 FPR64:$Rn))),5469 (FRINT64ZDr FPR64:$Rn)>;5470def : Pat<(v1f64 (int_aarch64_neon_frint32x (v1f64 FPR64:$Rn))),5471 (FRINT32XDr FPR64:$Rn)>;5472def : Pat<(v1f64 (int_aarch64_neon_frint64x (v1f64 FPR64:$Rn))),5473 (FRINT64XDr FPR64:$Rn)>;5474 5475// Emitting strict_lrint as two instructions is valid as any exceptions that5476// occur will happen in exactly one of the instructions (e.g. if the input is5477// not an integer the inexact exception will happen in the FRINTX but not then5478// in the FCVTZS as the output of FRINTX is an integer).5479let Predicates = [HasFullFP16] in {5480 def : Pat<(i32 (any_lrint f16:$Rn)),5481 (FCVTZSUWHr (FRINTXHr f16:$Rn))>;5482 def : Pat<(i64 (any_lrint f16:$Rn)),5483 (FCVTZSUXHr (FRINTXHr f16:$Rn))>;5484 def : Pat<(i64 (any_llrint f16:$Rn)),5485 (FCVTZSUXHr (FRINTXHr f16:$Rn))>;5486}5487def : Pat<(i32 (any_lrint f32:$Rn)),5488 (FCVTZSUWSr (FRINTXSr f32:$Rn))>;5489def : Pat<(i32 (any_lrint f64:$Rn)),5490 (FCVTZSUWDr (FRINTXDr f64:$Rn))>;5491def : Pat<(i64 (any_lrint f32:$Rn)),5492 (FCVTZSUXSr (FRINTXSr f32:$Rn))>;5493def : Pat<(i64 (any_lrint f64:$Rn)),5494 (FCVTZSUXDr (FRINTXDr f64:$Rn))>;5495def : Pat<(i64 (any_llrint f32:$Rn)),5496 (FCVTZSUXSr (FRINTXSr f32:$Rn))>;5497def : Pat<(i64 (any_llrint f64:$Rn)),5498 (FCVTZSUXDr (FRINTXDr f64:$Rn))>;5499 5500//===----------------------------------------------------------------------===//5501// Floating point two operand instructions.5502//===----------------------------------------------------------------------===//5503 5504defm FADD : TwoOperandFPData<0b0010, "fadd", any_fadd>;5505let SchedRW = [WriteFDiv] in {5506defm FDIV : TwoOperandFPData<0b0001, "fdiv", any_fdiv>;5507}5508defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", any_fmaxnum>;5509defm FMAX : TwoOperandFPData<0b0100, "fmax", any_fmaximum>;5510defm FMINNM : TwoOperandFPData<0b0111, "fminnm", any_fminnum>;5511defm FMIN : TwoOperandFPData<0b0101, "fmin", any_fminimum>;5512let SchedRW = [WriteFMul] in {5513defm FMUL : TwoOperandFPData<0b0000, "fmul", any_fmul>;5514defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", any_fmul>;5515}5516defm FSUB : TwoOperandFPData<0b0011, "fsub", any_fsub>;5517 5518multiclass FMULScalarFromIndexedLane0Patterns<string inst,5519 string inst_f16_suffix,5520 string inst_f32_suffix,5521 string inst_f64_suffix,5522 SDPatternOperator OpNode,5523 list<Predicate> preds = []> {5524 let Predicates = !listconcat(preds, [HasFullFP16]) in {5525 def : Pat<(f16 (OpNode (f16 FPR16:$Rn),5526 (f16 (vector_extract (v8f16 V128:$Rm), (i64 0))))),5527 (!cast<Instruction>(inst # inst_f16_suffix)5528 FPR16:$Rn, (f16 (EXTRACT_SUBREG V128:$Rm, hsub)))>;5529 }5530 let Predicates = preds in {5531 def : Pat<(f32 (OpNode (f32 FPR32:$Rn),5532 (f32 (vector_extract (v4f32 V128:$Rm), (i64 0))))),5533 (!cast<Instruction>(inst # inst_f32_suffix)5534 FPR32:$Rn, (EXTRACT_SUBREG V128:$Rm, ssub))>;5535 def : Pat<(f64 (OpNode (f64 FPR64:$Rn),5536 (f64 (vector_extract (v2f64 V128:$Rm), (i64 0))))),5537 (!cast<Instruction>(inst # inst_f64_suffix)5538 FPR64:$Rn, (EXTRACT_SUBREG V128:$Rm, dsub))>;5539 }5540}5541 5542defm : FMULScalarFromIndexedLane0Patterns<"FMUL", "Hrr", "Srr", "Drr",5543 any_fmul>;5544 5545// Match reassociated forms of FNMUL.5546def : Pat<(fmul (fneg FPR16:$a), (f16 FPR16:$b)),5547 (FNMULHrr FPR16:$a, FPR16:$b)>,5548 Requires<[HasFullFP16]>;5549def : Pat<(fmul (fneg FPR32:$a), (f32 FPR32:$b)),5550 (FNMULSrr FPR32:$a, FPR32:$b)>;5551def : Pat<(fmul (fneg FPR64:$a), (f64 FPR64:$b)),5552 (FNMULDrr FPR64:$a, FPR64:$b)>;5553 5554def : Pat<(v1f64 (fmaximum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),5555 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;5556def : Pat<(v1f64 (fminimum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),5557 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;5558def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),5559 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;5560def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),5561 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;5562 5563def : Pat<(fminnum_ieee (f64 FPR64:$a), (f64 FPR64:$b)),5564 (FMINNMDrr FPR64:$a, FPR64:$b)>;5565def : Pat<(fmaxnum_ieee (f64 FPR64:$a), (f64 FPR64:$b)),5566 (FMAXNMDrr FPR64:$a, FPR64:$b)>;5567def : Pat<(f64 (fcanonicalize f64:$a)),5568 (FMINNMDrr f64:$a, f64:$a)>;5569def : Pat<(fminnum_ieee (f32 FPR32:$a), (f32 FPR32:$b)),5570 (FMINNMSrr FPR32:$a, FPR32:$b)>;5571def : Pat<(fmaxnum_ieee (f32 FPR32:$a), (f32 FPR32:$b)),5572 (FMAXNMSrr FPR32:$a, FPR32:$b)>;5573def : Pat<(f32 (fcanonicalize f32:$a)),5574 (FMINNMSrr f32:$a, f32:$a)>;5575 5576let Predicates = [HasFullFP16] in {5577def : Pat<(fminnum_ieee (f16 FPR16:$a), (f16 FPR16:$b)),5578 (FMINNMHrr FPR16:$a, FPR16:$b)>;5579def : Pat<(fmaxnum_ieee (f16 FPR16:$a), (f16 FPR16:$b)),5580 (FMAXNMHrr FPR16:$a, FPR16:$b)>;5581def : Pat<(f16 (fcanonicalize f16:$a)),5582 (FMINNMHrr f16:$a, f16:$a)>;5583}5584//===----------------------------------------------------------------------===//5585// Floating point three operand instructions.5586//===----------------------------------------------------------------------===//5587 5588defm FMADD : ThreeOperandFPData<0, 0, "fmadd", any_fma>;5589defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",5590 TriOpFrag<(any_fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;5591defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",5592 TriOpFrag<(fneg (any_fma node:$LHS, node:$MHS, node:$RHS))> >;5593defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",5594 TriOpFrag<(any_fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;5595 5596// The following def pats catch the case where the LHS of an FMA is negated.5597// The TriOpFrag above catches the case where the middle operand is negated.5598 5599// N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike5600// the NEON variant.5601 5602// Here we handle first -(a + b*c) for FNMADD:5603 5604let Predicates = [HasNEON, HasFullFP16] in5605def : Pat<(f16 (fma (fneg FPR16:$Rn), FPR16:$Rm, FPR16:$Ra)),5606 (FMSUBHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>;5607 5608def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),5609 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;5610 5611def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),5612 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;5613 5614// Now it's time for "(-a) + (-b)*c"5615 5616let Predicates = [HasNEON, HasFullFP16] in5617def : Pat<(f16 (fma (fneg FPR16:$Rn), FPR16:$Rm, (fneg FPR16:$Ra))),5618 (FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>;5619 5620def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),5621 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;5622 5623def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),5624 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;5625 5626//===----------------------------------------------------------------------===//5627// Floating point comparison instructions.5628//===----------------------------------------------------------------------===//5629 5630defm FCMPE : FPComparison<1, "fcmpe", AArch64strict_fcmpe>;5631defm FCMP : FPComparison<0, "fcmp", AArch64any_fcmp>;5632 5633//===----------------------------------------------------------------------===//5634// Floating point conditional comparison instructions.5635//===----------------------------------------------------------------------===//5636 5637defm FCCMPE : FPCondComparison<1, "fccmpe">;5638defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>;5639 5640//===----------------------------------------------------------------------===//5641// Floating point conditional select instruction.5642//===----------------------------------------------------------------------===//5643 5644defm FCSEL : FPCondSelect<"fcsel">;5645 5646let Predicates = [HasFullFP16] in5647def : Pat<(bf16 (AArch64csel (bf16 FPR16:$Rn), (bf16 FPR16:$Rm), (i32 imm:$cond), NZCV)),5648 (FCSELHrrr FPR16:$Rn, FPR16:$Rm, imm:$cond)>;5649 5650// CSEL instructions providing f128 types need to be handled by a5651// pseudo-instruction since the eventual code will need to introduce basic5652// blocks and control flow.5653let Predicates = [HasFPARMv8] in5654def F128CSEL : Pseudo<(outs FPR128:$Rd),5655 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),5656 [(set (f128 FPR128:$Rd),5657 (AArch64csel FPR128:$Rn, FPR128:$Rm,5658 (i32 imm:$cond), NZCV))]> {5659 let Uses = [NZCV];5660 let usesCustomInserter = 1;5661 let hasNoSchedulingInfo = 1;5662}5663 5664//===----------------------------------------------------------------------===//5665// Instructions used for emitting unwind opcodes on ARM64 Windows.5666//===----------------------------------------------------------------------===//5667let isPseudo = 1 in {5668 def SEH_StackAlloc : Pseudo<(outs), (ins i32imm:$size), []>, Sched<[]>;5669 def SEH_SaveFPLR : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>;5670 def SEH_SaveFPLR_X : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>;5671 def SEH_SaveReg : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>;5672 def SEH_SaveReg_X : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>;5673 def SEH_SaveRegP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;5674 def SEH_SaveRegP_X : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;5675 def SEH_SaveFReg : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>;5676 def SEH_SaveFReg_X : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>;5677 def SEH_SaveFRegP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;5678 def SEH_SaveFRegP_X : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;5679 def SEH_SetFP : Pseudo<(outs), (ins), []>, Sched<[]>;5680 def SEH_AddFP : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>;5681 def SEH_Nop : Pseudo<(outs), (ins), []>, Sched<[]>;5682 def SEH_PrologEnd : Pseudo<(outs), (ins), []>, Sched<[]>;5683 def SEH_EpilogStart : Pseudo<(outs), (ins), []>, Sched<[]>;5684 def SEH_EpilogEnd : Pseudo<(outs), (ins), []>, Sched<[]>;5685 def SEH_PACSignLR : Pseudo<(outs), (ins), []>, Sched<[]>;5686 def SEH_SaveAnyRegI : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$offs), []>, Sched<[]>;5687 def SEH_SaveAnyRegIP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;5688 def SEH_SaveAnyRegQP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;5689 def SEH_SaveAnyRegQPX : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>;5690 def SEH_AllocZ : Pseudo<(outs), (ins i32imm:$offs), []>, Sched<[]>;5691 def SEH_SaveZReg : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>;5692 def SEH_SavePReg : Pseudo<(outs), (ins i32imm:$reg, i32imm:$offs), []>, Sched<[]>;5693}5694 5695// Pseudo instructions for Windows EH5696//===----------------------------------------------------------------------===//5697let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,5698 isCodeGenOnly = 1, isReturn = 1, isEHScopeReturn = 1, isPseudo = 1 in {5699 def CLEANUPRET : Pseudo<(outs), (ins), [(cleanupret bb)]>, Sched<[]>;5700 let usesCustomInserter = 1 in5701 def CATCHRET : Pseudo<(outs), (ins am_brcond:$dst, am_brcond:$src), [(catchret bb:$dst, bb:$src)]>,5702 Sched<[]>;5703}5704 5705// Pseudo instructions for homogeneous prolog/epilog5706let isPseudo = 1 in {5707 // Save CSRs in order, {FPOffset}5708 def HOM_Prolog : Pseudo<(outs), (ins variable_ops), []>, Sched<[]>;5709 // Restore CSRs in order5710 def HOM_Epilog : Pseudo<(outs), (ins variable_ops), []>, Sched<[]>;5711}5712 5713//===----------------------------------------------------------------------===//5714// Floating point immediate move.5715//===----------------------------------------------------------------------===//5716 5717let isReMaterializable = 1, isAsCheapAsAMove = 1 in {5718defm FMOV : FPMoveImmediate<"fmov">;5719}5720 5721let Predicates = [HasFullFP16] in {5722 def : Pat<(bf16 fpimmbf16:$in),5723 (FMOVHi (fpimm16XForm bf16:$in))>;5724}5725 5726//===----------------------------------------------------------------------===//5727// Advanced SIMD two vector instructions.5728//===----------------------------------------------------------------------===//5729 5730defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", abs>;5731defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;5732defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;5733defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;5734defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;5735defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;5736defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;5737defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;5738defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;5739defm FABS : SIMDTwoVectorFPNoException<0, 1, 0b01111, "fabs", fabs>;5740 5741def : Pat<(v8i8 (AArch64vashr (v8i8 V64:$Rn), (i32 7))),5742 (CMLTv8i8rz V64:$Rn)>;5743def : Pat<(v4i16 (AArch64vashr (v4i16 V64:$Rn), (i32 15))),5744 (CMLTv4i16rz V64:$Rn)>;5745def : Pat<(v2i32 (AArch64vashr (v2i32 V64:$Rn), (i32 31))),5746 (CMLTv2i32rz V64:$Rn)>;5747def : Pat<(v16i8 (AArch64vashr (v16i8 V128:$Rn), (i32 7))),5748 (CMLTv16i8rz V128:$Rn)>;5749def : Pat<(v8i16 (AArch64vashr (v8i16 V128:$Rn), (i32 15))),5750 (CMLTv8i16rz V128:$Rn)>;5751def : Pat<(v4i32 (AArch64vashr (v4i32 V128:$Rn), (i32 31))),5752 (CMLTv4i32rz V128:$Rn)>;5753def : Pat<(v2i64 (AArch64vashr (v2i64 V128:$Rn), (i32 63))),5754 (CMLTv2i64rz V128:$Rn)>;5755 5756defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;5757defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;5758defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;5759defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;5760defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;5761defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;5762defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;5763defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;5764def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),5765 (FCVTLv4i16 V64:$Rn)>;5766def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),5767 (i64 4)))),5768 (FCVTLv8i16 V128:$Rn)>;5769def : Pat<(v2f64 (any_fpextend (v2f32 V64:$Rn))),5770 (FCVTLv2i32 V64:$Rn)>;5771def : Pat<(v2f64 (any_fpextend (v2f32 (extract_high_v4f32 (v4f32 V128:$Rn))))),5772 (FCVTLv4i32 V128:$Rn)>;5773def : Pat<(v4f32 (any_fpextend (v4f16 V64:$Rn))),5774 (FCVTLv4i16 V64:$Rn)>;5775def : Pat<(v4f32 (any_fpextend (v4f16 (extract_high_v8f16 (v8f16 V128:$Rn))))),5776 (FCVTLv8i16 V128:$Rn)>;5777 5778defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;5779defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;5780defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;5781defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;5782defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;5783def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),5784 (FCVTNv4i16 V128:$Rn)>;5785def : Pat<(concat_vectors V64:$Rd,5786 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),5787 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;5788def : Pat<(v2f32 (any_fpround (v2f64 V128:$Rn))),5789 (FCVTNv2i32 V128:$Rn)>;5790def : Pat<(v4f16 (any_fpround (v4f32 V128:$Rn))),5791 (FCVTNv4i16 V128:$Rn)>;5792def : Pat<(concat_vectors V64:$Rd, (v2f32 (any_fpround (v2f64 V128:$Rn)))),5793 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;5794def : Pat<(concat_vectors V64:$Rd, (v4f16 (any_fpround (v4f32 V128:$Rn)))),5795 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;5796defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;5797defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;5798defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",5799 AArch64fcvtxnv>;5800defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", any_fp_to_sint>;5801defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", any_fp_to_uint>;5802 5803// AArch64's FCVT instructions saturate when out of range.5804multiclass SIMDTwoVectorFPToIntSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string INST> {5805 let Predicates = [HasFullFP16] in {5806 def : Pat<(v4i16 (to_int_sat v4f16:$Rn, i16)),5807 (!cast<Instruction>(INST # v4f16) v4f16:$Rn)>;5808 def : Pat<(v8i16 (to_int_sat v8f16:$Rn, i16)),5809 (!cast<Instruction>(INST # v8f16) v8f16:$Rn)>;5810 5811 def : Pat<(v4i16 (to_int_sat_gi v4f16:$Rn)),5812 (!cast<Instruction>(INST # v4f16) v4f16:$Rn)>;5813 def : Pat<(v8i16 (to_int_sat_gi v8f16:$Rn)),5814 (!cast<Instruction>(INST # v8f16) v8f16:$Rn)>;5815 }5816 def : Pat<(v2i32 (to_int_sat v2f32:$Rn, i32)),5817 (!cast<Instruction>(INST # v2f32) v2f32:$Rn)>;5818 def : Pat<(v4i32 (to_int_sat v4f32:$Rn, i32)),5819 (!cast<Instruction>(INST # v4f32) v4f32:$Rn)>;5820 def : Pat<(v2i64 (to_int_sat v2f64:$Rn, i64)),5821 (!cast<Instruction>(INST # v2f64) v2f64:$Rn)>;5822 5823 def : Pat<(v2i32 (to_int_sat_gi v2f32:$Rn)),5824 (!cast<Instruction>(INST # v2f32) v2f32:$Rn)>;5825 def : Pat<(v4i32 (to_int_sat_gi v4f32:$Rn)),5826 (!cast<Instruction>(INST # v4f32) v4f32:$Rn)>;5827 def : Pat<(v2i64 (to_int_sat_gi v2f64:$Rn)),5828 (!cast<Instruction>(INST # v2f64) v2f64:$Rn)>;5829}5830defm : SIMDTwoVectorFPToIntSatPats<fp_to_sint_sat, fp_to_sint_sat_gi, "FCVTZS">;5831defm : SIMDTwoVectorFPToIntSatPats<fp_to_uint_sat, fp_to_uint_sat_gi, "FCVTZU">;5832 5833def : Pat<(v4i16 (int_aarch64_neon_fcvtzs v4f16:$Rn)), (FCVTZSv4f16 $Rn)>;5834def : Pat<(v8i16 (int_aarch64_neon_fcvtzs v8f16:$Rn)), (FCVTZSv8f16 $Rn)>;5835def : Pat<(v2i32 (int_aarch64_neon_fcvtzs v2f32:$Rn)), (FCVTZSv2f32 $Rn)>;5836def : Pat<(v4i32 (int_aarch64_neon_fcvtzs v4f32:$Rn)), (FCVTZSv4f32 $Rn)>;5837def : Pat<(v2i64 (int_aarch64_neon_fcvtzs v2f64:$Rn)), (FCVTZSv2f64 $Rn)>;5838 5839def : Pat<(v4i16 (int_aarch64_neon_fcvtzu v4f16:$Rn)), (FCVTZUv4f16 $Rn)>;5840def : Pat<(v8i16 (int_aarch64_neon_fcvtzu v8f16:$Rn)), (FCVTZUv8f16 $Rn)>;5841def : Pat<(v2i32 (int_aarch64_neon_fcvtzu v2f32:$Rn)), (FCVTZUv2f32 $Rn)>;5842def : Pat<(v4i32 (int_aarch64_neon_fcvtzu v4f32:$Rn)), (FCVTZUv4f32 $Rn)>;5843def : Pat<(v2i64 (int_aarch64_neon_fcvtzu v2f64:$Rn)), (FCVTZUv2f64 $Rn)>;5844 5845defm FNEG : SIMDTwoVectorFPNoException<1, 1, 0b01111, "fneg", fneg>;5846defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;5847defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", any_fround>;5848defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", any_fnearbyint>;5849defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", any_ffloor>;5850defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", any_froundeven>;5851defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", any_fceil>;5852defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", any_frint>;5853defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", any_ftrunc>;5854 5855let Predicates = [HasFRInt3264] in {5856 defm FRINT32Z : FRIntNNTVector<0, 0, "frint32z", int_aarch64_neon_frint32z>;5857 defm FRINT64Z : FRIntNNTVector<0, 1, "frint64z", int_aarch64_neon_frint64z>;5858 defm FRINT32X : FRIntNNTVector<1, 0, "frint32x", int_aarch64_neon_frint32x>;5859 defm FRINT64X : FRIntNNTVector<1, 1, "frint64x", int_aarch64_neon_frint64x>;5860} // HasFRInt32645861 5862defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;5863defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", any_fsqrt>;5864defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",5865 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;5866defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;5867// Aliases for MVN -> NOT.5868let Predicates = [HasNEON] in {5869def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",5870 (NOTv8i8 V64:$Vd, V64:$Vn)>;5871def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",5872 (NOTv16i8 V128:$Vd, V128:$Vn)>;5873}5874 5875def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;5876def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;5877def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;5878def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;5879def : Pat<(vnot (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;5880def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;5881 5882defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", bitreverse>;5883defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;5884defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;5885defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;5886defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",5887 BinOpFrag<(add node:$LHS, (AArch64saddlp node:$RHS))> >;5888defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", AArch64saddlp>;5889defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", any_sint_to_fp>;5890defm SHLL : SIMDVectorLShiftLongBySizeBHS;5891defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;5892defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;5893defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", truncssat_s>;5894defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", truncssat_u>;5895defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;5896defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",5897 BinOpFrag<(add node:$LHS, (AArch64uaddlp node:$RHS))> >;5898defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp", AArch64uaddlp>;5899defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", any_uint_to_fp>;5900defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", truncusat_u>;5901defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;5902defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;5903defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;5904defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;5905 5906def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;5907def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;5908def : Pat<(v4bf16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;5909def : Pat<(v4bf16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;5910def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;5911def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;5912def : Pat<(v8bf16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;5913def : Pat<(v8bf16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;5914def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;5915def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;5916 5917// Patterns for vector long shift (by element width). These need to match all5918// three of zext, sext and anyext so it's easier to pull the patterns out of the5919// definition.5920multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {5921 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),5922 (SHLLv8i8 V64:$Rn)>;5923 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 (v16i8 V128:$Rn)))), (i32 8)),5924 (SHLLv16i8 V128:$Rn)>;5925 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),5926 (SHLLv4i16 V64:$Rn)>;5927 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 (v8i16 V128:$Rn)))), (i32 16)),5928 (SHLLv8i16 V128:$Rn)>;5929 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),5930 (SHLLv2i32 V64:$Rn)>;5931 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 (v4i32 V128:$Rn)))), (i32 32)),5932 (SHLLv4i32 V128:$Rn)>;5933}5934 5935defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;5936defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;5937defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;5938 5939// Select BSWAP vector instructions into REV instructions5940def : Pat<(v4i16 (bswap (v4i16 V64:$Rn))),5941 (v4i16 (REV16v8i8 (v4i16 V64:$Rn)))>;5942def : Pat<(v8i16 (bswap (v8i16 V128:$Rn))),5943 (v8i16 (REV16v16i8 (v8i16 V128:$Rn)))>;5944def : Pat<(v2i32 (bswap (v2i32 V64:$Rn))),5945 (v2i32 (REV32v8i8 (v2i32 V64:$Rn)))>;5946def : Pat<(v4i32 (bswap (v4i32 V128:$Rn))),5947 (v4i32 (REV32v16i8 (v4i32 V128:$Rn)))>;5948def : Pat<(v2i64 (bswap (v2i64 V128:$Rn))),5949 (v2i64 (REV64v16i8 (v2i64 V128:$Rn)))>;5950 5951// Patterns for funnel shifts to be matched to equivalent REV instructions5952def : Pat<(v2i64 (or (v2i64 (AArch64vshl (v2i64 V128:$Rn), (i32 32))),5953 (v2i64 (AArch64vlshr (v2i64 V128:$Rn), (i32 32))))),5954 (v2i64 (REV64v4i32 (v2i64 V128:$Rn)))>;5955def : Pat<(v4i32 (or (v4i32 (AArch64vshl (v4i32 V128:$Rn), (i32 16))),5956 (v4i32 (AArch64vlshr (v4i32 V128:$Rn), (i32 16))))),5957 (v4i32 (REV32v8i16 (v4i32 V128:$Rn)))>;5958def : Pat<(v2i32 (or (v2i32 (AArch64vshl (v2i32 V64:$Rn), (i32 16))),5959 (v2i32 (AArch64vlshr (v2i32 V64:$Rn), (i32 16))))),5960 (v2i32 (REV32v4i16 (v2i32 V64:$Rn)))>;5961 5962//===----------------------------------------------------------------------===//5963// Advanced SIMD three vector instructions.5964//===----------------------------------------------------------------------===//5965 5966defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;5967defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", AArch64addp>;5968defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;5969defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;5970defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;5971defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;5972defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;5973defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;5974foreach VT = [ v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64 ] in {5975def : Pat<(VT (vnot (AArch64cmeqz VT:$Rn))), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rn)>;5976}5977defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>;5978let Predicates = [HasNEON] in {5979foreach VT = [ v2f32, v4f32, v2f64 ] in5980def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;5981}5982let Predicates = [HasNEON, HasFullFP16] in {5983foreach VT = [ v4f16, v8f16 ] in5984def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;5985}5986defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",AArch64facge>;5987defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",AArch64facgt>;5988defm FADDP : SIMDThreeSameVectorFP<1,0,0b010,"faddp", AArch64faddp>;5989defm FADD : SIMDThreeSameVectorFP<0,0,0b010,"fadd", any_fadd>;5990defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;5991defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;5992defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;5993defm FDIV : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", any_fdiv>;5994defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;5995defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", any_fmaxnum>;5996defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>;5997defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", any_fmaximum>;5998defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>;5999defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", any_fminnum>;6000defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>;6001defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", any_fminimum>;6002 6003let Predicates = [HasNEON] in {6004def : Pat<(v2f64 (fminnum_ieee (v2f64 V128:$Rn), (v2f64 V128:$Rm))),6005 (v2f64 (FMINNMv2f64 (v2f64 V128:$Rn), (v2f64 V128:$Rm)))>;6006def : Pat<(v2f64 (fmaxnum_ieee (v2f64 V128:$Rn), (v2f64 V128:$Rm))),6007 (v2f64 (FMAXNMv2f64 (v2f64 V128:$Rn), (v2f64 V128:$Rm)))>;6008def : Pat<(v2f64 (fcanonicalize (v2f64 V128:$Rn))),6009 (v2f64 (FMINNMv2f64 (v2f64 V128:$Rn), (v2f64 V128:$Rn)))>;6010def : Pat<(v4f32 (fminnum_ieee (v4f32 V128:$Rn), (v4f32 V128:$Rm))),6011 (v4f32 (FMINNMv4f32 (v4f32 V128:$Rn), (v4f32 V128:$Rm)))>;6012def : Pat<(v4f32 (fmaxnum_ieee (v4f32 V128:$Rn), (v4f32 V128:$Rm))),6013 (v4f32 (FMAXNMv4f32 (v4f32 V128:$Rn), (v4f32 V128:$Rm)))>;6014def : Pat<(v4f32 (fcanonicalize (v4f32 V128:$Rn))),6015 (v4f32 (FMINNMv4f32 (v4f32 V128:$Rn), (v4f32 V128:$Rn)))>;6016def : Pat<(v2f32 (fminnum_ieee (v2f32 V64:$Rn), (v2f32 V64:$Rm))),6017 (v2f32 (FMINNMv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm)))>;6018def : Pat<(v2f32 (fmaxnum_ieee (v2f32 V64:$Rn), (v2f32 V64:$Rm))),6019 (v2f32 (FMAXNMv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm)))>;6020def : Pat<(v2f32 (fcanonicalize (v2f32 V64:$Rn))),6021 (v2f32 (FMINNMv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rn)))>;6022}6023 6024let Predicates = [HasNEON, HasFullFP16] in {6025def : Pat<(v8f16 (fminnum_ieee (v8f16 V128:$Rn), (v8f16 V128:$Rm))),6026 (v8f16 (FMINNMv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm)))>;6027def : Pat<(v8f16 (fmaxnum_ieee (v8f16 V128:$Rn), (v8f16 V128:$Rm))),6028 (v8f16 (FMAXNMv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm)))>;6029def : Pat<(v8f16 (fcanonicalize (v8f16 V128:$Rn))),6030 (v8f16 (FMINNMv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rn)))>;6031def : Pat<(v4f16 (fminnum_ieee (v4f16 V64:$Rn), (v4f16 V64:$Rm))),6032 (v4f16 (FMINNMv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm)))>;6033def : Pat<(v4f16 (fmaxnum_ieee (v4f16 V64:$Rn), (v4f16 V64:$Rm))),6034 (v4f16 (FMAXNMv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm)))>;6035def : Pat<(v4f16 (fcanonicalize (v4f16 V64:$Rn))),6036 (v4f16 (FMINNMv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rn)))>;6037}6038 6039// NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the6040// instruction expects the addend first, while the fma intrinsic puts it last.6041defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla",6042 TriOpFrag<(any_fma node:$RHS, node:$MHS, node:$LHS)> >;6043defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls",6044 TriOpFrag<(any_fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;6045 6046defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>;6047defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", any_fmul>;6048defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>;6049defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>;6050defm FSUB : SIMDThreeSameVectorFP<0,1,0b010,"fsub", any_fsub>;6051 6052// MLA and MLS are generated in MachineCombine6053defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla", null_frag>;6054defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls", null_frag>;6055 6056defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;6057let isCommutable = 1 in6058defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;6059defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",6060 TriOpFrag<(add node:$LHS, (abds node:$MHS, node:$RHS))> >;6061defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", abds>;6062defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", avgfloors>;6063defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;6064defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;6065defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>;6066defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;6067defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>;6068defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", saddsat>;6069defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;6070defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;6071defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;6072defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;6073defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", ssubsat>;6074defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd", avgceils>;6075defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;6076defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;6077defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;6078defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",6079 TriOpFrag<(add node:$LHS, (abdu node:$MHS, node:$RHS))> >;6080defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", abdu>;6081defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", avgflooru>;6082defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;6083defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;6084defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>;6085defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;6086defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>;6087defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", uaddsat>;6088defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;6089defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;6090defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", usubsat>;6091defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", avgceilu>;6092defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;6093defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;6094defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",6095 int_aarch64_neon_sqrdmlah>;6096defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",6097 int_aarch64_neon_sqrdmlsh>;6098 6099defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;6100defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",6101 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;6102defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;6103defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",6104 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;6105defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;6106 6107// Pseudo bitwise select pattern BSP.6108// It is expanded into BSL/BIT/BIF after register allocation.6109defm BSP : SIMDLogicalThreeVectorPseudo<TriOpFrag<(or (and node:$LHS, node:$MHS),6110 (and (vnot node:$LHS), node:$RHS))>>;6111defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl">;6112defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit">;6113defm BIF : SIMDLogicalThreeVectorTied<1, 0b11, "bif">;6114 6115def : Pat<(AArch64bsp (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),6116 (BSPv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;6117def : Pat<(AArch64bsp (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),6118 (BSPv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;6119def : Pat<(AArch64bsp (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),6120 (BSPv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;6121def : Pat<(AArch64bsp (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),6122 (BSPv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;6123 6124def : Pat<(AArch64bsp (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),6125 (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;6126def : Pat<(AArch64bsp (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),6127 (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;6128def : Pat<(AArch64bsp (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),6129 (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;6130def : Pat<(AArch64bsp (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),6131 (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;6132 6133// The following SetCC patterns are used for GlobalISel only6134multiclass SelectSetCC<PatFrags InFrag, string INST> {6135 def : Pat<(v8i8 (InFrag (v8i8 V64:$Rn), (v8i8 V64:$Rm))),6136 (v8i8 (!cast<Instruction>(INST # v8i8) (v8i8 V64:$Rn), (v8i8 V64:$Rm)))>;6137 def : Pat<(v16i8 (InFrag (v16i8 V128:$Rn), (v16i8 V128:$Rm))),6138 (v16i8 (!cast<Instruction>(INST # v16i8) (v16i8 V128:$Rn), (v16i8 V128:$Rm)))>;6139 def : Pat<(v4i16 (InFrag (v4i16 V64:$Rn), (v4i16 V64:$Rm))),6140 (v4i16 (!cast<Instruction>(INST # v4i16) (v4i16 V64:$Rn), (v4i16 V64:$Rm)))>;6141 def : Pat<(v8i16 (InFrag (v8i16 V128:$Rn), (v8i16 V128:$Rm))),6142 (v8i16 (!cast<Instruction>(INST # v8i16) (v8i16 V128:$Rn), (v8i16 V128:$Rm)))>;6143 def : Pat<(v2i32 (InFrag (v2i32 V64:$Rn), (v2i32 V64:$Rm))),6144 (v2i32 (!cast<Instruction>(INST # v2i32) (v2i32 V64:$Rn), (v2i32 V64:$Rm)))>;6145 def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), (v4i32 V128:$Rm))),6146 (v4i32 (!cast<Instruction>(INST # v4i32) (v4i32 V128:$Rn), (v4i32 V128:$Rm)))>;6147 def : Pat<(v2i64 (InFrag (v2i64 V128:$Rn), (v2i64 V128:$Rm))),6148 (v2i64 (!cast<Instruction>(INST # v2i64) (v2i64 V128:$Rn), (v2i64 V128:$Rm)))>;6149}6150 6151defm : SelectSetCC<seteq, "CMEQ">;6152defm : SelectSetCC<setgt, "CMGT">;6153defm : SelectSetCC<setge, "CMGE">;6154defm : SelectSetCC<setugt, "CMHI">;6155defm : SelectSetCC<setuge, "CMHS">;6156 6157multiclass SelectSetCCSwapOperands<PatFrags InFrag, string INST> {6158 def : Pat<(v8i8 (InFrag (v8i8 V64:$Rn), (v8i8 V64:$Rm))),6159 (v8i8 (!cast<Instruction>(INST # v8i8) (v8i8 V64:$Rm), (v8i8 V64:$Rn)))>;6160 def : Pat<(v16i8 (InFrag (v16i8 V128:$Rn), (v16i8 V128:$Rm))),6161 (v16i8 (!cast<Instruction>(INST # v16i8) (v16i8 V128:$Rm), (v16i8 V128:$Rn)))>;6162 def : Pat<(v4i16 (InFrag (v4i16 V64:$Rn), (v4i16 V64:$Rm))),6163 (v4i16 (!cast<Instruction>(INST # v4i16) (v4i16 V64:$Rm), (v4i16 V64:$Rn)))>;6164 def : Pat<(v8i16 (InFrag (v8i16 V128:$Rn), (v8i16 V128:$Rm))),6165 (v8i16 (!cast<Instruction>(INST # v8i16) (v8i16 V128:$Rm), (v8i16 V128:$Rn)))>;6166 def : Pat<(v2i32 (InFrag (v2i32 V64:$Rn), (v2i32 V64:$Rm))),6167 (v2i32 (!cast<Instruction>(INST # v2i32) (v2i32 V64:$Rm), (v2i32 V64:$Rn)))>;6168 def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), (v4i32 V128:$Rm))),6169 (v4i32 (!cast<Instruction>(INST # v4i32) (v4i32 V128:$Rm), (v4i32 V128:$Rn)))>;6170 def : Pat<(v2i64 (InFrag (v2i64 V128:$Rn), (v2i64 V128:$Rm))),6171 (v2i64 (!cast<Instruction>(INST # v2i64) (v2i64 V128:$Rm), (v2i64 V128:$Rn)))>;6172}6173 6174defm : SelectSetCCSwapOperands<setlt, "CMGT">;6175defm : SelectSetCCSwapOperands<setle, "CMGE">;6176defm : SelectSetCCSwapOperands<setult, "CMHI">;6177defm : SelectSetCCSwapOperands<setule, "CMHS">;6178 6179multiclass SelectSetCCZeroRHS<PatFrags InFrag, string INST> {6180 def : Pat<(v8i8 (InFrag (v8i8 V64:$Rn), immAllZerosV)),6181 (v8i8 (!cast<Instruction>(INST # v8i8rz) (v8i8 V64:$Rn)))>;6182 def : Pat<(v16i8 (InFrag (v16i8 V128:$Rn), immAllZerosV)),6183 (v16i8 (!cast<Instruction>(INST # v16i8rz) (v16i8 V128:$Rn)))>;6184 def : Pat<(v4i16 (InFrag (v4i16 V64:$Rn), immAllZerosV)),6185 (v4i16 (!cast<Instruction>(INST # v4i16rz) (v4i16 V64:$Rn)))>;6186 def : Pat<(v8i16 (InFrag (v8i16 V128:$Rn), immAllZerosV)),6187 (v8i16 (!cast<Instruction>(INST # v8i16rz) (v8i16 V128:$Rn)))>;6188 def : Pat<(v2i32 (InFrag (v2i32 V64:$Rn), immAllZerosV)),6189 (v2i32 (!cast<Instruction>(INST # v2i32rz) (v2i32 V64:$Rn)))>;6190 def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), immAllZerosV)),6191 (v4i32 (!cast<Instruction>(INST # v4i32rz) (v4i32 V128:$Rn)))>;6192 def : Pat<(v2i64 (InFrag (v2i64 V128:$Rn), immAllZerosV)),6193 (v2i64 (!cast<Instruction>(INST # v2i64rz) (v2i64 V128:$Rn)))>;6194}6195 6196defm : SelectSetCCZeroRHS<seteq, "CMEQ">;6197defm : SelectSetCCZeroRHS<setgt, "CMGT">;6198defm : SelectSetCCZeroRHS<setge, "CMGE">;6199defm : SelectSetCCZeroRHS<setlt, "CMLT">;6200defm : SelectSetCCZeroRHS<setle, "CMLE">;6201 6202multiclass SelectSetCCZeroLHS<PatFrags InFrag, string INST> {6203 def : Pat<(v8i8 (InFrag immAllZerosV, (v8i8 V64:$Rn))),6204 (v8i8 (!cast<Instruction>(INST # v8i8rz) (v8i8 V64:$Rn)))>;6205 def : Pat<(v16i8 (InFrag immAllZerosV, (v16i8 V128:$Rn))),6206 (v16i8 (!cast<Instruction>(INST # v16i8rz) (v16i8 V128:$Rn)))>;6207 def : Pat<(v4i16 (InFrag immAllZerosV, (v4i16 V64:$Rn))),6208 (v4i16 (!cast<Instruction>(INST # v4i16rz) (v4i16 V64:$Rn)))>;6209 def : Pat<(v8i16 (InFrag immAllZerosV, (v8i16 V128:$Rn))),6210 (v8i16 (!cast<Instruction>(INST # v8i16rz) (v8i16 V128:$Rn)))>;6211 def : Pat<(v2i32 (InFrag immAllZerosV, (v2i32 V64:$Rn))),6212 (v2i32 (!cast<Instruction>(INST # v2i32rz) (v2i32 V64:$Rn)))>;6213 def : Pat<(v4i32 (InFrag immAllZerosV, (v4i32 V128:$Rn))),6214 (v4i32 (!cast<Instruction>(INST # v4i32rz) (v4i32 V128:$Rn)))>;6215 def : Pat<(v2i64 (InFrag immAllZerosV, (v2i64 V128:$Rn))),6216 (v2i64 (!cast<Instruction>(INST # v2i64rz) (v2i64 V128:$Rn)))>;6217}6218 6219defm : SelectSetCCZeroLHS<seteq, "CMEQ">;6220defm : SelectSetCCZeroLHS<setgt, "CMLT">;6221defm : SelectSetCCZeroLHS<setge, "CMLE">;6222defm : SelectSetCCZeroLHS<setlt, "CMGT">;6223defm : SelectSetCCZeroLHS<setle, "CMGE">;6224 6225let Predicates = [HasNEON] in {6226def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",6227 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;6228def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",6229 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;6230def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",6231 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;6232def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",6233 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;6234 6235def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",6236 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;6237def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",6238 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;6239def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",6240 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;6241def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",6242 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;6243 6244def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #6245 "|cmls.8b\t$dst, $src1, $src2}",6246 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;6247def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #6248 "|cmls.16b\t$dst, $src1, $src2}",6249 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;6250def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #6251 "|cmls.4h\t$dst, $src1, $src2}",6252 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;6253def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #6254 "|cmls.8h\t$dst, $src1, $src2}",6255 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;6256def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #6257 "|cmls.2s\t$dst, $src1, $src2}",6258 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;6259def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #6260 "|cmls.4s\t$dst, $src1, $src2}",6261 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;6262def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #6263 "|cmls.2d\t$dst, $src1, $src2}",6264 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;6265 6266def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #6267 "|cmlo.8b\t$dst, $src1, $src2}",6268 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;6269def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #6270 "|cmlo.16b\t$dst, $src1, $src2}",6271 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;6272def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #6273 "|cmlo.4h\t$dst, $src1, $src2}",6274 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;6275def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #6276 "|cmlo.8h\t$dst, $src1, $src2}",6277 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;6278def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #6279 "|cmlo.2s\t$dst, $src1, $src2}",6280 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;6281def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #6282 "|cmlo.4s\t$dst, $src1, $src2}",6283 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;6284def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #6285 "|cmlo.2d\t$dst, $src1, $src2}",6286 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;6287 6288def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #6289 "|cmle.8b\t$dst, $src1, $src2}",6290 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;6291def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #6292 "|cmle.16b\t$dst, $src1, $src2}",6293 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;6294def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #6295 "|cmle.4h\t$dst, $src1, $src2}",6296 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;6297def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #6298 "|cmle.8h\t$dst, $src1, $src2}",6299 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;6300def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #6301 "|cmle.2s\t$dst, $src1, $src2}",6302 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;6303def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #6304 "|cmle.4s\t$dst, $src1, $src2}",6305 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;6306def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #6307 "|cmle.2d\t$dst, $src1, $src2}",6308 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;6309 6310def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #6311 "|cmlt.8b\t$dst, $src1, $src2}",6312 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;6313def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #6314 "|cmlt.16b\t$dst, $src1, $src2}",6315 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;6316def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #6317 "|cmlt.4h\t$dst, $src1, $src2}",6318 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;6319def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #6320 "|cmlt.8h\t$dst, $src1, $src2}",6321 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;6322def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #6323 "|cmlt.2s\t$dst, $src1, $src2}",6324 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;6325def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #6326 "|cmlt.4s\t$dst, $src1, $src2}",6327 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;6328def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #6329 "|cmlt.2d\t$dst, $src1, $src2}",6330 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;6331 6332let Predicates = [HasNEON, HasFullFP16] in {6333def : InstAlias<"{fcmle\t$dst.4h, $src1.4h, $src2.4h" #6334 "|fcmle.4h\t$dst, $src1, $src2}",6335 (FCMGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;6336def : InstAlias<"{fcmle\t$dst.8h, $src1.8h, $src2.8h" #6337 "|fcmle.8h\t$dst, $src1, $src2}",6338 (FCMGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;6339}6340def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #6341 "|fcmle.2s\t$dst, $src1, $src2}",6342 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;6343def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #6344 "|fcmle.4s\t$dst, $src1, $src2}",6345 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;6346def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #6347 "|fcmle.2d\t$dst, $src1, $src2}",6348 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;6349 6350let Predicates = [HasNEON, HasFullFP16] in {6351def : InstAlias<"{fcmlt\t$dst.4h, $src1.4h, $src2.4h" #6352 "|fcmlt.4h\t$dst, $src1, $src2}",6353 (FCMGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;6354def : InstAlias<"{fcmlt\t$dst.8h, $src1.8h, $src2.8h" #6355 "|fcmlt.8h\t$dst, $src1, $src2}",6356 (FCMGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;6357}6358def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #6359 "|fcmlt.2s\t$dst, $src1, $src2}",6360 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;6361def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #6362 "|fcmlt.4s\t$dst, $src1, $src2}",6363 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;6364def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #6365 "|fcmlt.2d\t$dst, $src1, $src2}",6366 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;6367 6368let Predicates = [HasNEON, HasFullFP16] in {6369def : InstAlias<"{facle\t$dst.4h, $src1.4h, $src2.4h" #6370 "|facle.4h\t$dst, $src1, $src2}",6371 (FACGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;6372def : InstAlias<"{facle\t$dst.8h, $src1.8h, $src2.8h" #6373 "|facle.8h\t$dst, $src1, $src2}",6374 (FACGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;6375}6376def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #6377 "|facle.2s\t$dst, $src1, $src2}",6378 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;6379def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #6380 "|facle.4s\t$dst, $src1, $src2}",6381 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;6382def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #6383 "|facle.2d\t$dst, $src1, $src2}",6384 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;6385 6386let Predicates = [HasNEON, HasFullFP16] in {6387def : InstAlias<"{faclt\t$dst.4h, $src1.4h, $src2.4h" #6388 "|faclt.4h\t$dst, $src1, $src2}",6389 (FACGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;6390def : InstAlias<"{faclt\t$dst.8h, $src1.8h, $src2.8h" #6391 "|faclt.8h\t$dst, $src1, $src2}",6392 (FACGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;6393}6394def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #6395 "|faclt.2s\t$dst, $src1, $src2}",6396 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;6397def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #6398 "|faclt.4s\t$dst, $src1, $src2}",6399 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;6400def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #6401 "|faclt.2d\t$dst, $src1, $src2}",6402 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;6403}6404 6405//===----------------------------------------------------------------------===//6406// Advanced SIMD three scalar instructions.6407//===----------------------------------------------------------------------===//6408 6409defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;6410defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;6411defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;6412defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;6413defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;6414defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;6415defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;6416defm FABD : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>;6417def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),6418 (FABD64 FPR64:$Rn, FPR64:$Rm)>;6419let Predicates = [HasNEON, HasFullFP16] in {6420def : Pat<(fabs (fsub f16:$Rn, f16:$Rm)), (FABD16 f16:$Rn, f16:$Rm)>;6421}6422let Predicates = [HasNEON] in {6423def : Pat<(fabs (fsub f32:$Rn, f32:$Rm)), (FABD32 f32:$Rn, f32:$Rm)>;6424def : Pat<(fabs (fsub f64:$Rn, f64:$Rm)), (FABD64 f64:$Rn, f64:$Rm)>;6425}6426defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b101, "facge",6427 int_aarch64_neon_facge>;6428defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b101, "facgt",6429 int_aarch64_neon_facgt>;6430defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;6431defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;6432defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;6433defm FMULX : SIMDFPThreeScalar<0, 0, 0b011, "fmulx", int_aarch64_neon_fmulx, HasNEONandIsStreamingSafe>;6434defm FRECPS : SIMDFPThreeScalar<0, 0, 0b111, "frecps", int_aarch64_neon_frecps, HasNEONandIsStreamingSafe>;6435defm FRSQRTS : SIMDFPThreeScalar<0, 1, 0b111, "frsqrts", int_aarch64_neon_frsqrts, HasNEONandIsStreamingSafe>;6436defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd, saddsat>;6437defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;6438defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;6439defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl", int_aarch64_neon_sqrshl, int_aarch64_neon_sqrshl>;6440defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl, int_aarch64_neon_sqshl>;6441defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub, ssubsat>;6442defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;6443defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;6444defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;6445defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd, uaddsat>;6446defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl", int_aarch64_neon_uqrshl, int_aarch64_neon_uqrshl>;6447defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl, int_aarch64_neon_uqshl>;6448defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub, usubsat>;6449defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;6450defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;6451let Predicates = [HasRDM] in {6452 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;6453 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;6454 def : Pat<(i32 (int_aarch64_neon_sqrdmlah (i32 FPR32:$Rd), (i32 FPR32:$Rn),6455 (i32 FPR32:$Rm))),6456 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;6457 def : Pat<(i32 (int_aarch64_neon_sqrdmlsh (i32 FPR32:$Rd), (i32 FPR32:$Rn),6458 (i32 FPR32:$Rm))),6459 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;6460}6461 6462defm : FMULScalarFromIndexedLane0Patterns<"FMULX", "16", "32", "64",6463 int_aarch64_neon_fmulx,6464 [HasNEONandIsStreamingSafe]>;6465 6466let Predicates = [HasNEON] in {6467def : InstAlias<"cmls $dst, $src1, $src2",6468 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;6469def : InstAlias<"cmle $dst, $src1, $src2",6470 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;6471def : InstAlias<"cmlo $dst, $src1, $src2",6472 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;6473def : InstAlias<"cmlt $dst, $src1, $src2",6474 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;6475}6476let Predicates = [HasFPARMv8] in {6477def : InstAlias<"fcmle $dst, $src1, $src2",6478 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;6479def : InstAlias<"fcmle $dst, $src1, $src2",6480 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;6481def : InstAlias<"fcmlt $dst, $src1, $src2",6482 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;6483def : InstAlias<"fcmlt $dst, $src1, $src2",6484 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;6485def : InstAlias<"facle $dst, $src1, $src2",6486 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;6487def : InstAlias<"facle $dst, $src1, $src2",6488 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;6489def : InstAlias<"faclt $dst, $src1, $src2",6490 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;6491def : InstAlias<"faclt $dst, $src1, $src2",6492 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;6493}6494 6495//===----------------------------------------------------------------------===//6496// Advanced SIMD three scalar instructions (mixed operands).6497//===----------------------------------------------------------------------===//6498defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",6499 int_aarch64_neon_sqdmulls_scalar>;6500defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;6501defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;6502 6503def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),6504 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),6505 (i32 FPR32:$Rm))))),6506 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;6507def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),6508 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),6509 (i32 FPR32:$Rm))))),6510 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;6511 6512//===----------------------------------------------------------------------===//6513// Advanced SIMD two scalar instructions.6514//===----------------------------------------------------------------------===//6515 6516defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", abs, [HasNoCSSC]>;6517defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;6518defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;6519defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;6520defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;6521defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;6522defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;6523defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>;6524defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;6525defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>;6526defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;6527defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas", int_aarch64_neon_fcvtas>;6528defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau", int_aarch64_neon_fcvtau>;6529defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms", int_aarch64_neon_fcvtms>;6530defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu", int_aarch64_neon_fcvtmu>;6531defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns", int_aarch64_neon_fcvtns>;6532defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu", int_aarch64_neon_fcvtnu>;6533defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps", int_aarch64_neon_fcvtps>;6534defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu", int_aarch64_neon_fcvtpu>;6535def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;6536defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs", any_fp_to_sint>;6537defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu", any_fp_to_uint>;6538defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">;6539defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">;6540defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">;6541defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",6542 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;6543defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>;6544defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;6545defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;6546defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;6547defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;6548defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",6549 int_aarch64_neon_suqadd>;6550defm UCVTF : SIMDFPTwoScalarCVT< 1, 0, 0b11101, "ucvtf", AArch64uitof>;6551defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;6552defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",6553 int_aarch64_neon_usqadd>;6554 6555// Floating-point conversion patterns.6556multiclass FPToIntegerSIMDScalarPatterns<SDPatternOperator OpN, string INST> {6557 let Predicates = [HasFPRCVT] in {6558 def : Pat<(f32 (bitconvert (i32 (OpN (f64 FPR64:$Rn))))),6559 (!cast<Instruction>(INST # SDr) FPR64:$Rn)>;6560 def : Pat<(f32 (bitconvert (i32 (OpN (f16 FPR16:$Rn))))),6561 (!cast<Instruction>(INST # SHr) FPR16:$Rn)>;6562 def : Pat<(f64 (bitconvert (i64 (OpN (f16 FPR16:$Rn))))),6563 (!cast<Instruction>(INST # DHr) FPR16:$Rn)>;6564 def : Pat<(f64 (bitconvert (i64 (OpN (f32 FPR32:$Rn))))),6565 (!cast<Instruction>(INST # DSr) FPR32:$Rn)>;6566 }6567 def : Pat<(f32 (bitconvert (i32 (OpN (f32 FPR32:$Rn))))),6568 (!cast<Instruction>(INST # v1i32) FPR32:$Rn)>;6569 def : Pat<(f64 (bitconvert (i64 (OpN (f64 FPR64:$Rn))))),6570 (!cast<Instruction>(INST # v1i64) FPR64:$Rn)>;6571 6572}6573defm: FPToIntegerSIMDScalarPatterns<int_aarch64_neon_fcvtas, "FCVTAS">;6574defm: FPToIntegerSIMDScalarPatterns<int_aarch64_neon_fcvtau, "FCVTAU">;6575defm: FPToIntegerSIMDScalarPatterns<int_aarch64_neon_fcvtms, "FCVTMS">;6576defm: FPToIntegerSIMDScalarPatterns<int_aarch64_neon_fcvtmu, "FCVTMU">;6577defm: FPToIntegerSIMDScalarPatterns<int_aarch64_neon_fcvtns, "FCVTNS">;6578defm: FPToIntegerSIMDScalarPatterns<int_aarch64_neon_fcvtnu, "FCVTNU">;6579defm: FPToIntegerSIMDScalarPatterns<int_aarch64_neon_fcvtps, "FCVTPS">;6580defm: FPToIntegerSIMDScalarPatterns<int_aarch64_neon_fcvtpu, "FCVTPU">;6581defm: FPToIntegerSIMDScalarPatterns<any_fp_to_sint, "FCVTZS">;6582defm: FPToIntegerSIMDScalarPatterns<any_fp_to_uint, "FCVTZU">;6583 6584multiclass FPToIntegerIntPats<Intrinsic round, string INST> {6585 let Predicates = [HasFullFP16] in {6586 def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>;6587 def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>;6588 }6589 def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>;6590 def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>;6591 def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>;6592 def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>;6593 6594 // For global-isel we can use register classes to determine6595 // which FCVT instruction to use.6596 let Predicates = [HasFPRCVT] in {6597 def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # SHr) $Rn)>;6598 def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # DHr) $Rn)>;6599 def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # DSr) $Rn)>;6600 def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # SDr) $Rn)>;6601 }6602 def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # v1i32) $Rn)>;6603 def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # v1i64) $Rn)>;6604 6605 let Predicates = [HasFPRCVT] in {6606 def : Pat<(f32 (bitconvert (i32 (round f16:$Rn)))), 6607 (!cast<Instruction>(INST # SHr) $Rn)>;6608 def : Pat<(f64 (bitconvert (i64 (round f16:$Rn)))), 6609 (!cast<Instruction>(INST # DHr) $Rn)>;6610 def : Pat<(f64 (bitconvert (i64 (round f32:$Rn)))), 6611 (!cast<Instruction>(INST # DSr) $Rn)>;6612 def : Pat<(f32 (bitconvert (i32 (round f64:$Rn)))), 6613 (!cast<Instruction>(INST # SDr) $Rn)>;6614 }6615 def : Pat<(f32 (bitconvert (i32 (round f32:$Rn)))), 6616 (!cast<Instruction>(INST # v1i32) $Rn)>;6617 def : Pat<(f64 (bitconvert (i64 (round f64:$Rn)))), 6618 (!cast<Instruction>(INST # v1i64) $Rn)>;6619 6620 let Predicates = [HasFullFP16] in {6621 def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),6622 (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;6623 def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),6624 (!cast<Instruction>(INST # SXHri) $Rn, $scale)>;6625 }6626 def : Pat<(i32 (round (fmul f32:$Rn, fixedpoint_f32_i32:$scale))),6627 (!cast<Instruction>(INST # SWSri) $Rn, $scale)>;6628 def : Pat<(i64 (round (fmul f32:$Rn, fixedpoint_f32_i64:$scale))),6629 (!cast<Instruction>(INST # SXSri) $Rn, $scale)>;6630 def : Pat<(i32 (round (fmul f64:$Rn, fixedpoint_f64_i32:$scale))),6631 (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;6632 def : Pat<(i64 (round (fmul f64:$Rn, fixedpoint_f64_i64:$scale))),6633 (!cast<Instruction>(INST # SXDri) $Rn, $scale)>;6634}6635 6636defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">;6637defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">;6638 6639// AArch64's FCVT instructions saturate when out of range.6640multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string INST> {6641 let Predicates = [HasFullFP16] in {6642 def : Pat<(i32 (to_int_sat f16:$Rn, i32)),6643 (!cast<Instruction>(INST # UWHr) f16:$Rn)>;6644 def : Pat<(i64 (to_int_sat f16:$Rn, i64)),6645 (!cast<Instruction>(INST # UXHr) f16:$Rn)>;6646 }6647 def : Pat<(i32 (to_int_sat f32:$Rn, i32)),6648 (!cast<Instruction>(INST # UWSr) f32:$Rn)>;6649 def : Pat<(i64 (to_int_sat f32:$Rn, i64)),6650 (!cast<Instruction>(INST # UXSr) f32:$Rn)>;6651 def : Pat<(i32 (to_int_sat f64:$Rn, i32)),6652 (!cast<Instruction>(INST # UWDr) f64:$Rn)>;6653 def : Pat<(i64 (to_int_sat f64:$Rn, i64)),6654 (!cast<Instruction>(INST # UXDr) f64:$Rn)>;6655 6656 let Predicates = [HasFullFP16] in {6657 def : Pat<(i32 (to_int_sat_gi f16:$Rn)),6658 (!cast<Instruction>(INST # UWHr) f16:$Rn)>;6659 def : Pat<(i64 (to_int_sat_gi f16:$Rn)),6660 (!cast<Instruction>(INST # UXHr) f16:$Rn)>;6661 }6662 def : Pat<(i32 (to_int_sat_gi f32:$Rn)),6663 (!cast<Instruction>(INST # UWSr) f32:$Rn)>;6664 def : Pat<(i64 (to_int_sat_gi f32:$Rn)),6665 (!cast<Instruction>(INST # UXSr) f32:$Rn)>;6666 def : Pat<(i32 (to_int_sat_gi f64:$Rn)),6667 (!cast<Instruction>(INST # UWDr) f64:$Rn)>;6668 def : Pat<(i64 (to_int_sat_gi f64:$Rn)),6669 (!cast<Instruction>(INST # UXDr) f64:$Rn)>;6670 6671 // For global-isel we can use register classes to determine6672 // which FCVT instruction to use.6673 let Predicates = [HasFPRCVT] in {6674 def : Pat<(i32 (to_int_sat_gi f16:$Rn)),6675 (!cast<Instruction>(INST # SHr) f16:$Rn)>;6676 def : Pat<(i64 (to_int_sat_gi f16:$Rn)),6677 (!cast<Instruction>(INST # DHr) f16:$Rn)>;6678 def : Pat<(i64 (to_int_sat_gi f32:$Rn)),6679 (!cast<Instruction>(INST # DSr) f32:$Rn)>;6680 def : Pat<(i32 (to_int_sat_gi f64:$Rn)),6681 (!cast<Instruction>(INST # SDr) f64:$Rn)>;6682 }6683 def : Pat<(i32 (to_int_sat_gi f32:$Rn)),6684 (!cast<Instruction>(INST # v1i32) f32:$Rn)>;6685 def : Pat<(i64 (to_int_sat_gi f64:$Rn)),6686 (!cast<Instruction>(INST # v1i64) f64:$Rn)>;6687 6688 let Predicates = [HasFPRCVT] in {6689 def : Pat<(f32 (bitconvert (i32 (to_int_sat f16:$Rn, i32)))),6690 (!cast<Instruction>(INST # SHr) f16:$Rn)>;6691 def : Pat<(f64 (bitconvert (i64 (to_int_sat f16:$Rn, i64)))),6692 (!cast<Instruction>(INST # DHr) f16:$Rn)>;6693 def : Pat<(f64 (bitconvert (i64 (to_int_sat f32:$Rn, i64)))),6694 (!cast<Instruction>(INST # DSr) f32:$Rn)>;6695 def : Pat<(f32 (bitconvert (i32 (to_int_sat f64:$Rn, i32)))),6696 (!cast<Instruction>(INST # SDr) f64:$Rn)>;6697 }6698 def : Pat<(f32 (bitconvert (i32 (to_int_sat f32:$Rn, i32)))),6699 (!cast<Instruction>(INST # v1i32) f32:$Rn)>;6700 def : Pat<(f64 (bitconvert (i64 (to_int_sat f64:$Rn, i64)))),6701 (!cast<Instruction>(INST # v1i64) f64:$Rn)>;6702 6703 let Predicates = [HasFullFP16] in {6704 def : Pat<(i32 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i32:$scale), i32)),6705 (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;6706 def : Pat<(i64 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i64:$scale), i64)),6707 (!cast<Instruction>(INST # SXHri) $Rn, $scale)>;6708 }6709 def : Pat<(i32 (to_int_sat (fmul f32:$Rn, fixedpoint_f32_i32:$scale), i32)),6710 (!cast<Instruction>(INST # SWSri) $Rn, $scale)>;6711 def : Pat<(i64 (to_int_sat (fmul f32:$Rn, fixedpoint_f32_i64:$scale), i64)),6712 (!cast<Instruction>(INST # SXSri) $Rn, $scale)>;6713 def : Pat<(i32 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i32:$scale), i32)),6714 (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;6715 def : Pat<(i64 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i64:$scale), i64)),6716 (!cast<Instruction>(INST # SXDri) $Rn, $scale)>;6717 6718 let Predicates = [HasFullFP16] in {6719 def : Pat<(i32 (to_int_sat_gi (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),6720 (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;6721 def : Pat<(i64 (to_int_sat_gi (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),6722 (!cast<Instruction>(INST # SXHri) $Rn, $scale)>;6723 }6724 def : Pat<(i32 (to_int_sat_gi (fmul f32:$Rn, fixedpoint_f32_i32:$scale))),6725 (!cast<Instruction>(INST # SWSri) $Rn, $scale)>;6726 def : Pat<(i64 (to_int_sat_gi (fmul f32:$Rn, fixedpoint_f32_i64:$scale))),6727 (!cast<Instruction>(INST # SXSri) $Rn, $scale)>;6728 def : Pat<(i32 (to_int_sat_gi (fmul f64:$Rn, fixedpoint_f64_i32:$scale))),6729 (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;6730 def : Pat<(i64 (to_int_sat_gi (fmul f64:$Rn, fixedpoint_f64_i64:$scale))),6731 (!cast<Instruction>(INST # SXDri) $Rn, $scale)>;6732}6733 6734defm : FPToIntegerSatPats<fp_to_sint_sat, fp_to_sint_sat_gi, "FCVTZS">;6735defm : FPToIntegerSatPats<fp_to_uint_sat, fp_to_uint_sat_gi, "FCVTZU">;6736 6737multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode to_int_sat_gi, SDNode round, string INST> {6738 def : Pat<(i32 (to_int (round f32:$Rn))),6739 (!cast<Instruction>(INST # UWSr) f32:$Rn)>;6740 def : Pat<(i64 (to_int (round f32:$Rn))),6741 (!cast<Instruction>(INST # UXSr) f32:$Rn)>;6742 def : Pat<(i32 (to_int (round f64:$Rn))),6743 (!cast<Instruction>(INST # UWDr) f64:$Rn)>;6744 def : Pat<(i64 (to_int (round f64:$Rn))),6745 (!cast<Instruction>(INST # UXDr) f64:$Rn)>;6746 6747 // For global-isel we can use register classes to determine6748 // which FCVT instruction to use.6749 let Predicates = [HasFPRCVT] in {6750 def : Pat<(i64 (to_int (round f32:$Rn))),6751 (!cast<Instruction>(INST # DSr) f32:$Rn)>;6752 def : Pat<(i32 (to_int (round f64:$Rn))),6753 (!cast<Instruction>(INST # SDr) f64:$Rn)>;6754 }6755 def : Pat<(i32 (to_int (round f32:$Rn))),6756 (!cast<Instruction>(INST # v1i32) f32:$Rn)>;6757 def : Pat<(i64 (to_int (round f64:$Rn))),6758 (!cast<Instruction>(INST # v1i64) f64:$Rn)>;6759 6760 let Predicates = [HasFPRCVT] in {6761 def : Pat<(f64 (bitconvert (i64 (to_int (round f32:$Rn))))),6762 (!cast<Instruction>(INST # DSr) f32:$Rn)>;6763 def : Pat<(f32 (bitconvert (i32 (to_int (round f64:$Rn))))),6764 (!cast<Instruction>(INST # SDr) f64:$Rn)>;6765 }6766 def : Pat<(f32 (bitconvert (i32 (to_int (round f32:$Rn))))),6767 (!cast<Instruction>(INST # v1i32) f32:$Rn)>;6768 def : Pat<(f64 (bitconvert (i64 (to_int (round f64:$Rn))))),6769 (!cast<Instruction>(INST # v1i64) f64:$Rn)>;6770 6771 // These instructions saturate like fp_to_[su]int_sat.6772 let Predicates = [HasFullFP16] in {6773 def : Pat<(i32 (to_int_sat (round f16:$Rn), i32)),6774 (!cast<Instruction>(INST # UWHr) f16:$Rn)>;6775 def : Pat<(i64 (to_int_sat (round f16:$Rn), i64)),6776 (!cast<Instruction>(INST # UXHr) f16:$Rn)>;6777 }6778 def : Pat<(i32 (to_int_sat (round f32:$Rn), i32)),6779 (!cast<Instruction>(INST # UWSr) f32:$Rn)>;6780 def : Pat<(i64 (to_int_sat (round f32:$Rn), i64)),6781 (!cast<Instruction>(INST # UXSr) f32:$Rn)>;6782 def : Pat<(i32 (to_int_sat (round f64:$Rn), i32)),6783 (!cast<Instruction>(INST # UWDr) f64:$Rn)>;6784 def : Pat<(i64 (to_int_sat (round f64:$Rn), i64)),6785 (!cast<Instruction>(INST # UXDr) f64:$Rn)>;6786 6787 // For global-isel we can use register classes to determine6788 // which FCVT instruction to use.6789 let Predicates = [HasFPRCVT] in {6790 def : Pat<(i32 (to_int_sat_gi (round f16:$Rn))),6791 (!cast<Instruction>(INST # SHr) f16:$Rn)>;6792 def : Pat<(i64 (to_int_sat_gi (round f16:$Rn))),6793 (!cast<Instruction>(INST # DHr) f16:$Rn)>;6794 def : Pat<(i64 (to_int_sat_gi (round f32:$Rn))),6795 (!cast<Instruction>(INST # DSr) f32:$Rn)>;6796 def : Pat<(i32 (to_int_sat_gi (round f64:$Rn))),6797 (!cast<Instruction>(INST # SDr) f64:$Rn)>;6798 }6799 def : Pat<(i32 (to_int_sat_gi (round f32:$Rn))),6800 (!cast<Instruction>(INST # v1i32) f32:$Rn)>;6801 def : Pat<(i64 (to_int_sat_gi (round f64:$Rn))),6802 (!cast<Instruction>(INST # v1i64) f64:$Rn)>;6803 6804 let Predicates = [HasFPRCVT] in {6805 def : Pat<(f32 (bitconvert (i32 (to_int_sat (round f16:$Rn), i32)))),6806 (!cast<Instruction>(INST # SHr) f16:$Rn)>;6807 def : Pat<(f64 (bitconvert (i64 (to_int_sat (round f16:$Rn), i64)))),6808 (!cast<Instruction>(INST # DHr) f16:$Rn)>;6809 def : Pat<(f64 (bitconvert (i64 (to_int_sat (round f32:$Rn), i64)))),6810 (!cast<Instruction>(INST # DSr) f32:$Rn)>;6811 def : Pat<(f32 (bitconvert (i32 (to_int_sat (round f64:$Rn), i32)))),6812 (!cast<Instruction>(INST # SDr) f64:$Rn)>;6813 }6814 def : Pat<(f32 (bitconvert (i32 (to_int_sat (round f32:$Rn), i32)))),6815 (!cast<Instruction>(INST # v1i32) f32:$Rn)>;6816 def : Pat<(f64 (bitconvert (i64 (to_int_sat (round f64:$Rn), i64)))),6817 (!cast<Instruction>(INST # v1i64) f64:$Rn)>;6818}6819 6820defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, fceil, "FCVTPS">;6821defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, fceil, "FCVTPU">;6822defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, ffloor, "FCVTMS">;6823defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, ffloor, "FCVTMU">;6824defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, ftrunc, "FCVTZS">;6825defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, ftrunc, "FCVTZU">;6826defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, fround, "FCVTAS">;6827defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, fround, "FCVTAU">;6828 6829// f16 -> s16 conversions6830let Predicates = [HasFullFP16] in {6831 def : Pat<(i16(fp_to_sint_sat_gi f16:$Rn)), (FCVTZSv1f16 f16:$Rn)>;6832 def : Pat<(i16(fp_to_uint_sat_gi f16:$Rn)), (FCVTZUv1f16 f16:$Rn)>;6833}6834 6835def : Pat<(v1i64 (AArch64vashr (v1i64 V64:$Rn), (i32 63))),6836 (CMLTv1i64rz V64:$Rn)>;6837 6838// f16 -> i16 conversions leave the bit pattern in a f326839class F16ToI16ScalarPat<SDNode cvt_isd, BaseSIMDTwoScalar instr>6840 : Pat<(f32 (cvt_isd (f16 FPR16:$Rn))),6841 (f32 (SUBREG_TO_REG (i64 0), (instr FPR16:$Rn), hsub))>;6842 6843let Predicates = [HasFullFP16] in {6844def : F16ToI16ScalarPat<AArch64fcvtzs_half, FCVTZSv1f16>;6845def : F16ToI16ScalarPat<AArch64fcvtzu_half, FCVTZUv1f16>;6846def : F16ToI16ScalarPat<AArch64fcvtas_half, FCVTASv1f16>;6847def : F16ToI16ScalarPat<AArch64fcvtau_half, FCVTAUv1f16>;6848def : F16ToI16ScalarPat<AArch64fcvtms_half, FCVTMSv1f16>;6849def : F16ToI16ScalarPat<AArch64fcvtmu_half, FCVTMUv1f16>;6850def : F16ToI16ScalarPat<AArch64fcvtns_half, FCVTNSv1f16>;6851def : F16ToI16ScalarPat<AArch64fcvtnu_half, FCVTNUv1f16>;6852def : F16ToI16ScalarPat<AArch64fcvtps_half, FCVTPSv1f16>;6853def : F16ToI16ScalarPat<AArch64fcvtpu_half, FCVTPUv1f16>;6854}6855 6856// Round FP64 to BF16.6857let Predicates = [HasNEONandIsStreamingSafe, HasBF16] in6858def : Pat<(bf16 (any_fpround (f64 FPR64:$Rn))),6859 (BFCVT (FCVTXNv1i64 $Rn))>;6860 6861def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),6862 (FCVTASv1i64 FPR64:$Rn)>;6863def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),6864 (FCVTAUv1i64 FPR64:$Rn)>;6865def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),6866 (FCVTMSv1i64 FPR64:$Rn)>;6867def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),6868 (FCVTMUv1i64 FPR64:$Rn)>;6869def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),6870 (FCVTNSv1i64 FPR64:$Rn)>;6871def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),6872 (FCVTNUv1i64 FPR64:$Rn)>;6873def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),6874 (FCVTPSv1i64 FPR64:$Rn)>;6875def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),6876 (FCVTPUv1i64 FPR64:$Rn)>;6877def : Pat<(v1i64 (int_aarch64_neon_fcvtzs (v1f64 FPR64:$Rn))),6878 (FCVTZSv1i64 FPR64:$Rn)>;6879def : Pat<(v1i64 (int_aarch64_neon_fcvtzu (v1f64 FPR64:$Rn))),6880 (FCVTZUv1i64 FPR64:$Rn)>;6881 6882def : Pat<(f16 (int_aarch64_neon_frecpe (f16 FPR16:$Rn))),6883 (FRECPEv1f16 FPR16:$Rn)>;6884def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),6885 (FRECPEv1i32 FPR32:$Rn)>;6886def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),6887 (FRECPEv1i64 FPR64:$Rn)>;6888def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),6889 (FRECPEv1i64 FPR64:$Rn)>;6890 6891def : Pat<(f32 (AArch64frecpe (f32 FPR32:$Rn))),6892 (FRECPEv1i32 FPR32:$Rn)>;6893def : Pat<(v2f32 (AArch64frecpe (v2f32 V64:$Rn))),6894 (FRECPEv2f32 V64:$Rn)>;6895def : Pat<(v4f32 (AArch64frecpe (v4f32 FPR128:$Rn))),6896 (FRECPEv4f32 FPR128:$Rn)>;6897def : Pat<(f64 (AArch64frecpe (f64 FPR64:$Rn))),6898 (FRECPEv1i64 FPR64:$Rn)>;6899def : Pat<(v1f64 (AArch64frecpe (v1f64 FPR64:$Rn))),6900 (FRECPEv1i64 FPR64:$Rn)>;6901def : Pat<(v2f64 (AArch64frecpe (v2f64 FPR128:$Rn))),6902 (FRECPEv2f64 FPR128:$Rn)>;6903 6904def : Pat<(f32 (AArch64frecps (f32 FPR32:$Rn), (f32 FPR32:$Rm))),6905 (FRECPS32 FPR32:$Rn, FPR32:$Rm)>;6906def : Pat<(v2f32 (AArch64frecps (v2f32 V64:$Rn), (v2f32 V64:$Rm))),6907 (FRECPSv2f32 V64:$Rn, V64:$Rm)>;6908def : Pat<(v4f32 (AArch64frecps (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))),6909 (FRECPSv4f32 FPR128:$Rn, FPR128:$Rm)>;6910def : Pat<(f64 (AArch64frecps (f64 FPR64:$Rn), (f64 FPR64:$Rm))),6911 (FRECPS64 FPR64:$Rn, FPR64:$Rm)>;6912def : Pat<(v2f64 (AArch64frecps (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))),6913 (FRECPSv2f64 FPR128:$Rn, FPR128:$Rm)>;6914 6915def : Pat<(f16 (int_aarch64_neon_frecpx (f16 FPR16:$Rn))),6916 (FRECPXv1f16 FPR16:$Rn)>;6917def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),6918 (FRECPXv1i32 FPR32:$Rn)>;6919def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),6920 (FRECPXv1i64 FPR64:$Rn)>;6921 6922def : Pat<(f16 (int_aarch64_neon_frsqrte (f16 FPR16:$Rn))),6923 (FRSQRTEv1f16 FPR16:$Rn)>;6924def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),6925 (FRSQRTEv1i32 FPR32:$Rn)>;6926def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),6927 (FRSQRTEv1i64 FPR64:$Rn)>;6928def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),6929 (FRSQRTEv1i64 FPR64:$Rn)>;6930 6931def : Pat<(f32 (AArch64frsqrte (f32 FPR32:$Rn))),6932 (FRSQRTEv1i32 FPR32:$Rn)>;6933def : Pat<(v2f32 (AArch64frsqrte (v2f32 V64:$Rn))),6934 (FRSQRTEv2f32 V64:$Rn)>;6935def : Pat<(v4f32 (AArch64frsqrte (v4f32 FPR128:$Rn))),6936 (FRSQRTEv4f32 FPR128:$Rn)>;6937def : Pat<(f64 (AArch64frsqrte (f64 FPR64:$Rn))),6938 (FRSQRTEv1i64 FPR64:$Rn)>;6939def : Pat<(v1f64 (AArch64frsqrte (v1f64 FPR64:$Rn))),6940 (FRSQRTEv1i64 FPR64:$Rn)>;6941def : Pat<(v2f64 (AArch64frsqrte (v2f64 FPR128:$Rn))),6942 (FRSQRTEv2f64 FPR128:$Rn)>;6943 6944def : Pat<(f32 (AArch64frsqrts (f32 FPR32:$Rn), (f32 FPR32:$Rm))),6945 (FRSQRTS32 FPR32:$Rn, FPR32:$Rm)>;6946def : Pat<(v2f32 (AArch64frsqrts (v2f32 V64:$Rn), (v2f32 V64:$Rm))),6947 (FRSQRTSv2f32 V64:$Rn, V64:$Rm)>;6948def : Pat<(v4f32 (AArch64frsqrts (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))),6949 (FRSQRTSv4f32 FPR128:$Rn, FPR128:$Rm)>;6950def : Pat<(f64 (AArch64frsqrts (f64 FPR64:$Rn), (f64 FPR64:$Rm))),6951 (FRSQRTS64 FPR64:$Rn, FPR64:$Rm)>;6952def : Pat<(v2f64 (AArch64frsqrts (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))),6953 (FRSQRTSv2f64 FPR128:$Rn, FPR128:$Rm)>;6954 6955// Some float -> int -> float conversion patterns for which we want to keep the6956// int values in FP registers using the corresponding NEON instructions to6957// avoid more costly int <-> fp register transfers.6958let HasOneUse = 1 in {6959def any_fp_to_sint_oneuse: PatFrag<(ops node:$src0), (any_fp_to_sint $src0)>;6960def any_fp_to_uint_oneuse: PatFrag<(ops node:$src0), (any_fp_to_uint $src0)>;6961}6962let Predicates = [HasNEONandIsSME2p2StreamingSafe] in {6963def : Pat<(f64 (any_sint_to_fp (i64 (any_fp_to_sint_oneuse f64:$Rn)))),6964 (SCVTFv1i64 (i64 (FCVTZSv1i64 f64:$Rn)))>;6965def : Pat<(f32 (any_sint_to_fp (i32 (any_fp_to_sint_oneuse f32:$Rn)))),6966 (SCVTFv1i32 (i32 (FCVTZSv1i32 f32:$Rn)))>;6967def : Pat<(f64 (any_uint_to_fp (i64 (any_fp_to_uint_oneuse f64:$Rn)))),6968 (UCVTFv1i64 (i64 (FCVTZUv1i64 f64:$Rn)))>;6969def : Pat<(f32 (any_uint_to_fp (i32 (any_fp_to_uint_oneuse f32:$Rn)))),6970 (UCVTFv1i32 (i32 (FCVTZUv1i32 f32:$Rn)))>;6971 6972let Predicates = [HasNEONandIsSME2p2StreamingSafe, HasFullFP16] in {6973def : Pat<(f16 (any_sint_to_fp (i32 (any_fp_to_sint_oneuse f16:$Rn)))),6974 (SCVTFv1i16 (f16 (FCVTZSv1f16 f16:$Rn)))>;6975def : Pat<(f16 (any_uint_to_fp (i32 (any_fp_to_uint_oneuse f16:$Rn)))),6976 (UCVTFv1i16 (f16 (FCVTZUv1f16 f16:$Rn)))>;6977}6978 6979def : Pat<(v4i32 (any_fp_to_sint (v4f32 (scalar_to_vector (f32 FPR32:$src))))),6980 (v4i32 (INSERT_SUBREG (IMPLICIT_DEF), (i32 (FCVTZSv1i32 (f32 FPR32:$src))), ssub))>;6981def : Pat<(v4i32 (any_fp_to_uint (v4f32 (scalar_to_vector (f32 FPR32:$src))))),6982 (v4i32 (INSERT_SUBREG (IMPLICIT_DEF), (i32 (FCVTZUv1i32 (f32 FPR32:$src))), ssub))>;6983def : Pat<(v2i64 (any_fp_to_sint (v2f64 (scalar_to_vector (f64 FPR64:$src))))),6984 (v2i64 (INSERT_SUBREG (IMPLICIT_DEF), (i64 (FCVTZSv1i64 (f64 FPR64:$src))), dsub))>;6985def : Pat<(v2i64 (any_fp_to_uint (v2f64 (scalar_to_vector (f64 FPR64:$src))))),6986 (v2i64 (INSERT_SUBREG (IMPLICIT_DEF), (i64 (FCVTZUv1i64 (f64 FPR64:$src))), dsub))>;6987 6988// int -> float conversion of value in lane 0 of simd vector should use6989// correct cvtf variant to avoid costly fpr <-> gpr register transfers.6990def : Pat<(f32 (sint_to_fp (i32 (vector_extract (v4i32 FPR128:$Rn), (i64 0))))),6991 (SCVTFv1i32 (i32 (EXTRACT_SUBREG (v4i32 FPR128:$Rn), ssub)))>;6992 6993def : Pat<(f32 (uint_to_fp (i32 (vector_extract (v4i32 FPR128:$Rn), (i64 0))))),6994 (UCVTFv1i32 (i32 (EXTRACT_SUBREG (v4i32 FPR128:$Rn), ssub)))>;6995 6996def : Pat<(f64 (sint_to_fp (i64 (vector_extract (v2i64 FPR128:$Rn), (i64 0))))),6997 (SCVTFv1i64 (i64 (EXTRACT_SUBREG (v2i64 FPR128:$Rn), dsub)))>;6998 6999def : Pat<(f64 (uint_to_fp (i64 (vector_extract (v2i64 FPR128:$Rn), (i64 0))))),7000 (UCVTFv1i64 (i64 (EXTRACT_SUBREG (v2i64 FPR128:$Rn), dsub)))>;7001 7002// fp16: integer extraction from vector must be at least 32-bits to be legal.7003// Actual extraction result is then an in-reg sign-extension of lower 16-bits.7004let Predicates = [HasNEONandIsSME2p2StreamingSafe, HasFullFP16] in {7005def : Pat<(f16 (sint_to_fp (i32 (sext_inreg (i32 (vector_extract7006 (v8i16 FPR128:$Rn), (i64 0))), i16)))),7007 (SCVTFv1i16 (f16 (EXTRACT_SUBREG (v8i16 FPR128:$Rn), hsub)))>;7008 7009// unsigned 32-bit extracted element is truncated to 16-bits using AND7010def : Pat<(f16 (uint_to_fp (i32 (and (i32 (vector_extract7011 (v8i16 FPR128:$Rn), (i64 0))), (i32 65535))))),7012 (UCVTFv1i16 (f16 (EXTRACT_SUBREG (v8i16 FPR128:$Rn), hsub)))>;7013}7014 7015// If an integer is about to be converted to a floating point value,7016// just load it on the floating point unit.7017// Here are the patterns for 8 and 16-bits to float.7018// 8-bits -> float.7019multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,7020 SDPatternOperator loadop, Instruction UCVTF,7021 ROAddrMode ro, Instruction LDRW, Instruction LDRX,7022 SubRegIndex sub> {7023 def : Pat<(DstTy (uint_to_fp (SrcTy7024 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,7025 ro.Wext:$extend))))),7026 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),7027 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),7028 sub))>;7029 7030 def : Pat<(DstTy (uint_to_fp (SrcTy7031 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,7032 ro.Wext:$extend))))),7033 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),7034 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),7035 sub))>;7036}7037 7038let Predicates = [HasNEONandIsSME2p2StreamingSafe, HasFullFP16] in {7039defm : UIntToFPROLoadPat<f16, i32, zextloadi8,7040 UCVTFv1i16, ro8, LDRBroW, LDRBroX, bsub>;7041def : Pat <(f16 (uint_to_fp (i327042 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),7043 (UCVTFv1i16 (INSERT_SUBREG (f16 (IMPLICIT_DEF)),7044 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;7045def : Pat <(f16 (uint_to_fp (i327046 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),7047 (UCVTFv1i16 (INSERT_SUBREG (f16 (IMPLICIT_DEF)),7048 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;7049}7050 7051defm : UIntToFPROLoadPat<f32, i32, zextloadi8,7052 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;7053def : Pat <(f32 (uint_to_fp (i327054 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),7055 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),7056 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;7057def : Pat <(f32 (uint_to_fp (i327058 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),7059 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),7060 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;7061// 16-bits -> float.7062defm : UIntToFPROLoadPat<f32, i32, zextloadi16,7063 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;7064def : Pat <(f32 (uint_to_fp (i327065 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),7066 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),7067 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;7068def : Pat <(f32 (uint_to_fp (i327069 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),7070 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),7071 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;7072// 32-bits are handled in target specific dag combine:7073// performIntToFpCombine.7074// 64-bits integer to 32-bits floating point, not possible with7075// UCVTF on floating point registers (both source and destination7076// must have the same size).7077 7078// Here are the patterns for 8, 16, 32, and 64-bits to double.7079// 8-bits -> double.7080defm : UIntToFPROLoadPat<f64, i32, zextloadi8,7081 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;7082def : Pat <(f64 (uint_to_fp (i327083 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),7084 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),7085 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;7086def : Pat <(f64 (uint_to_fp (i327087 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),7088 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),7089 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;7090// 16-bits -> double.7091defm : UIntToFPROLoadPat<f64, i32, zextloadi16,7092 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;7093def : Pat <(f64 (uint_to_fp (i327094 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),7095 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),7096 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;7097def : Pat <(f64 (uint_to_fp (i327098 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),7099 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),7100 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;7101// 32-bits -> double.7102defm : UIntToFPROLoadPat<f64, i32, load,7103 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;7104def : Pat <(f64 (uint_to_fp (i327105 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),7106 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),7107 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;7108def : Pat <(f64 (uint_to_fp (i327109 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),7110 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),7111 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;7112// 64-bits -> double are handled in target specific dag combine:7113// performIntToFpCombine.7114} // let Predicates = [HasNEON]7115 7116//===----------------------------------------------------------------------===//7117// Advanced SIMD three different-sized vector instructions.7118//===----------------------------------------------------------------------===//7119 7120defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;7121defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;7122defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;7123defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;7124let isCommutable = 1 in7125defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull", AArch64pmull>;7126defm SABAL : SIMDLongThreeVectorTiedBHS<0,0b0101,"sabal",7127 TriOpFrag<(add node:$LHS, (zext (abds node:$MHS, node:$RHS)))>>;7128defm SABDL : SIMDLongThreeVectorBHS<0, 0b0111, "sabdl",7129 BinOpFrag<(zext (abds node:$LHS, node:$RHS))>>;7130defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",7131 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;7132defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",7133 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;7134defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",7135 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>>;7136defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",7137 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>>;7138defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", AArch64smull>;7139defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal", saddsat>;7140defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl", ssubsat>;7141defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull", int_aarch64_neon_sqdmull>;7142let isCommutable = 0 in7143defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",7144 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;7145defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",7146 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;7147defm UABAL : SIMDLongThreeVectorTiedBHS<1, 0b0101, "uabal",7148 TriOpFrag<(add node:$LHS, (zext (abdu node:$MHS, node:$RHS)))>>;7149defm UABDL : SIMDLongThreeVectorBHS<1, 0b0111, "uabdl",7150 BinOpFrag<(zext (abdu node:$LHS, node:$RHS))>>;7151defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",7152 BinOpFrag<(add (zanyext node:$LHS), (zanyext node:$RHS))>>;7153defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",7154 BinOpFrag<(add node:$LHS, (zanyext node:$RHS))>>;7155defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",7156 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>>;7157defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",7158 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>>;7159defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", AArch64umull>;7160let isCommutable = 0 in7161defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",7162 BinOpFrag<(sub (zanyext node:$LHS), (zanyext node:$RHS))>>;7163defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",7164 BinOpFrag<(sub node:$LHS, (zanyext node:$RHS))>>;7165 7166// Additional patterns for [SU]ML[AS]L7167multiclass Neon_mul_acc_widen_patterns<SDPatternOperator opnode, SDPatternOperator vecopnode,7168 Instruction INST8B, Instruction INST4H, Instruction INST2S> {7169 def : Pat<(v4i16 (opnode7170 V64:$Ra,7171 (v4i16 (extract_subvector7172 (vecopnode (v8i8 V64:$Rn),(v8i8 V64:$Rm)),7173 (i64 0))))),7174 (EXTRACT_SUBREG (v8i16 (INST8B7175 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Ra, dsub),7176 V64:$Rn, V64:$Rm)), dsub)>;7177 def : Pat<(v2i32 (opnode7178 V64:$Ra,7179 (v2i32 (extract_subvector7180 (vecopnode (v4i16 V64:$Rn),(v4i16 V64:$Rm)),7181 (i64 0))))),7182 (EXTRACT_SUBREG (v4i32 (INST4H7183 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$Ra, dsub),7184 V64:$Rn, V64:$Rm)), dsub)>;7185 def : Pat<(v1i64 (opnode7186 V64:$Ra,7187 (v1i64 (extract_subvector7188 (vecopnode (v2i32 V64:$Rn),(v2i32 V64:$Rm)),7189 (i64 0))))),7190 (EXTRACT_SUBREG (v2i64 (INST2S7191 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), V64:$Ra, dsub),7192 V64:$Rn, V64:$Rm)), dsub)>;7193}7194 7195defm : Neon_mul_acc_widen_patterns<add, AArch64umull,7196 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;7197defm : Neon_mul_acc_widen_patterns<add, AArch64smull,7198 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;7199defm : Neon_mul_acc_widen_patterns<sub, AArch64umull,7200 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;7201defm : Neon_mul_acc_widen_patterns<sub, AArch64smull,7202 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;7203 7204 7205multiclass Neon_addl_extract_patterns<SDPatternOperator opnode, SDPatternOperator ext, string Inst> {7206 def : Pat<(v4i16 (opnode (extract_subvector (ext (v8i8 V64:$Rn)), (i64 0)),7207 (extract_subvector (ext (v8i8 V64:$Rm)), (i64 0)))),7208 (EXTRACT_SUBREG (v8i16 (!cast<Instruction>(Inst#"Lv8i8_v8i16") V64:$Rn, V64:$Rm)), dsub)>;7209 def : Pat<(v2i32 (opnode (extract_subvector (ext (v4i16 V64:$Rn)), (i64 0)),7210 (extract_subvector (ext (v4i16 V64:$Rm)), (i64 0)))),7211 (EXTRACT_SUBREG (v4i32 (!cast<Instruction>(Inst#"Lv4i16_v4i32") V64:$Rn, V64:$Rm)), dsub)>;7212 def : Pat<(v1i64 (opnode (extract_subvector (ext (v2i32 V64:$Rn)), (i64 0)),7213 (extract_subvector (ext (v2i32 V64:$Rm)), (i64 0)))),7214 (EXTRACT_SUBREG (v2i64 (!cast<Instruction>(Inst#"Lv2i32_v2i64") V64:$Rn, V64:$Rm)), dsub)>;7215 7216 def : Pat<(v4i16 (opnode (v4i16 V64:$Rn),7217 (extract_subvector (ext (v8i8 V64:$Rm)), (i64 0)))),7218 (EXTRACT_SUBREG (v8i16 (!cast<Instruction>(Inst#"Wv8i8_v8i16") (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Rn, dsub), V64:$Rm)), dsub)>;7219 def : Pat<(v2i32 (opnode (v2i32 V64:$Rn),7220 (extract_subvector (ext (v4i16 V64:$Rm)), (i64 0)))),7221 (EXTRACT_SUBREG (v4i32 (!cast<Instruction>(Inst#"Wv4i16_v4i32") (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$Rn, dsub), V64:$Rm)), dsub)>;7222 def : Pat<(v1i64 (opnode (v1i64 V64:$Rn),7223 (extract_subvector (ext (v2i32 V64:$Rm)), (i64 0)))),7224 (EXTRACT_SUBREG (v2i64 (!cast<Instruction>(Inst#"Wv2i32_v2i64") (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), V64:$Rn, dsub), V64:$Rm)), dsub)>;7225}7226 7227defm : Neon_addl_extract_patterns<add, zanyext, "UADD">;7228defm : Neon_addl_extract_patterns<add, sext, "SADD">;7229defm : Neon_addl_extract_patterns<sub, zanyext, "USUB">;7230defm : Neon_addl_extract_patterns<sub, sext, "SSUB">;7231 7232// CodeGen patterns for addhn and subhn instructions, which can actually be7233// written in LLVM IR without too much difficulty.7234 7235multiclass AddSubHNPatterns<Instruction ADDHN, Instruction ADDHN2, Instruction SUBHN,7236 Instruction SUBHN2, ValueType VT64, ValueType VT128, int Shift> {7237 def : Pat<(VT64 (trunc (VT128 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 Shift))))),7238 (ADDHN V128:$Rn, V128:$Rm)>;7239 let AddedComplexity = 10 in7240 def : Pat<(concat_vectors (VT64 V64:$Rd),7241 (trunc (VT128 (AArch64vlshr (add V128:$Rn, V128:$Rm),7242 (i32 Shift))))),7243 (ADDHN2 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>;7244 7245 def : Pat<(VT64 (trunc (VT128 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 Shift))))),7246 (SUBHN V128:$Rn, V128:$Rm)>;7247 let AddedComplexity = 10 in7248 def : Pat<(concat_vectors (VT64 V64:$Rd),7249 (trunc (VT128 (AArch64vlshr (sub V128:$Rn, V128:$Rm),7250 (i32 Shift))))),7251 (SUBHN2 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>;7252 7253 // xor by -1 can also be treated as sub7254 def : Pat<(VT64 (trunc (VT128 (AArch64vlshr (xor V128:$Rn, immAllOnesV:$Rm), (i32 Shift))))),7255 (SUBHN V128:$Rm, V128:$Rn)>;7256 let AddedComplexity = 10 in7257 def : Pat<(concat_vectors (VT64 V64:$Rd),7258 (trunc (VT128 (AArch64vlshr (xor V128:$Rn, immAllOnesV:$Rm),7259 (i32 Shift))))),7260 (SUBHN2 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), V128:$Rm, V128:$Rn)>;7261}7262 7263defm : AddSubHNPatterns<ADDHNv8i16_v8i8, ADDHNv8i16_v16i8,7264 SUBHNv8i16_v8i8, SUBHNv8i16_v16i8,7265 v8i8, v8i16, 8>;7266defm : AddSubHNPatterns<ADDHNv4i32_v4i16, ADDHNv4i32_v8i16,7267 SUBHNv4i32_v4i16, SUBHNv4i32_v8i16,7268 v4i16, v4i32, 16>;7269defm : AddSubHNPatterns<ADDHNv2i64_v2i32, ADDHNv2i64_v4i32,7270 SUBHNv2i64_v2i32, SUBHNv2i64_v4i32,7271 v2i32, v2i64, 32>;7272 7273//----------------------------------------------------------------------------7274// AdvSIMD bitwise extract from vector instruction.7275//----------------------------------------------------------------------------7276 7277defm EXT : SIMDBitwiseExtract<"ext">;7278 7279def AdjustExtImm : SDNodeXForm<imm, [{7280 return CurDAG->getTargetConstant(8 + N->getZExtValue(), SDLoc(N), MVT::i32);7281}]>;7282multiclass ExtPat<ValueType VT64, ValueType VT128, int N> {7283 def : Pat<(VT64 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),7284 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;7285 def : Pat<(VT128 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),7286 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;7287 // We use EXT to handle extract_subvector to copy the upper 64-bits of a7288 // 128-bit vector.7289 def : Pat<(VT64 (extract_subvector V128:$Rn, (i64 N))),7290 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;7291 // A 64-bit EXT of two halves of the same 128-bit register can be done as a7292 // single 128-bit EXT.7293 def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 0)),7294 (extract_subvector V128:$Rn, (i64 N)),7295 (i32 imm:$imm))),7296 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, imm:$imm), dsub)>;7297 // A 64-bit EXT of the high half of a 128-bit register can be done using a7298 // 128-bit EXT of the whole register with an adjustment to the immediate. The7299 // top half of the other operand will be unset, but that doesn't matter as it7300 // will not be used.7301 def : Pat<(VT64 (AArch64ext (extract_subvector V128:$Rn, (i64 N)),7302 V64:$Rm,7303 (i32 imm:$imm))),7304 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn,7305 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),7306 (AdjustExtImm imm:$imm)), dsub)>;7307}7308 7309defm : ExtPat<v8i8, v16i8, 8>;7310defm : ExtPat<v4i16, v8i16, 4>;7311defm : ExtPat<v4f16, v8f16, 4>;7312defm : ExtPat<v4bf16, v8bf16, 4>;7313defm : ExtPat<v2i32, v4i32, 2>;7314defm : ExtPat<v2f32, v4f32, 2>;7315defm : ExtPat<v1i64, v2i64, 1>;7316defm : ExtPat<v1f64, v2f64, 1>;7317 7318//----------------------------------------------------------------------------7319// AdvSIMD zip vector7320//----------------------------------------------------------------------------7321 7322defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;7323defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;7324defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;7325defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;7326defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;7327defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;7328 7329def trunc_optional_assert_ext : PatFrags<(ops node:$op0),7330 [(trunc node:$op0),7331 (assertzext (trunc node:$op0)),7332 (assertsext (trunc node:$op0))]>;7333 7334// concat_vectors(trunc(x), trunc(y)) -> uzp1(x, y)7335// concat_vectors(assertzext(trunc(x)), assertzext(trunc(y))) -> uzp1(x, y)7336// concat_vectors(assertsext(trunc(x)), assertsext(trunc(y))) -> uzp1(x, y)7337class concat_trunc_to_uzp1_pat<ValueType SrcTy, ValueType TruncTy, ValueType ConcatTy>7338 : Pat<(ConcatTy (concat_vectors (TruncTy (trunc_optional_assert_ext (SrcTy V128:$Vn))),7339 (TruncTy (trunc_optional_assert_ext (SrcTy V128:$Vm))))),7340 (!cast<Instruction>("UZP1"#ConcatTy) V128:$Vn, V128:$Vm)>;7341def : concat_trunc_to_uzp1_pat<v8i16, v8i8, v16i8>;7342def : concat_trunc_to_uzp1_pat<v4i32, v4i16, v8i16>;7343def : concat_trunc_to_uzp1_pat<v2i64, v2i32, v4i32>;7344 7345// trunc(concat_vectors(trunc(x), trunc(y))) -> xtn(uzp1(x, y))7346// trunc(concat_vectors(assertzext(trunc(x)), assertzext(trunc(y)))) -> xtn(uzp1(x, y))7347// trunc(concat_vectors(assertsext(trunc(x)), assertsext(trunc(y)))) -> xtn(uzp1(x, y))7348class trunc_concat_trunc_to_xtn_uzp1_pat<ValueType SrcTy, ValueType TruncTy, ValueType ConcatTy,7349 ValueType Ty>7350 : Pat<(Ty (trunc_optional_assert_ext7351 (ConcatTy (concat_vectors7352 (TruncTy (trunc_optional_assert_ext (SrcTy V128:$Vn))),7353 (TruncTy (trunc_optional_assert_ext (SrcTy V128:$Vm))))))),7354 (!cast<Instruction>("XTN"#Ty) (!cast<Instruction>("UZP1"#ConcatTy) V128:$Vn, V128:$Vm))>;7355def : trunc_concat_trunc_to_xtn_uzp1_pat<v4i32, v4i16, v8i16, v8i8>;7356def : trunc_concat_trunc_to_xtn_uzp1_pat<v2i64, v2i32, v4i32, v4i16>;7357 7358def : Pat<(v8i8 (trunc (concat_vectors (v4i16 V64:$Vn), (v4i16 V64:$Vm)))),7359 (UZP1v8i8 V64:$Vn, V64:$Vm)>;7360def : Pat<(v4i16 (trunc (concat_vectors (v2i32 V64:$Vn), (v2i32 V64:$Vm)))),7361 (UZP1v4i16 V64:$Vn, V64:$Vm)>;7362 7363def : Pat<(v16i8 (concat_vectors7364 (v8i8 (trunc (AArch64vlshr (v8i16 V128:$Vn), (i32 8)))),7365 (v8i8 (trunc (AArch64vlshr (v8i16 V128:$Vm), (i32 8)))))),7366 (UZP2v16i8 V128:$Vn, V128:$Vm)>;7367def : Pat<(v8i16 (concat_vectors7368 (v4i16 (trunc (AArch64vlshr (v4i32 V128:$Vn), (i32 16)))),7369 (v4i16 (trunc (AArch64vlshr (v4i32 V128:$Vm), (i32 16)))))),7370 (UZP2v8i16 V128:$Vn, V128:$Vm)>;7371def : Pat<(v4i32 (concat_vectors7372 (v2i32 (trunc (AArch64vlshr (v2i64 V128:$Vn), (i32 32)))),7373 (v2i32 (trunc (AArch64vlshr (v2i64 V128:$Vm), (i32 32)))))),7374 (UZP2v4i32 V128:$Vn, V128:$Vm)>;7375 7376// extract_subvec(anyext) can use zip. Check for one use on the anyext, otherwise7377// the extract_subvector can be free.7378let HasOneUse = 1 in7379def anyext_oneuse: PatFrag<(ops node:$src0), (anyext $src0)>;7380def : Pat<(v4i16 (extract_subvector (v8i16 (anyext_oneuse (v8i8 V64:$Vn))), (i64 0))),7381 (ZIP1v8i8 V64:$Vn, V64:$Vn)>;7382def : Pat<(v2i32 (extract_subvector (v4i32 (anyext_oneuse (v4i16 V64:$Vn))), (i64 0))),7383 (ZIP1v4i16 V64:$Vn, V64:$Vn)>;7384def : Pat<(v1i64 (extract_subvector (v2i64 (anyext_oneuse (v2i32 V64:$Vn))), (i64 0))),7385 (ZIP1v2i32 V64:$Vn, V64:$Vn)>;7386def : Pat<(v4i16 (extract_subvector (v8i16 (anyext_oneuse (v8i8 V64:$Vn))), (i64 4))),7387 (ZIP2v8i8 V64:$Vn, V64:$Vn)>;7388def : Pat<(v2i32 (extract_subvector (v4i32 (anyext_oneuse (v4i16 V64:$Vn))), (i64 2))),7389 (ZIP2v4i16 V64:$Vn, V64:$Vn)>;7390def : Pat<(v1i64 (extract_subvector (v2i64 (anyext_oneuse (v2i32 V64:$Vn))), (i64 1))),7391 (ZIP2v2i32 V64:$Vn, V64:$Vn)>;7392 7393//----------------------------------------------------------------------------7394// AdvSIMD TBL/TBX instructions7395//----------------------------------------------------------------------------7396 7397defm TBL : SIMDTableLookup< 0, "tbl">;7398defm TBX : SIMDTableLookupTied<1, "tbx">;7399 7400def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),7401 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;7402def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),7403 (TBLv16i8One V128:$Ri, V128:$Rn)>;7404 7405def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),7406 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),7407 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;7408def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),7409 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),7410 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;7411 7412//----------------------------------------------------------------------------7413// AdvSIMD LUT instructions7414//----------------------------------------------------------------------------7415let Predicates = [HasLUT] in {7416 defm LUT2 : BaseSIMDTableLookupIndexed2<"luti2">;7417 defm LUT4 : BaseSIMDTableLookupIndexed4<"luti4">;7418 7419 multiclass Luti2_patterns<Instruction Instr, ValueType VT64, ValueType VT128>{7420 def : Pat<(VT128 (int_aarch64_neon_vluti2_lane VT64:$Rn,7421 v8i8:$Rm, i32:$idx)),7422 (Instr (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub),7423 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rm, dsub), VectorIndexS32b_timm:$idx)>;7424 def : Pat<(VT128 (int_aarch64_neon_vluti2_laneq VT64:$Rn,7425 v16i8:$Rm, i32:$idx)),7426 (Instr (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub),7427 V128:$Rm, VectorIndexS32b_timm:$idx)>;7428 def : Pat<(VT128 (int_aarch64_neon_vluti2_lane VT128:$Rn,7429 v8i8:$Rm, i32:$idx)),7430 (Instr V128:$Rn, (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rm, dsub),7431 VectorIndexS32b_timm:$idx)>;7432 def : Pat<(VT128 (int_aarch64_neon_vluti2_laneq VT128:$Rn,7433 v16i8:$Rm, i32:$idx)),7434 (Instr V128:$Rn, V128:$Rm, VectorIndexS32b_timm:$idx)>;7435 }7436 7437 defm : Luti2_patterns<LUT2_B, v8i8, v16i8>;7438 defm : Luti2_patterns<LUT2_H, v4i16, v8i16>;7439 defm : Luti2_patterns<LUT2_H, v4f16, v8f16>;7440 defm : Luti2_patterns<LUT2_H, v4bf16, v8bf16>;7441 7442 def : Pat<(v16i8 (int_aarch64_neon_vluti4q_laneq v16i8:$Rn,7443 v16i8:$Rm, i32:$idx)),7444 (LUT4_B VecListOne16b:$Rn, V128:$Rm, VectorIndexD32b_timm:$idx)>;7445 def : Pat<(v16i8 (int_aarch64_neon_vluti4q_lane v16i8:$Rn,7446 v8i8:$Rm, i32:$idx)),7447 (LUT4_B VecListOne16b:$Rn, (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rm, dsub), VectorIndexD32b_timm:$idx)>;7448 7449 foreach VT = [v8i16, v8f16, v8bf16] in {7450 def : Pat<(VT (int_aarch64_neon_vluti4q_laneq_x2 VT:$Rn1,7451 VT:$Rn2, v16i8:$Rm, i32:$idx)),7452 (LUT4_H (REG_SEQUENCE QQ, VecListOne8h:$Rn1, qsub0, VecListOne8h:$Rn2, qsub1), V128:$Rm, VectorIndexS32b_timm:$idx)>;7453 def : Pat<(VT (int_aarch64_neon_vluti4q_lane_x2 VT:$Rn1,7454 VT:$Rn2, v8i8:$Rm, i32:$idx)),7455 (LUT4_H (REG_SEQUENCE QQ, VecListOne8h:$Rn1, qsub0, VecListOne8h:$Rn2, qsub1),7456 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rm, dsub), VectorIndexS32b_timm:$idx)>;7457 }7458}7459 7460//----------------------------------------------------------------------------7461// AdvSIMD scalar DUP instruction7462//----------------------------------------------------------------------------7463 7464defm DUP : SIMDScalarDUP<"mov">;7465 7466//----------------------------------------------------------------------------7467// AdvSIMD scalar pairwise instructions7468//----------------------------------------------------------------------------7469 7470defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;7471defm FADDP : SIMDFPPairwiseScalar<0, 0b01101, "faddp">;7472defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, "fmaxnmp">;7473defm FMAXP : SIMDFPPairwiseScalar<0, 0b01111, "fmaxp">;7474defm FMINNMP : SIMDFPPairwiseScalar<1, 0b01100, "fminnmp">;7475defm FMINP : SIMDFPPairwiseScalar<1, 0b01111, "fminp">;7476 7477// Only the lower half of the result of the inner FADDP is used in the patterns7478// below, so the second operand does not matter. Re-use the first input7479// operand, so no additional dependencies need to be introduced.7480let Predicates = [HasFullFP16] in {7481def : Pat<(f16 (vecreduce_fadd (v8f16 V128:$Rn))),7482 (FADDPv2i16p7483 (EXTRACT_SUBREG7484 (FADDPv8f16 (FADDPv8f16 V128:$Rn, V128:$Rn), V128:$Rn),7485 dsub))>;7486def : Pat<(f16 (vecreduce_fadd (v4f16 V64:$Rn))),7487 (FADDPv2i16p (FADDPv4f16 V64:$Rn, V64:$Rn))>;7488}7489def : Pat<(f32 (vecreduce_fadd (v4f32 V128:$Rn))),7490 (FADDPv2i32p7491 (EXTRACT_SUBREG7492 (FADDPv4f32 V128:$Rn, V128:$Rn),7493 dsub))>;7494def : Pat<(f32 (vecreduce_fadd (v2f32 V64:$Rn))),7495 (FADDPv2i32p V64:$Rn)>;7496def : Pat<(f64 (vecreduce_fadd (v2f64 V128:$Rn))),7497 (FADDPv2i64p V128:$Rn)>;7498 7499def : Pat<(v2i64 (AArch64saddv V128:$Rn)),7500 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;7501def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),7502 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;7503def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),7504 (FADDPv2i32p V64:$Rn)>;7505def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),7506 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;7507def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),7508 (FADDPv2i64p V128:$Rn)>;7509def : Pat<(f32 (AArch64fmaxnmv (v2f32 V64:$Rn))),7510 (FMAXNMPv2i32p V64:$Rn)>;7511def : Pat<(f64 (AArch64fmaxnmv (v2f64 V128:$Rn))),7512 (FMAXNMPv2i64p V128:$Rn)>;7513def : Pat<(f32 (AArch64fmaxv (v2f32 V64:$Rn))),7514 (FMAXPv2i32p V64:$Rn)>;7515def : Pat<(f64 (AArch64fmaxv (v2f64 V128:$Rn))),7516 (FMAXPv2i64p V128:$Rn)>;7517def : Pat<(f32 (AArch64fminnmv (v2f32 V64:$Rn))),7518 (FMINNMPv2i32p V64:$Rn)>;7519def : Pat<(f64 (AArch64fminnmv (v2f64 V128:$Rn))),7520 (FMINNMPv2i64p V128:$Rn)>;7521def : Pat<(f32 (AArch64fminv (v2f32 V64:$Rn))),7522 (FMINPv2i32p V64:$Rn)>;7523def : Pat<(f64 (AArch64fminv (v2f64 V128:$Rn))),7524 (FMINPv2i64p V128:$Rn)>;7525 7526//----------------------------------------------------------------------------7527// AdvSIMD INS/DUP instructions7528//----------------------------------------------------------------------------7529 7530def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;7531def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;7532def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;7533def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;7534def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;7535def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;7536def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;7537 7538def DUPv2i64lane : SIMDDup64FromElement;7539def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;7540def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;7541def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;7542def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;7543def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;7544def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;7545 7546// DUP from a 64-bit register to a 64-bit register is just a copy7547def : Pat<(v1i64 (AArch64dup (i64 GPR64:$Rn))),7548 (COPY_TO_REGCLASS GPR64:$Rn, FPR64)>;7549def : Pat<(v1f64 (AArch64dup (f64 FPR64:$Rn))),7550 (COPY_TO_REGCLASS FPR64:$Rn, FPR64)>;7551 7552def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),7553 (v2f32 (DUPv2i32lane7554 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),7555 (i64 0)))>;7556def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),7557 (v4f32 (DUPv4i32lane7558 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),7559 (i64 0)))>;7560def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),7561 (v2f64 (DUPv2i64lane7562 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),7563 (i64 0)))>;7564def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),7565 (v4f16 (DUPv4i16lane7566 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),7567 (i64 0)))>;7568def : Pat<(v4bf16 (AArch64dup (bf16 FPR16:$Rn))),7569 (v4bf16 (DUPv4i16lane7570 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),7571 (i64 0)))>;7572def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),7573 (v8f16 (DUPv8i16lane7574 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),7575 (i64 0)))>;7576def : Pat<(v8bf16 (AArch64dup (bf16 FPR16:$Rn))),7577 (v8bf16 (DUPv8i16lane7578 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),7579 (i64 0)))>;7580 7581// Patterns for importing fpr i8 G_DUP under GISel.7582def : Pat<(v8i8 (AArch64dup (i8 FPR8:$Rn))),7583 (v8i8 (DUPv8i8lane7584 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rn, bsub),7585 (i64 0)))>;7586def : Pat<(v16i8 (AArch64dup (i8 FPR8:$Rn))),7587 (v16i8 (DUPv16i8lane7588 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rn, bsub),7589 (i64 0)))>;7590 7591def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),7592 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;7593def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),7594 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;7595 7596def : Pat<(v4bf16 (AArch64duplane16 (v8bf16 V128:$Rn), VectorIndexH:$imm)),7597 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;7598def : Pat<(v8bf16 (AArch64duplane16 (v8bf16 V128:$Rn), VectorIndexH:$imm)),7599 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;7600 7601def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),7602 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;7603def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),7604 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;7605def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),7606 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;7607 7608// Also covers DUP (truncate i64 to i32)7609def : Pat<(v2i32 (AArch64dup (i32 (extractelt (v4i32 V128:$Rn), imm:$idx)))),7610 (DUPv2i32lane V128:$Rn, imm:$idx)>;7611def : Pat<(v4i32 (AArch64dup (i32 (extractelt (v4i32 V128:$Rn), imm:$idx)))),7612 (DUPv4i32lane V128:$Rn, imm:$idx)>;7613 7614// If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane7615// instruction even if the types don't match: we just have to remap the lane7616// carefully. N.b. this trick only applies to truncations.7617def VecIndex_x2 : SDNodeXForm<imm, [{7618 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);7619}]>;7620def VecIndex_x4 : SDNodeXForm<imm, [{7621 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);7622}]>;7623def VecIndex_x8 : SDNodeXForm<imm, [{7624 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);7625}]>;7626 7627class DUPWithTruncPat<ValueType ResVT, ValueType SrcVT, ValueType ScalVT,7628 Instruction DUP, SDNodeXForm IdxXFORM>7629 : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (SrcVT V128:$Rn), imm:$idx)))),7630 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;7631 7632// DUP (truncate i16 to i8)7633def : DUPWithTruncPat<v8i8, v8i16, i32, DUPv8i8lane, VecIndex_x2>;7634def : DUPWithTruncPat<v16i8, v8i16, i32, DUPv16i8lane, VecIndex_x2>;7635// DUP (truncate i32/64 to i8)7636def : DUPWithTruncPat<v8i8, v4i32, i32, DUPv8i8lane, VecIndex_x4>;7637def : DUPWithTruncPat<v16i8, v4i32, i32, DUPv16i8lane, VecIndex_x4>;7638// DUP (truncate i32/i64 to i16)7639def : DUPWithTruncPat<v4i16, v4i32, i32, DUPv4i16lane, VecIndex_x2>;7640def : DUPWithTruncPat<v8i16, v4i32, i32, DUPv8i16lane, VecIndex_x2>;7641 7642// SMOV and UMOV definitions, with some extra patterns for convenience7643defm SMOV : SMov;7644defm UMOV : UMov;7645 7646def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),7647 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;7648def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),7649 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;7650def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),7651 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;7652def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),7653 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;7654def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),7655 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;7656def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),7657 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;7658 7659def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn),7660 VectorIndexB:$idx)))), i8),7661 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;7662def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn),7663 VectorIndexH:$idx)))), i16),7664 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;7665 7666// Extracting i8 or i16 elements will have the zero-extend transformed to7667// an 'and' mask by type legalization since neither i8 nor i16 are legal types7668// for AArch64. Match these patterns here since UMOV already zeroes out the high7669// bits of the destination register.7670def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),7671 (i32 0xff)),7672 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;7673def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),7674 (i32 0xffff)),7675 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;7676 7677def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn),7678 VectorIndexB:$idx)))), (i64 0xff))),7679 (SUBREG_TO_REG (i64 0), (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx)), sub_32)>;7680def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn),7681 VectorIndexH:$idx)))), (i64 0xffff))),7682 (SUBREG_TO_REG (i64 0), (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx)), sub_32)>;7683 7684defm INS : SIMDIns;7685 7686def : Pat<(v16i8 (vec_ins_or_scal_vec GPR32:$Rn)),7687 (SUBREG_TO_REG (i32 0),7688 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;7689def : Pat<(v8i8 (vec_ins_or_scal_vec GPR32:$Rn)),7690 (SUBREG_TO_REG (i32 0),7691 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;7692 7693// The top bits will be zero from the FMOVWSr7694def : Pat<(v8i8 (bitconvert (i64 (zext GPR32:$Rn)))),7695 (SUBREG_TO_REG (i32 0), (f32 (FMOVWSr GPR32:$Rn)), ssub)>;7696 7697def : Pat<(v8i16 (vec_ins_or_scal_vec GPR32:$Rn)),7698 (SUBREG_TO_REG (i32 0),7699 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;7700def : Pat<(v4i16 (vec_ins_or_scal_vec GPR32:$Rn)),7701 (SUBREG_TO_REG (i32 0),7702 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;7703 7704def : Pat<(v2i32 (vec_ins_or_scal_vec GPR32:$Rn)),7705 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GPR32:$Rn, ssub)>;7706def : Pat<(v4i32 (vec_ins_or_scal_vec GPR32:$Rn)),7707 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GPR32:$Rn, ssub)>;7708def : Pat<(v2i64 (vec_ins_or_scal_vec GPR64:$Rn)),7709 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GPR64:$Rn, dsub)>;7710 7711def : Pat<(v4f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),7712 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;7713def : Pat<(v8f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),7714 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;7715 7716def : Pat<(v4bf16 (vec_ins_or_scal_vec (bf16 FPR16:$Rn))),7717 (INSERT_SUBREG (v4bf16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;7718def : Pat<(v8bf16 (vec_ins_or_scal_vec (bf16 FPR16:$Rn))),7719 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;7720 7721def : Pat<(v4f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),7722 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;7723def : Pat<(v8f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),7724 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;7725 7726def : Pat<(v4bf16 (vec_ins_or_scal_vec (bf16 FPR16:$Rn))),7727 (INSERT_SUBREG (v4bf16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;7728def : Pat<(v8bf16 (vec_ins_or_scal_vec (bf16 FPR16:$Rn))),7729 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;7730 7731def : Pat<(v4f32 (vec_ins_or_scal_vec (f32 FPR32:$Rn))),7732 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;7733def : Pat<(v2f32 (vec_ins_or_scal_vec (f32 FPR32:$Rn))),7734 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;7735 7736def : Pat<(v2f64 (vec_ins_or_scal_vec (f64 FPR64:$Rn))),7737 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;7738 7739def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),7740 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),7741 (EXTRACT_SUBREG7742 (INSvi16lane7743 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),7744 VectorIndexS:$imm,7745 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),7746 (i64 0)),7747 dsub)>;7748 7749let Predicates = [UseWzrToVecMove] in {7750def : Pat<(vector_insert (v8f16 V128:$Rn), (f16 fpimm0), (i64 VectorIndexH:$imm)),7751 (INSvi16gpr V128:$Rn, VectorIndexH:$imm, WZR)>;7752def : Pat<(vector_insert (v4f16 V64:$Rn), (f16 fpimm0), (i64 VectorIndexH:$imm)),7753 (EXTRACT_SUBREG (INSvi16gpr (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)), VectorIndexH:$imm, WZR), dsub)>;7754def : Pat<(vector_insert (v4f32 V128:$Rn), (f32 fpimm0), (i64 VectorIndexS:$imm)),7755 (INSvi32gpr V128:$Rn, VectorIndexS:$imm, WZR)>;7756def : Pat<(vector_insert (v2f32 V64:$Rn), (f32 fpimm0), (i64 VectorIndexS:$imm)),7757 (EXTRACT_SUBREG (INSvi32gpr (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)), VectorIndexS:$imm, WZR), dsub)>;7758def : Pat<(vector_insert v2f64:$Rn, (f64 fpimm0), (i64 VectorIndexD:$imm)),7759 (INSvi64gpr V128:$Rn, VectorIndexS:$imm, XZR)>;7760}7761 7762def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),7763 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),7764 (INSvi16lane7765 V128:$Rn, VectorIndexH:$imm,7766 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),7767 (i64 0))>;7768 7769def : Pat<(v4bf16 (vector_insert (v4bf16 V64:$Rn),7770 (bf16 FPR16:$Rm), (i64 VectorIndexS:$imm))),7771 (EXTRACT_SUBREG7772 (INSvi16lane7773 (v8bf16 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), V64:$Rn, dsub)),7774 VectorIndexS:$imm,7775 (v8bf16 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),7776 (i64 0)),7777 dsub)>;7778 7779def : Pat<(v8bf16 (vector_insert (v8bf16 V128:$Rn),7780 (bf16 FPR16:$Rm), (i64 VectorIndexH:$imm))),7781 (INSvi16lane7782 V128:$Rn, VectorIndexH:$imm,7783 (v8bf16 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),7784 (i64 0))>;7785 7786def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),7787 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),7788 (EXTRACT_SUBREG7789 (INSvi32lane7790 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),7791 VectorIndexS:$imm,7792 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),7793 (i64 0)),7794 dsub)>;7795def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),7796 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),7797 (INSvi32lane7798 V128:$Rn, VectorIndexS:$imm,7799 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),7800 (i64 0))>;7801def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),7802 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),7803 (INSvi64lane7804 V128:$Rn, VectorIndexD:$imm,7805 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),7806 (i64 0))>;7807 7808def : Pat<(v2i32 (vector_insert (v2i32 V64:$Rn), (i32 GPR32:$Rm), (i64 VectorIndexS:$imm))),7809 (EXTRACT_SUBREG7810 (INSvi32gpr (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$Rn, dsub)),7811 VectorIndexS:$imm, GPR32:$Rm),7812 dsub)>;7813def : Pat<(v4i16 (vector_insert (v4i16 V64:$Rn), (i32 GPR32:$Rm), (i64 VectorIndexH:$imm))),7814 (EXTRACT_SUBREG7815 (INSvi16gpr (v8i16 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), V64:$Rn, dsub)),7816 VectorIndexH:$imm, GPR32:$Rm),7817 dsub)>;7818def : Pat<(v8i8 (vector_insert (v8i8 V64:$Rn), (i32 GPR32:$Rm), (i64 VectorIndexB:$imm))),7819 (EXTRACT_SUBREG7820 (INSvi8gpr (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), V64:$Rn, dsub)),7821 VectorIndexB:$imm, GPR32:$Rm),7822 dsub)>;7823 7824def : Pat<(v8i8 (vector_insert (v8i8 V64:$Rn), (i8 FPR8:$Rm), (i64 VectorIndexB:$imm))),7825 (EXTRACT_SUBREG7826 (INSvi8lane (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), V64:$Rn, dsub)),7827 VectorIndexB:$imm, (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rm, bsub)), (i64 0)),7828 dsub)>;7829def : Pat<(v16i8 (vector_insert (v16i8 V128:$Rn), (i8 FPR8:$Rm), (i64 VectorIndexB:$imm))),7830 (INSvi8lane V128:$Rn, VectorIndexB:$imm,7831 (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rm, bsub)), (i64 0))>;7832 7833// Copy an element at a constant index in one vector into a constant indexed7834// element of another.7835// FIXME refactor to a shared class/dev parameterized on vector type, vector7836// index type and INS extension7837def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane7838 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),7839 VectorIndexB:$idx2)),7840 (v16i8 (INSvi8lane7841 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)7842 )>;7843def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane7844 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),7845 VectorIndexH:$idx2)),7846 (v8i16 (INSvi16lane7847 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)7848 )>;7849def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane7850 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),7851 VectorIndexS:$idx2)),7852 (v4i32 (INSvi32lane7853 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)7854 )>;7855def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane7856 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),7857 VectorIndexD:$idx2)),7858 (v2i64 (INSvi64lane7859 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)7860 )>;7861 7862// Move elements between vectors7863multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64, ValueType VTSVE,7864 ValueType VTScal, Operand SVEIdxTy, Instruction INS, Instruction DUP, SubRegIndex DUPSub> {7865 // Extracting from the lowest 128-bits of an SVE vector7866 def : Pat<(VT128 (vector_insert undef,7867 (VTScal (vector_extract VTSVE:$Rm, (i64 SVEIdxTy:$Immn))),7868 (i64 0))),7869 (INSERT_SUBREG (VT128 (IMPLICIT_DEF)),7870 (DUP (VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)), SVEIdxTy:$Immn),7871 DUPSub)>;7872 7873 def : Pat<(VT128 (vector_insert VT128:$Rn,7874 (VTScal (vector_extract VTSVE:$Rm, (i64 SVEIdxTy:$Immn))),7875 (i64 imm:$Immd))),7876 (INS VT128:$Rn, imm:$Immd, (VT128 (EXTRACT_SUBREG ZPR:$Rm, zsub)), SVEIdxTy:$Immn)>;7877 7878 def : Pat<(VT64 (vector_insert VT64:$Rn,7879 (VTScal (vector_extract VTSVE:$Rm, (i64 SVEIdxTy:$Immn))),7880 (i64 imm:$Immd))),7881 (EXTRACT_SUBREG7882 (INS (SUBREG_TO_REG (i64 0), VT64:$Rn, dsub), imm:$Immd,7883 (VT128 (EXTRACT_SUBREG ZPR:$Rm, zsub)), SVEIdxTy:$Immn),7884 dsub)>;7885 // Extracting from another NEON vector7886 def : Pat<(VT128 (vector_insert V128:$src,7887 (VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))),7888 (i64 imm:$Immd))),7889 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;7890 7891 def : Pat<(VT128 (vector_insert undef,7892 (VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))),7893 (i64 0))),7894 (INSERT_SUBREG (VT128 (IMPLICIT_DEF)), (DUP V128:$Rn, imm:$Immn), DUPSub)>;7895 7896 def : Pat<(VT128 (vector_insert V128:$src,7897 (VTScal (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))),7898 (i64 imm:$Immd))),7899 (INS V128:$src, imm:$Immd,7900 (VT128 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub)), imm:$Immn)>;7901 7902 def : Pat<(VT64 (vector_insert V64:$src,7903 (VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))),7904 (i64 imm:$Immd))),7905 (EXTRACT_SUBREG (INS (VT128 (SUBREG_TO_REG (i64 0), V64:$src, dsub)),7906 imm:$Immd, V128:$Rn, imm:$Immn),7907 dsub)>;7908 7909 def : Pat<(VT64 (vector_insert V64:$src,7910 (VTScal (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))),7911 (i64 imm:$Immd))),7912 (EXTRACT_SUBREG7913 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,7914 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),7915 dsub)>;7916}7917 7918defm : Neon_INS_elt_pattern<v8f16, v4f16, nxv8f16, f16, VectorIndexH, INSvi16lane, DUPi16, hsub>;7919defm : Neon_INS_elt_pattern<v8bf16, v4bf16, nxv8bf16, bf16, VectorIndexH, INSvi16lane, DUPi16, hsub>;7920defm : Neon_INS_elt_pattern<v4f32, v2f32, nxv4f32, f32, VectorIndexS, INSvi32lane, DUPi32, ssub>;7921defm : Neon_INS_elt_pattern<v2f64, v1f64, nxv2f64, f64, VectorIndexD, INSvi64lane, DUPi64, dsub>;7922 7923// Accept i8 scalar argument in GlobalISel.7924defm : Neon_INS_elt_pattern<v16i8, v8i8, nxv16i8, i8, VectorIndexB, INSvi8lane, DUPi8, bsub>;7925defm : Neon_INS_elt_pattern<v16i8, v8i8, nxv16i8, i32, VectorIndexB, INSvi8lane, DUPi8, bsub>;7926defm : Neon_INS_elt_pattern<v8i16, v4i16, nxv8i16, i32, VectorIndexH, INSvi16lane, DUPi16, hsub>;7927defm : Neon_INS_elt_pattern<v4i32, v2i32, nxv4i32, i32, VectorIndexS, INSvi32lane, DUPi32, ssub>;7928defm : Neon_INS_elt_pattern<v2i64, v1i64, nxv2i64, i64, VectorIndexD, INSvi64lane, DUPi64, dsub>;7929 7930// Insert from bitcast7931// vector_insert(bitcast(f32 src), n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)7932def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),7933 (INSvi32lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>;7934def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),7935 (EXTRACT_SUBREG7936 (INSvi32lane (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$src, dsub)),7937 imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0),7938 dsub)>;7939def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), (i64 imm:$Immd))),7940 (INSvi64lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>;7941 7942// Patterns for i8/i16 -> v2i32/v4i16 lane moves via insert and extract that go via i32.7943multiclass Neon_INS_elt_ext_pattern<ValueType VT128, ValueType VT64, ValueType OutVT,7944 Instruction INS, Instruction DUP, SubRegIndex DUPSub,7945 SDNodeXForm VecIndexMult> {7946 // VT64->OutVT7947 def : Pat<(OutVT (vector_insert (OutVT V64:$src),7948 (i32 (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))),7949 (i64 imm:$Immd))),7950 (EXTRACT_SUBREG7951 (INS (INSERT_SUBREG (VT128 (IMPLICIT_DEF)), V64:$src, dsub), (VecIndexMult imm:$Immd),7952 (INSERT_SUBREG (VT128 (IMPLICIT_DEF)), V64:$Rn, dsub), imm:$Immn),7953 dsub)>;7954 def : Pat<(OutVT (scalar_to_vector (i32 (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))))),7955 (EXTRACT_SUBREG7956 (VT128 (SUBREG_TO_REG7957 (i64 0),7958 (DUP (INSERT_SUBREG (VT128 (IMPLICIT_DEF)), V64:$Rn, dsub), imm:$Immn),7959 DUPSub)),7960 dsub)>;7961 7962 // VT128->OutVT7963 def : Pat<(OutVT (vector_insert (OutVT V64:$src),7964 (i32 (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))),7965 (i64 imm:$Immd))),7966 (EXTRACT_SUBREG7967 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), (VecIndexMult imm:$Immd),7968 V128:$Rn, imm:$Immn),7969 dsub)>;7970 def : Pat<(OutVT (scalar_to_vector (i32 (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))))),7971 (EXTRACT_SUBREG7972 (VT128 (SUBREG_TO_REG7973 (i64 0),7974 (DUP V128:$Rn, imm:$Immn),7975 DUPSub)),7976 dsub)>;7977}7978 7979defm : Neon_INS_elt_ext_pattern<v16i8, v8i8, v4i16, INSvi8lane, DUPi8, bsub, VecIndex_x2>;7980defm : Neon_INS_elt_ext_pattern<v16i8, v8i8, v2i32, INSvi8lane, DUPi8, bsub, VecIndex_x4>;7981defm : Neon_INS_elt_ext_pattern<v8i16, v4i16, v2i32, INSvi16lane, DUPi16, hsub, VecIndex_x2>;7982 7983// bitcast of an extract7984// f32 bitcast(vector_extract(v4i32 src, 0)) -> EXTRACT_SUBREG(src)7985def : Pat<(f32 (bitconvert (i32 (vector_extract v16i8:$src, (i64 0))))),7986 (EXTRACT_SUBREG V128:$src, bsub)>;7987def : Pat<(f32 (bitconvert (i32 (vector_extract v8i16:$src, (i64 0))))),7988 (EXTRACT_SUBREG V128:$src, hsub)>;7989def : Pat<(f32 (bitconvert (i32 (vector_extract v4i32:$src, (i64 0))))),7990 (EXTRACT_SUBREG V128:$src, ssub)>;7991def : Pat<(f64 (bitconvert (i64 (vector_extract v2i64:$src, (i64 0))))),7992 (EXTRACT_SUBREG V128:$src, dsub)>;7993 7994// f32 bitcast(vector_extract(v4i32 src, lane)) -> DUPi32(src, lane)7995def : Pat<(f32 (bitconvert (i32 (vector_extract v16i8:$src, imm:$Immd)))),7996 (EXTRACT_SUBREG (v16i8 (SUBREG_TO_REG (i64 0), (DUPi8 V128:$src, imm:$Immd), bsub)), ssub)>;7997def : Pat<(f32 (bitconvert (i32 (vector_extract v8i16:$src, imm:$Immd)))),7998 (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (DUPi16 V128:$src, imm:$Immd), hsub)), ssub)>;7999def : Pat<(f32 (bitconvert (i32 (vector_extract v4i32:$src, imm:$Immd)))),8000 (DUPi32 V128:$src, imm:$Immd)>;8001def : Pat<(f64 (bitconvert (i64 (vector_extract v2i64:$src, imm:$Immd)))),8002 (DUPi64 V128:$src, imm:$Immd)>;8003 8004// Floating point vector extractions are codegen'd as either a sequence of8005// subregister extractions, or a MOV (aka DUP here) if8006// the lane number is anything other than zero.8007def : Pat<(f64 (vector_extract (v2f64 V128:$Rn), (i64 0))),8008 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;8009def : Pat<(f32 (vector_extract (v4f32 V128:$Rn), (i64 0))),8010 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;8011def : Pat<(f16 (vector_extract (v8f16 V128:$Rn), (i64 0))),8012 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;8013def : Pat<(bf16 (vector_extract (v8bf16 V128:$Rn), (i64 0))),8014 (bf16 (EXTRACT_SUBREG V128:$Rn, hsub))>;8015 8016 8017def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),8018 (f64 (DUPi64 V128:$Rn, VectorIndexD:$idx))>;8019def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),8020 (f32 (DUPi32 V128:$Rn, VectorIndexS:$idx))>;8021def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),8022 (f16 (DUPi16 V128:$Rn, VectorIndexH:$idx))>;8023def : Pat<(vector_extract (v8bf16 V128:$Rn), VectorIndexH:$idx),8024 (bf16 (DUPi16 V128:$Rn, VectorIndexH:$idx))>;8025 8026// All concat_vectors operations are canonicalised to act on i64 vectors for8027// AArch64. In the general case we need an instruction, which had just as well be8028// INS.8029multiclass ConcatPat<ValueType DstTy, ValueType SrcTy,8030 ComplexPattern ExtractHigh> {8031 def : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),8032 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,8033 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;8034 8035 // If the high lanes are zero we can instead emit a d->d register mov, which8036 // will implicitly clear the upper bits.8037 def : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), immAllZerosV)),8038 (SUBREG_TO_REG (i64 0), (FMOVDr V64:$Rn), dsub)>;8039 8040 // If the high lanes are undef we can just ignore them:8041 def : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),8042 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;8043 8044 // Concatting the high half of two vectors is the insert of the first8045 // into the low half of the second.8046 def : Pat<(DstTy (concat_vectors (ExtractHigh (DstTy V128:$Rn)),8047 (ExtractHigh (DstTy V128:$Rm)))),8048 (INSvi64lane V128:$Rm, (i64 0), V128:$Rn, (i64 1))>;8049}8050 8051defm : ConcatPat<v2i64, v1i64, extract_high_v2i64>;8052defm : ConcatPat<v2f64, v1f64, extract_high_v2f64>;8053defm : ConcatPat<v4i32, v2i32, extract_high_v4i32>;8054defm : ConcatPat<v4f32, v2f32, extract_high_v4f32>;8055defm : ConcatPat<v8i16, v4i16, extract_high_v8i16>;8056defm : ConcatPat<v8f16, v4f16, extract_high_v8f16>;8057defm : ConcatPat<v8bf16, v4bf16, extract_high_v8bf16>;8058defm : ConcatPat<v16i8, v8i8, extract_high_v16i8>;8059 8060//----------------------------------------------------------------------------8061// AdvSIMD across lanes instructions8062//----------------------------------------------------------------------------8063 8064defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;8065defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;8066defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;8067defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;8068defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;8069defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;8070defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;8071defm FMAXNMV : SIMDFPAcrossLanes<0b01100, 0, "fmaxnmv", AArch64fmaxnmv>;8072defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", AArch64fmaxv>;8073defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", AArch64fminnmv>;8074defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", AArch64fminv>;8075 8076def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (sext (v8i8 V64:$op))))), (i64 0))),8077 (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (SADDLVv8i8v V64:$op), hsub)), ssub)>;8078def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (zext (v8i8 V64:$op))))), (i64 0))),8079 (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub)), ssub)>;8080def : Pat<(v8i16 (AArch64uaddv (v8i16 (sext (v8i8 V64:$op))))),8081 (v8i16 (SUBREG_TO_REG (i64 0), (SADDLVv8i8v V64:$op), hsub))>;8082def : Pat<(v8i16 (AArch64uaddv (v8i16 (zext (v8i8 V64:$op))))),8083 (v8i16 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub))>;8084def : Pat<(v4i32 (AArch64uaddv (v4i32 (sext (v4i16 V64:$op))))),8085 (v4i32 (SUBREG_TO_REG (i64 0), (SADDLVv4i16v V64:$op), ssub))>;8086def : Pat<(v4i32 (AArch64uaddv (v4i32 (zext (v4i16 V64:$op))))),8087 (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv4i16v V64:$op), ssub))>;8088 8089multiclass SIMDAcrossLaneLongPairIntrinsic<string Opc, SDPatternOperator addlp> {8090 // Patterns for addv(addlp(x)) ==> addlv8091 def : Pat<(i32 (vector_extract (v8i16 (insert_subvector undef,8092 (v4i16 (AArch64uaddv (v4i16 (addlp (v8i8 V64:$op))))),8093 (i64 0))), (i64 0))),8094 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),8095 (!cast<Instruction>(Opc#"v8i8v") V64:$op), hsub), ssub)>;8096 def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (addlp (v16i8 V128:$op))))), (i64 0))),8097 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),8098 (!cast<Instruction>(Opc#"v16i8v") V128:$op), hsub), ssub)>;8099 def : Pat<(v4i32 (AArch64uaddv (v4i32 (addlp (v8i16 V128:$op))))),8100 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (!cast<Instruction>(Opc#"v8i16v") V128:$op), ssub)>;8101 8102 // Patterns for addp(addlp(x)) ==> addlv8103 def : Pat<(v2i32 (AArch64uaddv (v2i32 (addlp (v4i16 V64:$op))))),8104 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (!cast<Instruction>(Opc#"v4i16v") V64:$op), ssub)>;8105 def : Pat<(v2i64 (AArch64uaddv (v2i64 (addlp (v4i32 V128:$op))))),8106 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (!cast<Instruction>(Opc#"v4i32v") V128:$op), dsub)>;8107}8108 8109defm : SIMDAcrossLaneLongPairIntrinsic<"UADDLV", AArch64uaddlp>;8110defm : SIMDAcrossLaneLongPairIntrinsic<"SADDLV", AArch64saddlp>;8111 8112// Pattern is used for GlobalISel8113multiclass SIMDAcrossLaneLongPairIntrinsicGISel<string Opc, SDPatternOperator addlp> {8114 // Patterns for addv(addlp(x)) ==> addlv8115 def : Pat<(i16 (vecreduce_add (v4i16 (addlp (v8i8 V64:$Rn))))),8116 (!cast<Instruction>(Opc#"v8i8v") V64:$Rn)>;8117 def : Pat<(i16 (vecreduce_add (v8i16 (addlp (v16i8 V128:$Rn))))),8118 (!cast<Instruction>(Opc#"v16i8v") V128:$Rn)>;8119 def : Pat<(i32 (vecreduce_add (v4i32 (addlp (v8i16 V128:$Rn))))),8120 (!cast<Instruction>(Opc#"v8i16v") V128:$Rn)>;8121 8122 // Patterns for addp(addlp(x))) ==> addlv8123 def : Pat<(i32 (vecreduce_add (v2i32 (addlp (v4i16 V64:$Rn))))),8124 (!cast<Instruction>(Opc#"v4i16v") V64:$Rn)>;8125 def : Pat<(i64 (vecreduce_add (v2i64 (addlp (v4i32 V128:$Rn))))),8126 (!cast<Instruction>(Opc#"v4i32v") V128:$Rn)>;8127}8128 8129defm : SIMDAcrossLaneLongPairIntrinsicGISel<"UADDLV", AArch64uaddlp>;8130defm : SIMDAcrossLaneLongPairIntrinsicGISel<"SADDLV", AArch64saddlp>;8131 8132def : Pat<(v2i64 (AArch64uaddlv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))),8133 (v2i64 (SUBREG_TO_REG (i64 0), (UADDLVv8i16v V128:$op), ssub))>;8134 8135def : Pat<(v4i32 (AArch64uaddlv (v8i16 (AArch64uaddlp (v16i8 V128:$op))))),8136 (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv16i8v V128:$op), hsub))>;8137 8138def : Pat<(v4i32 (AArch64uaddlv (v4i16 (AArch64uaddlp (v8i8 V64:$op))))),8139 (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub))>;8140 8141multiclass SIMDAcrossLaneLongReductionIntrinsic<string Opc, SDPatternOperator addlv> {8142 def : Pat<(v4i32 (addlv (v8i8 V64:$Rn))),8143 (v4i32 (SUBREG_TO_REG (i64 0), (!cast<Instruction>(Opc#"v8i8v") V64:$Rn), hsub))>;8144 8145 def : Pat<(v4i32 (addlv (v4i16 V64:$Rn))),8146 (v4i32 (SUBREG_TO_REG (i64 0), (!cast<Instruction>(Opc#"v4i16v") V64:$Rn), ssub))>;8147 8148 def : Pat<(v4i32 (addlv (v16i8 V128:$Rn))),8149 (v4i32 (SUBREG_TO_REG (i64 0), (!cast<Instruction>(Opc#"v16i8v") V128:$Rn), hsub))>;8150 8151 def : Pat<(v4i32 (addlv (v8i16 V128:$Rn))),8152 (v4i32 (SUBREG_TO_REG (i64 0), (!cast<Instruction>(Opc#"v8i16v") V128:$Rn), ssub))>;8153 8154 def : Pat<(v2i64 (addlv (v4i32 V128:$Rn))),8155 (v2i64 (SUBREG_TO_REG (i64 0), (!cast<Instruction>(Opc#"v4i32v") V128:$Rn), dsub))>;8156}8157 8158defm : SIMDAcrossLaneLongReductionIntrinsic<"UADDLV", AArch64uaddlv>;8159defm : SIMDAcrossLaneLongReductionIntrinsic<"SADDLV", AArch64saddlv>;8160 8161// Patterns for across-vector intrinsics, that have a node equivalent, that8162// returns a vector (with only the low lane defined) instead of a scalar.8163// In effect, opNode is the same as (scalar_to_vector (IntNode)).8164multiclass SIMDAcrossLanesIntrinsic<string baseOpc,8165 SDPatternOperator opNode> {8166// If a lane instruction caught the vector_extract around opNode, we can8167// directly match the latter to the instruction.8168def : Pat<(v8i8 (opNode V64:$Rn)),8169 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),8170 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;8171def : Pat<(v16i8 (opNode V128:$Rn)),8172 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),8173 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;8174def : Pat<(v4i16 (opNode V64:$Rn)),8175 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),8176 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;8177def : Pat<(v8i16 (opNode V128:$Rn)),8178 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),8179 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;8180def : Pat<(v4i32 (opNode V128:$Rn)),8181 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),8182 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;8183 8184 8185// If none did, fallback to the explicit patterns, consuming the vector_extract.8186def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),8187 (i64 0)), (i64 0))),8188 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),8189 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),8190 bsub), ssub)>;8191def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),8192 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),8193 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),8194 bsub), ssub)>;8195def : Pat<(i32 (vector_extract (insert_subvector undef,8196 (v4i16 (opNode V64:$Rn)), (i64 0)), (i64 0))),8197 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),8198 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),8199 hsub), ssub)>;8200def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),8201 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),8202 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),8203 hsub), ssub)>;8204def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),8205 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),8206 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),8207 ssub), ssub)>;8208 8209}8210 8211multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,8212 SDPatternOperator opNode>8213 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {8214// If there is a sign extension after this intrinsic, consume it as smov already8215// performed it8216def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,8217 (opNode (v8i8 V64:$Rn)), (i64 0)), (i64 0))), i8)),8218 (i32 (SMOVvi8to328219 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),8220 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),8221 (i64 0)))>;8222def : Pat<(i32 (sext_inreg (i32 (vector_extract8223 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),8224 (i32 (SMOVvi8to328225 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),8226 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),8227 (i64 0)))>;8228def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,8229 (opNode (v4i16 V64:$Rn)), (i64 0)), (i64 0))), i16)),8230 (i32 (SMOVvi16to328231 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),8232 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),8233 (i64 0)))>;8234def : Pat<(i32 (sext_inreg (i32 (vector_extract8235 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),8236 (i32 (SMOVvi16to328237 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),8238 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),8239 (i64 0)))>;8240}8241 8242multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,8243 SDPatternOperator opNode>8244 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {8245// If there is a masking operation keeping only what has been actually8246// generated, consume it.8247def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,8248 (opNode (v8i8 V64:$Rn)), (i64 0)), (i64 0))), maski8_or_more)),8249 (i32 (EXTRACT_SUBREG8250 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),8251 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),8252 ssub))>;8253def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),8254 maski8_or_more)),8255 (i32 (EXTRACT_SUBREG8256 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),8257 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),8258 ssub))>;8259def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,8260 (opNode (v4i16 V64:$Rn)), (i64 0)), (i64 0))), maski16_or_more)),8261 (i32 (EXTRACT_SUBREG8262 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),8263 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),8264 ssub))>;8265def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),8266 maski16_or_more)),8267 (i32 (EXTRACT_SUBREG8268 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),8269 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),8270 ssub))>;8271}8272 8273// For vecreduce_add, used by GlobalISel not SDAG8274def : Pat<(i8 (vecreduce_add (v8i8 V64:$Rn))),8275 (i8 (ADDVv8i8v V64:$Rn))>;8276def : Pat<(i8 (vecreduce_add (v16i8 V128:$Rn))),8277 (i8 (ADDVv16i8v V128:$Rn))>;8278def : Pat<(i16 (vecreduce_add (v4i16 V64:$Rn))),8279 (i16 (ADDVv4i16v V64:$Rn))>;8280def : Pat<(i16 (vecreduce_add (v8i16 V128:$Rn))),8281 (i16 (ADDVv8i16v V128:$Rn))>;8282def : Pat<(i32 (vecreduce_add (v2i32 V64:$Rn))),8283 (i32 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub))>;8284def : Pat<(i32 (vecreduce_add (v4i32 V128:$Rn))),8285 (i32 (ADDVv4i32v V128:$Rn))>;8286def : Pat<(i64 (vecreduce_add (v2i64 V128:$Rn))),8287 (i64 (ADDPv2i64p V128:$Rn))>;8288 8289defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;8290// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm8291def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),8292 (ADDPv2i32 V64:$Rn, V64:$Rn)>;8293 8294defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;8295// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm8296def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),8297 (ADDPv2i32 V64:$Rn, V64:$Rn)>;8298 8299defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;8300def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),8301 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;8302 8303defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;8304def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),8305 (SMINPv2i32 V64:$Rn, V64:$Rn)>;8306 8307defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;8308def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),8309 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;8310 8311defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;8312def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),8313 (UMINPv2i32 V64:$Rn, V64:$Rn)>;8314 8315// For vecreduce_{opc} used by GlobalISel, not SDAG at the moment8316// because GlobalISel allows us to specify the return register to be a FPR8317multiclass SIMDAcrossLanesVecReductionIntrinsic<string baseOpc,8318 SDPatternOperator opNode> {8319def : Pat<(i8 (opNode (v8i8 FPR64:$Rn))),8320 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) FPR64:$Rn)>;8321 8322def : Pat<(i8 (opNode (v16i8 FPR128:$Rn))),8323 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) FPR128:$Rn)>;8324 8325def : Pat<(i16 (opNode (v4i16 FPR64:$Rn))),8326 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) FPR64:$Rn)>;8327 8328def : Pat<(i16 (opNode (v8i16 FPR128:$Rn))),8329 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) FPR128:$Rn)>;8330 8331def : Pat<(i32 (opNode (v4i32 V128:$Rn))),8332 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn)>;8333}8334 8335// For v2i32 source type, the pairwise instruction can be used instead8336defm : SIMDAcrossLanesVecReductionIntrinsic<"UMINV", vecreduce_umin>;8337def : Pat<(i32 (vecreduce_umin (v2i32 V64:$Rn))),8338 (i32 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub))>;8339 8340defm : SIMDAcrossLanesVecReductionIntrinsic<"UMAXV", vecreduce_umax>;8341def : Pat<(i32 (vecreduce_umax (v2i32 V64:$Rn))),8342 (i32 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub))>;8343 8344defm : SIMDAcrossLanesVecReductionIntrinsic<"SMINV", vecreduce_smin>;8345def : Pat<(i32 (vecreduce_smin (v2i32 V64:$Rn))),8346 (i32 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub))>;8347 8348defm : SIMDAcrossLanesVecReductionIntrinsic<"SMAXV", vecreduce_smax>;8349def : Pat<(i32 (vecreduce_smax (v2i32 V64:$Rn))),8350 (i32 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub))>;8351 8352// The SADDLV v2i32 gets mapped to SADDLP.8353def : Pat<(v2i64 (AArch64saddlv (v2i32 V64:$Rn))),8354 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (SADDLPv2i32_v1i64 V64:$Rn), dsub))>;8355// The UADDLV v2i32 gets mapped to UADDLP.8356def : Pat<(v2i64 (AArch64uaddlv (v2i32 V64:$Rn))),8357 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (UADDLPv2i32_v1i64 V64:$Rn), dsub))>;8358 8359//------------------------------------------------------------------------------8360// AdvSIMD modified immediate instructions8361//------------------------------------------------------------------------------8362 8363// AdvSIMD BIC8364defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;8365// AdvSIMD ORR8366defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;8367 8368let Predicates = [HasNEON] in {8369def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;8370def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;8371def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;8372def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;8373 8374def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;8375def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;8376def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;8377def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;8378 8379def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;8380def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;8381def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;8382def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;8383 8384def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;8385def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;8386def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;8387def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;8388}8389 8390// AdvSIMD FMOV8391let isReMaterializable = 1, isAsCheapAsAMove = 1 in {8392def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8,8393 "fmov", ".2d",8394 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;8395def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1111, V64, fpimm8,8396 "fmov", ".2s",8397 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;8398def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1111, V128, fpimm8,8399 "fmov", ".4s",8400 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;8401let Predicates = [HasNEON, HasFullFP16] in {8402def FMOVv4f16_ns : SIMDModifiedImmVectorNoShift<0, 0, 1, 0b1111, V64, fpimm8,8403 "fmov", ".4h",8404 [(set (v4f16 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;8405def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8,8406 "fmov", ".8h",8407 [(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;8408} // Predicates = [HasNEON, HasFullFP16]8409}8410 8411// AdvSIMD MOVI8412 8413// EDIT byte mask: scalar8414let isReMaterializable = 1, isAsCheapAsAMove = 1 in8415def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",8416 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;8417// The movi_edit node has the immediate value already encoded, so we use8418// a plain imm0_255 here.8419def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),8420 (MOVID imm0_255:$shift)>;8421 8422// EDIT byte mask: 2d8423 8424// The movi_edit node has the immediate value already encoded, so we use8425// a plain imm0_255 in the pattern8426let isReMaterializable = 1, isAsCheapAsAMove = 1 in8427def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128,8428 simdimmtype10,8429 "movi", ".2d",8430 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;8431 8432let Predicates = [HasNEON] in {8433def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;8434def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;8435def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;8436def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;8437def : Pat<(v2f64 immAllZerosV), (MOVIv2d_ns (i32 0))>;8438def : Pat<(v4f32 immAllZerosV), (MOVIv2d_ns (i32 0))>;8439def : Pat<(v8f16 immAllZerosV), (MOVIv2d_ns (i32 0))>;8440def : Pat<(v8bf16 immAllZerosV), (MOVIv2d_ns (i32 0))>;8441 8442// Prefer NEON instructions when zeroing ZPRs because they are potentially zero-latency.8443let AddedComplexity = 5 in {8444def : Pat<(nxv2i64 (splat_vector (i64 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8445def : Pat<(nxv4i32 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8446def : Pat<(nxv8i16 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8447def : Pat<(nxv16i8 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8448def : Pat<(nxv2f64 (splat_vector (f64 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8449def : Pat<(nxv2f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8450def : Pat<(nxv4f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8451def : Pat<(nxv2f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8452def : Pat<(nxv4f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8453def : Pat<(nxv8f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8454def : Pat<(nxv2bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8455def : Pat<(nxv4bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8456def : Pat<(nxv8bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>;8457}8458 8459def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;8460def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;8461def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;8462def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;8463 8464// Set 64-bit vectors to all 0/1 by extracting from a 128-bit register as the8465// extract is free and this gives better MachineCSE results.8466def : Pat<(v1i64 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>;8467def : Pat<(v2i32 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>;8468def : Pat<(v4i16 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>;8469def : Pat<(v8i8 immAllZerosV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub)>;8470def : Pat<(v1f64 immAllZerosV), (MOVID (i32 0))>;8471def : Pat<(v2f32 immAllZerosV), (MOVID (i32 0))>;8472def : Pat<(v4f16 immAllZerosV), (MOVID (i32 0))>;8473def : Pat<(v4bf16 immAllZerosV), (MOVID (i32 0))>;8474 8475def : Pat<(v1i64 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;8476def : Pat<(v2i32 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;8477def : Pat<(v4i16 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;8478def : Pat<(v8i8 immAllOnesV), (EXTRACT_SUBREG (MOVIv2d_ns (i32 255)), dsub)>;8479}8480 8481// EDIT per word & halfword: 2s, 4h, 4s, & 8h8482let isReMaterializable = 1, isAsCheapAsAMove = 1 in8483defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;8484 8485let Predicates = [HasNEON] in {8486 // Using the MOVI to materialize fp constants.8487 def : Pat<(f32 fpimm32SIMDModImmType4:$in),8488 (EXTRACT_SUBREG (MOVIv2i32 (fpimm32SIMDModImmType4XForm f32:$in),8489 (i32 24)),8490 ssub)>;8491}8492 8493let Predicates = [HasNEON] in {8494def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;8495def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;8496def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;8497def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;8498 8499def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;8500def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;8501def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;8502def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;8503}8504 8505def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),8506 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;8507def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),8508 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;8509def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),8510 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;8511def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),8512 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;8513 8514let isReMaterializable = 1, isAsCheapAsAMove = 1 in {8515// EDIT per word: 2s & 4s with MSL shifter8516def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",8517 [(set (v2i32 V64:$Rd),8518 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;8519def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",8520 [(set (v4i32 V128:$Rd),8521 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;8522 8523// Per byte: 8b & 16b8524def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1110, V64, imm0_255,8525 "movi", ".8b",8526 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;8527 8528def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255,8529 "movi", ".16b",8530 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;8531}8532 8533// AdvSIMD MVNI8534 8535// EDIT per word & halfword: 2s, 4h, 4s, & 8h8536let isReMaterializable = 1, isAsCheapAsAMove = 1 in8537defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;8538 8539let Predicates = [HasNEON] in {8540def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;8541def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;8542def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;8543def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;8544 8545def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;8546def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;8547def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;8548def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;8549}8550 8551def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),8552 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;8553def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),8554 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;8555def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),8556 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;8557def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),8558 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;8559 8560// EDIT per word: 2s & 4s with MSL shifter8561let isReMaterializable = 1, isAsCheapAsAMove = 1 in {8562def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",8563 [(set (v2i32 V64:$Rd),8564 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;8565def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",8566 [(set (v4i32 V128:$Rd),8567 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;8568}8569 8570// SABA patterns for add(x, abs(y)) -> saba(x, y, 0)8571def : Pat<(v8i8 (add V64:$Vn, (abs V64:$Vm))),8572 (SABAv8i8 V64:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;8573def : Pat<(v4i16 (add V64:$Vn, (abs V64:$Vm))),8574 (SABAv4i16 V64:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;8575def : Pat<(v2i32 (add V64:$Vn, (abs V64:$Vm))),8576 (SABAv2i32 V64:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;8577def : Pat<(v16i8 (add V128:$Vn, (abs V128:$Vm))),8578 (SABAv16i8 V128:$Vn, V128:$Vm, (MOVIv2d_ns (i32 0)))>;8579def : Pat<(v8i16 (add V128:$Vn, (abs V128:$Vm))),8580 (SABAv8i16 V128:$Vn, V128:$Vm, (MOVIv2d_ns (i32 0)))>;8581def : Pat<(v4i32 (add V128:$Vn, (abs V128:$Vm))),8582 (SABAv4i32 V128:$Vn, V128:$Vm, (MOVIv2d_ns (i32 0)))>;8583 8584// SABAL patterns for add(x, zext(abs(y))) -> sabal(x, y, 0)8585def : Pat<(v8i16 (add V128:$Vn, (zext (abs (v8i8 V64:$Vm))))),8586 (SABALv8i8_v8i16 V128:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;8587def : Pat<(v4i32 (add V128:$Vn, (zext (abs (v4i16 V64:$Vm))))),8588 (SABALv4i16_v4i32 V128:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;8589def : Pat<(v2i64 (add V128:$Vn, (zext (abs (v2i32 V64:$Vm))))),8590 (SABALv2i32_v2i64 V128:$Vn, V64:$Vm, (EXTRACT_SUBREG (MOVIv2d_ns (i32 0)), dsub))>;8591 8592 8593//----------------------------------------------------------------------------8594// AdvSIMD indexed element8595//----------------------------------------------------------------------------8596 8597let hasSideEffects = 0 in {8598 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">;8599 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">;8600}8601 8602// NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the8603// instruction expects the addend first, while the intrinsic expects it last.8604 8605// On the other hand, there are quite a few valid combinatorial options due to8606// the commutativity of multiplication and the fact that (-x) * y = x * (-y).8607defm : SIMDFPIndexedTiedPatterns<"FMLA",8608 TriOpFrag<(any_fma node:$RHS, node:$MHS, node:$LHS)>>;8609defm : SIMDFPIndexedTiedPatterns<"FMLA",8610 TriOpFrag<(any_fma node:$MHS, node:$RHS, node:$LHS)>>;8611 8612defm : SIMDFPIndexedTiedPatterns<"FMLS",8613 TriOpFrag<(any_fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;8614defm : SIMDFPIndexedTiedPatterns<"FMLS",8615 TriOpFrag<(any_fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;8616defm : SIMDFPIndexedTiedPatterns<"FMLS",8617 TriOpFrag<(any_fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;8618defm : SIMDFPIndexedTiedPatterns<"FMLS",8619 TriOpFrag<(any_fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;8620 8621multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {8622 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit8623 // and DUP scalar.8624 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),8625 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),8626 VectorIndexS:$idx))),8627 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;8628 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),8629 (v2f32 (AArch64duplane328630 (v4f32 (insert_subvector undef,8631 (v2f32 (fneg V64:$Rm)),8632 (i64 0))),8633 VectorIndexS:$idx)))),8634 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,8635 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),8636 VectorIndexS:$idx)>;8637 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),8638 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),8639 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,8640 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;8641 8642 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit8643 // and DUP scalar.8644 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),8645 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),8646 VectorIndexS:$idx))),8647 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,8648 VectorIndexS:$idx)>;8649 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),8650 (v4f32 (AArch64duplane328651 (v4f32 (insert_subvector undef,8652 (v2f32 (fneg V64:$Rm)),8653 (i64 0))),8654 VectorIndexS:$idx)))),8655 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,8656 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),8657 VectorIndexS:$idx)>;8658 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),8659 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),8660 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,8661 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;8662 8663 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar8664 // (DUPLANE from 64-bit would be trivial).8665 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),8666 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),8667 VectorIndexD:$idx))),8668 (FMLSv2i64_indexed8669 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;8670 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),8671 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),8672 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,8673 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;8674 8675 // 2 variants for 32-bit scalar version: extract from .2s or from .4s8676 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),8677 (vector_extract (v4f32 (fneg V128:$Rm)),8678 VectorIndexS:$idx))),8679 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,8680 V128:$Rm, VectorIndexS:$idx)>;8681 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),8682 (vector_extract (v4f32 (insert_subvector undef,8683 (v2f32 (fneg V64:$Rm)),8684 (i64 0))),8685 VectorIndexS:$idx))),8686 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,8687 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;8688 8689 // 1 variant for 64-bit scalar version: extract from .1d or from .2d8690 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),8691 (vector_extract (v2f64 (fneg V128:$Rm)),8692 VectorIndexS:$idx))),8693 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,8694 V128:$Rm, VectorIndexS:$idx)>;8695}8696 8697defm : FMLSIndexedAfterNegPatterns<8698 TriOpFrag<(any_fma node:$RHS, node:$MHS, node:$LHS)> >;8699defm : FMLSIndexedAfterNegPatterns<8700 TriOpFrag<(any_fma node:$MHS, node:$RHS, node:$LHS)> >;8701 8702defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;8703defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", any_fmul>;8704 8705def : Pat<(v2f32 (any_fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),8706 (FMULv2i32_indexed V64:$Rn,8707 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),8708 (i64 0))>;8709def : Pat<(v4f32 (any_fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),8710 (FMULv4i32_indexed V128:$Rn,8711 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),8712 (i64 0))>;8713def : Pat<(v2f64 (any_fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),8714 (FMULv2i64_indexed V128:$Rn,8715 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),8716 (i64 0))>;8717 8718defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;8719defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;8720 8721defm SQDMULH : SIMDIndexedHSPatterns<int_aarch64_neon_sqdmulh_lane,8722 int_aarch64_neon_sqdmulh_laneq>;8723defm SQRDMULH : SIMDIndexedHSPatterns<int_aarch64_neon_sqrdmulh_lane,8724 int_aarch64_neon_sqrdmulh_laneq>;8725 8726// Generated by MachineCombine8727defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla", null_frag>;8728defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls", null_frag>;8729 8730defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;8731defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",8732 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>>;8733defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",8734 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>>;8735defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull", AArch64smull>;8736defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal", saddsat,8737 int_aarch64_neon_sqadd>;8738defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl", ssubsat,8739 int_aarch64_neon_sqsub>;8740defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",8741 int_aarch64_neon_sqrdmlah>;8742defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",8743 int_aarch64_neon_sqrdmlsh>;8744defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;8745defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",8746 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>>;8747defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",8748 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>>;8749defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull", AArch64umull>;8750 8751// A scalar sqdmull with the second operand being a vector lane can be8752// handled directly with the indexed instruction encoding.8753def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),8754 (vector_extract (v4i32 V128:$Vm),8755 VectorIndexS:$idx)),8756 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;8757 8758//----------------------------------------------------------------------------8759// AdvSIMD scalar shift instructions8760//----------------------------------------------------------------------------8761defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">;8762defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">;8763defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">;8764defm UCVTF : SIMDFPScalarRShift<1, 0b11100, "ucvtf">;8765// Codegen patterns for the above. We don't put these directly on the8766// instructions because TableGen's type inference can't handle the truth.8767// Having the same base pattern for fp <--> int totally freaks it out.8768def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),8769 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;8770def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),8771 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;8772def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),8773 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;8774def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),8775 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;8776def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),8777 vecshiftR64:$imm)),8778 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;8779def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),8780 vecshiftR64:$imm)),8781 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;8782def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),8783 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;8784def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),8785 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;8786def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),8787 vecshiftR64:$imm)),8788 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;8789def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),8790 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;8791def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),8792 vecshiftR64:$imm)),8793 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;8794def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),8795 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;8796 8797// Patterns for FP16 Intrinsics - requires reg copy to/from as i16s not supported.8798 8799def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), vecshiftR16:$imm)),8800 (SCVTFh (f16 (EXTRACT_SUBREG FPR32:$Rn, hsub)), vecshiftR16:$imm)>;8801def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),8802 (SCVTFh (f16 (EXTRACT_SUBREG FPR32:$Rn, hsub)), vecshiftR16:$imm)>;8803def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),8804 (SCVTFh (f16 (EXTRACT_SUBREG FPR64:$Rn, hsub)), vecshiftR16:$imm)>;8805def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp8806 (and FPR32:$Rn, (i32 65535)),8807 vecshiftR16:$imm)),8808 (UCVTFh (f16 (EXTRACT_SUBREG FPR32:$Rn, hsub)), vecshiftR16:$imm)>;8809def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)),8810 (UCVTFh (f16 (EXTRACT_SUBREG FPR32:$Rn, hsub)), vecshiftR16:$imm)>;8811def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),8812 (UCVTFh (f16 (EXTRACT_SUBREG FPR64:$Rn, hsub)), vecshiftR16:$imm)>;8813def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR32:$imm)),8814 (i32 (INSERT_SUBREG8815 (i32 (IMPLICIT_DEF)),8816 (FCVTZSh FPR16:$Rn, vecshiftR32:$imm),8817 hsub))>;8818def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR64:$imm)),8819 (i64 (INSERT_SUBREG8820 (i64 (IMPLICIT_DEF)),8821 (FCVTZSh FPR16:$Rn, vecshiftR64:$imm),8822 hsub))>;8823def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR32:$imm)),8824 (i32 (INSERT_SUBREG8825 (i32 (IMPLICIT_DEF)),8826 (FCVTZUh FPR16:$Rn, vecshiftR32:$imm),8827 hsub))>;8828def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR64:$imm)),8829 (i64 (INSERT_SUBREG8830 (i64 (IMPLICIT_DEF)),8831 (FCVTZUh FPR16:$Rn, vecshiftR64:$imm),8832 hsub))>;8833def : Pat<(i32 (int_aarch64_neon_facge (f16 FPR16:$Rn), (f16 FPR16:$Rm))),8834 (i32 (INSERT_SUBREG8835 (i32 (IMPLICIT_DEF)),8836 (FACGE16 FPR16:$Rn, FPR16:$Rm),8837 hsub))>;8838def : Pat<(i32 (int_aarch64_neon_facgt (f16 FPR16:$Rn), (f16 FPR16:$Rm))),8839 (i32 (INSERT_SUBREG8840 (i32 (IMPLICIT_DEF)),8841 (FACGT16 FPR16:$Rn, FPR16:$Rm),8842 hsub))>;8843 8844defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;8845defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli", AArch64vsli>;8846defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",8847 int_aarch64_neon_sqrshrn>;8848defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",8849 int_aarch64_neon_sqrshrun>;8850defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;8851defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;8852defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",8853 int_aarch64_neon_sqshrn>;8854defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",8855 int_aarch64_neon_sqshrun>;8856defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri", AArch64vsri>;8857defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;8858defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",8859 TriOpFrag<(add node:$LHS,8860 (AArch64srshri node:$MHS, node:$RHS))>>;8861defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;8862defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",8863 TriOpFrag<(add_and_or_is_add node:$LHS,8864 (AArch64vashr node:$MHS, node:$RHS))>>;8865defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",8866 int_aarch64_neon_uqrshrn>;8867defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;8868defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",8869 int_aarch64_neon_uqshrn>;8870defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;8871defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",8872 TriOpFrag<(add node:$LHS,8873 (AArch64urshri node:$MHS, node:$RHS))>>;8874defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;8875defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",8876 TriOpFrag<(add_and_or_is_add node:$LHS,8877 (AArch64vlshr node:$MHS, node:$RHS))>>;8878 8879//----------------------------------------------------------------------------8880// AdvSIMD vector shift instructions8881//----------------------------------------------------------------------------8882defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;8883defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;8884defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf",8885 int_aarch64_neon_vcvtfxs2fp>;8886defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn", AArch64rshrn>;8887defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;8888 8889let Predicates = [HasNEON] in {8890def : Pat<(v2f32 (sint_to_fp (v2i32 (AArch64vashr_exact v2i32:$Vn, i32:$shift)))),8891 (SCVTFv2i32_shift $Vn, vecshiftR32:$shift)>;8892 8893def : Pat<(v4f32 (sint_to_fp (v4i32 (AArch64vashr_exact v4i32:$Vn, i32:$shift)))),8894 (SCVTFv4i32_shift $Vn, vecshiftR32:$shift)>;8895 8896def : Pat<(v2f64 (sint_to_fp (v2i64 (AArch64vashr_exact v2i64:$Vn, i32:$shift)))),8897 (SCVTFv2i64_shift $Vn, vecshiftR64:$shift)>;8898}8899 8900let Predicates = [HasNEON, HasFullFP16] in {8901def : Pat<(v4f16 (sint_to_fp (v4i16 (AArch64vashr_exact v4i16:$Vn, i32:$shift)))),8902 (SCVTFv4i16_shift $Vn, vecshiftR16:$shift)>;8903 8904def : Pat<(v8f16 (sint_to_fp (v8i16 (AArch64vashr_exact v8i16:$Vn, i32:$shift)))),8905 (SCVTFv8i16_shift $Vn, vecshiftR16:$shift)>;8906}8907 8908// X << 1 ==> X + X8909class SHLToADDPat<ValueType ty, RegisterClass regtype>8910 : Pat<(ty (AArch64vshl (ty regtype:$Rn), (i32 1))),8911 (!cast<Instruction>("ADD"#ty) regtype:$Rn, regtype:$Rn)>;8912 8913def : SHLToADDPat<v16i8, FPR128>;8914def : SHLToADDPat<v8i16, FPR128>;8915def : SHLToADDPat<v4i32, FPR128>;8916def : SHLToADDPat<v2i64, FPR128>;8917def : SHLToADDPat<v8i8, FPR64>;8918def : SHLToADDPat<v4i16, FPR64>;8919def : SHLToADDPat<v2i32, FPR64>;8920 8921defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",8922 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;8923defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", AArch64vsli>;8924defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",8925 BinOpFrag<(truncssat_s (AArch64srshri node:$LHS, node:$RHS))>>;8926defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",8927 BinOpFrag<(truncssat_u (AArch64srshri node:$LHS, node:$RHS))>>;8928defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;8929defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;8930defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",8931 BinOpFrag<(truncssat_s (AArch64vashr node:$LHS, node:$RHS))>>;8932defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",8933 BinOpFrag<(truncssat_u (AArch64vashr node:$LHS, node:$RHS))>>;8934defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", AArch64vsri>;8935defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;8936defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",8937 TriOpFrag<(add node:$LHS,8938 (AArch64srshri node:$MHS, node:$RHS))> >;8939defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",8940 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;8941 8942defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;8943defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",8944 TriOpFrag<(add_and_or_is_add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;8945defm UCVTF : SIMDVectorRShiftToFP<1, 0b11100, "ucvtf",8946 int_aarch64_neon_vcvtfxu2fp>;8947defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",8948 BinOpFrag<(truncusat_u (AArch64urshri node:$LHS, node:$RHS))>>;8949defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;8950defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",8951 BinOpFrag<(truncusat_u (AArch64vlshr node:$LHS, node:$RHS))>>;8952defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;8953defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",8954 TriOpFrag<(add node:$LHS,8955 (AArch64urshri node:$MHS, node:$RHS))> >;8956defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",8957 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;8958defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;8959defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",8960 TriOpFrag<(add_and_or_is_add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;8961 8962def VImm0080: PatLeaf<(AArch64movi_shift (i32 128), (i32 0))>;8963def VImm00008000: PatLeaf<(AArch64movi_shift (i32 128), (i32 8))>;8964def VImm0000000080000000: PatLeaf<(AArch64NvCast (v2f64 (fneg (AArch64NvCast (v4i32 (AArch64movi_shift (i32 128), (i32 24)))))))>;8965 8966// RADDHN patterns for when RSHRN shifts by half the size of the vector element8967def : Pat<(v8i8 (trunc (AArch64vlshr (add (v8i16 V128:$Vn), VImm0080), (i32 8)))),8968 (RADDHNv8i16_v8i8 V128:$Vn, (v8i16 (MOVIv2d_ns (i32 0))))>;8969def : Pat<(v4i16 (trunc (AArch64vlshr (add (v4i32 V128:$Vn), VImm00008000), (i32 16)))),8970 (RADDHNv4i32_v4i16 V128:$Vn, (v4i32 (MOVIv2d_ns (i32 0))))>;8971let AddedComplexity = 5 in8972def : Pat<(v2i32 (trunc (AArch64vlshr (add (v2i64 V128:$Vn), VImm0000000080000000), (i32 32)))),8973 (RADDHNv2i64_v2i32 V128:$Vn, (v2i64 (MOVIv2d_ns (i32 0))))>;8974def : Pat<(v8i8 (int_aarch64_neon_rshrn (v8i16 V128:$Vn), (i32 8))),8975 (RADDHNv8i16_v8i8 V128:$Vn, (v8i16 (MOVIv2d_ns (i32 0))))>;8976def : Pat<(v4i16 (int_aarch64_neon_rshrn (v4i32 V128:$Vn), (i32 16))),8977 (RADDHNv4i32_v4i16 V128:$Vn, (v4i32 (MOVIv2d_ns (i32 0))))>;8978def : Pat<(v2i32 (int_aarch64_neon_rshrn (v2i64 V128:$Vn), (i32 32))),8979 (RADDHNv2i64_v2i32 V128:$Vn, (v2i64 (MOVIv2d_ns (i32 0))))>;8980 8981// RADDHN2 patterns for when RSHRN shifts by half the size of the vector element8982def : Pat<(v16i8 (concat_vectors8983 (v8i8 V64:$Vd),8984 (v8i8 (trunc (AArch64vlshr (add (v8i16 V128:$Vn), VImm0080), (i32 8)))))),8985 (RADDHNv8i16_v16i88986 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn,8987 (v8i16 (MOVIv2d_ns (i32 0))))>;8988def : Pat<(v8i16 (concat_vectors8989 (v4i16 V64:$Vd),8990 (v4i16 (trunc (AArch64vlshr (add (v4i32 V128:$Vn), VImm00008000), (i32 16)))))),8991 (RADDHNv4i32_v8i168992 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn,8993 (v4i32 (MOVIv2d_ns (i32 0))))>;8994let AddedComplexity = 5 in8995def : Pat<(v4i32 (concat_vectors8996 (v2i32 V64:$Vd),8997 (v2i32 (trunc (AArch64vlshr (add (v2i64 V128:$Vn), VImm0000000080000000), (i32 32)))))),8998 (RADDHNv2i64_v4i328999 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn,9000 (v2i64 (MOVIv2d_ns (i32 0))))>;9001def : Pat<(v16i8 (concat_vectors9002 (v8i8 V64:$Vd),9003 (v8i8 (int_aarch64_neon_rshrn (v8i16 V128:$Vn), (i32 8))))),9004 (RADDHNv8i16_v16i89005 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn,9006 (v8i16 (MOVIv2d_ns (i32 0))))>;9007def : Pat<(v8i16 (concat_vectors9008 (v4i16 V64:$Vd),9009 (v4i16 (int_aarch64_neon_rshrn (v4i32 V128:$Vn), (i32 16))))),9010 (RADDHNv4i32_v8i169011 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn,9012 (v4i32 (MOVIv2d_ns (i32 0))))>;9013def : Pat<(v4i32 (concat_vectors9014 (v2i32 V64:$Vd),9015 (v2i32 (int_aarch64_neon_rshrn (v2i64 V128:$Vn), (i32 32))))),9016 (RADDHNv2i64_v4i329017 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn,9018 (v2i64 (MOVIv2d_ns (i32 0))))>;9019 9020// SHRN patterns for when a logical right shift was used instead of arithmetic9021// (the immediate guarantees no sign bits actually end up in the result so it9022// doesn't matter).9023def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),9024 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;9025def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),9026 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;9027def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),9028 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;9029 9030def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),9031 (trunc (AArch64vlshr (v8i16 V128:$Rn),9032 vecshiftR16Narrow:$imm)))),9033 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),9034 V128:$Rn, vecshiftR16Narrow:$imm)>;9035def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),9036 (trunc (AArch64vlshr (v4i32 V128:$Rn),9037 vecshiftR32Narrow:$imm)))),9038 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),9039 V128:$Rn, vecshiftR32Narrow:$imm)>;9040def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),9041 (trunc (AArch64vlshr (v2i64 V128:$Rn),9042 vecshiftR64Narrow:$imm)))),9043 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),9044 V128:$Rn, vecshiftR32Narrow:$imm)>;9045 9046def : Pat<(shl (v8i16 (zext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),9047 (USHLLv8i8_shift V64:$Rm, (i32 imm32_0_7:$size))>;9048def : Pat<(shl (v4i32 (zext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),9049 (USHLLv4i16_shift V64:$Rm, (i32 imm32_0_15:$size))>;9050def : Pat<(shl (v2i64 (zext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),9051 (USHLLv2i32_shift V64:$Rm, (trunc_imm imm0_31:$size))>;9052 9053def : Pat<(shl (v8i16 (sext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),9054 (SSHLLv8i8_shift V64:$Rm, (i32 imm32_0_7:$size))>;9055def : Pat<(shl (v4i32 (sext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),9056 (SSHLLv4i16_shift V64:$Rm, (i32 imm32_0_15:$size))>;9057def : Pat<(shl (v2i64 (sext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),9058 (SSHLLv2i32_shift V64:$Rm, (trunc_imm imm0_31:$size))>;9059 9060// Vector sign and zero extensions are implemented with SSHLL and USSHLL.9061// Anyexts are implemented as zexts.9062def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;9063def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;9064def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;9065def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;9066def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;9067def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;9068def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;9069def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;9070def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;9071// Also match an extend from the upper half of a 128 bit source register.9072def : Pat<(v8i16 (anyext (v8i8 (extract_high_v16i8 (v16i8 V128:$Rn)) ))),9073 (USHLLv16i8_shift V128:$Rn, (i32 0))>;9074def : Pat<(v8i16 (zext (v8i8 (extract_high_v16i8 (v16i8 V128:$Rn)) ))),9075 (USHLLv16i8_shift V128:$Rn, (i32 0))>;9076def : Pat<(v8i16 (sext (v8i8 (extract_high_v16i8 (v16i8 V128:$Rn)) ))),9077 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;9078def : Pat<(v4i32 (anyext (v4i16 (extract_high_v8i16 (v8i16 V128:$Rn)) ))),9079 (USHLLv8i16_shift V128:$Rn, (i32 0))>;9080def : Pat<(v4i32 (zext (v4i16 (extract_high_v8i16 (v8i16 V128:$Rn)) ))),9081 (USHLLv8i16_shift V128:$Rn, (i32 0))>;9082def : Pat<(v4i32 (sext (v4i16 (extract_high_v8i16 (v8i16 V128:$Rn)) ))),9083 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;9084def : Pat<(v2i64 (anyext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))),9085 (USHLLv4i32_shift V128:$Rn, (i32 0))>;9086def : Pat<(v2i64 (zext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))),9087 (USHLLv4i32_shift V128:$Rn, (i32 0))>;9088def : Pat<(v2i64 (sext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))),9089 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;9090 9091let Predicates = [HasNEON] in {9092// Vector shift sxtl aliases9093def : InstAlias<"sxtl.8h $dst, $src1",9094 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;9095def : InstAlias<"sxtl $dst.8h, $src1.8b",9096 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;9097def : InstAlias<"sxtl.4s $dst, $src1",9098 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;9099def : InstAlias<"sxtl $dst.4s, $src1.4h",9100 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;9101def : InstAlias<"sxtl.2d $dst, $src1",9102 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;9103def : InstAlias<"sxtl $dst.2d, $src1.2s",9104 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;9105 9106// Vector shift sxtl2 aliases9107def : InstAlias<"sxtl2.8h $dst, $src1",9108 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;9109def : InstAlias<"sxtl2 $dst.8h, $src1.16b",9110 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;9111def : InstAlias<"sxtl2.4s $dst, $src1",9112 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;9113def : InstAlias<"sxtl2 $dst.4s, $src1.8h",9114 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;9115def : InstAlias<"sxtl2.2d $dst, $src1",9116 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;9117def : InstAlias<"sxtl2 $dst.2d, $src1.4s",9118 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;9119 9120// Vector shift uxtl aliases9121def : InstAlias<"uxtl.8h $dst, $src1",9122 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;9123def : InstAlias<"uxtl $dst.8h, $src1.8b",9124 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;9125def : InstAlias<"uxtl.4s $dst, $src1",9126 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;9127def : InstAlias<"uxtl $dst.4s, $src1.4h",9128 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;9129def : InstAlias<"uxtl.2d $dst, $src1",9130 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;9131def : InstAlias<"uxtl $dst.2d, $src1.2s",9132 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;9133 9134// Vector shift uxtl2 aliases9135def : InstAlias<"uxtl2.8h $dst, $src1",9136 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;9137def : InstAlias<"uxtl2 $dst.8h, $src1.16b",9138 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;9139def : InstAlias<"uxtl2.4s $dst, $src1",9140 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;9141def : InstAlias<"uxtl2 $dst.4s, $src1.8h",9142 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;9143def : InstAlias<"uxtl2.2d $dst, $src1",9144 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;9145def : InstAlias<"uxtl2 $dst.2d, $src1.4s",9146 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;9147}9148 9149// fpextend from bf16 to f32 is just a shift left by 169150let Predicates = [HasNEON] in {9151def : Pat<(f32 (any_fpextend (bf16 FPR16:$Rn))),9152 (f32 (EXTRACT_SUBREG9153 (v4i32 (SHLLv4i16 (v4i16 (SUBREG_TO_REG (i64 0), (bf16 FPR16:$Rn), hsub)))),9154 ssub))>;9155def : Pat<(v4f32 (any_fpextend (v4bf16 V64:$Rn))),9156 (SHLLv4i16 V64:$Rn)>;9157def : Pat<(v4f32 (any_fpextend (extract_high_v8bf16 (v8bf16 V128:$Rn)))),9158 (SHLLv8i16 V128:$Rn)>;9159}9160// Fallback pattern for when we don't have NEON9161def : Pat<(f32 (any_fpextend (bf16 FPR16:$Rn))),9162 (f32 (COPY_TO_REGCLASS9163 (i32 (UBFMWri (COPY_TO_REGCLASS9164 (f32 (SUBREG_TO_REG (i32 0), (bf16 FPR16:$Rn), hsub)),9165 GPR32),9166 (i64 16), (i64 15))),9167 FPR32))>;9168 9169def abs_f16 :9170 OutPatFrag<(ops node:$Rn),9171 (EXTRACT_SUBREG (f32 (COPY_TO_REGCLASS9172 (i32 (ANDWri9173 (i32 (COPY_TO_REGCLASS (INSERT_SUBREG (f32 (IMPLICIT_DEF)),9174 node:$Rn, hsub), GPR32)),9175 (i32 (logical_imm32_XFORM(i32 0x7fff))))),9176 FPR32)), hsub)>;9177 9178def : Pat<(f16 (fabs (f16 FPR16:$Rn))), (f16 (abs_f16 (f16 FPR16:$Rn)))>;9179def : Pat<(bf16 (fabs (bf16 FPR16:$Rn))), (bf16 (abs_f16 (bf16 FPR16:$Rn)))>;9180 9181def neg_f16 :9182 OutPatFrag<(ops node:$Rn),9183 (EXTRACT_SUBREG (f32 (COPY_TO_REGCLASS9184 (i32 (EORWri9185 (i32 (COPY_TO_REGCLASS (INSERT_SUBREG (f32 (IMPLICIT_DEF)),9186 node:$Rn, hsub), GPR32)),9187 (i32 (logical_imm32_XFORM(i32 0x8000))))),9188 FPR32)), hsub)>;9189 9190def : Pat<(f16 (fneg (f16 FPR16:$Rn))), (f16 (neg_f16 (f16 FPR16:$Rn)))>;9191def : Pat<(bf16 (fneg (bf16 FPR16:$Rn))), (bf16 (neg_f16 (bf16 FPR16:$Rn)))>;9192 9193let Predicates = [HasNEON] in {9194def : Pat<(v4f16 (fabs (v4f16 V64:$Rn))), (v4f16 (BICv4i16 (v4f16 V64:$Rn), (i32 128), (i32 8)))>;9195def : Pat<(v4bf16 (fabs (v4bf16 V64:$Rn))), (v4bf16 (BICv4i16 (v4bf16 V64:$Rn), (i32 128), (i32 8)))>;9196def : Pat<(v8f16 (fabs (v8f16 V128:$Rn))), (v8f16 (BICv8i16 (v8f16 V128:$Rn), (i32 128), (i32 8)))>;9197def : Pat<(v8bf16 (fabs (v8bf16 V128:$Rn))), (v8bf16 (BICv8i16 (v8bf16 V128:$Rn), (i32 128), (i32 8)))>;9198 9199def : Pat<(v4f16 (fneg (v4f16 V64:$Rn))), (v4f16 (EORv8i8 (v4f16 V64:$Rn), (MOVIv4i16 (i32 128), (i32 8))))>;9200def : Pat<(v4bf16 (fneg (v4bf16 V64:$Rn))), (v4bf16 (EORv8i8 (v4bf16 V64:$Rn), (v4i16 (MOVIv4i16 (i32 0x80), (i32 8)))))>;9201def : Pat<(v8f16 (fneg (v8f16 V128:$Rn))), (v8f16 (EORv16i8 (v8f16 V128:$Rn), (MOVIv8i16 (i32 128), (i32 8))))>;9202def : Pat<(v8bf16 (fneg (v8bf16 V128:$Rn))), (v8bf16 (EORv16i8 (v8bf16 V128:$Rn), (v8i16 (MOVIv8i16 (i32 0x80), (i32 8)))))>;9203}9204 9205// If an integer is about to be converted to a floating point value,9206// just load it on the floating point unit.9207// These patterns are more complex because floating point loads do not9208// support sign extension.9209// The sign extension has to be explicitly added and is only supported for9210// one step: byte-to-half, half-to-word, word-to-doubleword.9211// SCVTF GPR -> FPR is 9 cycles.9212// SCVTF FPR -> FPR is 4 cyclces.9213// (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.9214// Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR9215// and still being faster.9216// However, this is not good for code size.9217// 8-bits -> float. 2 sizes step-up.9218class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>9219 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),9220 (SCVTFv1i32 (f32 (EXTRACT_SUBREG9221 (SSHLLv4i16_shift9222 (f649223 (EXTRACT_SUBREG9224 (SSHLLv8i8_shift9225 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),9226 INST,9227 bsub),9228 0),9229 dsub)),9230 0),9231 ssub)))>,9232 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32, HasNEON]>;9233 9234def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),9235 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;9236def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),9237 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;9238def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),9239 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;9240def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),9241 (LDURBi GPR64sp:$Rn, simm9:$offset)>;9242 9243// 16-bits -> float. 1 size step-up.9244class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>9245 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),9246 (SCVTFv1i32 (f32 (EXTRACT_SUBREG9247 (SSHLLv4i16_shift9248 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),9249 INST,9250 hsub),9251 0),9252 ssub)))>,9253 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32, HasNEON]>;9254 9255def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),9256 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;9257def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),9258 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;9259def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),9260 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;9261def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),9262 (LDURHi GPR64sp:$Rn, simm9:$offset)>;9263 9264// 32-bits to 32-bits are handled in target specific dag combine:9265// performIntToFpCombine.9266// 64-bits integer to 32-bits floating point, not possible with9267// SCVTF on floating point registers (both source and destination9268// must have the same size).9269 9270// Here are the patterns for 8, 16, 32, and 64-bits to double.9271// 8-bits -> double. 3 size step-up: give up.9272// 16-bits -> double. 2 size step.9273class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>9274 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),9275 (SCVTFv1i64 (f64 (EXTRACT_SUBREG9276 (SSHLLv2i32_shift9277 (f649278 (EXTRACT_SUBREG9279 (SSHLLv4i16_shift9280 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),9281 INST,9282 hsub),9283 0),9284 dsub)),9285 0),9286 dsub)))>,9287 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32, HasNEON]>;9288 9289def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),9290 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;9291def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),9292 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;9293def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),9294 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;9295def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),9296 (LDURHi GPR64sp:$Rn, simm9:$offset)>;9297// 32-bits -> double. 1 size step-up.9298class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>9299 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),9300 (SCVTFv1i64 (f64 (EXTRACT_SUBREG9301 (SSHLLv2i32_shift9302 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),9303 INST,9304 ssub),9305 0),9306 dsub)))>,9307 Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32, HasNEON]>;9308 9309def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),9310 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;9311def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),9312 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;9313def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),9314 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;9315def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),9316 (LDURSi GPR64sp:$Rn, simm9:$offset)>;9317 9318// 64-bits -> double are handled in target specific dag combine:9319// performIntToFpCombine.9320 9321 9322//----------------------------------------------------------------------------9323// AdvSIMD Load-Store Structure9324//----------------------------------------------------------------------------9325defm LD1 : SIMDLd1Multiple<"ld1">;9326defm LD2 : SIMDLd2Multiple<"ld2">;9327defm LD3 : SIMDLd3Multiple<"ld3">;9328defm LD4 : SIMDLd4Multiple<"ld4">;9329 9330defm ST1 : SIMDSt1Multiple<"st1">;9331defm ST2 : SIMDSt2Multiple<"st2">;9332defm ST3 : SIMDSt3Multiple<"st3">;9333defm ST4 : SIMDSt4Multiple<"st4">;9334 9335class Ld1Pat<ValueType ty, Instruction INST>9336 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;9337 9338def : Ld1Pat<v16i8, LD1Onev16b>;9339def : Ld1Pat<v8i16, LD1Onev8h>;9340def : Ld1Pat<v4i32, LD1Onev4s>;9341def : Ld1Pat<v2i64, LD1Onev2d>;9342def : Ld1Pat<v8i8, LD1Onev8b>;9343def : Ld1Pat<v4i16, LD1Onev4h>;9344def : Ld1Pat<v2i32, LD1Onev2s>;9345def : Ld1Pat<v1i64, LD1Onev1d>;9346 9347class St1Pat<ValueType ty, Instruction INST>9348 : Pat<(store ty:$Vt, GPR64sp:$Rn),9349 (INST ty:$Vt, GPR64sp:$Rn)>;9350 9351def : St1Pat<v16i8, ST1Onev16b>;9352def : St1Pat<v8i16, ST1Onev8h>;9353def : St1Pat<v4i32, ST1Onev4s>;9354def : St1Pat<v2i64, ST1Onev2d>;9355def : St1Pat<v8i8, ST1Onev8b>;9356def : St1Pat<v4i16, ST1Onev4h>;9357def : St1Pat<v2i32, ST1Onev2s>;9358def : St1Pat<v1i64, ST1Onev1d>;9359 9360class St1PostPat<ValueType ty, Instruction INST, int off>9361 : Pat<(post_store ty:$Vt, GPR64sp:$Rn, (i64 off)),9362 (INST ty:$Vt, GPR64sp:$Rn, XZR)>;9363 9364let Predicates = [IsBE] in {9365 def : St1PostPat<v16i8, ST1Onev16b_POST, 16>;9366 def : St1PostPat<v8i16, ST1Onev8h_POST, 16>;9367 def : St1PostPat<v4i32, ST1Onev4s_POST, 16>;9368 def : St1PostPat<v2i64, ST1Onev2d_POST, 16>;9369 def : St1PostPat<v8i8, ST1Onev8b_POST, 8>;9370 def : St1PostPat<v4i16, ST1Onev4h_POST, 8>;9371 def : St1PostPat<v2i32, ST1Onev2s_POST, 8>;9372 def : St1PostPat<v1i64, ST1Onev1d_POST, 8>;9373}9374 9375//---9376// Single-element9377//---9378 9379defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;9380defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;9381defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;9382defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;9383let mayLoad = 1, hasSideEffects = 0 in {9384defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;9385defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;9386defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;9387defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;9388defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;9389defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;9390defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;9391defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;9392defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;9393defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;9394defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;9395defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;9396defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;9397defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;9398defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;9399defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;9400}9401 9402def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),9403 (LD1Rv8b GPR64sp:$Rn)>;9404def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),9405 (LD1Rv16b GPR64sp:$Rn)>;9406def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),9407 (LD1Rv4h GPR64sp:$Rn)>;9408def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),9409 (LD1Rv8h GPR64sp:$Rn)>;9410def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),9411 (LD1Rv2s GPR64sp:$Rn)>;9412def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),9413 (LD1Rv4s GPR64sp:$Rn)>;9414def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),9415 (LD1Rv2d GPR64sp:$Rn)>;9416def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),9417 (LD1Rv1d GPR64sp:$Rn)>;9418 9419def : Pat<(v8i8 (AArch64duplane8 (v16i8 (insert_subvector undef, (v8i8 (load GPR64sp:$Rn)), (i64 0))), (i64 0))),9420 (LD1Rv8b GPR64sp:$Rn)>;9421def : Pat<(v16i8 (AArch64duplane8 (v16i8 (load GPR64sp:$Rn)), (i64 0))),9422 (LD1Rv16b GPR64sp:$Rn)>;9423def : Pat<(v4i16 (AArch64duplane16 (v8i16 (insert_subvector undef, (v4i16 (load GPR64sp:$Rn)), (i64 0))), (i64 0))),9424 (LD1Rv4h GPR64sp:$Rn)>;9425def : Pat<(v8i16 (AArch64duplane16 (v8i16 (load GPR64sp:$Rn)), (i64 0))),9426 (LD1Rv8h GPR64sp:$Rn)>;9427def : Pat<(v2i32 (AArch64duplane32 (v4i32 (insert_subvector undef, (v2i32 (load GPR64sp:$Rn)), (i64 0))), (i64 0))),9428 (LD1Rv2s GPR64sp:$Rn)>;9429def : Pat<(v4i32 (AArch64duplane32 (v4i32 (load GPR64sp:$Rn)), (i64 0))),9430 (LD1Rv4s GPR64sp:$Rn)>;9431def : Pat<(v2i64 (AArch64duplane64 (v2i64 (load GPR64sp:$Rn)), (i64 0))),9432 (LD1Rv2d GPR64sp:$Rn)>;9433 9434// Grab the floating point version too9435def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),9436 (LD1Rv2s GPR64sp:$Rn)>;9437def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),9438 (LD1Rv4s GPR64sp:$Rn)>;9439def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),9440 (LD1Rv2d GPR64sp:$Rn)>;9441def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),9442 (LD1Rv1d GPR64sp:$Rn)>;9443def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),9444 (LD1Rv4h GPR64sp:$Rn)>;9445def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),9446 (LD1Rv8h GPR64sp:$Rn)>;9447def : Pat<(v4bf16 (AArch64dup (bf16 (load GPR64sp:$Rn)))),9448 (LD1Rv4h GPR64sp:$Rn)>;9449def : Pat<(v8bf16 (AArch64dup (bf16 (load GPR64sp:$Rn)))),9450 (LD1Rv8h GPR64sp:$Rn)>;9451 9452class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,9453 ValueType VTy, ValueType STy, Instruction LD1>9454 : Pat<(vector_insert (VTy VecListOne128:$Rd),9455 (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)),9456 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;9457 9458// Accept i8 scalar argument in GlobalISel.9459def : Ld1Lane128Pat<load, VectorIndexB, v16i8, i8, LD1i8>;9460def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;9461def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;9462def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;9463def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;9464def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;9465def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;9466def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;9467def : Ld1Lane128Pat<load, VectorIndexH, v8bf16, bf16, LD1i16>;9468 9469// Generate LD1 for extload if memory type does not match the9470// destination type, for example:9471//9472// (v4i32 (insert_vector_elt (load anyext from i8) idx))9473//9474// In this case, the index must be adjusted to match LD1 type.9475//9476class Ld1Lane128IdxOpPat<SDPatternOperator scalar_load, Operand9477 VecIndex, ValueType VTy, ValueType STy,9478 Instruction LD1, SDNodeXForm IdxOp>9479 : Pat<(vector_insert (VTy VecListOne128:$Rd),9480 (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)),9481 (LD1 VecListOne128:$Rd, (IdxOp VecIndex:$idx), GPR64sp:$Rn)>;9482 9483class Ld1Lane64IdxOpPat<SDPatternOperator scalar_load, Operand VecIndex,9484 ValueType VTy, ValueType STy, Instruction LD1,9485 SDNodeXForm IdxOp>9486 : Pat<(vector_insert (VTy VecListOne64:$Rd),9487 (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)),9488 (EXTRACT_SUBREG9489 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),9490 (IdxOp VecIndex:$idx), GPR64sp:$Rn),9491 dsub)>;9492 9493def VectorIndexStoH : SDNodeXForm<imm, [{9494 return CurDAG->getTargetConstant(N->getZExtValue() * 2, SDLoc(N), MVT::i64);9495}]>;9496def VectorIndexStoB : SDNodeXForm<imm, [{9497 return CurDAG->getTargetConstant(N->getZExtValue() * 4, SDLoc(N), MVT::i64);9498}]>;9499def VectorIndexHtoB : SDNodeXForm<imm, [{9500 return CurDAG->getTargetConstant(N->getZExtValue() * 2, SDLoc(N), MVT::i64);9501}]>;9502 9503def : Ld1Lane128IdxOpPat<extloadi16, VectorIndexS, v4i32, i32, LD1i16, VectorIndexStoH>;9504def : Ld1Lane128IdxOpPat<extloadi8, VectorIndexS, v4i32, i32, LD1i8, VectorIndexStoB>;9505def : Ld1Lane128IdxOpPat<extloadi8, VectorIndexH, v8i16, i32, LD1i8, VectorIndexHtoB>;9506 9507def : Ld1Lane64IdxOpPat<extloadi16, VectorIndexS, v2i32, i32, LD1i16, VectorIndexStoH>;9508def : Ld1Lane64IdxOpPat<extloadi8, VectorIndexS, v2i32, i32, LD1i8, VectorIndexStoB>;9509def : Ld1Lane64IdxOpPat<extloadi8, VectorIndexH, v4i16, i32, LD1i8, VectorIndexHtoB>;9510 9511// Same as above, but the first element is populated using9512// scalar_to_vector + insert_subvector instead of insert_vector_elt.9513let Predicates = [HasNEON] in {9514 class Ld1Lane128FirstElm<ValueType ResultTy, ValueType VecTy,9515 SDPatternOperator ExtLoad, Instruction LD1>9516 : Pat<(ResultTy (vec_ins_or_scal_vec (i32 (ExtLoad GPR64sp:$Rn)))),9517 (ResultTy (EXTRACT_SUBREG9518 (LD1 (VecTy (IMPLICIT_DEF)), 0, GPR64sp:$Rn), dsub))>;9519 9520 def : Ld1Lane128FirstElm<v2i32, v8i16, extloadi16, LD1i16>;9521 def : Ld1Lane128FirstElm<v2i32, v16i8, extloadi8, LD1i8>;9522 def : Ld1Lane128FirstElm<v4i16, v16i8, extloadi8, LD1i8>;9523}9524class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,9525 ValueType VTy, ValueType STy, Instruction LD1>9526 : Pat<(vector_insert (VTy VecListOne64:$Rd),9527 (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)),9528 (EXTRACT_SUBREG9529 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),9530 VecIndex:$idx, GPR64sp:$Rn),9531 dsub)>;9532 9533// Accept i8 scalar argument in GlobalISel.9534def : Ld1Lane64Pat<load, VectorIndexB, v8i8, i8, LD1i8>;9535def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;9536def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;9537def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;9538def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;9539def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;9540def : Ld1Lane64Pat<load, VectorIndexH, v4bf16, bf16, LD1i16>;9541 9542 9543defm LD1 : SIMDLdSt1SingleAliases<"ld1">;9544defm LD2 : SIMDLdSt2SingleAliases<"ld2">;9545defm LD3 : SIMDLdSt3SingleAliases<"ld3">;9546defm LD4 : SIMDLdSt4SingleAliases<"ld4">;9547 9548// Stores9549defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;9550defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;9551defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;9552defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;9553 9554let AddedComplexity = 19 in9555class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,9556 ValueType VTy, ValueType STy, Instruction ST1>9557 : Pat<(scalar_store9558 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),9559 GPR64sp:$Rn),9560 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;9561 9562def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;9563def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;9564def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;9565def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;9566def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;9567def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;9568def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;9569def : St1Lane128Pat<store, VectorIndexH, v8bf16, bf16, ST1i16>;9570 9571let AddedComplexity = 19 in9572class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,9573 ValueType VTy, ValueType STy, Instruction ST1>9574 : Pat<(scalar_store9575 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),9576 GPR64sp:$Rn),9577 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),9578 VecIndex:$idx, GPR64sp:$Rn)>;9579 9580def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;9581def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;9582def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;9583def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;9584def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;9585def : St1Lane64Pat<store, VectorIndexH, v4bf16, bf16, ST1i16>;9586 9587multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,9588 ValueType VTy, ValueType STy, Instruction ST1,9589 int offset> {9590 def : Pat<(scalar_store9591 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),9592 GPR64sp:$Rn, offset),9593 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),9594 VecIndex:$idx, GPR64sp:$Rn, XZR)>;9595 9596 def : Pat<(scalar_store9597 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),9598 GPR64sp:$Rn, GPR64:$Rm),9599 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),9600 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;9601}9602 9603defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;9604defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,9605 2>;9606defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;9607defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;9608defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;9609defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;9610defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;9611defm : St1LanePost64Pat<post_store, VectorIndexH, v4bf16, bf16, ST1i16_POST, 2>;9612 9613multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,9614 ValueType VTy, ValueType STy, Instruction ST1,9615 int offset> {9616 def : Pat<(scalar_store9617 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),9618 GPR64sp:$Rn, offset),9619 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;9620 9621 def : Pat<(scalar_store9622 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),9623 GPR64sp:$Rn, GPR64:$Rm),9624 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;9625}9626 9627defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,9628 1>;9629defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,9630 2>;9631defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;9632defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;9633defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;9634defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;9635defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;9636defm : St1LanePost128Pat<post_store, VectorIndexH, v8bf16, bf16, ST1i16_POST, 2>;9637 9638let mayStore = 1, hasSideEffects = 0 in {9639defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;9640defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;9641defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;9642defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;9643defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;9644defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;9645defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;9646defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;9647defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;9648defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;9649defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;9650defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;9651}9652 9653defm ST1 : SIMDLdSt1SingleAliases<"st1">;9654defm ST2 : SIMDLdSt2SingleAliases<"st2">;9655defm ST3 : SIMDLdSt3SingleAliases<"st3">;9656defm ST4 : SIMDLdSt4SingleAliases<"st4">;9657 9658//----------------------------------------------------------------------------9659// Crypto extensions9660//----------------------------------------------------------------------------9661 9662let Predicates = [HasAES] in {9663let isCommutable = 1 in {9664def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;9665def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;9666}9667def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;9668def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;9669}9670 9671// Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required9672// for AES fusion on some CPUs.9673let hasSideEffects = 0, mayStore = 0, mayLoad = 0, Predicates = [HasAES] in {9674def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">,9675 Sched<[WriteVq]>;9676def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">,9677 Sched<[WriteVq]>;9678}9679 9680// Only use constrained versions of AES(I)MC instructions if they are paired with9681// AESE/AESD.9682def : Pat<(v16i8 (int_aarch64_crypto_aesmc9683 (v16i8 (int_aarch64_crypto_aese (v16i8 V128:$src1),9684 (v16i8 V128:$src2))))),9685 (v16i8 (AESMCrrTied (v16i8 (AESErr (v16i8 V128:$src1),9686 (v16i8 V128:$src2)))))>,9687 Requires<[HasFuseAES]>;9688 9689def : Pat<(v16i8 (int_aarch64_crypto_aesimc9690 (v16i8 (int_aarch64_crypto_aesd (v16i8 V128:$src1),9691 (v16i8 V128:$src2))))),9692 (v16i8 (AESIMCrrTied (v16i8 (AESDrr (v16i8 V128:$src1),9693 (v16i8 V128:$src2)))))>,9694 Requires<[HasFuseAES]>;9695 9696let Predicates = [HasSHA2] in {9697def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;9698def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;9699def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;9700def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;9701def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;9702def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;9703def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;9704 9705def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;9706def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;9707def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;9708}9709 9710//----------------------------------------------------------------------------9711// Compiler-pseudos9712//----------------------------------------------------------------------------9713// FIXME: Like for X86, these should go in their own separate .td file.9714 9715// For an anyext, we don't care what the high bits are, so we can perform an9716// INSERT_SUBREF into an IMPLICIT_DEF.9717def : Pat<(i64 (anyext GPR32:$src)),9718 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;9719 9720// When we need to explicitly zero-extend, we use a 32-bit MOV instruction and9721// then assert the extension has happened.9722def : Pat<(i64 (zext GPR32:$src)),9723 (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>;9724 9725// To sign extend, we use a signed bitfield move instruction (SBFM) on the9726// containing super-reg.9727def : Pat<(i64 (sext GPR32:$src)),9728 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;9729def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;9730def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;9731def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;9732def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;9733def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;9734def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;9735def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;9736 9737def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),9738 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),9739 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;9740def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),9741 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),9742 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;9743 9744def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),9745 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),9746 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;9747def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),9748 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),9749 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;9750 9751def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),9752 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),9753 (i64 (i64shift_a imm0_63:$imm)),9754 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;9755 9756def : Pat<(shl (i64 (zext GPR32:$Rn)), (i64 imm0_63:$imm)),9757 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),9758 (i64 (i64shift_a imm0_63:$imm)),9759 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;9760 9761// sra patterns have an AddedComplexity of 10, so make sure we have a higher9762// AddedComplexity for the following patterns since we want to match sext + sra9763// patterns before we attempt to match a single sra node.9764let AddedComplexity = 20 in {9765// We support all sext + sra combinations which preserve at least one bit of the9766// original value which is to be sign extended. E.g. we support shifts up to9767// bitwidth-1 bits.9768def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),9769 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;9770def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),9771 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;9772 9773def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),9774 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;9775def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),9776 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;9777 9778def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),9779 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),9780 (i64 imm0_31:$imm), 31)>;9781} // AddedComplexity = 209782 9783// To truncate, we can simply extract from a subregister.9784def : Pat<(i32 (trunc GPR64sp:$src)),9785 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;9786 9787// __builtin_trap() uses the BRK instruction on AArch64.9788def : Pat<(trap), (BRK 1)>;9789def : Pat<(debugtrap), (BRK 0xF000)>;9790 9791def ubsan_trap_xform : SDNodeXForm<timm, [{9792 return CurDAG->getTargetConstant(N->getZExtValue() | ('U' << 8), SDLoc(N), MVT::i32);9793}]>;9794 9795def gi_ubsan_trap_xform : GICustomOperandRenderer<"renderUbsanTrap">,9796 GISDNodeXFormEquiv<ubsan_trap_xform>;9797 9798def ubsan_trap_imm : TImmLeaf<i32, [{9799 return isUInt<8>(Imm);9800}], ubsan_trap_xform>;9801 9802def : Pat<(ubsantrap ubsan_trap_imm:$kind), (BRK ubsan_trap_imm:$kind)>;9803 9804// Multiply high patterns which multiply the lower subvector using smull/umull9805// and the upper subvector with smull2/umull2. Then shuffle the high the high9806// part of both results together.9807def : Pat<(v16i8 (mulhs V128:$Rn, V128:$Rm)),9808 (UZP2v16i89809 (SMULLv8i8_v8i16 (EXTRACT_SUBREG V128:$Rn, dsub),9810 (EXTRACT_SUBREG V128:$Rm, dsub)),9811 (SMULLv16i8_v8i16 V128:$Rn, V128:$Rm))>;9812def : Pat<(v8i16 (mulhs V128:$Rn, V128:$Rm)),9813 (UZP2v8i169814 (SMULLv4i16_v4i32 (EXTRACT_SUBREG V128:$Rn, dsub),9815 (EXTRACT_SUBREG V128:$Rm, dsub)),9816 (SMULLv8i16_v4i32 V128:$Rn, V128:$Rm))>;9817def : Pat<(v4i32 (mulhs V128:$Rn, V128:$Rm)),9818 (UZP2v4i329819 (SMULLv2i32_v2i64 (EXTRACT_SUBREG V128:$Rn, dsub),9820 (EXTRACT_SUBREG V128:$Rm, dsub)),9821 (SMULLv4i32_v2i64 V128:$Rn, V128:$Rm))>;9822 9823def : Pat<(v16i8 (mulhu V128:$Rn, V128:$Rm)),9824 (UZP2v16i89825 (UMULLv8i8_v8i16 (EXTRACT_SUBREG V128:$Rn, dsub),9826 (EXTRACT_SUBREG V128:$Rm, dsub)),9827 (UMULLv16i8_v8i16 V128:$Rn, V128:$Rm))>;9828def : Pat<(v8i16 (mulhu V128:$Rn, V128:$Rm)),9829 (UZP2v8i169830 (UMULLv4i16_v4i32 (EXTRACT_SUBREG V128:$Rn, dsub),9831 (EXTRACT_SUBREG V128:$Rm, dsub)),9832 (UMULLv8i16_v4i32 V128:$Rn, V128:$Rm))>;9833def : Pat<(v4i32 (mulhu V128:$Rn, V128:$Rm)),9834 (UZP2v4i329835 (UMULLv2i32_v2i64 (EXTRACT_SUBREG V128:$Rn, dsub),9836 (EXTRACT_SUBREG V128:$Rm, dsub)),9837 (UMULLv4i32_v2i64 V128:$Rn, V128:$Rm))>;9838 9839def : Pat<(v4i16 (AArch64sqdmulh (v4i16 V64:$Rn), (v4i16 V64:$Rm))),9840 (SQDMULHv4i16 V64:$Rn, V64:$Rm)>;9841def : Pat<(v2i32 (AArch64sqdmulh (v2i32 V64:$Rn), (v2i32 V64:$Rm))),9842 (SQDMULHv2i32 V64:$Rn, V64:$Rm)>;9843def : Pat<(v8i16 (AArch64sqdmulh (v8i16 V128:$Rn), (v8i16 V128:$Rm))),9844 (SQDMULHv8i16 V128:$Rn, V128:$Rm)>;9845def : Pat<(v4i32 (AArch64sqdmulh (v4i32 V128:$Rn), (v4i32 V128:$Rm))),9846 (SQDMULHv4i32 V128:$Rn, V128:$Rm)>;9847 9848// Conversions within AdvSIMD types in the same register size are free.9849// But because we need a consistent lane ordering, in big endian many9850// conversions require one or more REV instructions.9851//9852// Consider a simple memory load followed by a bitconvert then a store.9853// v0 = load v2i329854// v1 = BITCAST v2i32 v0 to v4i169855// store v4i16 v29856//9857// In big endian mode every memory access has an implicit byte swap. LDR and9858// STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that9859// is, they treat the vector as a sequence of elements to be byte-swapped.9860// The two pairs of instructions are fundamentally incompatible. We've decided9861// to use LD1/ST1 only to simplify compiler implementation.9862//9863// LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes9864// the original code sequence:9865// v0 = load v2i329866// v1 = REV v2i32 (implicit)9867// v2 = BITCAST v2i32 v1 to v4i169868// v3 = REV v4i16 v2 (implicit)9869// store v4i16 v39870//9871// But this is now broken - the value stored is different to the value loaded9872// due to lane reordering. To fix this, on every BITCAST we must perform two9873// other REVs:9874// v0 = load v2i329875// v1 = REV v2i32 (implicit)9876// v2 = REV v2i329877// v3 = BITCAST v2i32 v2 to v4i169878// v4 = REV v4i169879// v5 = REV v4i16 v4 (implicit)9880// store v4i16 v59881//9882// This means an extra two instructions, but actually in most cases the two REV9883// instructions can be combined into one. For example:9884// (REV64_2s (REV64_4h X)) === (REV32_4h X)9885//9886// There is also no 128-bit REV instruction. This must be synthesized with an9887// EXT instruction.9888//9889// Most bitconverts require some sort of conversion. The only exceptions are:9890// a) Identity conversions - vNfX <-> vNiX9891// b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX9892//9893 9894// Natural vector casts (64 bit)9895foreach VT = [ v8i8, v4i16, v4f16, v4bf16, v2i32, v2f32, v1i64, v1f64, f64 ] in9896 foreach VT2 = [ v8i8, v4i16, v4f16, v4bf16, v2i32, v2f32, v1i64, v1f64, f64 ] in9897 def : Pat<(VT (AArch64NvCast (VT2 FPR64:$src))),9898 (VT FPR64:$src)>;9899 9900// Natural vector casts (128 bit)9901foreach VT = [ v16i8, v8i16, v8f16, v8bf16, v4i32, v4f32, v2i64, v2f64 ] in9902 foreach VT2 = [ v16i8, v8i16, v8f16, v8bf16, v4i32, v4f32, v2i64, v2f64 ] in9903 def : Pat<(VT (AArch64NvCast (VT2 FPR128:$src))),9904 (VT FPR128:$src)>;9905 9906let Predicates = [IsLE] in {9907def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9908def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9909def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9910def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9911def : Pat<(v4bf16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9912def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9913 9914def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),9915 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;9916def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),9917 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;9918def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),9919 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;9920def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),9921 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;9922def : Pat<(i64 (bitconvert (v4bf16 V64:$Vn))),9923 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;9924def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),9925 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;9926def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),9927 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;9928}9929let Predicates = [IsBE] in {9930def : Pat<(v8i8 (bitconvert GPR64:$Xn)),9931 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;9932def : Pat<(v4i16 (bitconvert GPR64:$Xn)),9933 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;9934def : Pat<(v2i32 (bitconvert GPR64:$Xn)),9935 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;9936def : Pat<(v4f16 (bitconvert GPR64:$Xn)),9937 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;9938def : Pat<(v4bf16 (bitconvert GPR64:$Xn)),9939 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;9940def : Pat<(v2f32 (bitconvert GPR64:$Xn)),9941 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;9942 9943def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),9944 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;9945def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),9946 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;9947def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),9948 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;9949def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),9950 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;9951def : Pat<(i64 (bitconvert (v4bf16 V64:$Vn))),9952 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;9953def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),9954 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;9955}9956def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9957def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9958def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),9959 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;9960def : Pat<(v1i64 (vec_ins_or_scal_vec GPR64:$Xn)),9961 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9962def : Pat<(v1f64 (vec_ins_or_scal_vec GPR64:$Xn)),9963 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9964def : Pat<(v1f64 (vec_ins_or_scal_vec (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;9965 9966def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),9967 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;9968def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),9969 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;9970def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),9971 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;9972def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),9973 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;9974def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),9975 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;9976 9977def : Pat<(f16 (bitconvert (bf16 FPR16:$src))), (f16 FPR16:$src)>;9978def : Pat<(bf16 (bitconvert (f16 FPR16:$src))), (bf16 FPR16:$src)>;9979 9980let Predicates = [IsLE] in {9981def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;9982def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;9983def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;9984def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;9985def : Pat<(v1i64 (bitconvert (v4bf16 FPR64:$src))), (v1i64 FPR64:$src)>;9986def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;9987}9988let Predicates = [IsBE] in {9989def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),9990 (v1i64 (REV64v2i32 FPR64:$src))>;9991def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),9992 (v1i64 (REV64v4i16 FPR64:$src))>;9993def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),9994 (v1i64 (REV64v8i8 FPR64:$src))>;9995def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),9996 (v1i64 (REV64v4i16 FPR64:$src))>;9997def : Pat<(v1i64 (bitconvert (v4bf16 FPR64:$src))),9998 (v1i64 (REV64v4i16 FPR64:$src))>;9999def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),10000 (v1i64 (REV64v2i32 FPR64:$src))>;10001}10002def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;10003def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;10004 10005let Predicates = [IsLE] in {10006def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;10007def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;10008def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;10009def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;10010def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;10011def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;10012def : Pat<(v2i32 (bitconvert (v4bf16 FPR64:$src))), (v2i32 FPR64:$src)>;10013}10014let Predicates = [IsBE] in {10015def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),10016 (v2i32 (REV64v2i32 FPR64:$src))>;10017def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),10018 (v2i32 (REV32v4i16 FPR64:$src))>;10019def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),10020 (v2i32 (REV32v8i8 FPR64:$src))>;10021def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),10022 (v2i32 (REV64v2i32 FPR64:$src))>;10023def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),10024 (v2i32 (REV64v2i32 FPR64:$src))>;10025def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),10026 (v2i32 (REV32v4i16 FPR64:$src))>;10027def : Pat<(v2i32 (bitconvert (v4bf16 FPR64:$src))),10028 (v2i32 (REV32v4i16 FPR64:$src))>;10029}10030def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;10031 10032let Predicates = [IsLE] in {10033def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;10034def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;10035def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;10036def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;10037def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;10038def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;10039}10040let Predicates = [IsBE] in {10041def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),10042 (v4i16 (REV64v4i16 FPR64:$src))>;10043def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),10044 (v4i16 (REV32v4i16 FPR64:$src))>;10045def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),10046 (v4i16 (REV16v8i8 FPR64:$src))>;10047def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),10048 (v4i16 (REV64v4i16 FPR64:$src))>;10049def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),10050 (v4i16 (REV32v4i16 FPR64:$src))>;10051def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),10052 (v4i16 (REV64v4i16 FPR64:$src))>;10053}10054def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;10055def : Pat<(v4i16 (bitconvert (v4bf16 FPR64:$src))), (v4i16 FPR64:$src)>;10056 10057let Predicates = [IsLE] in {10058def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;10059def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;10060def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;10061def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;10062def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;10063def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;10064 10065def : Pat<(v4bf16 (bitconvert (v1i64 FPR64:$src))), (v4bf16 FPR64:$src)>;10066def : Pat<(v4bf16 (bitconvert (v2i32 FPR64:$src))), (v4bf16 FPR64:$src)>;10067def : Pat<(v4bf16 (bitconvert (v8i8 FPR64:$src))), (v4bf16 FPR64:$src)>;10068def : Pat<(v4bf16 (bitconvert (f64 FPR64:$src))), (v4bf16 FPR64:$src)>;10069def : Pat<(v4bf16 (bitconvert (v2f32 FPR64:$src))), (v4bf16 FPR64:$src)>;10070def : Pat<(v4bf16 (bitconvert (v1f64 FPR64:$src))), (v4bf16 FPR64:$src)>;10071}10072let Predicates = [IsBE] in {10073def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),10074 (v4f16 (REV64v4i16 FPR64:$src))>;10075def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),10076 (v4f16 (REV32v4i16 FPR64:$src))>;10077def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),10078 (v4f16 (REV16v8i8 FPR64:$src))>;10079def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),10080 (v4f16 (REV64v4i16 FPR64:$src))>;10081def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),10082 (v4f16 (REV32v4i16 FPR64:$src))>;10083def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),10084 (v4f16 (REV64v4i16 FPR64:$src))>;10085 10086def : Pat<(v4bf16 (bitconvert (v1i64 FPR64:$src))),10087 (v4bf16 (REV64v4i16 FPR64:$src))>;10088def : Pat<(v4bf16 (bitconvert (v2i32 FPR64:$src))),10089 (v4bf16 (REV32v4i16 FPR64:$src))>;10090def : Pat<(v4bf16 (bitconvert (v8i8 FPR64:$src))),10091 (v4bf16 (REV16v8i8 FPR64:$src))>;10092def : Pat<(v4bf16 (bitconvert (f64 FPR64:$src))),10093 (v4bf16 (REV64v4i16 FPR64:$src))>;10094def : Pat<(v4bf16 (bitconvert (v2f32 FPR64:$src))),10095 (v4bf16 (REV32v4i16 FPR64:$src))>;10096def : Pat<(v4bf16 (bitconvert (v1f64 FPR64:$src))),10097 (v4bf16 (REV64v4i16 FPR64:$src))>;10098}10099def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),10100 (v4f16 FPR64:$src)>;10101def : Pat<(v4f16 (bitconvert (v4bf16 FPR64:$src))),10102 (v4f16 FPR64:$src)>;10103def : Pat<(v4bf16 (bitconvert (v4i16 FPR64:$src))),10104 (v4bf16 FPR64:$src)>;10105def : Pat<(v4bf16 (bitconvert (v4f16 FPR64:$src))),10106 (v4bf16 FPR64:$src)>;10107 10108let Predicates = [IsLE] in {10109def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;10110def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;10111def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;10112def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;10113def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;10114def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;10115def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;10116def : Pat<(v8i8 (bitconvert (v4bf16 FPR64:$src))), (v8i8 FPR64:$src)>;10117}10118let Predicates = [IsBE] in {10119def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),10120 (v8i8 (REV64v8i8 FPR64:$src))>;10121def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),10122 (v8i8 (REV32v8i8 FPR64:$src))>;10123def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),10124 (v8i8 (REV16v8i8 FPR64:$src))>;10125def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),10126 (v8i8 (REV64v8i8 FPR64:$src))>;10127def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),10128 (v8i8 (REV32v8i8 FPR64:$src))>;10129def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),10130 (v8i8 (REV64v8i8 FPR64:$src))>;10131def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),10132 (v8i8 (REV16v8i8 FPR64:$src))>;10133def : Pat<(v8i8 (bitconvert (v4bf16 FPR64:$src))),10134 (v8i8 (REV16v8i8 FPR64:$src))>;10135}10136 10137let Predicates = [IsLE] in {10138def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;10139def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;10140def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;10141def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;10142def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;10143def : Pat<(f64 (bitconvert (v4bf16 FPR64:$src))), (f64 FPR64:$src)>;10144}10145let Predicates = [IsBE] in {10146def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),10147 (f64 (REV64v2i32 FPR64:$src))>;10148def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),10149 (f64 (REV64v4i16 FPR64:$src))>;10150def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),10151 (f64 (REV64v2i32 FPR64:$src))>;10152def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),10153 (f64 (REV64v8i8 FPR64:$src))>;10154def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),10155 (f64 (REV64v4i16 FPR64:$src))>;10156def : Pat<(f64 (bitconvert (v4bf16 FPR64:$src))),10157 (f64 (REV64v4i16 FPR64:$src))>;10158}10159def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;10160def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;10161 10162let Predicates = [IsLE] in {10163def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;10164def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;10165def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;10166def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;10167def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;10168def : Pat<(v1f64 (bitconvert (v4bf16 FPR64:$src))), (v1f64 FPR64:$src)>;10169}10170let Predicates = [IsBE] in {10171def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),10172 (v1f64 (REV64v2i32 FPR64:$src))>;10173def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),10174 (v1f64 (REV64v4i16 FPR64:$src))>;10175def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),10176 (v1f64 (REV64v8i8 FPR64:$src))>;10177def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),10178 (v1f64 (REV64v2i32 FPR64:$src))>;10179def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),10180 (v1f64 (REV64v4i16 FPR64:$src))>;10181def : Pat<(v1f64 (bitconvert (v4bf16 FPR64:$src))),10182 (v1f64 (REV64v4i16 FPR64:$src))>;10183}10184def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;10185def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;10186 10187let Predicates = [IsLE] in {10188def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;10189def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;10190def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;10191def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;10192def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;10193def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;10194def : Pat<(v2f32 (bitconvert (v4bf16 FPR64:$src))), (v2f32 FPR64:$src)>;10195}10196let Predicates = [IsBE] in {10197def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),10198 (v2f32 (REV64v2i32 FPR64:$src))>;10199def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),10200 (v2f32 (REV32v4i16 FPR64:$src))>;10201def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),10202 (v2f32 (REV32v8i8 FPR64:$src))>;10203def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),10204 (v2f32 (REV64v2i32 FPR64:$src))>;10205def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),10206 (v2f32 (REV64v2i32 FPR64:$src))>;10207def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),10208 (v2f32 (REV32v4i16 FPR64:$src))>;10209def : Pat<(v2f32 (bitconvert (v4bf16 FPR64:$src))),10210 (v2f32 (REV32v4i16 FPR64:$src))>;10211}10212def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;10213 10214let Predicates = [IsLE] in {10215def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;10216def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;10217def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;10218def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;10219def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;10220def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;10221def : Pat<(f128 (bitconvert (v8bf16 FPR128:$src))), (f128 FPR128:$src)>;10222def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;10223}10224let Predicates = [IsBE] in {10225def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),10226 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;10227def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),10228 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),10229 (REV64v4i32 FPR128:$src), (i32 8)))>;10230def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),10231 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),10232 (REV64v8i16 FPR128:$src), (i32 8)))>;10233def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),10234 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),10235 (REV64v8i16 FPR128:$src), (i32 8)))>;10236def : Pat<(f128 (bitconvert (v8bf16 FPR128:$src))),10237 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),10238 (REV64v8i16 FPR128:$src), (i32 8)))>;10239def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),10240 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;10241def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),10242 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),10243 (REV64v4i32 FPR128:$src), (i32 8)))>;10244def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),10245 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),10246 (REV64v16i8 FPR128:$src), (i32 8)))>;10247}10248 10249let Predicates = [IsLE] in {10250def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;10251def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;10252def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;10253def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;10254def : Pat<(v2f64 (bitconvert (v8bf16 FPR128:$src))), (v2f64 FPR128:$src)>;10255def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;10256def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;10257}10258let Predicates = [IsBE] in {10259def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),10260 (v2f64 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;10261def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),10262 (v2f64 (REV64v4i32 FPR128:$src))>;10263def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),10264 (v2f64 (REV64v8i16 FPR128:$src))>;10265def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),10266 (v2f64 (REV64v8i16 FPR128:$src))>;10267def : Pat<(v2f64 (bitconvert (v8bf16 FPR128:$src))),10268 (v2f64 (REV64v8i16 FPR128:$src))>;10269def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),10270 (v2f64 (REV64v16i8 FPR128:$src))>;10271def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),10272 (v2f64 (REV64v4i32 FPR128:$src))>;10273}10274def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;10275 10276let Predicates = [IsLE] in {10277def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;10278def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;10279def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;10280def : Pat<(v4f32 (bitconvert (v8bf16 FPR128:$src))), (v4f32 FPR128:$src)>;10281def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;10282def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;10283def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;10284}10285let Predicates = [IsBE] in {10286def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),10287 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),10288 (REV64v4i32 FPR128:$src), (i32 8)))>;10289def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),10290 (v4f32 (REV32v8i16 FPR128:$src))>;10291def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),10292 (v4f32 (REV32v8i16 FPR128:$src))>;10293def : Pat<(v4f32 (bitconvert (v8bf16 FPR128:$src))),10294 (v4f32 (REV32v8i16 FPR128:$src))>;10295def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),10296 (v4f32 (REV32v16i8 FPR128:$src))>;10297def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),10298 (v4f32 (REV64v4i32 FPR128:$src))>;10299def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),10300 (v4f32 (REV64v4i32 FPR128:$src))>;10301}10302def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;10303 10304let Predicates = [IsLE] in {10305def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;10306def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;10307def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;10308def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;10309def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;10310def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;10311def : Pat<(v2i64 (bitconvert (v8bf16 FPR128:$src))), (v2i64 FPR128:$src)>;10312}10313let Predicates = [IsBE] in {10314def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),10315 (v2i64 (EXTv16i8 FPR128:$src,10316 FPR128:$src, (i32 8)))>;10317def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),10318 (v2i64 (REV64v4i32 FPR128:$src))>;10319def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),10320 (v2i64 (REV64v8i16 FPR128:$src))>;10321def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),10322 (v2i64 (REV64v16i8 FPR128:$src))>;10323def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),10324 (v2i64 (REV64v4i32 FPR128:$src))>;10325def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),10326 (v2i64 (REV64v8i16 FPR128:$src))>;10327def : Pat<(v2i64 (bitconvert (v8bf16 FPR128:$src))),10328 (v2i64 (REV64v8i16 FPR128:$src))>;10329}10330def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;10331 10332let Predicates = [IsLE] in {10333def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;10334def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;10335def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;10336def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;10337def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;10338def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;10339def : Pat<(v4i32 (bitconvert (v8bf16 FPR128:$src))), (v4i32 FPR128:$src)>;10340}10341let Predicates = [IsBE] in {10342def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),10343 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),10344 (REV64v4i32 FPR128:$src),10345 (i32 8)))>;10346def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),10347 (v4i32 (REV64v4i32 FPR128:$src))>;10348def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),10349 (v4i32 (REV32v8i16 FPR128:$src))>;10350def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),10351 (v4i32 (REV32v16i8 FPR128:$src))>;10352def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),10353 (v4i32 (REV64v4i32 FPR128:$src))>;10354def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),10355 (v4i32 (REV32v8i16 FPR128:$src))>;10356def : Pat<(v4i32 (bitconvert (v8bf16 FPR128:$src))),10357 (v4i32 (REV32v8i16 FPR128:$src))>;10358}10359def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;10360 10361let Predicates = [IsLE] in {10362def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;10363def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;10364def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;10365def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;10366def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;10367def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;10368}10369let Predicates = [IsBE] in {10370def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),10371 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),10372 (REV64v8i16 FPR128:$src),10373 (i32 8)))>;10374def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),10375 (v8i16 (REV64v8i16 FPR128:$src))>;10376def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),10377 (v8i16 (REV32v8i16 FPR128:$src))>;10378def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),10379 (v8i16 (REV16v16i8 FPR128:$src))>;10380def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),10381 (v8i16 (REV64v8i16 FPR128:$src))>;10382def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),10383 (v8i16 (REV32v8i16 FPR128:$src))>;10384}10385def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;10386def : Pat<(v8i16 (bitconvert (v8bf16 FPR128:$src))), (v8i16 FPR128:$src)>;10387 10388let Predicates = [IsLE] in {10389def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;10390def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;10391def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;10392def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;10393def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;10394def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;10395 10396def : Pat<(v8bf16 (bitconvert (f128 FPR128:$src))), (v8bf16 FPR128:$src)>;10397def : Pat<(v8bf16 (bitconvert (v2i64 FPR128:$src))), (v8bf16 FPR128:$src)>;10398def : Pat<(v8bf16 (bitconvert (v4i32 FPR128:$src))), (v8bf16 FPR128:$src)>;10399def : Pat<(v8bf16 (bitconvert (v16i8 FPR128:$src))), (v8bf16 FPR128:$src)>;10400def : Pat<(v8bf16 (bitconvert (v2f64 FPR128:$src))), (v8bf16 FPR128:$src)>;10401def : Pat<(v8bf16 (bitconvert (v4f32 FPR128:$src))), (v8bf16 FPR128:$src)>;10402}10403let Predicates = [IsBE] in {10404def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),10405 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),10406 (REV64v8i16 FPR128:$src),10407 (i32 8)))>;10408def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),10409 (v8f16 (REV64v8i16 FPR128:$src))>;10410def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),10411 (v8f16 (REV32v8i16 FPR128:$src))>;10412def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),10413 (v8f16 (REV16v16i8 FPR128:$src))>;10414def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),10415 (v8f16 (REV64v8i16 FPR128:$src))>;10416def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),10417 (v8f16 (REV32v8i16 FPR128:$src))>;10418 10419def : Pat<(v8bf16 (bitconvert (f128 FPR128:$src))),10420 (v8bf16 (EXTv16i8 (REV64v8i16 FPR128:$src),10421 (REV64v8i16 FPR128:$src),10422 (i32 8)))>;10423def : Pat<(v8bf16 (bitconvert (v2i64 FPR128:$src))),10424 (v8bf16 (REV64v8i16 FPR128:$src))>;10425def : Pat<(v8bf16 (bitconvert (v4i32 FPR128:$src))),10426 (v8bf16 (REV32v8i16 FPR128:$src))>;10427def : Pat<(v8bf16 (bitconvert (v16i8 FPR128:$src))),10428 (v8bf16 (REV16v16i8 FPR128:$src))>;10429def : Pat<(v8bf16 (bitconvert (v2f64 FPR128:$src))),10430 (v8bf16 (REV64v8i16 FPR128:$src))>;10431def : Pat<(v8bf16 (bitconvert (v4f32 FPR128:$src))),10432 (v8bf16 (REV32v8i16 FPR128:$src))>;10433}10434def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),10435 (v8f16 FPR128:$src)>;10436def : Pat<(v8bf16 (bitconvert (v8i16 FPR128:$src))),10437 (v8bf16 FPR128:$src)>;10438def : Pat<(v8f16 (bitconvert (v8bf16 FPR128:$src))),10439 (v8f16 FPR128:$src)>;10440def : Pat<(v8bf16 (bitconvert (v8f16 FPR128:$src))),10441 (v8bf16 FPR128:$src)>;10442 10443let Predicates = [IsLE] in {10444def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;10445def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;10446def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;10447def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;10448def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;10449def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;10450def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;10451def : Pat<(v16i8 (bitconvert (v8bf16 FPR128:$src))), (v16i8 FPR128:$src)>;10452}10453let Predicates = [IsBE] in {10454def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),10455 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),10456 (REV64v16i8 FPR128:$src),10457 (i32 8)))>;10458def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),10459 (v16i8 (REV64v16i8 FPR128:$src))>;10460def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),10461 (v16i8 (REV32v16i8 FPR128:$src))>;10462def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),10463 (v16i8 (REV16v16i8 FPR128:$src))>;10464def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),10465 (v16i8 (REV64v16i8 FPR128:$src))>;10466def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),10467 (v16i8 (REV32v16i8 FPR128:$src))>;10468def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),10469 (v16i8 (REV16v16i8 FPR128:$src))>;10470def : Pat<(v16i8 (bitconvert (v8bf16 FPR128:$src))),10471 (v16i8 (REV16v16i8 FPR128:$src))>;10472}10473 10474def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))),10475 (EXTRACT_SUBREG V128:$Rn, dsub)>;10476def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))),10477 (EXTRACT_SUBREG V128:$Rn, dsub)>;10478def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))),10479 (EXTRACT_SUBREG V128:$Rn, dsub)>;10480def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))),10481 (EXTRACT_SUBREG V128:$Rn, dsub)>;10482def : Pat<(v4bf16 (extract_subvector V128:$Rn, (i64 0))),10483 (EXTRACT_SUBREG V128:$Rn, dsub)>;10484def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))),10485 (EXTRACT_SUBREG V128:$Rn, dsub)>;10486def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))),10487 (EXTRACT_SUBREG V128:$Rn, dsub)>;10488def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))),10489 (EXTRACT_SUBREG V128:$Rn, dsub)>;10490 10491def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),10492 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;10493def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),10494 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;10495def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),10496 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;10497def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),10498 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;10499 10500// A 64-bit subvector insert to the first 128-bit vector position10501// is a subregister copy that needs no instruction.10502multiclass InsertSubvectorUndef<ValueType Ty> {10503 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (Ty 0)),10504 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;10505 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (Ty 0)),10506 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;10507 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (Ty 0)),10508 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;10509 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (Ty 0)),10510 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;10511 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (Ty 0)),10512 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;10513 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (Ty 0)),10514 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;10515 def : Pat<(insert_subvector undef, (v4bf16 FPR64:$src), (Ty 0)),10516 (INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;10517 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (Ty 0)),10518 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;10519}10520 10521defm : InsertSubvectorUndef<i32>;10522defm : InsertSubvectorUndef<i64>;10523 10524// Use pair-wise add instructions when summing up the lanes for v2f64, v2i6410525// or v2f32.10526def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),10527 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),10528 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;10529def : Pat<(f64 (any_fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),10530 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),10531 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;10532 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,10533 // so we match on v4f32 here, not v2f32. This will also catch adding10534 // the low two lanes of a true v4f32 vector.10535def : Pat<(any_fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),10536 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),10537 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;10538def : Pat<(any_fadd (vector_extract (v8f16 FPR128:$Rn), (i64 0)),10539 (vector_extract (v8f16 FPR128:$Rn), (i64 1))),10540 (f16 (FADDPv2i16p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;10541 10542// Prefer using the bottom lanes of addp Rn, Rn compared to10543// addp extractlow(Rn), extracthigh(Rn)10544def : Pat<(AArch64addp (v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 0))),10545 (v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 2)))),10546 (v2i32 (EXTRACT_SUBREG (ADDPv4i32 $Rn, $Rn), dsub))>;10547def : Pat<(AArch64addp (v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 0))),10548 (v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 4)))),10549 (v4i16 (EXTRACT_SUBREG (ADDPv8i16 $Rn, $Rn), dsub))>;10550def : Pat<(AArch64addp (v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 0))),10551 (v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 8)))),10552 (v8i8 (EXTRACT_SUBREG (ADDPv16i8 $Rn, $Rn), dsub))>;10553 10554def : Pat<(AArch64faddp (v2f32 (extract_subvector (v4f32 FPR128:$Rn), (i64 0))),10555 (v2f32 (extract_subvector (v4f32 FPR128:$Rn), (i64 2)))),10556 (v2f32 (EXTRACT_SUBREG (FADDPv4f32 $Rn, $Rn), dsub))>;10557def : Pat<(AArch64faddp (v4f16 (extract_subvector (v8f16 FPR128:$Rn), (i64 0))),10558 (v4f16 (extract_subvector (v8f16 FPR128:$Rn), (i64 4)))),10559 (v4f16 (EXTRACT_SUBREG (FADDPv8f16 $Rn, $Rn), dsub))>;10560 10561// add(uzp1(X, Y), uzp2(X, Y)) -> addp(X, Y)10562def : Pat<(v2i64 (add (AArch64zip1 (v2i64 FPR128:$Rn), (v2i64 FPR128:$Rm)),10563 (AArch64zip2 (v2i64 FPR128:$Rn), (v2i64 FPR128:$Rm)))),10564 (v2i64 (ADDPv2i64 $Rn, $Rm))>;10565def : Pat<(v4i32 (add (AArch64uzp1 (v4i32 FPR128:$Rn), (v4i32 FPR128:$Rm)),10566 (AArch64uzp2 (v4i32 FPR128:$Rn), (v4i32 FPR128:$Rm)))),10567 (v4i32 (ADDPv4i32 $Rn, $Rm))>;10568def : Pat<(v8i16 (add (AArch64uzp1 (v8i16 FPR128:$Rn), (v8i16 FPR128:$Rm)),10569 (AArch64uzp2 (v8i16 FPR128:$Rn), (v8i16 FPR128:$Rm)))),10570 (v8i16 (ADDPv8i16 $Rn, $Rm))>;10571def : Pat<(v16i8 (add (AArch64uzp1 (v16i8 FPR128:$Rn), (v16i8 FPR128:$Rm)),10572 (AArch64uzp2 (v16i8 FPR128:$Rn), (v16i8 FPR128:$Rm)))),10573 (v16i8 (ADDPv16i8 $Rn, $Rm))>;10574 10575def : Pat<(v2i32 (add (AArch64zip1 (extract_subvector (v4i32 FPR128:$Rn), (i64 0)),10576 (extract_subvector (v4i32 FPR128:$Rn), (i64 2))),10577 (AArch64zip2 (extract_subvector (v4i32 FPR128:$Rn), (i64 0)),10578 (extract_subvector (v4i32 FPR128:$Rn), (i64 2))))),10579 (EXTRACT_SUBREG (ADDPv4i32 $Rn, $Rn), dsub)>;10580def : Pat<(v4i16 (add (trunc (v4i32 (bitconvert FPR128:$Rn))),10581 (extract_subvector (AArch64uzp2 (v8i16 FPR128:$Rn), undef), (i64 0)))),10582 (EXTRACT_SUBREG (ADDPv8i16 $Rn, $Rn), dsub)>;10583def : Pat<(v8i8 (add (trunc (v8i16 (bitconvert FPR128:$Rn))),10584 (extract_subvector (AArch64uzp2 (v16i8 FPR128:$Rn), undef), (i64 0)))),10585 (EXTRACT_SUBREG (ADDPv16i8 $Rn, $Rn), dsub)>;10586 10587def : Pat<(v2f64 (fadd (AArch64zip1 (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm)),10588 (AArch64zip2 (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm)))),10589 (v2f64 (FADDPv2f64 $Rn, $Rm))>;10590def : Pat<(v4f32 (fadd (AArch64uzp1 (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm)),10591 (AArch64uzp2 (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm)))),10592 (v4f32 (FADDPv4f32 $Rn, $Rm))>;10593let Predicates = [HasFullFP16] in10594def : Pat<(v8f16 (fadd (AArch64uzp1 (v8f16 FPR128:$Rn), (v8f16 FPR128:$Rm)),10595 (AArch64uzp2 (v8f16 FPR128:$Rn), (v8f16 FPR128:$Rm)))),10596 (v8f16 (FADDPv8f16 $Rn, $Rm))>;10597 10598// Scalar 64-bit shifts in FPR64 registers.10599def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),10600 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;10601def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),10602 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;10603def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),10604 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;10605def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),10606 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;10607 10608// Patterns for nontemporal/no-allocate stores.10609// We have to resort to tricks to turn a single-input store into a store pair,10610// because there is no single-input nontemporal store, only STNP.10611let Predicates = [IsLE] in {10612let AddedComplexity = 15 in {10613class NTStore128Pat<ValueType VT> :10614 Pat<(nontemporalstore (VT FPR128:$Rt),10615 (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),10616 (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub),10617 (DUPi64 FPR128:$Rt, (i64 1)),10618 GPR64sp:$Rn, simm7s8:$offset)>;10619 10620def : NTStore128Pat<v2i64>;10621def : NTStore128Pat<v4i32>;10622def : NTStore128Pat<v8i16>;10623def : NTStore128Pat<v16i8>;10624 10625class NTStore64Pat<ValueType VT> :10626 Pat<(nontemporalstore (VT FPR64:$Rt),10627 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),10628 (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub),10629 (DUPi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)),10630 GPR64sp:$Rn, simm7s4:$offset)>;10631 10632// FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64?10633def : NTStore64Pat<v1f64>;10634def : NTStore64Pat<v1i64>;10635def : NTStore64Pat<v2i32>;10636def : NTStore64Pat<v4i16>;10637def : NTStore64Pat<v8i8>;10638 10639def : Pat<(nontemporalstore GPR64:$Rt,10640 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),10641 (STNPWi (EXTRACT_SUBREG GPR64:$Rt, sub_32),10642 (EXTRACT_SUBREG (UBFMXri GPR64:$Rt, 32, 63), sub_32),10643 GPR64sp:$Rn, simm7s4:$offset)>;10644} // AddedComplexity=1010645} // Predicates = [IsLE]10646 10647// Tail call return handling. These are all compiler pseudo-instructions,10648// so no encoding information or anything like that.10649let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {10650 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff), []>,10651 Sched<[WriteBrReg]>;10652 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>,10653 Sched<[WriteBrReg]>;10654 // Indirect tail-call with any register allowed, used by MachineOutliner when10655 // this is proven safe.10656 // FIXME: If we have to add any more hacks like this, we should instead relax10657 // some verifier checks for outlined functions.10658 def TCRETURNriALL : Pseudo<(outs), (ins GPR64:$dst, i32imm:$FPDiff), []>,10659 Sched<[WriteBrReg]>;10660 10661 // Indirect tail-calls with reduced register classes, needed for BTI and10662 // PAuthLR.10663 def TCRETURNrix16x17 : Pseudo<(outs), (ins tcGPRx16x17:$dst, i32imm:$FPDiff), []>,10664 Sched<[WriteBrReg]>;10665 def TCRETURNrix17 : Pseudo<(outs), (ins tcGPRx17:$dst, i32imm:$FPDiff), []>,10666 Sched<[WriteBrReg]>;10667 def TCRETURNrinotx16 : Pseudo<(outs), (ins tcGPRnotx16:$dst, i32imm:$FPDiff), []>,10668 Sched<[WriteBrReg]>;10669}10670 10671def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),10672 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>,10673 Requires<[TailCallAny]>;10674def : Pat<(AArch64tcret tcGPRx16x17:$dst, (i32 timm:$FPDiff)),10675 (TCRETURNrix16x17 tcGPRx16x17:$dst, imm:$FPDiff)>,10676 Requires<[TailCallX16X17]>;10677def : Pat<(AArch64tcret tcGPRx17:$dst, (i32 timm:$FPDiff)),10678 (TCRETURNrix17 tcGPRx17:$dst, imm:$FPDiff)>,10679 Requires<[TailCallX17]>;10680def : Pat<(AArch64tcret tcGPRnotx16:$dst, (i32 timm:$FPDiff)),10681 (TCRETURNrinotx16 tcGPRnotx16:$dst, imm:$FPDiff)>,10682 Requires<[TailCallNotX16]>;10683 10684def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),10685 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;10686def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),10687 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;10688 10689let Size = 8 in10690def MOVMCSym : Pseudo<(outs GPR64:$dst), (ins i64imm:$sym), []>, Sched<[]>;10691def : Pat<(i64 (AArch64LocalRecover mcsym:$sym)), (MOVMCSym mcsym:$sym)>;10692 10693// Extracting lane zero is a special case where we can just use a plain10694// EXTRACT_SUBREG instruction, which will become FMOV. This is easier for the10695// rest of the compiler, especially the register allocator and copy propagation,10696// to reason about, so is preferred when it's possible to use it.10697let AddedComplexity = 10 in {10698 def : Pat<(i64 (extractelt (v2i64 V128:$V), (i64 0))), (EXTRACT_SUBREG V128:$V, dsub)>;10699 def : Pat<(i32 (extractelt (v4i32 V128:$V), (i64 0))), (EXTRACT_SUBREG V128:$V, ssub)>;10700 def : Pat<(i32 (extractelt (v2i32 V64:$V), (i64 0))), (EXTRACT_SUBREG V64:$V, ssub)>;10701}10702 10703// dot_v4i810704class mul_v4i8<SDPatternOperator ldop> :10705 PatFrag<(ops node:$Rn, node:$Rm, node:$offset),10706 (mul (ldop (add node:$Rn, node:$offset)),10707 (ldop (add node:$Rm, node:$offset)))>;10708class mulz_v4i8<SDPatternOperator ldop> :10709 PatFrag<(ops node:$Rn, node:$Rm),10710 (mul (ldop node:$Rn), (ldop node:$Rm))>;10711 10712def load_v4i8 :10713 OutPatFrag<(ops node:$R),10714 (INSERT_SUBREG10715 (v2i32 (IMPLICIT_DEF)),10716 (i32 (COPY_TO_REGCLASS (LDRWui node:$R, (i64 0)), FPR32)),10717 ssub)>;10718 10719class dot_v4i8<Instruction DOT, SDPatternOperator ldop> :10720 Pat<(i32 (add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 3)),10721 (add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 2)),10722 (add (mul_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 1)),10723 (mulz_v4i8<ldop> GPR64sp:$Rn, GPR64sp:$Rm))))),10724 (EXTRACT_SUBREG (i64 (DOT (DUPv2i32gpr WZR),10725 (load_v4i8 GPR64sp:$Rn),10726 (load_v4i8 GPR64sp:$Rm))),10727 sub_32)>, Requires<[HasDotProd]>;10728 10729// dot_v8i810730class ee_v8i8<SDPatternOperator extend> :10731 PatFrag<(ops node:$V, node:$K),10732 (v4i16 (extract_subvector (v8i16 (extend node:$V)), node:$K))>;10733 10734class mul_v8i8<SDPatternOperator mulop, SDPatternOperator extend> :10735 PatFrag<(ops node:$M, node:$N, node:$K),10736 (mulop (v4i16 (ee_v8i8<extend> node:$M, node:$K)),10737 (v4i16 (ee_v8i8<extend> node:$N, node:$K)))>;10738 10739class idot_v8i8<SDPatternOperator mulop, SDPatternOperator extend> :10740 PatFrag<(ops node:$M, node:$N),10741 (i32 (extractelt10742 (v4i32 (AArch64uaddv10743 (add (mul_v8i8<mulop, extend> node:$M, node:$N, (i64 0)),10744 (mul_v8i8<mulop, extend> node:$M, node:$N, (i64 4))))),10745 (i64 0)))>;10746 10747// vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm10748def VADDV_32 : OutPatFrag<(ops node:$R), (ADDPv2i32 node:$R, node:$R)>;10749 10750class odot_v8i8<Instruction DOT> :10751 OutPatFrag<(ops node:$Vm, node:$Vn),10752 (EXTRACT_SUBREG10753 (VADDV_3210754 (i64 (DOT (DUPv2i32gpr WZR),10755 (v8i8 node:$Vm),10756 (v8i8 node:$Vn)))),10757 sub_32)>;10758 10759class dot_v8i8<Instruction DOT, SDPatternOperator mulop,10760 SDPatternOperator extend> :10761 Pat<(idot_v8i8<mulop, extend> V64:$Vm, V64:$Vn),10762 (odot_v8i8<DOT> V64:$Vm, V64:$Vn)>,10763 Requires<[HasDotProd]>;10764 10765// dot_v16i810766class ee_v16i8<SDPatternOperator extend> :10767 PatFrag<(ops node:$V, node:$K1, node:$K2),10768 (v4i16 (extract_subvector10769 (v8i16 (extend10770 (v8i8 (extract_subvector node:$V, node:$K1)))), node:$K2))>;10771 10772class mul_v16i8<SDPatternOperator mulop, SDPatternOperator extend> :10773 PatFrag<(ops node:$M, node:$N, node:$K1, node:$K2),10774 (v4i3210775 (mulop (v4i16 (ee_v16i8<extend> node:$M, node:$K1, node:$K2)),10776 (v4i16 (ee_v16i8<extend> node:$N, node:$K1, node:$K2))))>;10777 10778class idot_v16i8<SDPatternOperator m, SDPatternOperator x> :10779 PatFrag<(ops node:$M, node:$N),10780 (i32 (extractelt10781 (v4i32 (AArch64uaddv10782 (add10783 (add (mul_v16i8<m, x> node:$M, node:$N, (i64 0), (i64 0)),10784 (mul_v16i8<m, x> node:$M, node:$N, (i64 8), (i64 0))),10785 (add (mul_v16i8<m, x> node:$M, node:$N, (i64 0), (i64 4)),10786 (mul_v16i8<m, x> node:$M, node:$N, (i64 8), (i64 4)))))),10787 (i64 0)))>;10788 10789class odot_v16i8<Instruction DOT> :10790 OutPatFrag<(ops node:$Vm, node:$Vn),10791 (i32 (ADDVv4i32v10792 (DOT (DUPv4i32gpr WZR), node:$Vm, node:$Vn)))>;10793 10794class dot_v16i8<Instruction DOT, SDPatternOperator mulop,10795 SDPatternOperator extend> :10796 Pat<(idot_v16i8<mulop, extend> V128:$Vm, V128:$Vn),10797 (odot_v16i8<DOT> V128:$Vm, V128:$Vn)>,10798 Requires<[HasDotProd]>;10799 10800let AddedComplexity = 10 in {10801 def : dot_v4i8<SDOTv8i8, sextloadi8>;10802 def : dot_v4i8<UDOTv8i8, zextloadi8>;10803 def : dot_v8i8<SDOTv8i8, AArch64smull, sext>;10804 def : dot_v8i8<UDOTv8i8, AArch64umull, zext>;10805 def : dot_v16i8<SDOTv16i8, AArch64smull, sext>;10806 def : dot_v16i8<UDOTv16i8, AArch64umull, zext>;10807 10808 // FIXME: add patterns to generate vector by element dot product.10809 // FIXME: add SVE dot-product patterns.10810}10811 10812// Custom DAG nodes and isel rules to make a 64-byte block out of eight GPRs,10813// so that it can be used as input to inline asm, and vice versa.10814def LS64_BUILD : SDNode<"AArch64ISD::LS64_BUILD", SDTypeProfile<1, 8, []>>;10815def LS64_EXTRACT : SDNode<"AArch64ISD::LS64_EXTRACT", SDTypeProfile<1, 2, []>>;10816def : Pat<(i64x8 (LS64_BUILD GPR64:$x0, GPR64:$x1, GPR64:$x2, GPR64:$x3,10817 GPR64:$x4, GPR64:$x5, GPR64:$x6, GPR64:$x7)),10818 (REG_SEQUENCE GPR64x8Class,10819 $x0, x8sub_0, $x1, x8sub_1, $x2, x8sub_2, $x3, x8sub_3,10820 $x4, x8sub_4, $x5, x8sub_5, $x6, x8sub_6, $x7, x8sub_7)>;10821foreach i = 0-7 in {10822 def : Pat<(i64 (LS64_EXTRACT (i64x8 GPR64x8:$val), (i32 i))),10823 (EXTRACT_SUBREG $val, !cast<SubRegIndex>("x8sub_"#i))>;10824}10825 10826let Predicates = [HasLS64] in {10827 let mayLoad = 1 in10828 def LD64B: LoadStore64B<0b101, "ld64b", (ins GPR64sp:$Rn),10829 (outs GPR64x8:$Rt)>;10830 let mayStore = 1 in10831 def ST64B: LoadStore64B<0b001, "st64b", (ins GPR64x8:$Rt, GPR64sp:$Rn),10832 (outs)>;10833 def ST64BV: Store64BV<0b011, "st64bv">;10834 def ST64BV0: Store64BV<0b010, "st64bv0">;10835 10836 class ST64BPattern<Intrinsic intrinsic, Instruction instruction>10837 : Pat<(intrinsic GPR64sp:$addr, GPR64:$x0, GPR64:$x1, GPR64:$x2, GPR64:$x3, GPR64:$x4, GPR64:$x5, GPR64:$x6, GPR64:$x7),10838 (instruction (REG_SEQUENCE GPR64x8Class, $x0, x8sub_0, $x1, x8sub_1, $x2, x8sub_2, $x3, x8sub_3, $x4, x8sub_4, $x5, x8sub_5, $x6, x8sub_6, $x7, x8sub_7), $addr)>;10839 10840 def : ST64BPattern<int_aarch64_st64b, ST64B>;10841 def : ST64BPattern<int_aarch64_st64bv, ST64BV>;10842 def : ST64BPattern<int_aarch64_st64bv0, ST64BV0>;10843}10844 10845let Predicates = [HasMOPS] in {10846 let Defs = [NZCV] in {10847 defm CPYFP : MOPSMemoryCopyInsns<0b00, "cpyfp">;10848 10849 defm CPYP : MOPSMemoryMoveInsns<0b00, "cpyp">;10850 10851 defm SETP : MOPSMemorySetInsns<0b00, "setp">;10852 }10853 let Uses = [NZCV] in {10854 defm CPYFM : MOPSMemoryCopyInsns<0b01, "cpyfm">;10855 defm CPYFE : MOPSMemoryCopyInsns<0b10, "cpyfe">;10856 10857 defm CPYM : MOPSMemoryMoveInsns<0b01, "cpym">;10858 defm CPYE : MOPSMemoryMoveInsns<0b10, "cpye">;10859 10860 defm SETM : MOPSMemorySetInsns<0b01, "setm">;10861 defm SETE : MOPSMemorySetInsns<0b10, "sete">;10862 }10863}10864let Predicates = [HasMOPS, HasMTE] in {10865 let Defs = [NZCV] in {10866 defm SETGP : MOPSMemorySetTaggingInsns<0b00, "setgp">;10867 }10868 let Uses = [NZCV] in {10869 defm SETGM : MOPSMemorySetTaggingInsns<0b01, "setgm">;10870 // Can't use SETGE because it's a reserved name in TargetSelectionDAG.td10871 defm MOPSSETGE : MOPSMemorySetTaggingInsns<0b10, "setge">;10872 }10873}10874 10875// MOPS operations always contain three 4-byte instructions10876let Predicates = [HasMOPS], Defs = [NZCV], Size = 12, mayStore = 1 in {10877 let mayLoad = 1 in {10878 def MOPSMemoryCopyPseudo : Pseudo<(outs GPR64common:$Rd_wb, GPR64common:$Rs_wb, GPR64:$Rn_wb),10879 (ins GPR64common:$Rd, GPR64common:$Rs, GPR64:$Rn),10880 [], "$Rd = $Rd_wb,$Rs = $Rs_wb,$Rn = $Rn_wb">, Sched<[]>;10881 def MOPSMemoryMovePseudo : Pseudo<(outs GPR64common:$Rd_wb, GPR64common:$Rs_wb, GPR64:$Rn_wb),10882 (ins GPR64common:$Rd, GPR64common:$Rs, GPR64:$Rn),10883 [], "$Rd = $Rd_wb,$Rs = $Rs_wb,$Rn = $Rn_wb">, Sched<[]>;10884 }10885 let mayLoad = 0 in {10886 def MOPSMemorySetPseudo : Pseudo<(outs GPR64common:$Rd_wb, GPR64:$Rn_wb),10887 (ins GPR64common:$Rd, GPR64:$Rn, GPR64:$Rm),10888 [], "$Rd = $Rd_wb,$Rn = $Rn_wb,@earlyclobber $Rn_wb">, Sched<[]>;10889 }10890}10891let Predicates = [HasMOPS, HasMTE], Defs = [NZCV], Size = 12, mayLoad = 0, mayStore = 1 in {10892 def MOPSMemorySetTaggingPseudo : Pseudo<(outs GPR64common:$Rd_wb, GPR64:$Rn_wb),10893 (ins GPR64common:$Rd, GPR64:$Rn, GPR64:$Rm),10894 [], "$Rd = $Rd_wb,$Rn = $Rn_wb">, Sched<[]>;10895}10896 10897//-----------------------------------------------------------------------------10898// MOPS Granule Only Protection (FEAT_MOPS_GO)10899 10900let Predicates = [HasMOPS_GO, HasMTE] in {10901 defm SETGOP : MOPSGoMemorySetTaggingInsns<0b00, "setgop">;10902 defm SETGOM : MOPSGoMemorySetTaggingInsns<0b01, "setgom">;10903 defm SETGOE : MOPSGoMemorySetTaggingInsns<0b10, "setgoe">;10904}10905 10906//-----------------------------------------------------------------------------10907// v8.3 Pointer Authentication late patterns10908 10909def : Pat<(int_ptrauth_blend GPR64:$Rd, imm64_0_65535:$imm),10910 (MOVKXi GPR64:$Rd, (trunc_imm imm64_0_65535:$imm), 48)>;10911def : Pat<(int_ptrauth_blend GPR64:$Rd, GPR64:$Rn),10912 (BFMXri GPR64:$Rd, GPR64:$Rn, 16, 15)>;10913 10914//-----------------------------------------------------------------------------10915 10916// This gets lowered into an instruction sequence of 20 bytes10917let Defs = [X16, X17], mayStore = 1, isCodeGenOnly = 1, Size = 20 in10918def StoreSwiftAsyncContext10919 : Pseudo<(outs), (ins GPR64:$ctx, GPR64sp:$base, simm9:$offset),10920 []>, Sched<[]>;10921 10922// Asserts that a function argument (i32) is zero-extended to i8 by10923// the caller10924def AArch64AssertZExtBool : SDNode<"AArch64ISD::ASSERT_ZEXT_BOOL", SDT_assert>;10925def : Pat<(AArch64AssertZExtBool GPR32:$op),10926 (i32 GPR32:$op)>;10927 10928//===----------------------------===//10929// 2022 Architecture Extensions:10930//===----------------------------===//10931 10932def : InstAlias<"clrbhb", (HINT 22), 0>;10933let Predicates = [HasCLRBHB] in {10934 def : InstAlias<"clrbhb", (HINT 22), 1>;10935}10936 10937//===----------------------------------------------------------------------===//10938// Translation Hardening Extension (FEAT_THE)10939//===----------------------------------------------------------------------===//10940defm RCW : ReadCheckWriteCompareAndSwap;10941 10942defm RCWCLR : ReadCheckWriteOperation<0b001, "clr">;10943defm RCWSET : ReadCheckWriteOperation<0b011, "set">;10944defm RCWSWP : ReadCheckWriteOperation<0b010, "swp">;10945 10946//===----------------------------------------------------------------------===//10947// General Data-Processing Instructions (FEAT_V94_DP)10948//===----------------------------------------------------------------------===//10949defm ABS : OneOperandData<0b001000, "abs", abs>, Requires<[HasCSSC]>;10950defm CNT : OneOperandData<0b000111, "cnt", ctpop>, Requires<[HasCSSC]>;10951defm CTZ : OneOperandData<0b000110, "ctz", cttz>, Requires<[HasCSSC]>;10952 10953defm SMAX : ComparisonOp<0, 0, "smax", smax>, Requires<[HasCSSC]>;10954defm SMIN : ComparisonOp<0, 1, "smin", smin>, Requires<[HasCSSC]>;10955defm UMAX : ComparisonOp<1, 0, "umax", umax>, Requires<[HasCSSC]>;10956defm UMIN : ComparisonOp<1, 1, "umin", umin>, Requires<[HasCSSC]>;10957 10958def RPRFM:10959 I<(outs), (ins rprfop:$Rt, GPR64:$Rm, GPR64sp:$Rn),10960 "rprfm", "\t$Rt, $Rm, [$Rn]", "", []>,10961 Sched<[]> {10962 bits<6> Rt;10963 bits<5> Rn;10964 bits<5> Rm;10965 let Inst{2-0} = Rt{2-0};10966 let Inst{4-3} = 0b11;10967 let Inst{9-5} = Rn;10968 let Inst{11-10} = 0b10;10969 let Inst{13-12} = Rt{4-3};10970 let Inst{14} = 0b1;10971 let Inst{15} = Rt{5};10972 let Inst{20-16} = Rm;10973 let Inst{31-21} = 0b11111000101;10974 let mayLoad = 0;10975 let mayStore = 0;10976 let hasSideEffects = 1;10977 // RPRFM overlaps with PRFM (reg), when the decoder method of PRFM returns10978 // Fail, the decoder should attempt to decode RPRFM. This requires setting10979 // the decoder namespace to "Fallback".10980 let DecoderNamespace = "Fallback";10981}10982 10983//===----------------------------------------------------------------------===//10984// 128-bit Atomics (FEAT_LSE128)10985//===----------------------------------------------------------------------===//10986let Predicates = [HasLSE128] in {10987 def SWPP : LSE128Base<0b000, 0b00, 0b1, "swpp">;10988 def SWPPA : LSE128Base<0b000, 0b10, 0b1, "swppa">;10989 def SWPPAL : LSE128Base<0b000, 0b11, 0b1, "swppal">;10990 def SWPPL : LSE128Base<0b000, 0b01, 0b1, "swppl">;10991 def LDCLRP : LSE128Base<0b001, 0b00, 0b0, "ldclrp">;10992 def LDCLRPA : LSE128Base<0b001, 0b10, 0b0, "ldclrpa">;10993 def LDCLRPAL : LSE128Base<0b001, 0b11, 0b0, "ldclrpal">;10994 def LDCLRPL : LSE128Base<0b001, 0b01, 0b0, "ldclrpl">;10995 def LDSETP : LSE128Base<0b011, 0b00, 0b0, "ldsetp">;10996 def LDSETPA : LSE128Base<0b011, 0b10, 0b0, "ldsetpa">;10997 def LDSETPAL : LSE128Base<0b011, 0b11, 0b0, "ldsetpal">;10998 def LDSETPL : LSE128Base<0b011, 0b01, 0b0, "ldsetpl">;10999}11000 11001//===----------------------------------------------------------------------===//11002// RCPC Instructions (FEAT_LRCPC3)11003//===----------------------------------------------------------------------===//11004 11005let Predicates = [HasRCPC3] in {11006 // size opc opc211007 def STILPWpre: BaseLRCPC3IntegerLoadStorePair<0b10, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn, #-8]!", "$Rn = $wback">;11008 def STILPXpre: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn, #-16]!", "$Rn = $wback">;11009 def STILPW: BaseLRCPC3IntegerLoadStorePair<0b10, 0b00, 0b0001, (outs), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn]", "">;11010 def STILPX: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0001, (outs), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn]", "">;11011 def LDIAPPWpost: BaseLRCPC3IntegerLoadStorePair<0b10, 0b01, 0b0000, (outs GPR64sp:$wback, GPR32:$Rt, GPR32:$Rt2), (ins GPR64sp:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn], #8", "$Rn = $wback">;11012 def LDIAPPXpost: BaseLRCPC3IntegerLoadStorePair<0b11, 0b01, 0b0000, (outs GPR64sp:$wback, GPR64:$Rt, GPR64:$Rt2), (ins GPR64sp:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn], #16", "$Rn = $wback">;11013 def LDIAPPW: BaseLRCPC3IntegerLoadStorePair<0b10, 0b01, 0b0001, (outs GPR32:$Rt, GPR32:$Rt2), (ins GPR64sp0:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn]", "">;11014 def LDIAPPX: BaseLRCPC3IntegerLoadStorePair<0b11, 0b01, 0b0001, (outs GPR64:$Rt, GPR64:$Rt2), (ins GPR64sp0:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn]", "">;11015 11016 def : Pat<(AArch64ldiapp GPR64sp:$Rn), (LDIAPPX GPR64sp:$Rn)>;11017 def : Pat<(AArch64stilp GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), (STILPX GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn)>;11018 11019 // Aliases for when offset=011020 def : InstAlias<"stilp\t$Rt, $Rt2, [$Rn, #0]", (STILPW GPR32: $Rt, GPR32: $Rt2, GPR64sp:$Rn)>;11021 def : InstAlias<"stilp\t$Rt, $Rt2, [$Rn, #0]", (STILPX GPR64: $Rt, GPR64: $Rt2, GPR64sp:$Rn)>;11022 11023 // size opc11024 def STLRWpre: BaseLRCPC3IntegerLoadStore<0b10, 0b10, (outs GPR64sp:$wback), (ins GPR32:$Rt, GPR64sp:$Rn), "stlr", "\t$Rt, [$Rn, #-4]!", "$Rn = $wback">;11025 def STLRXpre: BaseLRCPC3IntegerLoadStore<0b11, 0b10, (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64sp:$Rn), "stlr", "\t$Rt, [$Rn, #-8]!", "$Rn = $wback">;11026 def LDAPRWpost: BaseLRCPC3IntegerLoadStore<0b10, 0b11, (outs GPR64sp:$wback, GPR32:$Rt), (ins GPR64sp:$Rn), "ldapr", "\t$Rt, [$Rn], #4", "$Rn = $wback">;11027 def LDAPRXpost: BaseLRCPC3IntegerLoadStore<0b11, 0b11, (outs GPR64sp:$wback, GPR64:$Rt), (ins GPR64sp:$Rn), "ldapr", "\t$Rt, [$Rn], #8", "$Rn = $wback">;11028}11029 11030let Predicates = [HasRCPC3, HasNEON] in {11031 // size opc regtype11032 defm STLURb: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b00, FPR8 , (outs), (ins FPR8 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">;11033 defm STLURh: LRCPC3NEONLoadStoreUnscaledOffset<0b01, 0b00, FPR16 , (outs), (ins FPR16 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">;11034 defm STLURs: LRCPC3NEONLoadStoreUnscaledOffset<0b10, 0b00, FPR32 , (outs), (ins FPR32 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">;11035 defm STLURd: LRCPC3NEONLoadStoreUnscaledOffset<0b11, 0b00, FPR64 , (outs), (ins FPR64 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">;11036 defm STLURq: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b10, FPR128, (outs), (ins FPR128:$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">;11037 defm LDAPURb: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b01, FPR8 , (outs FPR8 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;11038 defm LDAPURh: LRCPC3NEONLoadStoreUnscaledOffset<0b01, 0b01, FPR16 , (outs FPR16 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;11039 defm LDAPURs: LRCPC3NEONLoadStoreUnscaledOffset<0b10, 0b01, FPR32 , (outs FPR32 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;11040 defm LDAPURd: LRCPC3NEONLoadStoreUnscaledOffset<0b11, 0b01, FPR64 , (outs FPR64 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;11041 defm LDAPURq: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b11, FPR128, (outs FPR128:$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;11042 11043 // L11044 def STL1: LRCPC3NEONLdStSingle<0b0, (outs), (ins VecListOned:$Vt, VectorIndexD:$Q, GPR64sp:$Rn) , "stl1", "">;11045 def LDAP1: LRCPC3NEONLdStSingle<0b1, (outs VecListOned:$dst), (ins VecListOned:$Vt, VectorIndexD:$Q, GPR64sp0:$Rn), "ldap1", "$Vt = $dst">;11046 11047 // Aliases for when offset=011048 def : InstAlias<"stl1\t$Vt$Q, [$Rn, #0]", (STL1 VecListOned:$Vt, VectorIndexD:$Q, GPR64sp:$Rn)>;11049}11050 11051//===----------------------------------------------------------------------===//11052// 128-bit System Instructions (FEAT_SYSINSTR128)11053//===----------------------------------------------------------------------===//11054let Predicates = [HasD128] in {11055 def SYSPxt : SystemPXtI<0, "sysp">;11056 11057 def SYSPxt_XZR11058 : BaseSystemI<0, (outs),11059 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, SyspXzrPairOperand:$xzr_pair),11060 "sysp", "\t$op1, $Cn, $Cm, $op2, $xzr_pair">,11061 Sched<[WriteSys]>11062 {11063 // Had to use a custom decoder because tablegen interprets this as having 4 fields (why?)11064 // and therefore autogenerates a decoder that builds an MC representation that has 4 fields11065 // (decodeToMCInst), but when printing we expect the MC representation to have 5 fields (one11066 // extra for the XZR) because AArch64InstPrinter::printInstruction in AArch64GenAsmWriter.inc11067 // is based off of the asm template (maybe) and therefore wants to print 5 operands.11068 // I could add a bits<5> xzr_pair. But without a way to constrain it to 0b11111 here it would11069 // overlap with the main SYSP instruction.11070 let DecoderMethod = "DecodeSyspXzrInstruction";11071 bits<3> op1;11072 bits<4> Cn;11073 bits<4> Cm;11074 bits<3> op2;11075 let Inst{22} = 0b1; // override BaseSystemI11076 let Inst{20-19} = 0b01;11077 let Inst{18-16} = op1;11078 let Inst{15-12} = Cn;11079 let Inst{11-8} = Cm;11080 let Inst{7-5} = op2;11081 let Inst{4-0} = 0b11111;11082 }11083 11084 def : InstAlias<"sysp $op1, $Cn, $Cm, $op2",11085 (SYSPxt_XZR imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR)>;11086}11087 11088//---11089// 128-bit System Registers (FEAT_SYSREG128)11090//---11091 11092// Instruction encoding:11093//11094// 31 22|21|20|19|18 16|15 12|11 8|7 5|4 011095// MRRS 1101010101| 1| 1|o0| op1| Cn| Cm|op2| Rt11096// MSRR 1101010101| 0| 1|o0| op1| Cn| Cm|op2| Rt11097 11098// Instruction syntax:11099//11100// MRRS <Xt>, <Xt+1>, <sysreg|S<op0>_<op1>_<Cn>_<Cm>_<op2>>11101// MSRR <sysreg|S<op0>_<op1>_<Cn>_<Cm>_<op2>>, <Xt>, <Xt+1>11102//11103// ...where t is even (X0, X2, etc).11104 11105let Predicates = [HasD128] in {11106 def MRRS : RtSystemI128<1,11107 (outs MrrsMssrPairClassOperand:$Rt), (ins mrs_sysreg_op:$systemreg),11108 "mrrs", "\t$Rt, $systemreg">11109 {11110 bits<16> systemreg;11111 let Inst{20-5} = systemreg;11112 }11113 11114 def MSRR : RtSystemI128<0,11115 (outs), (ins msr_sysreg_op:$systemreg, MrrsMssrPairClassOperand:$Rt),11116 "msrr", "\t$systemreg, $Rt">11117 {11118 bits<16> systemreg;11119 let Inst{20-5} = systemreg;11120 }11121}11122 11123//===----------------------------===//11124// 2023 Architecture Extensions:11125//===----------------------------===//11126 11127let Predicates = [HasFP8] in {11128 defm F1CVTL : SIMD_FP8_CVTL<0b00, "f1cvtl", v8f16, int_aarch64_neon_fp8_cvtl1>;11129 defm F2CVTL : SIMD_FP8_CVTL<0b01, "f2cvtl", v8f16, int_aarch64_neon_fp8_cvtl2>;11130 defm BF1CVTL : SIMD_FP8_CVTL<0b10, "bf1cvtl", v8bf16, int_aarch64_neon_fp8_cvtl1>;11131 defm BF2CVTL : SIMD_FP8_CVTL<0b11, "bf2cvtl", v8bf16, int_aarch64_neon_fp8_cvtl2>;11132 defm FCVTN_F16 : SIMD_FP8_CVTN_F16<"fcvtn", int_aarch64_neon_fp8_fcvtn>;11133 defm FCVTN_F32 : SIMD_FP8_CVTN_F32<"fcvtn", int_aarch64_neon_fp8_fcvtn>;11134 defm FSCALE : SIMDThreeVectorFscale<0b1, 0b1, 0b111, "fscale", int_aarch64_neon_fp8_fscale>;11135} // End let Predicates = [HasFP8]11136 11137// fminimum(abs(a), abs(b)) -> famin(a, b)11138// fminnum[nnan](abs(a), abs(b)) -> famin(a, b)11139def AArch64famin : PatFrags<(ops node:$Rn, node:$Rm),11140 [(int_aarch64_neon_famin node:$Rn, node:$Rm),11141 (fminimum (fabs node:$Rn), (fabs node:$Rm)),11142 (fminnum_nnan (fabs node:$Rn), (fabs node:$Rm))]>;11143 11144// fmaximum(abs(a), abs(b)) -> famax(a, b)11145// fmaxnum[nnan](abs(a), abs(b)) -> famax(a, b)11146def AArch64famax : PatFrags<(ops node:$Rn, node:$Rm),11147 [(int_aarch64_neon_famax node:$Rn, node:$Rm),11148 (fmaximum (fabs node:$Rn), (fabs node:$Rm)),11149 (fmaxnum_nnan (fabs node:$Rn), (fabs node:$Rm))]>;11150 11151let Predicates = [HasNEON, HasFAMINMAX] in {11152 defm FAMAX : SIMDThreeSameVectorFP<0b0, 0b1, 0b011, "famax", AArch64famax>;11153 defm FAMIN : SIMDThreeSameVectorFP<0b1, 0b1, 0b011, "famin", AArch64famin>;11154} // End let Predicates = [HasNEON, HasFAMINMAX]11155 11156let Predicates = [HasFP8FMA] in {11157 defm FMLALBlane : SIMDThreeSameVectorMLAIndex<0b0, "fmlalb", int_aarch64_neon_fp8_fmlalb_lane>;11158 defm FMLALTlane : SIMDThreeSameVectorMLAIndex<0b1, "fmlalt", int_aarch64_neon_fp8_fmlalt_lane>;11159 defm FMLALLBBlane : SIMDThreeSameVectorMLALIndex<0b0, 0b00, "fmlallbb", int_aarch64_neon_fp8_fmlallbb_lane>;11160 defm FMLALLBTlane : SIMDThreeSameVectorMLALIndex<0b0, 0b01, "fmlallbt", int_aarch64_neon_fp8_fmlallbt_lane>;11161 defm FMLALLTBlane : SIMDThreeSameVectorMLALIndex<0b1, 0b00, "fmlalltb", int_aarch64_neon_fp8_fmlalltb_lane>;11162 defm FMLALLTTlane : SIMDThreeSameVectorMLALIndex<0b1, 0b01, "fmlalltt", int_aarch64_neon_fp8_fmlalltt_lane>;11163}11164 11165let Predicates = [HasFP8FMA], Uses = [FPMR, FPCR], mayLoad = 1 in {11166 defm FMLALB : SIMDThreeSameVectorMLA<0b0, "fmlalb", int_aarch64_neon_fp8_fmlalb>;11167 defm FMLALT : SIMDThreeSameVectorMLA<0b1, "fmlalt", int_aarch64_neon_fp8_fmlalt>;11168 defm FMLALLBB : SIMDThreeSameVectorMLAL<0b0, 0b00, "fmlallbb", int_aarch64_neon_fp8_fmlallbb>;11169 defm FMLALLBT : SIMDThreeSameVectorMLAL<0b0, 0b01, "fmlallbt", int_aarch64_neon_fp8_fmlallbt>;11170 defm FMLALLTB : SIMDThreeSameVectorMLAL<0b1, 0b00, "fmlalltb", int_aarch64_neon_fp8_fmlalltb>;11171 defm FMLALLTT : SIMDThreeSameVectorMLAL<0b1, 0b01, "fmlalltt", int_aarch64_neon_fp8_fmlalltt>;11172} // End let Predicates = [HasFP8FMA]11173 11174let Predicates = [HasFP8DOT2] in {11175 defm FDOTlane : SIMD_FP8_Dot2_Index<"fdot", int_aarch64_neon_fp8_fdot2_lane>;11176 defm FDOT : SIMD_FP8_Dot2<"fdot", int_aarch64_neon_fp8_fdot2>;11177} // End let Predicates = [HasFP8DOT2]11178 11179let Predicates = [HasFP8DOT4] in {11180 defm FDOTlane : SIMD_FP8_Dot4_Index<"fdot", int_aarch64_neon_fp8_fdot4_lane>;11181 defm FDOT : SIMD_FP8_Dot4<"fdot", int_aarch64_neon_fp8_fdot4>;11182} // End let Predicates = [HasFP8DOT4]11183 11184//===----------------------------------------------------------------------===//11185// Checked Pointer Arithmetic (FEAT_CPA)11186//===----------------------------------------------------------------------===//11187let Predicates = [HasCPA] in {11188 // Scalar add/subtract11189 defm ADDPT : AddSubCPA<0, "addpt">;11190 defm SUBPT : AddSubCPA<1, "subpt">;11191 11192 // Scalar multiply-add/subtract11193 def MADDPT : MulAccumCPA<0, "maddpt">;11194 def MSUBPT : MulAccumCPA<1, "msubpt">;11195 11196 def : Pat<(ptradd GPR64sp:$Rn, GPR64sp:$Rm),11197 (ADDPT_shift GPR64sp:$Rn, GPR64sp:$Rm, (i64 0))>;11198 def : Pat<(ptradd GPR64sp:$Rn, (shl GPR64sp:$Rm, (i64 imm0_7:$imm))),11199 (ADDPT_shift GPR64sp:$Rn, GPR64sp:$Rm,11200 (i64 imm0_7:$imm))>;11201 def : Pat<(ptradd GPR64sp:$Rn, (ineg GPR64sp:$Rm)),11202 (SUBPT_shift GPR64sp:$Rn, GPR64sp:$Rm, (i64 0))>;11203 def : Pat<(ptradd GPR64sp:$Rn, (ineg (shl GPR64sp:$Rm, (i64 imm0_7:$imm)))),11204 (SUBPT_shift GPR64sp:$Rn, GPR64sp:$Rm,11205 (i64 imm0_7:$imm))>;11206 def : Pat<(ptradd GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)),11207 (MADDPT GPR64:$Rn, GPR64:$Rm, GPR64:$Ra)>;11208 def : Pat<(ptradd GPR64:$Ra, (mul GPR64:$Rn, (ineg GPR64:$Rm))),11209 (MSUBPT GPR64:$Rn, GPR64:$Rm, GPR64:$Ra)>;11210}11211 11212def round_v4fp32_to_v4bf16 :11213 OutPatFrag<(ops node:$Rn),11214 // NaN? Round : Quiet(NaN)11215 (BSPv16i8 (FCMEQv4f32 $Rn, $Rn),11216 (ADDv4i3211217 (ADDv4i32 $Rn,11218 // Extract the LSB of the fp32 *truncated* to bf16.11219 (ANDv16i8 (USHRv4i32_shift V128:$Rn, (i32 16)),11220 (MOVIv4i32 (i32 1), (i32 0)))),11221 // Bias which will help us break ties correctly.11222 (MOVIv4s_msl (i32 127), (i32 264))),11223 // Set the quiet bit in the NaN.11224 (ORRv4i32 $Rn, (i32 64), (i32 16)))>;11225 11226multiclass PromoteUnaryv8f16Tov4f32<SDPatternOperator InOp, Instruction OutInst> {11227 let Predicates = [HasNoFullFP16] in11228 def : Pat<(InOp (v8f16 V128:$Rn)),11229 (v8f16 (FCVTNv8i1611230 (INSERT_SUBREG (IMPLICIT_DEF),11231 (v4f16 (FCVTNv4i1611232 (v4f32 (OutInst11233 (v4f32 (FCVTLv4i16 (v4i16 (EXTRACT_SUBREG V128:$Rn, dsub)))))))),11234 dsub),11235 (v4f32 (OutInst (v4f32 (FCVTLv8i16 V128:$Rn))))))>;11236 11237 let Predicates = [HasBF16] in11238 def : Pat<(InOp (v8bf16 V128:$Rn)),11239 (v8bf16 (BFCVTN211240 (INSERT_SUBREG (IMPLICIT_DEF),11241 (v4bf16 (BFCVTN11242 (v4f32 (OutInst11243 (v4f32 (SHLLv4i16 (v4i16 (EXTRACT_SUBREG V128:$Rn, dsub)))))))),11244 dsub),11245 (v4f32 (OutInst (v4f32 (SHLLv8i16 V128:$Rn))))))>;11246 11247 let Predicates = [HasNoBF16] in11248 def : Pat<(InOp (v8bf16 V128:$Rn)),11249 (UZP2v8i1611250 (round_v4fp32_to_v4bf16 (v4f32 (OutInst11251 (v4f32 (SHLLv4i16 (v4i16 (EXTRACT_SUBREG V128:$Rn, dsub))))))),11252 (round_v4fp32_to_v4bf16 (v4f32 (OutInst11253 (v4f32 (SHLLv8i16 V128:$Rn))))))>;11254}11255defm : PromoteUnaryv8f16Tov4f32<any_fceil, FRINTPv4f32>;11256defm : PromoteUnaryv8f16Tov4f32<any_ffloor, FRINTMv4f32>;11257defm : PromoteUnaryv8f16Tov4f32<any_fnearbyint, FRINTIv4f32>;11258defm : PromoteUnaryv8f16Tov4f32<any_fround, FRINTAv4f32>;11259defm : PromoteUnaryv8f16Tov4f32<any_froundeven, FRINTNv4f32>;11260defm : PromoteUnaryv8f16Tov4f32<any_frint, FRINTXv4f32>;11261defm : PromoteUnaryv8f16Tov4f32<any_ftrunc, FRINTZv4f32>;11262 11263multiclass PromoteBinaryv8f16Tov4f32<SDPatternOperator InOp, Instruction OutInst> {11264 let Predicates = [HasNoFullFP16] in11265 def : Pat<(InOp (v8f16 V128:$Rn), (v8f16 V128:$Rm)),11266 (v8f16 (FCVTNv8i1611267 (INSERT_SUBREG (IMPLICIT_DEF),11268 (v4f16 (FCVTNv4i1611269 (v4f32 (OutInst11270 (v4f32 (FCVTLv4i16 (v4i16 (EXTRACT_SUBREG V128:$Rn, dsub)))),11271 (v4f32 (FCVTLv4i16 (v4i16 (EXTRACT_SUBREG V128:$Rm, dsub)))))))),11272 dsub),11273 (v4f32 (OutInst (v4f32 (FCVTLv8i16 V128:$Rn)),11274 (v4f32 (FCVTLv8i16 V128:$Rm))))))>;11275 11276 let Predicates = [HasBF16] in11277 def : Pat<(InOp (v8bf16 V128:$Rn), (v8bf16 V128:$Rm)),11278 (v8bf16 (BFCVTN211279 (INSERT_SUBREG (IMPLICIT_DEF),11280 (v4bf16 (BFCVTN11281 (v4f32 (OutInst11282 (v4f32 (SHLLv4i16 (v4i16 (EXTRACT_SUBREG V128:$Rn, dsub)))),11283 (v4f32 (SHLLv4i16 (v4i16 (EXTRACT_SUBREG V128:$Rm, dsub)))))))),11284 dsub),11285 (v4f32 (OutInst (v4f32 (SHLLv8i16 V128:$Rn)),11286 (v4f32 (SHLLv8i16 V128:$Rm))))))>;11287 11288 let Predicates = [HasNoBF16] in11289 def : Pat<(InOp (v8bf16 V128:$Rn), (v8bf16 V128:$Rm)),11290 (UZP2v8i1611291 (round_v4fp32_to_v4bf16 (v4f32 (OutInst11292 (v4f32 (SHLLv4i16 (v4i16 (EXTRACT_SUBREG V128:$Rn, dsub)))),11293 (v4f32 (SHLLv4i16 (v4i16 (EXTRACT_SUBREG V128:$Rm, dsub))))))),11294 (round_v4fp32_to_v4bf16 (v4f32 (OutInst11295 (v4f32 (SHLLv8i16 V128:$Rn)),11296 (v4f32 (SHLLv8i16 V128:$Rm))))))>;11297}11298defm : PromoteBinaryv8f16Tov4f32<any_fadd, FADDv4f32>;11299defm : PromoteBinaryv8f16Tov4f32<any_fdiv, FDIVv4f32>;11300defm : PromoteBinaryv8f16Tov4f32<any_fmul, FMULv4f32>;11301defm : PromoteBinaryv8f16Tov4f32<any_fsub, FSUBv4f32>;11302 11303//===----------------------------------------------------------------------===//11304// Compare and Branch (FEAT_CMPBR)11305//===----------------------------------------------------------------------===//11306 11307let Predicates = [HasCMPBR] in {11308 defm CBGT : CmpBranchRegister<0b000, "cbgt">;11309 defm CBGE : CmpBranchRegister<0b001, "cbge">;11310 defm CBHI : CmpBranchRegister<0b010, "cbhi">;11311 defm CBHS : CmpBranchRegister<0b011, "cbhs">;11312 defm CBEQ : CmpBranchRegister<0b110, "cbeq">;11313 defm CBNE : CmpBranchRegister<0b111, "cbne">;11314 11315 def CBHGTWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b000, 0b11, "cbhgt">;11316 def CBHGEWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b001, 0b11, "cbhge">;11317 def CBHHIWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b010, 0b11, "cbhhi">;11318 def CBHHSWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b011, 0b11, "cbhhs">;11319 def CBHEQWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b110, 0b11, "cbheq">;11320 def CBHNEWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b111, 0b11, "cbhne">;11321 11322 def CBBGTWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b000, 0b10, "cbbgt">;11323 def CBBGEWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b001, 0b10, "cbbge">;11324 def CBBHIWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b010, 0b10, "cbbhi">;11325 def CBBHSWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b011, 0b10, "cbbhs">;11326 def CBBEQWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b110, 0b10, "cbbeq">;11327 def CBBNEWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b111, 0b10, "cbbne">;11328 11329 defm CBGT : CmpBranchImmediate<0b000, "uimm6", "cbgt">;11330 defm CBLT : CmpBranchImmediate<0b001, "uimm6", "cblt">;11331 defm CBHI : CmpBranchImmediate<0b010, "uimm6", "cbhi">;11332 defm CBLO : CmpBranchImmediate<0b011, "uimm6", "cblo">;11333 defm CBEQ : CmpBranchImmediate<0b110, "uimm6", "cbeq">;11334 defm CBNE : CmpBranchImmediate<0b111, "uimm6", "cbne">;11335 11336 defm : CmpBranchImmediateAlias<"cbge", "CBGT", "uimm6p1">;11337 defm : CmpBranchImmediateAlias<"cbhs", "CBHI", "uimm6p1">;11338 defm : CmpBranchImmediateAlias<"cble", "CBLT", "uimm6m1">;11339 defm : CmpBranchImmediateAlias<"cbls", "CBLO", "uimm6m1">;11340 11341 defm : CmpBranchRegisterAlias<"cble", "CBGE">;11342 defm : CmpBranchRegisterAlias<"cblo", "CBHI">;11343 defm : CmpBranchRegisterAlias<"cbls", "CBHS">;11344 defm : CmpBranchRegisterAlias<"cblt", "CBGT">;11345 11346 defm : CmpBranchWRegisterAlias<"cbble", "CBBGE">;11347 defm : CmpBranchWRegisterAlias<"cbblo", "CBBHI">;11348 defm : CmpBranchWRegisterAlias<"cbbls", "CBBHS">;11349 defm : CmpBranchWRegisterAlias<"cbblt", "CBBGT">;11350 11351 defm : CmpBranchWRegisterAlias<"cbhle", "CBHGE">;11352 defm : CmpBranchWRegisterAlias<"cbhlo", "CBHHI">;11353 defm : CmpBranchWRegisterAlias<"cbhls", "CBHHS">;11354 defm : CmpBranchWRegisterAlias<"cbhlt", "CBHGT">;11355 11356 // Pseudos for codegen11357 def CBBAssertExt : CmpBranchExtRegisterPseudo;11358 def CBHAssertExt : CmpBranchExtRegisterPseudo;11359 def CBWPrr : CmpBranchRegisterPseudo<GPR32>;11360 def CBXPrr : CmpBranchRegisterPseudo<GPR64>;11361 def CBWPri : CmpBranchImmediatePseudo<GPR32, uimm6_32b>;11362 def CBXPri : CmpBranchImmediatePseudo<GPR64, uimm6_64b>;11363 11364 def : Pat<(AArch64CB i32:$Cond, GPR32:$Rn, CmpBranchUImm6Operand_32b:$Imm,11365 bb:$Target),11366 (CBWPri i32:$Cond, GPR32:$Rn, uimm6_32b:$Imm, am_brcmpcond:$Target)>;11367 def : Pat<(AArch64CB i32:$Cond, GPR64:$Rn, CmpBranchUImm6Operand_64b:$Imm,11368 bb:$Target),11369 (CBXPri i32:$Cond, GPR64:$Rn, uimm6_64b:$Imm, am_brcmpcond:$Target)>;11370 def : Pat<(AArch64CB i32:$Cond, GPR32:$Rn, GPR32:$Rt, bb:$Target),11371 (CBWPrr ccode:$Cond, GPR32:$Rn, GPR32:$Rt, am_brcmpcond:$Target)>;11372 def : Pat<(AArch64CB i32:$Cond, GPR64:$Rn, GPR64:$Rt, bb:$Target),11373 (CBXPrr ccode:$Cond, GPR64:$Rn, GPR64:$Rt, am_brcmpcond:$Target)>;11374 11375 def : Pat<(AArch64CB i32:$Cond,11376 (CmpBranchBExtOperand GPR32:$Rn, simm8_32b:$ExtTypeRn),11377 (CmpBranchBExtOperand GPR32:$Rt, simm8_32b:$ExtTypeRt),11378 bb:$Target),11379 (CBBAssertExt ccode:$Cond, GPR32:$Rn, GPR32:$Rt, bb:$Target,11380 simm8_32b:$ExtTypeRn, simm8_32b:$ExtTypeRt)>;11381 11382 def : Pat<(AArch64CB i32:$Cond,11383 (CmpBranchHExtOperand GPR32:$Rn, simm8_32b:$ExtTypeRn),11384 (CmpBranchHExtOperand GPR32:$Rt, simm8_32b:$ExtTypeRt),11385 bb:$Target),11386 (CBHAssertExt ccode:$Cond, GPR32:$Rn, GPR32:$Rt, bb:$Target,11387 simm8_32b:$ExtTypeRn, simm8_32b:$ExtTypeRt)>;11388} // HasCMPBR11389 11390 11391//===-----------------------------------------------------===//11392// Atomic floating-point in-memory instructions (FEAT_LSFE)11393//===-----------------------------------------------------===//11394 11395let Predicates = [HasLSFE] in {11396 // Floating-point Atomic Load11397 defm LDFADDA : AtomicFPLoad<0b10, 0b000, "ldfadda">;11398 defm LDFADDAL : AtomicFPLoad<0b11, 0b000, "ldfaddal">;11399 defm LDFADD : AtomicFPLoad<0b00, 0b000, "ldfadd">;11400 defm LDFADDL : AtomicFPLoad<0b01, 0b000, "ldfaddl">;11401 defm LDFMAXA : AtomicFPLoad<0b10, 0b100, "ldfmaxa">;11402 defm LDFMAXAL : AtomicFPLoad<0b11, 0b100, "ldfmaxal">;11403 defm LDFMAX : AtomicFPLoad<0b00, 0b100, "ldfmax">;11404 defm LDFMAXL : AtomicFPLoad<0b01, 0b100, "ldfmaxl">;11405 defm LDFMINA : AtomicFPLoad<0b10, 0b101, "ldfmina">;11406 defm LDFMINAL : AtomicFPLoad<0b11, 0b101, "ldfminal">;11407 defm LDFMIN : AtomicFPLoad<0b00, 0b101, "ldfmin">;11408 defm LDFMINL : AtomicFPLoad<0b01, 0b101, "ldfminl">;11409 defm LDFMAXNMA : AtomicFPLoad<0b10, 0b110, "ldfmaxnma">;11410 defm LDFMAXNMAL : AtomicFPLoad<0b11, 0b110, "ldfmaxnmal">;11411 defm LDFMAXNM : AtomicFPLoad<0b00, 0b110, "ldfmaxnm">;11412 defm LDFMAXNML : AtomicFPLoad<0b01, 0b110, "ldfmaxnml">;11413 defm LDFMINNMA : AtomicFPLoad<0b10, 0b111, "ldfminnma">;11414 defm LDFMINNMAL : AtomicFPLoad<0b11, 0b111, "ldfminnmal">;11415 defm LDFMINNM : AtomicFPLoad<0b00, 0b111, "ldfminnm">;11416 defm LDFMINNML : AtomicFPLoad<0b01, 0b111, "ldfminnml">;11417 // BFloat1611418 def LDBFADDA : BaseAtomicFPLoad<FPR16, 0b00, 0b10, 0b000, "ldbfadda">;11419 def LDBFADDAL : BaseAtomicFPLoad<FPR16, 0b00, 0b11, 0b000, "ldbfaddal">;11420 def LDBFADD : BaseAtomicFPLoad<FPR16, 0b00, 0b00, 0b000, "ldbfadd">;11421 def LDBFADDL : BaseAtomicFPLoad<FPR16, 0b00, 0b01, 0b000, "ldbfaddl">;11422 def LDBFMAXA : BaseAtomicFPLoad<FPR16, 0b00, 0b10, 0b100, "ldbfmaxa">;11423 def LDBFMAXAL : BaseAtomicFPLoad<FPR16, 0b00, 0b11, 0b100, "ldbfmaxal">;11424 def LDBFMAX : BaseAtomicFPLoad<FPR16, 0b00, 0b00, 0b100, "ldbfmax">;11425 def LDBFMAXL : BaseAtomicFPLoad<FPR16, 0b00, 0b01, 0b100, "ldbfmaxl">;11426 def LDBFMINA : BaseAtomicFPLoad<FPR16, 0b00, 0b10, 0b101, "ldbfmina">;11427 def LDBFMINAL : BaseAtomicFPLoad<FPR16, 0b00, 0b11, 0b101, "ldbfminal">;11428 def LDBFMIN : BaseAtomicFPLoad<FPR16, 0b00, 0b00, 0b101, "ldbfmin">;11429 def LDBFMINL : BaseAtomicFPLoad<FPR16, 0b00, 0b01, 0b101, "ldbfminl">;11430 def LDBFMAXNMA : BaseAtomicFPLoad<FPR16, 0b00, 0b10, 0b110, "ldbfmaxnma">;11431 def LDBFMAXNMAL : BaseAtomicFPLoad<FPR16, 0b00, 0b11, 0b110, "ldbfmaxnmal">;11432 def LDBFMAXNM : BaseAtomicFPLoad<FPR16, 0b00, 0b00, 0b110, "ldbfmaxnm">;11433 def LDBFMAXNML : BaseAtomicFPLoad<FPR16, 0b00, 0b01, 0b110, "ldbfmaxnml">;11434 def LDBFMINNMA : BaseAtomicFPLoad<FPR16, 0b00, 0b10, 0b111, "ldbfminnma">;11435 def LDBFMINNMAL : BaseAtomicFPLoad<FPR16, 0b00, 0b11, 0b111, "ldbfminnmal">;11436 def LDBFMINNM : BaseAtomicFPLoad<FPR16, 0b00, 0b00, 0b111, "ldbfminnm">;11437 def LDBFMINNML : BaseAtomicFPLoad<FPR16, 0b00, 0b01, 0b111, "ldbfminnml">;11438 11439 // Floating-point Atomic Store11440 defm STFADD : AtomicFPStore<0b0, 0b000, "stfadd">;11441 defm STFADDL : AtomicFPStore<0b1, 0b000, "stfaddl">;11442 defm STFMAX : AtomicFPStore<0b0, 0b100, "stfmax">;11443 defm STFMAXL : AtomicFPStore<0b1, 0b100, "stfmaxl">;11444 defm STFMIN : AtomicFPStore<0b0, 0b101, "stfmin">;11445 defm STFMINL : AtomicFPStore<0b1, 0b101, "stfminl">;11446 defm STFMAXNM : AtomicFPStore<0b0, 0b110, "stfmaxnm">;11447 defm STFMAXNML : AtomicFPStore<0b1, 0b110, "stfmaxnml">;11448 defm STFMINNM : AtomicFPStore<0b0, 0b111, "stfminnm">;11449 defm STFMINNML : AtomicFPStore<0b1, 0b111, "stfminnml">;11450 // BFloat1611451 def STBFADD : BaseAtomicFPStore<FPR16, 0b00, 0b0, 0b000, "stbfadd">;11452 def STBFADDL : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b000, "stbfaddl">;11453 def STBFMAX : BaseAtomicFPStore<FPR16, 0b00, 0b0, 0b100, "stbfmax">;11454 def STBFMAXL : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b100, "stbfmaxl">;11455 def STBFMIN : BaseAtomicFPStore<FPR16, 0b00, 0b0, 0b101, "stbfmin">;11456 def STBFMINL : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b101, "stbfminl">;11457 def STBFMAXNM : BaseAtomicFPStore<FPR16, 0b00, 0b0, 0b110, "stbfmaxnm">;11458 def STBFMAXNML : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b110, "stbfmaxnml">;11459 def STBFMINNM : BaseAtomicFPStore<FPR16, 0b00, 0b0, 0b111, "stbfminnm">;11460 def STBFMINNML : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b111, "stbfminnml">;11461}11462 11463let Predicates = [HasF16F32DOT] in {11464 defm FDOT :SIMDThreeSameVectorFDot<"fdot">;11465 defm FDOTlane: SIMDThreeSameVectorFDOTIndex<"fdot">;11466}11467 11468let Predicates = [HasF16MM] in11469 defm FMMLA : SIMDThreeSameVectorFMLA<"fmmla">;11470 11471let Predicates = [HasF16F32MM] in11472 defm FMMLA : SIMDThreeSameVectorFMLAWiden<"fmmla">;11473 11474let Uses = [FPMR, FPCR] in11475 defm FMMLA : SIMDThreeSameVectorFP8MatrixMul<"fmmla", int_aarch64_neon_fmmla>;11476 11477//===----------------------------------------------------------------------===//11478// Contention Management Hints (FEAT_CMH)11479//===----------------------------------------------------------------------===//11480 11481let Predicates = [HasCMH] in {11482 defm SHUH : SHUH<"shuh">; // Shared Update Hint instruction11483 def STCPH : STCPHInst<"stcph">; // Store Concurrent Priority Hint instruction11484}11485 11486//===----------------------------------------------------------------------===//11487// Permission Overlays Extension 2 (FEAT_S1POE2)11488//===----------------------------------------------------------------------===//11489 11490let Predicates = [HasS1POE2] in {11491 defm TCHANGEBrr : TCHANGEReg<"tchangeb", true>;11492 defm TCHANGEFrr : TCHANGEReg<"tchangef", false>;11493 defm TCHANGEBri : TCHANGEImm<"tchangeb", true>;11494 defm TCHANGEFri : TCHANGEImm<"tchangef", false>;11495}11496 11497//===----------------------------------------------------------------------===//11498// TIndex Exception-like Vector (FEAT_TEV)11499//===----------------------------------------------------------------------===//11500 11501let Predicates = [HasTEV] in {11502 defm TENTER : TENTER<"tenter">;11503 defm TEXIT : TEXIT<"texit">;11504}11505 11506include "AArch64InstrAtomics.td"11507include "AArch64SVEInstrInfo.td"11508include "AArch64SMEInstrInfo.td"11509include "AArch64InstrGISel.td"11510