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1//=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9//10//===----------------------------------------------------------------------===//11 12/// General Purpose Registers: W, X.13def GPRRegBank : RegisterBank<"GPR", [XSeqPairsClass]>;14 15/// Floating Point, Vector, Scalable Vector Registers: B, H, S, D, Q, Z.16def FPRRegBank : RegisterBank<"FPR", [QQQQ, ZPR]>;17 18/// Conditional register: NZCV.19def CCRegBank : RegisterBank<"CC", [CCR]>;20