brintos / llvm-project-archived public Read only

1//=- AArch64RegisterInfo.td - Describe the AArch64 Registers -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9//10//===----------------------------------------------------------------------===//11 12 13class AArch64Reg<bits<16> enc, string n, list<Register> subregs = [],14               list<string> altNames = []>15        : Register<n, altNames> {16  let HWEncoding = enc;17  let Namespace = "AArch64";18  let SubRegs = subregs;19}20 21let Namespace = "AArch64" in {22  // SubRegIndexes for GPR registers23  def sub_32   : SubRegIndex<32>;24  def sube64   : SubRegIndex<64>;25  def subo64   : SubRegIndex<64>;26  def sube32   : SubRegIndex<32>;27  def subo32   : SubRegIndex<32>;28 29  // SubRegIndexes for FPR/Vector registers30  def bsub    : SubRegIndex<8, 0>;31  def hsub    : SubRegIndex<16, 0>;32  def ssub    : SubRegIndex<32, 0>;33  def dsub    : SubRegIndex<64, 0>;34  def zsub    : SubRegIndex<128, 0>;35 36  // The _hi SubRegIndexes describe the high bits of a register which are not37  // separately addressable. They need to be described so that partially38  // overlapping registers end up with a different lane mask. This is required39  // to enable subreg liveness tracking.40  //41  // For example: 8-bit B0 is a sub-register of 16-bit H0.42  // * B0 is described with 'bsub'.43  // * H0 is described with 'bsub + bsub_hi' == 'hsub'.44  def bsub_hi   : SubRegIndex<8, 8>;45  def hsub_hi   : SubRegIndex<16, 16>;46  def ssub_hi   : SubRegIndex<32, 32>;47  def dsub_hi   : SubRegIndex<64, 64>;48  def zsub_hi   : SubRegIndex<-1, 128>;49  // sub_32_hi describes the top 32 bits in e.g. X050  def sub_32_hi : SubRegIndex<32, 32>;51  // Note: Code depends on these having consecutive numbers52  def zsub0 : SubRegIndex<-1>;53  def zsub1 : SubRegIndex<-1>;54  def zsub2 : SubRegIndex<-1>;55  def zsub3 : SubRegIndex<-1>;56  // Note: Code depends on these having consecutive numbers57  def qsub0 : SubRegIndex<128>;58  def qsub1 : ComposedSubRegIndex<zsub1, zsub>;59  def qsub2 : ComposedSubRegIndex<zsub2, zsub>;60  def qsub3 : ComposedSubRegIndex<zsub3, zsub>;61  // Note: Code depends on these having consecutive numbers62  def dsub0 : SubRegIndex<64>;63  def dsub1 : ComposedSubRegIndex<qsub1, dsub>;64  def dsub2 : ComposedSubRegIndex<qsub2, dsub>;65  def dsub3 : ComposedSubRegIndex<qsub3, dsub>;66 67  // SubRegIndexes for SME Matrix tiles68  def zasubb  : SubRegIndex<2048>; // (16 x 16)/1 bytes  = 2048 bits69  def zasubh0 : SubRegIndex<1024>; // (16 x 16)/2 bytes  = 1024 bits70  def zasubh1 : SubRegIndex<1024>; // (16 x 16)/2 bytes  = 1024 bits71  def zasubs0 : SubRegIndex<512>;  // (16 x 16)/4 bytes  = 512 bits72  def zasubs1 : SubRegIndex<512>;  // (16 x 16)/4 bytes  = 512 bits73  def zasubd0 : SubRegIndex<256>;  // (16 x 16)/8 bytes  = 256 bits74  def zasubd1 : SubRegIndex<256>;  // (16 x 16)/8 bytes  = 256 bits75  def zasubq0 : SubRegIndex<128>;  // (16 x 16)/16 bytes = 128 bits76  def zasubq1 : SubRegIndex<128>;  // (16 x 16)/16 bytes = 128 bits77 78  // SubRegIndexes for SVE Predicates79  def psub  : SubRegIndex<-1>;80  // Note: Code depends on these having consecutive numbers81  def psub0 : SubRegIndex<-1>;82  def psub1 : SubRegIndex<-1>;83}84 85let Namespace = "AArch64" in {86  def vreg : RegAltNameIndex;87  def vlist1 : RegAltNameIndex;88}89 90//===----------------------------------------------------------------------===//91// Registers92//===----------------------------------------------------------------------===//93 94foreach i = 0-30 in {95  // Define W0_HI, W1_HI, .. W30_HI96  def W#i#_HI : AArch64Reg<-1,  "w"#i#"_hi"> { let isArtificial = 1; }97}98def WSP_HI : AArch64Reg<-1,  "wsp_hi"> { let isArtificial = 1; }99def WZR_HI : AArch64Reg<-1,  "wzr_hi"> { let isArtificial = 1; }100 101def W0    : AArch64Reg<0,   "w0" >, DwarfRegNum<[0]>;102def W1    : AArch64Reg<1,   "w1" >, DwarfRegNum<[1]>;103def W2    : AArch64Reg<2,   "w2" >, DwarfRegNum<[2]>;104def W3    : AArch64Reg<3,   "w3" >, DwarfRegNum<[3]>;105def W4    : AArch64Reg<4,   "w4" >, DwarfRegNum<[4]>;106def W5    : AArch64Reg<5,   "w5" >, DwarfRegNum<[5]>;107def W6    : AArch64Reg<6,   "w6" >, DwarfRegNum<[6]>;108def W7    : AArch64Reg<7,   "w7" >, DwarfRegNum<[7]>;109def W8    : AArch64Reg<8,   "w8" >, DwarfRegNum<[8]>;110def W9    : AArch64Reg<9,   "w9" >, DwarfRegNum<[9]>;111def W10   : AArch64Reg<10, "w10">, DwarfRegNum<[10]>;112def W11   : AArch64Reg<11, "w11">, DwarfRegNum<[11]>;113def W12   : AArch64Reg<12, "w12">, DwarfRegNum<[12]>;114def W13   : AArch64Reg<13, "w13">, DwarfRegNum<[13]>;115def W14   : AArch64Reg<14, "w14">, DwarfRegNum<[14]>;116def W15   : AArch64Reg<15, "w15">, DwarfRegNum<[15]>;117def W16   : AArch64Reg<16, "w16">, DwarfRegNum<[16]>;118def W17   : AArch64Reg<17, "w17">, DwarfRegNum<[17]>;119def W18   : AArch64Reg<18, "w18">, DwarfRegNum<[18]>;120def W19   : AArch64Reg<19, "w19">, DwarfRegNum<[19]>;121def W20   : AArch64Reg<20, "w20">, DwarfRegNum<[20]>;122def W21   : AArch64Reg<21, "w21">, DwarfRegNum<[21]>;123def W22   : AArch64Reg<22, "w22">, DwarfRegNum<[22]>;124def W23   : AArch64Reg<23, "w23">, DwarfRegNum<[23]>;125def W24   : AArch64Reg<24, "w24">, DwarfRegNum<[24]>;126def W25   : AArch64Reg<25, "w25">, DwarfRegNum<[25]>;127def W26   : AArch64Reg<26, "w26">, DwarfRegNum<[26]>;128def W27   : AArch64Reg<27, "w27">, DwarfRegNum<[27]>;129def W28   : AArch64Reg<28, "w28">, DwarfRegNum<[28]>;130def W29   : AArch64Reg<29, "w29">, DwarfRegNum<[29]>;131def W30   : AArch64Reg<30, "w30">, DwarfRegNum<[30]>;132def WSP   : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>;133def WZR   : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP> { let isConstant = true; }134 135let SubRegIndices = [sub_32, sub_32_hi], CoveredBySubRegs = 1 in {136def X0    : AArch64Reg<0,   "x0",  [W0,  W0_HI]>, DwarfRegAlias<W0>;137def X1    : AArch64Reg<1,   "x1",  [W1,  W1_HI]>, DwarfRegAlias<W1>;138def X2    : AArch64Reg<2,   "x2",  [W2,  W2_HI]>, DwarfRegAlias<W2>;139def X3    : AArch64Reg<3,   "x3",  [W3,  W3_HI]>, DwarfRegAlias<W3>;140def X4    : AArch64Reg<4,   "x4",  [W4,  W4_HI]>, DwarfRegAlias<W4>;141def X5    : AArch64Reg<5,   "x5",  [W5,  W5_HI]>, DwarfRegAlias<W5>;142def X6    : AArch64Reg<6,   "x6",  [W6,  W6_HI]>, DwarfRegAlias<W6>;143def X7    : AArch64Reg<7,   "x7",  [W7,  W7_HI]>, DwarfRegAlias<W7>;144def X8    : AArch64Reg<8,   "x8",  [W8,  W8_HI]>, DwarfRegAlias<W8>;145def X9    : AArch64Reg<9,   "x9",  [W9,  W9_HI]>, DwarfRegAlias<W9>;146def X10   : AArch64Reg<10, "x10", [W10, W10_HI]>, DwarfRegAlias<W10>;147def X11   : AArch64Reg<11, "x11", [W11, W11_HI]>, DwarfRegAlias<W11>;148def X12   : AArch64Reg<12, "x12", [W12, W12_HI]>, DwarfRegAlias<W12>;149def X13   : AArch64Reg<13, "x13", [W13, W13_HI]>, DwarfRegAlias<W13>;150def X14   : AArch64Reg<14, "x14", [W14, W14_HI]>, DwarfRegAlias<W14>;151def X15   : AArch64Reg<15, "x15", [W15, W15_HI]>, DwarfRegAlias<W15>;152def X16   : AArch64Reg<16, "x16", [W16, W16_HI]>, DwarfRegAlias<W16>;153def X17   : AArch64Reg<17, "x17", [W17, W17_HI]>, DwarfRegAlias<W17>;154def X18   : AArch64Reg<18, "x18", [W18, W18_HI]>, DwarfRegAlias<W18>;155def X19   : AArch64Reg<19, "x19", [W19, W19_HI]>, DwarfRegAlias<W19>;156def X20   : AArch64Reg<20, "x20", [W20, W20_HI]>, DwarfRegAlias<W20>;157def X21   : AArch64Reg<21, "x21", [W21, W21_HI]>, DwarfRegAlias<W21>;158def X22   : AArch64Reg<22, "x22", [W22, W22_HI]>, DwarfRegAlias<W22>;159def X23   : AArch64Reg<23, "x23", [W23, W23_HI]>, DwarfRegAlias<W23>;160def X24   : AArch64Reg<24, "x24", [W24, W24_HI]>, DwarfRegAlias<W24>;161def X25   : AArch64Reg<25, "x25", [W25, W25_HI]>, DwarfRegAlias<W25>;162def X26   : AArch64Reg<26, "x26", [W26, W26_HI]>, DwarfRegAlias<W26>;163def X27   : AArch64Reg<27, "x27", [W27, W27_HI]>, DwarfRegAlias<W27>;164def X28   : AArch64Reg<28, "x28", [W28, W28_HI]>, DwarfRegAlias<W28>;165def FP    : AArch64Reg<29, "x29", [W29, W29_HI]>, DwarfRegAlias<W29>;166def LR    : AArch64Reg<30, "x30", [W30, W30_HI]>, DwarfRegAlias<W30>;167def SP    : AArch64Reg<31, "sp",  [WSP, WSP_HI]>, DwarfRegAlias<WSP>;168def XZR   : AArch64Reg<31, "xzr", [WZR, WZR_HI]>, DwarfRegAlias<WSP> { let isConstant = true; }169}170 171// Condition code register.172def NZCV  : AArch64Reg<0, "nzcv">;173 174// First fault status register175def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>;176 177// Purely virtual Vector Granule (VG) Dwarf register178def VG : AArch64Reg<0, "vg">, DwarfRegNum<[46]>;179 180// Floating-point control register181def FPCR : AArch64Reg<0, "fpcr">;182 183// Floating-point Mode Register184def FPMR : AArch64Reg<0, "fpmr">;185 186// Floating-point status register.187def FPSR : AArch64Reg<0, "fpsr">;188 189// GPR register classes with the intersections of GPR32/GPR32sp and190// GPR64/GPR64sp for use by the coalescer.191def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> {192  let AltOrders = [(rotl GPR32common, 8)];193  let AltOrderSelect = [{ return 1; }];194}195def GPR64common : RegisterClass<"AArch64", [i64], 64,196                                (add (sequence "X%u", 0, 28), FP, LR)> {197  let AltOrders = [(rotl GPR64common, 8)];198  let AltOrderSelect = [{ return 1; }];199  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>";200}201// GPR register classes which exclude SP/WSP.202def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> {203  let AltOrders = [(rotl GPR32, 8)];204  let AltOrderSelect = [{ return 1; }];205  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>";206}207def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> {208  let AltOrders = [(rotl GPR64, 8)];209  let AltOrderSelect = [{ return 1; }];210  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>";211}212 213// GPR register classes which include SP/WSP.214def GPR32sp : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WSP)> {215  let AltOrders = [(rotl GPR32sp, 8)];216  let AltOrderSelect = [{ return 1; }];217  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>";218}219def GPR64sp : RegisterClass<"AArch64", [i64], 64, (add GPR64common, SP)> {220  let AltOrders = [(rotl GPR64sp, 8)];221  let AltOrderSelect = [{ return 1; }];222  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID,0, 32>";223}224 225def GPR32sponly : RegisterClass<"AArch64", [i32], 32, (add WSP)>;226def GPR64sponly : RegisterClass<"AArch64", [i64], 64, (add SP)>;227 228def GPR64spPlus0Operand : AsmOperandClass {229  let Name = "GPR64sp0";230  let RenderMethod = "addRegOperands";231  let PredicateMethod = "isGPR64<AArch64::GPR64spRegClassID>";232  let ParserMethod = "tryParseGPR64sp0Operand";233}234 235def GPR64sp0 : RegisterOperand<GPR64sp> {236  let ParserMatchClass = GPR64spPlus0Operand;237}238 239// GPR32/GPR64 but with zero-register substitution enabled.240// TODO: Roll this out to GPR32/GPR64/GPR32all/GPR64all.241def GPR32z : RegisterOperand<GPR32> {242  let GIZeroRegister = WZR;243}244def GPR64z : RegisterOperand<GPR64> {245  let GIZeroRegister = XZR;246}247 248// GPR argument registers.249def GPR32arg : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 7)>;250def GPR64arg : RegisterClass<"AArch64", [i64], 64, (sequence "X%u", 0, 7)>;251 252// GPR register classes which include WZR/XZR AND SP/WSP. This is not a253// constraint used by any instructions, it is used as a common super-class.254def GPR32all : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR, WSP)>;255def GPR64all : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR, SP)>;256 257// For tail calls, we can't use callee-saved registers, as they are restored258// to the saved value before the tail call, which would clobber a call address.259// This is for indirect tail calls to store the address of the destination.260def tcGPR64 : RegisterClass<"AArch64", [i64], 64, (sub GPR64common, X19, X20, X21,261                                                     X22, X23, X24, X25, X26,262                                                     X27, X28, FP, LR)>;263 264// Restricted sets of tail call registers, for use when branch target265// enforcement or PAuthLR are enabled.266// For BTI, x16 and x17 are the only registers which can be used to indirectly267// branch (not call) to the "BTI c" instruction at the start of a BTI-protected268// function.269// For PAuthLR, x16 must be used in the function epilogue for other purposes,270// so cannot hold the function pointer.271def tcGPRx17 : RegisterClass<"AArch64", [i64], 64, (add X17)>;272def tcGPRx16x17 : RegisterClass<"AArch64", [i64], 64, (add X16, X17)>;273def tcGPRnotx16 : RegisterClass<"AArch64", [i64], 64, (sub tcGPR64, X16)>;274// LR checking code expects either x16 or x17 to be available as a scratch275// register - for that reason restrict one of two register operands of276// AUTH_TCRETURN* pseudos.277def tcGPRnotx16x17 : RegisterClass<"AArch64", [i64], 64, (sub tcGPR64, X16, X17)>;278 279// Register set that excludes registers that are reserved for procedure calls.280// This is used for pseudo-instructions that are actually implemented using a281// procedure call.282def GPR64noip : RegisterClass<"AArch64", [i64], 64, (sub GPR64, X16, X17, LR)> {283  let AltOrders = [(rotl GPR64noip, 8)];284  let AltOrderSelect = [{ return 1; }];285}286 287// GPR register classes for post increment amount of vector load/store that288// has alternate printing when Rm=31 and prints a constant immediate value289// equal to the total number of bytes transferred.290 291// FIXME: TableGen *should* be able to do these itself now. There appears to be292// a bug in counting how many operands a Post-indexed MCInst should have which293// means the aliases don't trigger.294def GPR64pi1  : RegisterOperand<GPR64, "printPostIncOperand<1>">;295def GPR64pi2  : RegisterOperand<GPR64, "printPostIncOperand<2>">;296def GPR64pi3  : RegisterOperand<GPR64, "printPostIncOperand<3>">;297def GPR64pi4  : RegisterOperand<GPR64, "printPostIncOperand<4>">;298def GPR64pi6  : RegisterOperand<GPR64, "printPostIncOperand<6>">;299def GPR64pi8  : RegisterOperand<GPR64, "printPostIncOperand<8>">;300def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand<12>">;301def GPR64pi16 : RegisterOperand<GPR64, "printPostIncOperand<16>">;302def GPR64pi24 : RegisterOperand<GPR64, "printPostIncOperand<24>">;303def GPR64pi32 : RegisterOperand<GPR64, "printPostIncOperand<32>">;304def GPR64pi48 : RegisterOperand<GPR64, "printPostIncOperand<48>">;305def GPR64pi64 : RegisterOperand<GPR64, "printPostIncOperand<64>">;306 307// Condition code regclass.308defvar FlagsVT = i32;309def CCR : RegisterClass<"AArch64", [FlagsVT], 32, (add NZCV)> {310  let CopyCost = -1;  // Don't allow copying of status registers.311 312  // CCR is not allocatable.313  let isAllocatable = 0;314}315 316//===----------------------------------------------------------------------===//317// Floating Point Scalar Registers318//===----------------------------------------------------------------------===//319 320foreach i = 0-31 in {321  def B#i#_HI : AArch64Reg<-1,  "b"#i#"_hi"> { let isArtificial = 1; }322  def H#i#_HI : AArch64Reg<-1,  "h"#i#"_hi"> { let isArtificial = 1; }323  def S#i#_HI : AArch64Reg<-1,  "s"#i#"_hi"> { let isArtificial = 1; }324  def D#i#_HI : AArch64Reg<-1,  "d"#i#"_hi"> { let isArtificial = 1; }325  def Q#i#_HI : AArch64Reg<-1,  "q"#i#"_hi"> { let isArtificial = 1; }326}327 328def B0    : AArch64Reg<0,   "b0">, DwarfRegNum<[64]>;329def B1    : AArch64Reg<1,   "b1">, DwarfRegNum<[65]>;330def B2    : AArch64Reg<2,   "b2">, DwarfRegNum<[66]>;331def B3    : AArch64Reg<3,   "b3">, DwarfRegNum<[67]>;332def B4    : AArch64Reg<4,   "b4">, DwarfRegNum<[68]>;333def B5    : AArch64Reg<5,   "b5">, DwarfRegNum<[69]>;334def B6    : AArch64Reg<6,   "b6">, DwarfRegNum<[70]>;335def B7    : AArch64Reg<7,   "b7">, DwarfRegNum<[71]>;336def B8    : AArch64Reg<8,   "b8">, DwarfRegNum<[72]>;337def B9    : AArch64Reg<9,   "b9">, DwarfRegNum<[73]>;338def B10   : AArch64Reg<10, "b10">, DwarfRegNum<[74]>;339def B11   : AArch64Reg<11, "b11">, DwarfRegNum<[75]>;340def B12   : AArch64Reg<12, "b12">, DwarfRegNum<[76]>;341def B13   : AArch64Reg<13, "b13">, DwarfRegNum<[77]>;342def B14   : AArch64Reg<14, "b14">, DwarfRegNum<[78]>;343def B15   : AArch64Reg<15, "b15">, DwarfRegNum<[79]>;344def B16   : AArch64Reg<16, "b16">, DwarfRegNum<[80]>;345def B17   : AArch64Reg<17, "b17">, DwarfRegNum<[81]>;346def B18   : AArch64Reg<18, "b18">, DwarfRegNum<[82]>;347def B19   : AArch64Reg<19, "b19">, DwarfRegNum<[83]>;348def B20   : AArch64Reg<20, "b20">, DwarfRegNum<[84]>;349def B21   : AArch64Reg<21, "b21">, DwarfRegNum<[85]>;350def B22   : AArch64Reg<22, "b22">, DwarfRegNum<[86]>;351def B23   : AArch64Reg<23, "b23">, DwarfRegNum<[87]>;352def B24   : AArch64Reg<24, "b24">, DwarfRegNum<[88]>;353def B25   : AArch64Reg<25, "b25">, DwarfRegNum<[89]>;354def B26   : AArch64Reg<26, "b26">, DwarfRegNum<[90]>;355def B27   : AArch64Reg<27, "b27">, DwarfRegNum<[91]>;356def B28   : AArch64Reg<28, "b28">, DwarfRegNum<[92]>;357def B29   : AArch64Reg<29, "b29">, DwarfRegNum<[93]>;358def B30   : AArch64Reg<30, "b30">, DwarfRegNum<[94]>;359def B31   : AArch64Reg<31, "b31">, DwarfRegNum<[95]>;360 361let SubRegIndices = [bsub, bsub_hi] in {362def H0    : AArch64Reg<0,   "h0", [B0, B0_HI]>, DwarfRegAlias<B0>;363def H1    : AArch64Reg<1,   "h1", [B1, B1_HI]>, DwarfRegAlias<B1>;364def H2    : AArch64Reg<2,   "h2", [B2, B2_HI]>, DwarfRegAlias<B2>;365def H3    : AArch64Reg<3,   "h3", [B3, B3_HI]>, DwarfRegAlias<B3>;366def H4    : AArch64Reg<4,   "h4", [B4, B4_HI]>, DwarfRegAlias<B4>;367def H5    : AArch64Reg<5,   "h5", [B5, B5_HI]>, DwarfRegAlias<B5>;368def H6    : AArch64Reg<6,   "h6", [B6, B6_HI]>, DwarfRegAlias<B6>;369def H7    : AArch64Reg<7,   "h7", [B7, B7_HI]>, DwarfRegAlias<B7>;370def H8    : AArch64Reg<8,   "h8", [B8, B8_HI]>, DwarfRegAlias<B8>;371def H9    : AArch64Reg<9,   "h9", [B9, B9_HI]>, DwarfRegAlias<B9>;372def H10   : AArch64Reg<10, "h10", [B10, B10_HI]>, DwarfRegAlias<B10>;373def H11   : AArch64Reg<11, "h11", [B11, B11_HI]>, DwarfRegAlias<B11>;374def H12   : AArch64Reg<12, "h12", [B12, B12_HI]>, DwarfRegAlias<B12>;375def H13   : AArch64Reg<13, "h13", [B13, B13_HI]>, DwarfRegAlias<B13>;376def H14   : AArch64Reg<14, "h14", [B14, B14_HI]>, DwarfRegAlias<B14>;377def H15   : AArch64Reg<15, "h15", [B15, B15_HI]>, DwarfRegAlias<B15>;378def H16   : AArch64Reg<16, "h16", [B16, B16_HI]>, DwarfRegAlias<B16>;379def H17   : AArch64Reg<17, "h17", [B17, B17_HI]>, DwarfRegAlias<B17>;380def H18   : AArch64Reg<18, "h18", [B18, B18_HI]>, DwarfRegAlias<B18>;381def H19   : AArch64Reg<19, "h19", [B19, B19_HI]>, DwarfRegAlias<B19>;382def H20   : AArch64Reg<20, "h20", [B20, B20_HI]>, DwarfRegAlias<B20>;383def H21   : AArch64Reg<21, "h21", [B21, B21_HI]>, DwarfRegAlias<B21>;384def H22   : AArch64Reg<22, "h22", [B22, B22_HI]>, DwarfRegAlias<B22>;385def H23   : AArch64Reg<23, "h23", [B23, B23_HI]>, DwarfRegAlias<B23>;386def H24   : AArch64Reg<24, "h24", [B24, B24_HI]>, DwarfRegAlias<B24>;387def H25   : AArch64Reg<25, "h25", [B25, B25_HI]>, DwarfRegAlias<B25>;388def H26   : AArch64Reg<26, "h26", [B26, B26_HI]>, DwarfRegAlias<B26>;389def H27   : AArch64Reg<27, "h27", [B27, B27_HI]>, DwarfRegAlias<B27>;390def H28   : AArch64Reg<28, "h28", [B28, B28_HI]>, DwarfRegAlias<B28>;391def H29   : AArch64Reg<29, "h29", [B29, B29_HI]>, DwarfRegAlias<B29>;392def H30   : AArch64Reg<30, "h30", [B30, B30_HI]>, DwarfRegAlias<B30>;393def H31   : AArch64Reg<31, "h31", [B31, B31_HI]>, DwarfRegAlias<B31>;394}395 396let SubRegIndices = [hsub, hsub_hi] in {397def S0    : AArch64Reg<0,   "s0", [H0, H0_HI]>, DwarfRegAlias<B0>;398def S1    : AArch64Reg<1,   "s1", [H1, H1_HI]>, DwarfRegAlias<B1>;399def S2    : AArch64Reg<2,   "s2", [H2, H2_HI]>, DwarfRegAlias<B2>;400def S3    : AArch64Reg<3,   "s3", [H3, H3_HI]>, DwarfRegAlias<B3>;401def S4    : AArch64Reg<4,   "s4", [H4, H4_HI]>, DwarfRegAlias<B4>;402def S5    : AArch64Reg<5,   "s5", [H5, H5_HI]>, DwarfRegAlias<B5>;403def S6    : AArch64Reg<6,   "s6", [H6, H6_HI]>, DwarfRegAlias<B6>;404def S7    : AArch64Reg<7,   "s7", [H7, H7_HI]>, DwarfRegAlias<B7>;405def S8    : AArch64Reg<8,   "s8", [H8, H8_HI]>, DwarfRegAlias<B8>;406def S9    : AArch64Reg<9,   "s9", [H9, H9_HI]>, DwarfRegAlias<B9>;407def S10   : AArch64Reg<10, "s10", [H10, H10_HI]>, DwarfRegAlias<B10>;408def S11   : AArch64Reg<11, "s11", [H11, H11_HI]>, DwarfRegAlias<B11>;409def S12   : AArch64Reg<12, "s12", [H12, H12_HI]>, DwarfRegAlias<B12>;410def S13   : AArch64Reg<13, "s13", [H13, H13_HI]>, DwarfRegAlias<B13>;411def S14   : AArch64Reg<14, "s14", [H14, H14_HI]>, DwarfRegAlias<B14>;412def S15   : AArch64Reg<15, "s15", [H15, H15_HI]>, DwarfRegAlias<B15>;413def S16   : AArch64Reg<16, "s16", [H16, H16_HI]>, DwarfRegAlias<B16>;414def S17   : AArch64Reg<17, "s17", [H17, H17_HI]>, DwarfRegAlias<B17>;415def S18   : AArch64Reg<18, "s18", [H18, H18_HI]>, DwarfRegAlias<B18>;416def S19   : AArch64Reg<19, "s19", [H19, H19_HI]>, DwarfRegAlias<B19>;417def S20   : AArch64Reg<20, "s20", [H20, H20_HI]>, DwarfRegAlias<B20>;418def S21   : AArch64Reg<21, "s21", [H21, H21_HI]>, DwarfRegAlias<B21>;419def S22   : AArch64Reg<22, "s22", [H22, H22_HI]>, DwarfRegAlias<B22>;420def S23   : AArch64Reg<23, "s23", [H23, H23_HI]>, DwarfRegAlias<B23>;421def S24   : AArch64Reg<24, "s24", [H24, H24_HI]>, DwarfRegAlias<B24>;422def S25   : AArch64Reg<25, "s25", [H25, H25_HI]>, DwarfRegAlias<B25>;423def S26   : AArch64Reg<26, "s26", [H26, H26_HI]>, DwarfRegAlias<B26>;424def S27   : AArch64Reg<27, "s27", [H27, H27_HI]>, DwarfRegAlias<B27>;425def S28   : AArch64Reg<28, "s28", [H28, H28_HI]>, DwarfRegAlias<B28>;426def S29   : AArch64Reg<29, "s29", [H29, H29_HI]>, DwarfRegAlias<B29>;427def S30   : AArch64Reg<30, "s30", [H30, H30_HI]>, DwarfRegAlias<B30>;428def S31   : AArch64Reg<31, "s31", [H31, H31_HI]>, DwarfRegAlias<B31>;429}430 431let SubRegIndices = [ssub, ssub_hi], RegAltNameIndices = [vreg, vlist1] in {432def D0    : AArch64Reg<0,   "d0", [S0, S0_HI], ["v0", ""]>, DwarfRegAlias<B0>;433def D1    : AArch64Reg<1,   "d1", [S1, S1_HI], ["v1", ""]>, DwarfRegAlias<B1>;434def D2    : AArch64Reg<2,   "d2", [S2, S2_HI], ["v2", ""]>, DwarfRegAlias<B2>;435def D3    : AArch64Reg<3,   "d3", [S3, S3_HI], ["v3", ""]>, DwarfRegAlias<B3>;436def D4    : AArch64Reg<4,   "d4", [S4, S4_HI], ["v4", ""]>, DwarfRegAlias<B4>;437def D5    : AArch64Reg<5,   "d5", [S5, S5_HI], ["v5", ""]>, DwarfRegAlias<B5>;438def D6    : AArch64Reg<6,   "d6", [S6, S6_HI], ["v6", ""]>, DwarfRegAlias<B6>;439def D7    : AArch64Reg<7,   "d7", [S7, S7_HI], ["v7", ""]>, DwarfRegAlias<B7>;440def D8    : AArch64Reg<8,   "d8", [S8, S8_HI], ["v8", ""]>, DwarfRegAlias<B8>;441def D9    : AArch64Reg<9,   "d9", [S9, S9_HI], ["v9", ""]>, DwarfRegAlias<B9>;442def D10   : AArch64Reg<10, "d10", [S10, S10_HI], ["v10", ""]>, DwarfRegAlias<B10>;443def D11   : AArch64Reg<11, "d11", [S11, S11_HI], ["v11", ""]>, DwarfRegAlias<B11>;444def D12   : AArch64Reg<12, "d12", [S12, S12_HI], ["v12", ""]>, DwarfRegAlias<B12>;445def D13   : AArch64Reg<13, "d13", [S13, S13_HI], ["v13", ""]>, DwarfRegAlias<B13>;446def D14   : AArch64Reg<14, "d14", [S14, S14_HI], ["v14", ""]>, DwarfRegAlias<B14>;447def D15   : AArch64Reg<15, "d15", [S15, S15_HI], ["v15", ""]>, DwarfRegAlias<B15>;448def D16   : AArch64Reg<16, "d16", [S16, S16_HI], ["v16", ""]>, DwarfRegAlias<B16>;449def D17   : AArch64Reg<17, "d17", [S17, S17_HI], ["v17", ""]>, DwarfRegAlias<B17>;450def D18   : AArch64Reg<18, "d18", [S18, S18_HI], ["v18", ""]>, DwarfRegAlias<B18>;451def D19   : AArch64Reg<19, "d19", [S19, S19_HI], ["v19", ""]>, DwarfRegAlias<B19>;452def D20   : AArch64Reg<20, "d20", [S20, S20_HI], ["v20", ""]>, DwarfRegAlias<B20>;453def D21   : AArch64Reg<21, "d21", [S21, S21_HI], ["v21", ""]>, DwarfRegAlias<B21>;454def D22   : AArch64Reg<22, "d22", [S22, S22_HI], ["v22", ""]>, DwarfRegAlias<B22>;455def D23   : AArch64Reg<23, "d23", [S23, S23_HI], ["v23", ""]>, DwarfRegAlias<B23>;456def D24   : AArch64Reg<24, "d24", [S24, S24_HI], ["v24", ""]>, DwarfRegAlias<B24>;457def D25   : AArch64Reg<25, "d25", [S25, S25_HI], ["v25", ""]>, DwarfRegAlias<B25>;458def D26   : AArch64Reg<26, "d26", [S26, S26_HI], ["v26", ""]>, DwarfRegAlias<B26>;459def D27   : AArch64Reg<27, "d27", [S27, S27_HI], ["v27", ""]>, DwarfRegAlias<B27>;460def D28   : AArch64Reg<28, "d28", [S28, S28_HI], ["v28", ""]>, DwarfRegAlias<B28>;461def D29   : AArch64Reg<29, "d29", [S29, S29_HI], ["v29", ""]>, DwarfRegAlias<B29>;462def D30   : AArch64Reg<30, "d30", [S30, S30_HI], ["v30", ""]>, DwarfRegAlias<B30>;463def D31   : AArch64Reg<31, "d31", [S31, S31_HI], ["v31", ""]>, DwarfRegAlias<B31>;464}465 466let SubRegIndices = [dsub, dsub_hi], RegAltNameIndices = [vreg, vlist1] in {467def Q0    : AArch64Reg<0,   "q0", [D0, D0_HI], ["v0", ""]>, DwarfRegAlias<B0>;468def Q1    : AArch64Reg<1,   "q1", [D1, D1_HI], ["v1", ""]>, DwarfRegAlias<B1>;469def Q2    : AArch64Reg<2,   "q2", [D2, D2_HI], ["v2", ""]>, DwarfRegAlias<B2>;470def Q3    : AArch64Reg<3,   "q3", [D3, D3_HI], ["v3", ""]>, DwarfRegAlias<B3>;471def Q4    : AArch64Reg<4,   "q4", [D4, D4_HI], ["v4", ""]>, DwarfRegAlias<B4>;472def Q5    : AArch64Reg<5,   "q5", [D5, D5_HI], ["v5", ""]>, DwarfRegAlias<B5>;473def Q6    : AArch64Reg<6,   "q6", [D6, D6_HI], ["v6", ""]>, DwarfRegAlias<B6>;474def Q7    : AArch64Reg<7,   "q7", [D7, D7_HI], ["v7", ""]>, DwarfRegAlias<B7>;475def Q8    : AArch64Reg<8,   "q8", [D8, D8_HI], ["v8", ""]>, DwarfRegAlias<B8>;476def Q9    : AArch64Reg<9,   "q9", [D9, D9_HI], ["v9", ""]>, DwarfRegAlias<B9>;477def Q10   : AArch64Reg<10, "q10", [D10, D10_HI], ["v10", ""]>, DwarfRegAlias<B10>;478def Q11   : AArch64Reg<11, "q11", [D11, D11_HI], ["v11", ""]>, DwarfRegAlias<B11>;479def Q12   : AArch64Reg<12, "q12", [D12, D12_HI], ["v12", ""]>, DwarfRegAlias<B12>;480def Q13   : AArch64Reg<13, "q13", [D13, D13_HI], ["v13", ""]>, DwarfRegAlias<B13>;481def Q14   : AArch64Reg<14, "q14", [D14, D14_HI], ["v14", ""]>, DwarfRegAlias<B14>;482def Q15   : AArch64Reg<15, "q15", [D15, D15_HI], ["v15", ""]>, DwarfRegAlias<B15>;483def Q16   : AArch64Reg<16, "q16", [D16, D16_HI], ["v16", ""]>, DwarfRegAlias<B16>;484def Q17   : AArch64Reg<17, "q17", [D17, D17_HI], ["v17", ""]>, DwarfRegAlias<B17>;485def Q18   : AArch64Reg<18, "q18", [D18, D18_HI], ["v18", ""]>, DwarfRegAlias<B18>;486def Q19   : AArch64Reg<19, "q19", [D19, D19_HI], ["v19", ""]>, DwarfRegAlias<B19>;487def Q20   : AArch64Reg<20, "q20", [D20, D20_HI], ["v20", ""]>, DwarfRegAlias<B20>;488def Q21   : AArch64Reg<21, "q21", [D21, D21_HI], ["v21", ""]>, DwarfRegAlias<B21>;489def Q22   : AArch64Reg<22, "q22", [D22, D22_HI], ["v22", ""]>, DwarfRegAlias<B22>;490def Q23   : AArch64Reg<23, "q23", [D23, D23_HI], ["v23", ""]>, DwarfRegAlias<B23>;491def Q24   : AArch64Reg<24, "q24", [D24, D24_HI], ["v24", ""]>, DwarfRegAlias<B24>;492def Q25   : AArch64Reg<25, "q25", [D25, D25_HI], ["v25", ""]>, DwarfRegAlias<B25>;493def Q26   : AArch64Reg<26, "q26", [D26, D26_HI], ["v26", ""]>, DwarfRegAlias<B26>;494def Q27   : AArch64Reg<27, "q27", [D27, D27_HI], ["v27", ""]>, DwarfRegAlias<B27>;495def Q28   : AArch64Reg<28, "q28", [D28, D28_HI], ["v28", ""]>, DwarfRegAlias<B28>;496def Q29   : AArch64Reg<29, "q29", [D29, D29_HI], ["v29", ""]>, DwarfRegAlias<B29>;497def Q30   : AArch64Reg<30, "q30", [D30, D30_HI], ["v30", ""]>, DwarfRegAlias<B30>;498def Q31   : AArch64Reg<31, "q31", [D31, D31_HI], ["v31", ""]>, DwarfRegAlias<B31>;499}500 501def FPR8  : RegisterClass<"AArch64", [i8, aarch64mfp8], 8, (sequence "B%u", 0, 31)> {502  let Size = 8;503  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>";504}505def FPR16 : RegisterClass<"AArch64", [f16, bf16, i16], 16, (sequence "H%u", 0, 31)> {506  let Size = 16;507  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>";508}509 510def FPR16_lo : RegisterClass<"AArch64", [f16], 16, (trunc FPR16, 16)> {511  let Size = 16;512}513def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)> {514  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>";515}516def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,517                                      v1i64, v4f16, v4bf16],518                                     64, (sequence "D%u", 0, 31)> {519  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>";520}521def FPR64_lo : RegisterClass<"AArch64",522                             [v8i8, v4i16, v2i32, v1i64, v4f16, v4bf16, v2f32,523                              v1f64],524                             64, (trunc FPR64, 16)>;525 526// We don't (yet) have an f128 legal type, so don't use that here. We527// normalize 128-bit vectors to v2f64 for arg passing and such, so use528// that here.529def FPR128 : RegisterClass<"AArch64",530                           [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, f128,531                            v8f16, v8bf16],532                           128, (sequence "Q%u", 0, 31)> {533  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>";534}535 536// The lower 16 vector registers.  Some instructions can only take registers537// in this range.538def FPR128_lo : RegisterClass<"AArch64",539                              [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16,540                               v8bf16],541                              128, (trunc FPR128, 16)> {542  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 16>";543}544 545// The lower 8 vector registers.  Some instructions can only take registers546// in this range.547def FPR128_0to7 : RegisterClass<"AArch64",548                                [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16,549                                 v8bf16],550                                128, (trunc FPR128, 8)> {551  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 8>";552}553 554// Pairs, triples, and quads of 64-bit vector registers.555def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;556def DSeqTriples : RegisterTuples<[dsub0, dsub1, dsub2],557                                 [(rotl FPR64, 0), (rotl FPR64, 1),558                                  (rotl FPR64, 2)]>;559def DSeqQuads : RegisterTuples<[dsub0, dsub1, dsub2, dsub3],560                               [(rotl FPR64, 0), (rotl FPR64, 1),561                                (rotl FPR64, 2), (rotl FPR64, 3)]>;562def DD   : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> {563  let Size = 128;564  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::DDRegClassID, 0, 32>";565}566def DDD  : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {567  let Size = 192;568  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::DDDRegClassID, 0, 32>";569}570def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {571  let Size = 256;572  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::DDDDRegClassID, 0, 32>";573}574 575// Pairs, triples, and quads of 128-bit vector registers.576def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>;577def QSeqTriples : RegisterTuples<[qsub0, qsub1, qsub2],578                                 [(rotl FPR128, 0), (rotl FPR128, 1),579                                  (rotl FPR128, 2)]>;580def QSeqQuads : RegisterTuples<[qsub0, qsub1, qsub2, qsub3],581                               [(rotl FPR128, 0), (rotl FPR128, 1),582                                (rotl FPR128, 2), (rotl FPR128, 3)]>;583def QQ   : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> {584  let Size = 256;585  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::QQRegClassID, 0, 32>";586}587def QQQ  : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> {588  let Size = 384;589  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::QQQRegClassID, 0, 32>";590}591def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {592  let Size = 512;593  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::QQQQRegClassID, 0, 32>";594}595 596 597// Vector operand versions of the FP registers. Alternate name printing and598// assembler matching.599def VectorReg64AsmOperand : AsmOperandClass {600  let Name = "VectorReg64";601  let PredicateMethod = "isNeonVectorReg";602}603def VectorReg128AsmOperand : AsmOperandClass {604  let Name = "VectorReg128";605  let PredicateMethod = "isNeonVectorReg";606}607 608def V64  : RegisterOperand<FPR64, "printVRegOperand"> {609  let ParserMatchClass = VectorReg64AsmOperand;610}611 612def V128 : RegisterOperand<FPR128, "printVRegOperand"> {613  let ParserMatchClass = VectorReg128AsmOperand;614}615 616def VectorRegLoAsmOperand : AsmOperandClass {617  let Name = "VectorRegLo";618  let PredicateMethod = "isNeonVectorRegLo";619}620def V64_lo : RegisterOperand<FPR64_lo, "printVRegOperand"> {621  let ParserMatchClass = VectorRegLoAsmOperand;622}623def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> {624  let ParserMatchClass = VectorRegLoAsmOperand;625}626 627def VectorReg0to7AsmOperand : AsmOperandClass {628  let Name = "VectorReg0to7";629  let PredicateMethod = "isNeonVectorReg0to7";630}631 632def V128_0to7 : RegisterOperand<FPR128_0to7, "printVRegOperand"> {633  let ParserMatchClass = VectorReg0to7AsmOperand;634}635 636class TypedVecListAsmOperand<int count, string vecty, int lanes, int eltsize>637    : AsmOperandClass {638  let Name = "TypedVectorList" # count # "_" # lanes # eltsize;639 640  let PredicateMethod641      = "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";642  let RenderMethod = "addVectorListOperands<" # vecty  # ", "  # count # ">";643}644 645class TypedVecListRegOperand<RegisterClass Reg, int lanes, string eltsize>646    : RegisterOperand<Reg, "printTypedVectorList<" # lanes # ", '"647                                                   # eltsize # "'>">;648 649multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {650  // With implicit types (probably on instruction instead). E.g. { v0, v1 } or {v0, v2, v4}.651  def _64AsmOperand : AsmOperandClass {652    let Name = NAME # "64";653    let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";654    let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_DReg, " # count # ">";655  }656 657  def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {658    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_64AsmOperand");659  }660 661  def _128AsmOperand : AsmOperandClass {662    let Name = NAME # "128";663    let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";664    let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_QReg, " # count # ">";665  }666 667  def "128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {668    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_128AsmOperand");669  }670 671  // With implicit types (probably on instruction instead), consecutive registers. E.g. { v0, v1, v2 }672  def _Consecutive128AsmOperand : AsmOperandClass {673    let Name = NAME # "Consecutive128";674    let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ", true>";675    let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_QReg, " # count # ", true>";676  }677 678  def "Consecutive128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {679    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_Consecutive128AsmOperand");680  }681 682  // 64-bit register lists with explicit type.683 684  // { v0.8b, v1.8b }685  def _8bAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_DReg", 8, 8>;686  def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {687    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_8bAsmOperand");688  }689 690  // { v0.4h, v1.4h }691  def _4hAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_DReg", 4, 16>;692  def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {693    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_4hAsmOperand");694  }695 696  // { v0.2s, v1.2s }697  def _2sAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_DReg", 2, 32>;698  def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {699    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_2sAsmOperand");700  }701 702  // { v0.1d, v1.1d }703  def _1dAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_DReg", 1, 64>;704  def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {705    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_1dAsmOperand");706  }707 708  // 128-bit register lists with explicit type709 710  // { v0.16b, v1.16b }711  def _16bAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 16, 8>;712  def "16b" : TypedVecListRegOperand<Reg128, 16, "b"> {713    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_16bAsmOperand");714  }715 716  // { v0.8h, v1.8h }717  def _8hAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 8, 16>;718  def "8h" : TypedVecListRegOperand<Reg128, 8, "h"> {719    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_8hAsmOperand");720  }721 722  // { v0.4s, v1.4s }723  def _4sAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 4, 32>;724  def "4s" : TypedVecListRegOperand<Reg128, 4, "s"> {725    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_4sAsmOperand");726  }727 728  // { v0.2d, v1.2d }729  def _2dAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 2, 64>;730  def "2d" : TypedVecListRegOperand<Reg128, 2, "d"> {731    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_2dAsmOperand");732  }733 734  // { v0.b, v1.b }735  def _bAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 0, 8>;736  def "b" : TypedVecListRegOperand<Reg128, 0, "b"> {737    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_bAsmOperand");738  }739 740  // { v0.h, v1.h }741  def _hAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 0, 16>;742  def "h" : TypedVecListRegOperand<Reg128, 0, "h"> {743    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_hAsmOperand");744  }745 746  // { v0.s, v1.s }747  def _sAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 0, 32>;748  def "s" : TypedVecListRegOperand<Reg128, 0, "s"> {749    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_sAsmOperand");750  }751 752  // { v0.d, v1.d }753  def _dAsmOperand : TypedVecListAsmOperand<count, "AArch64Operand::VecListIdx_QReg", 0, 64>;754  def "d" : TypedVecListRegOperand<Reg128, 0, "d"> {755    let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_dAsmOperand");756  }757 758 759}760 761defm VecListOne   : VectorList<1, FPR64, FPR128>;762defm VecListTwo   : VectorList<2, DD,    QQ>;763defm VecListThree : VectorList<3, DDD,   QQQ>;764defm VecListFour  : VectorList<4, DDDD,  QQQQ>;765 766class FPRAsmOperand<string RC> : AsmOperandClass {767  let Name = "FPRAsmOperand" # RC;768  let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";769  let RenderMethod = "addRegOperands";770}771 772// Register operand versions of the scalar FP registers.773def FPR8Op  : RegisterOperand<FPR8, "printOperand"> {774  let ParserMatchClass = FPRAsmOperand<"FPR8">;775}776 777def FPR16Op  : RegisterOperand<FPR16, "printOperand"> {778  let ParserMatchClass = FPRAsmOperand<"FPR16">;779}780 781def FPR16Op_lo  : RegisterOperand<FPR16_lo, "printOperand"> {782  let ParserMatchClass = FPRAsmOperand<"FPR16_lo">;783}784 785def FPR32Op  : RegisterOperand<FPR32, "printOperand"> {786  let ParserMatchClass = FPRAsmOperand<"FPR32">;787}788 789def FPR64Op  : RegisterOperand<FPR64, "printOperand"> {790  let ParserMatchClass = FPRAsmOperand<"FPR64">;791}792 793def FPR128Op : RegisterOperand<FPR128, "printOperand"> {794  let ParserMatchClass = FPRAsmOperand<"FPR128">;795}796 797//===----------------------------------------------------------------------===//798// ARMv8.1a atomic CASP register operands799 800 801def WSeqPairs : RegisterTuples<[sube32, subo32],802                               [(decimate (rotl GPR32, 0), 2),803                                (decimate (rotl GPR32, 1), 2)]>;804def XSeqPairs : RegisterTuples<[sube64, subo64],805                               [(decimate (rotl GPR64, 0), 2),806                                (decimate (rotl GPR64, 1), 2)]>;807 808def WSeqPairsClass   : RegisterClass<"AArch64", [untyped], 32,809                                     (add WSeqPairs)>{810  let Size = 64;811}812def XSeqPairsClass   : RegisterClass<"AArch64", [untyped], 64,813                                     (add XSeqPairs)>{814  let Size = 128;815}816 817 818let RenderMethod = "addRegOperands", ParserMethod="tryParseGPRSeqPair" in {819  def WSeqPairsAsmOperandClass : AsmOperandClass { let Name = "WSeqPair"; }820  def XSeqPairsAsmOperandClass : AsmOperandClass { let Name = "XSeqPair"; }821}822 823def WSeqPairClassOperand :824    RegisterOperand<WSeqPairsClass, "printGPRSeqPairsClassOperand<32>"> {825  let ParserMatchClass = WSeqPairsAsmOperandClass;826}827def XSeqPairClassOperand :828    RegisterOperand<XSeqPairsClass, "printGPRSeqPairsClassOperand<64>"> {829  let ParserMatchClass = XSeqPairsAsmOperandClass;830}831// Reuse the parsing and register numbers from XSeqPairs, but encoding is different.832def MrrsMssrPairClassOperand :833    RegisterOperand<XSeqPairsClass, "printGPRSeqPairsClassOperand<64>"> {834  let ParserMatchClass = XSeqPairsAsmOperandClass;835}836def SyspXzrPairOperandMatcherClass : AsmOperandClass {837  let Name = "SyspXzrPair";838  let RenderMethod = "addSyspXzrPairOperand";839  let ParserMethod = "tryParseSyspXzrPair";840}841def SyspXzrPairOperand :842    RegisterOperand<GPR64, "printSyspXzrPair"> { // needed to allow alias with XZR operand843  let ParserMatchClass = SyspXzrPairOperandMatcherClass;844}845 846 847 848//===----- END: v8.1a atomic CASP register operands -----------------------===//849 850//===----------------------------------------------------------------------===//851// Armv8.7a accelerator extension register operands: 8 consecutive GPRs852// starting with an even one853 854let Namespace = "AArch64" in {855  foreach i = 0-7 in856    def "x8sub_"#i : SubRegIndex<64, !mul(64, i)>;857}858 859def Tuples8X : RegisterTuples<860  !foreach(i, [0,1,2,3,4,5,6,7], !cast<SubRegIndex>("x8sub_"#i)),861  !foreach(i, [0,1,2,3,4,5,6,7], (trunc (decimate (rotl GPR64, i), 2), 12))>;862 863def GPR64x8Class : RegisterClass<"AArch64", [i64x8], 512, (trunc Tuples8X, 12)> {864  let Size = 512;865}866def GPR64x8AsmOp : AsmOperandClass {867  let Name = "GPR64x8";868  let ParserMethod = "tryParseGPR64x8";869  let RenderMethod = "addRegOperands";870}871def GPR64x8 : RegisterOperand<GPR64x8Class, "printGPR64x8"> {872  let ParserMatchClass = GPR64x8AsmOp;873  let PrintMethod = "printGPR64x8";874}875 876//===----- END: v8.7a accelerator extension register operands -------------===//877 878// SVE predicate-as-counter registers879  def PN0    : AArch64Reg<0,   "pn0">, DwarfRegNum<[48]>;880  def PN1    : AArch64Reg<1,   "pn1">, DwarfRegNum<[49]>;881  def PN2    : AArch64Reg<2,   "pn2">, DwarfRegNum<[50]>;882  def PN3    : AArch64Reg<3,   "pn3">, DwarfRegNum<[51]>;883  def PN4    : AArch64Reg<4,   "pn4">, DwarfRegNum<[52]>;884  def PN5    : AArch64Reg<5,   "pn5">, DwarfRegNum<[53]>;885  def PN6    : AArch64Reg<6,   "pn6">, DwarfRegNum<[54]>;886  def PN7    : AArch64Reg<7,   "pn7">, DwarfRegNum<[55]>;887  def PN8    : AArch64Reg<8,   "pn8">, DwarfRegNum<[56]>;888  def PN9    : AArch64Reg<9,   "pn9">, DwarfRegNum<[57]>;889  def PN10   : AArch64Reg<10, "pn10">, DwarfRegNum<[58]>;890  def PN11   : AArch64Reg<11, "pn11">, DwarfRegNum<[59]>;891  def PN12   : AArch64Reg<12, "pn12">, DwarfRegNum<[60]>;892  def PN13   : AArch64Reg<13, "pn13">, DwarfRegNum<[61]>;893  def PN14   : AArch64Reg<14, "pn14">, DwarfRegNum<[62]>;894  def PN15   : AArch64Reg<15, "pn15">, DwarfRegNum<[63]>;895 896// SVE predicate registers897let SubRegIndices = [psub] in {898  def P0    : AArch64Reg<0,   "p0", [PN0]>, DwarfRegAlias<PN0>;899  def P1    : AArch64Reg<1,   "p1", [PN1]>, DwarfRegAlias<PN1>;900  def P2    : AArch64Reg<2,   "p2", [PN2]>, DwarfRegAlias<PN2>;901  def P3    : AArch64Reg<3,   "p3", [PN3]>, DwarfRegAlias<PN3>;902  def P4    : AArch64Reg<4,   "p4", [PN4]>, DwarfRegAlias<PN4>;903  def P5    : AArch64Reg<5,   "p5", [PN5]>, DwarfRegAlias<PN5>;904  def P6    : AArch64Reg<6,   "p6", [PN6]>, DwarfRegAlias<PN6>;905  def P7    : AArch64Reg<7,   "p7", [PN7]>, DwarfRegAlias<PN7>;906  def P8    : AArch64Reg<8,   "p8", [PN8]>, DwarfRegAlias<PN8>;907  def P9    : AArch64Reg<9,   "p9", [PN9]>, DwarfRegAlias<PN9>;908  def P10   : AArch64Reg<10, "p10", [PN10]>, DwarfRegAlias<PN10>;909  def P11   : AArch64Reg<11, "p11", [PN11]>, DwarfRegAlias<PN11>;910  def P12   : AArch64Reg<12, "p12", [PN12]>, DwarfRegAlias<PN12>;911  def P13   : AArch64Reg<13, "p13", [PN13]>, DwarfRegAlias<PN13>;912  def P14   : AArch64Reg<14, "p14", [PN14]>, DwarfRegAlias<PN14>;913  def P15   : AArch64Reg<15, "p15", [PN15]>, DwarfRegAlias<PN15>;914}915 916// SVE variable-size vector registers917let SubRegIndices = [zsub, zsub_hi] in {918def Z0    : AArch64Reg<0,   "z0",  [Q0, Q0_HI]>, DwarfRegNum<[96]>;919def Z1    : AArch64Reg<1,   "z1",  [Q1, Q1_HI]>, DwarfRegNum<[97]>;920def Z2    : AArch64Reg<2,   "z2",  [Q2, Q2_HI]>, DwarfRegNum<[98]>;921def Z3    : AArch64Reg<3,   "z3",  [Q3, Q3_HI]>, DwarfRegNum<[99]>;922def Z4    : AArch64Reg<4,   "z4",  [Q4, Q4_HI]>, DwarfRegNum<[100]>;923def Z5    : AArch64Reg<5,   "z5",  [Q5, Q5_HI]>, DwarfRegNum<[101]>;924def Z6    : AArch64Reg<6,   "z6",  [Q6, Q6_HI]>, DwarfRegNum<[102]>;925def Z7    : AArch64Reg<7,   "z7",  [Q7, Q7_HI]>, DwarfRegNum<[103]>;926def Z8    : AArch64Reg<8,   "z8",  [Q8, Q8_HI]>, DwarfRegNum<[104]>;927def Z9    : AArch64Reg<9,   "z9",  [Q9, Q9_HI]>, DwarfRegNum<[105]>;928def Z10   : AArch64Reg<10, "z10", [Q10, Q10_HI]>, DwarfRegNum<[106]>;929def Z11   : AArch64Reg<11, "z11", [Q11, Q11_HI]>, DwarfRegNum<[107]>;930def Z12   : AArch64Reg<12, "z12", [Q12, Q12_HI]>, DwarfRegNum<[108]>;931def Z13   : AArch64Reg<13, "z13", [Q13, Q13_HI]>, DwarfRegNum<[109]>;932def Z14   : AArch64Reg<14, "z14", [Q14, Q14_HI]>, DwarfRegNum<[110]>;933def Z15   : AArch64Reg<15, "z15", [Q15, Q15_HI]>, DwarfRegNum<[111]>;934def Z16   : AArch64Reg<16, "z16", [Q16, Q16_HI]>, DwarfRegNum<[112]>;935def Z17   : AArch64Reg<17, "z17", [Q17, Q17_HI]>, DwarfRegNum<[113]>;936def Z18   : AArch64Reg<18, "z18", [Q18, Q18_HI]>, DwarfRegNum<[114]>;937def Z19   : AArch64Reg<19, "z19", [Q19, Q19_HI]>, DwarfRegNum<[115]>;938def Z20   : AArch64Reg<20, "z20", [Q20, Q20_HI]>, DwarfRegNum<[116]>;939def Z21   : AArch64Reg<21, "z21", [Q21, Q21_HI]>, DwarfRegNum<[117]>;940def Z22   : AArch64Reg<22, "z22", [Q22, Q22_HI]>, DwarfRegNum<[118]>;941def Z23   : AArch64Reg<23, "z23", [Q23, Q23_HI]>, DwarfRegNum<[119]>;942def Z24   : AArch64Reg<24, "z24", [Q24, Q24_HI]>, DwarfRegNum<[120]>;943def Z25   : AArch64Reg<25, "z25", [Q25, Q25_HI]>, DwarfRegNum<[121]>;944def Z26   : AArch64Reg<26, "z26", [Q26, Q26_HI]>, DwarfRegNum<[122]>;945def Z27   : AArch64Reg<27, "z27", [Q27, Q27_HI]>, DwarfRegNum<[123]>;946def Z28   : AArch64Reg<28, "z28", [Q28, Q28_HI]>, DwarfRegNum<[124]>;947def Z29   : AArch64Reg<29, "z29", [Q29, Q29_HI]>, DwarfRegNum<[125]>;948def Z30   : AArch64Reg<30, "z30", [Q30, Q30_HI]>, DwarfRegNum<[126]>;949def Z31   : AArch64Reg<31, "z31", [Q31, Q31_HI]>, DwarfRegNum<[127]>;950}951 952// Enum describing the element size for destructive953// operations.954class ElementSizeEnum<bits<3> val> {955  bits<3> Value = val;956}957 958def ElementSizeNone : ElementSizeEnum<0>;959def ElementSizeB    : ElementSizeEnum<1>;960def ElementSizeH    : ElementSizeEnum<2>;961def ElementSizeS    : ElementSizeEnum<3>;962def ElementSizeD    : ElementSizeEnum<4>;963def ElementSizeQ    : ElementSizeEnum<5>;  // Unused964 965class SVERegOp <string Suffix, AsmOperandClass C,966                ElementSizeEnum Size,967                RegisterClass RC> : RegisterOperand<RC> {968  ElementSizeEnum ElementSize;969 970  let ElementSize = Size;971  let PrintMethod = !if(!eq(Suffix, ""),972                        "printSVERegOp<>",973                        "printSVERegOp<'" # Suffix # "'>");974  let ParserMatchClass = C;975}976 977class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,978                RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}979 980//******************************************************************************981 982// SVE predicate register classes.983class PPRClass<int firstreg, int lastreg, int step = 1> : RegisterClass<"AArch64",984                                  [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1 ], 16,985                                  (sequence "P%u", firstreg, lastreg, step)> {986  let Size = 16;987}988 989def PPR    : PPRClass<0, 15> {990  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PPRRegClassID, 0, 16>";991}992def PPR_3b : PPRClass<0, 7> { // Restricted 3 bit SVE predicate register class.993  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PPRRegClassID, 0, 8>";994}995def PPR_p8to15 : PPRClass<8, 15> {996  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PPRRegClassID, 8, 8>";997}998 999def PPRMul2 : PPRClass<0, 14, 2>;1000 1001class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {1002  let Name = "SVE" # name # "Reg";1003  let PredicateMethod = "isSVEPredicateVectorRegOfWidth<"1004                            # Width # ", " # "AArch64::" # RegClass # "RegClassID>";1005  let DiagnosticType = "InvalidSVE" # name # "Reg";1006  let RenderMethod = "addRegOperands";1007  let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateVector>";1008}1009 1010def PPRAsmOpAny   : PPRAsmOperand<"PredicateAny",   "PPR",     0>;1011def PPRAsmOp8     : PPRAsmOperand<"PredicateB",     "PPR",     8>;1012def PPRAsmOp16    : PPRAsmOperand<"PredicateH",     "PPR",    16>;1013def PPRAsmOp32    : PPRAsmOperand<"PredicateS",     "PPR",    32>;1014def PPRAsmOp64    : PPRAsmOperand<"PredicateD",     "PPR",    64>;1015def PPRAsmOp3bAny : PPRAsmOperand<"Predicate3bAny", "PPR_3b",  0>;1016 1017class PPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,1018                RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}1019 1020def PPRAny   : PPRRegOp<"",  PPRAsmOpAny,   ElementSizeNone, PPR>;1021def PPR8     : PPRRegOp<"b", PPRAsmOp8,     ElementSizeB,    PPR>;1022def PPR16    : PPRRegOp<"h", PPRAsmOp16,    ElementSizeH,    PPR>;1023def PPR32    : PPRRegOp<"s", PPRAsmOp32,    ElementSizeS,    PPR>;1024def PPR64    : PPRRegOp<"d", PPRAsmOp64,    ElementSizeD,    PPR>;1025def PPR3bAny : PPRRegOp<"",  PPRAsmOp3bAny, ElementSizeNone, PPR_3b>;1026 1027class PNRClass<int firstreg, int lastreg> : RegisterClass<1028                                  "AArch64",1029                                  [ aarch64svcount ], 16,1030                                  (sequence "PN%u", firstreg, lastreg)> {1031  let Size = 16;1032}1033 1034def PNR        : PNRClass<0, 15> {1035  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PNRRegClassID, 0, 16>";1036}1037def PNR_3b     : PNRClass<0, 7>;1038def PNR_p8to15 : PNRClass<8, 15>;1039 1040// SVE predicate-as-counter operand1041class PNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass {1042  let Name = "SVE" # name # "Reg";1043  let PredicateMethod = "isSVEPredicateAsCounterRegOfWidth<"1044                            # Width # ", " # "AArch64::"1045                            # RegClass # "RegClassID>";1046  let DiagnosticType = "InvalidSVE" # name # "Reg";1047  let RenderMethod = "addRegOperands";1048  let ParserMethod   = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";1049}1050 1051def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PNR", 0>;1052def PNRAsmOp8  : PNRAsmOperand<"PNPredicateB",   "PNR", 8>;1053def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH",   "PNR", 16>;1054def PNRAsmOp32 : PNRAsmOperand<"PNPredicateS",   "PNR", 32>;1055def PNRAsmOp64 : PNRAsmOperand<"PNPredicateD",   "PNR", 64>;1056 1057class PNRRegOp<string Suffix, AsmOperandClass C, int Size, RegisterClass RC>1058    : SVERegOp<Suffix, C, ElementSizeNone, RC> {1059  let PrintMethod = "printPredicateAsCounter<" # Size # ">";1060}1061def PNRAny : PNRRegOp<"",  PNRAsmOpAny, 0,  PNR>;1062def PNR8   : PNRRegOp<"b", PNRAsmOp8,   8,  PNR>;1063def PNR16  : PNRRegOp<"h", PNRAsmOp16,  16, PNR>;1064def PNR32  : PNRRegOp<"s", PNRAsmOp32,  32, PNR>;1065def PNR64  : PNRRegOp<"d", PNRAsmOp64,  64, PNR>;1066 1067def PNRAsmAny_p8to15  : PNRAsmOperand<"PNPredicateAny_p8to15", "PNR_p8to15", 0>;1068def PNRAsmOp8_p8to15  : PNRAsmOperand<"PNPredicateB_p8to15",   "PNR_p8to15", 8>;1069def PNRAsmOp16_p8to15 : PNRAsmOperand<"PNPredicateH_p8to15",   "PNR_p8to15", 16>;1070def PNRAsmOp32_p8to15 : PNRAsmOperand<"PNPredicateS_p8to15",   "PNR_p8to15", 32>;1071def PNRAsmOp64_p8to15 : PNRAsmOperand<"PNPredicateD_p8to15",   "PNR_p8to15", 64>;1072 1073class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int Width, RegisterClass RC>1074    : SVERegOp<Suffix, C, ElementSizeNone, RC> {1075  let PrintMethod   = "printPredicateAsCounter<" # Width # ">";1076  let EncoderMethod = "EncodePNR_p8to15";1077  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PNRRegClassID, 8, 8>";1078}1079 1080def PNRAny_p8to15 : PNRP8to15RegOp<"",  PNRAsmAny_p8to15,  0,  PNR_p8to15>;1081def PNR8_p8to15   : PNRP8to15RegOp<"b", PNRAsmOp8_p8to15,  8,  PNR_p8to15>;1082def PNR16_p8to15  : PNRP8to15RegOp<"h", PNRAsmOp16_p8to15, 16, PNR_p8to15>;1083def PNR32_p8to15  : PNRP8to15RegOp<"s", PNRAsmOp32_p8to15, 32, PNR_p8to15>;1084def PNR64_p8to15  : PNRP8to15RegOp<"d", PNRAsmOp64_p8to15, 64, PNR_p8to15>;1085 1086class PPRorPNRClass : RegisterClass<1087                                  "AArch64",1088                                  [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1, aarch64svcount ], 16,1089                                  (add PPR, PNR)> {1090  let Size = 16;1091}1092 1093class PPRorPNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass {1094  let Name = "SVE" # name # "Reg";1095  let PredicateMethod = "isSVEPredicateOrPredicateAsCounterRegOfWidth<"1096                            # Width # ", " # "AArch64::"1097                            # RegClass # "RegClassID>";1098  let DiagnosticType = "InvalidSVE" # name # "Reg";1099  let RenderMethod = "addPPRorPNRRegOperands";1100  let ParserMethod = "tryParseSVEPredicateOrPredicateAsCounterVector";1101}1102 1103def PPRorPNR         : PPRorPNRClass {1104  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PPRorPNRRegClassID, 0, 16>";1105}1106def PPRorPNRAsmOp8   : PPRorPNRAsmOperand<"PPRorPNRB", "PPRorPNR", 8>;1107def PPRorPNRAsmOpAny : PPRorPNRAsmOperand<"PPRorPNRAny", "PPRorPNR", 0>;1108def PPRorPNRAny      : PPRRegOp<"", PPRorPNRAsmOpAny, ElementSizeNone, PPRorPNR>;1109def PPRorPNR8        : PPRRegOp<"b", PPRorPNRAsmOp8, ElementSizeB, PPRorPNR>;1110 1111// Pairs of SVE predicate vector registers.1112def PSeqPairs : RegisterTuples<[psub0, psub1], [(rotl PPR, 0), (rotl PPR, 1)]>;1113 1114def PPR2 : RegisterClass<"AArch64", [untyped], 16, (add PSeqPairs)> {1115  let Size = 32;1116  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::PPR2RegClassID, 0, 16>";1117}1118 1119class PPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass {1120  let Name = "SVEPredicateList" # NumRegs # "x" # ElementWidth;1121  let ParserMethod = "tryParseVectorList<RegKind::SVEPredicateVector>";1122  let PredicateMethod = "isTypedVectorList<RegKind::SVEPredicateVector, "1123                            # NumRegs #", 0, "#ElementWidth #">";1124  let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_PReg, "1125                         # NumRegs #">";1126}1127 1128def PP_b : RegisterOperand<PPR2, "printTypedVectorList<0,'b'>"> {1129  let ParserMatchClass = PPRVectorList<8, 2>;1130}1131 1132def PP_h : RegisterOperand<PPR2, "printTypedVectorList<0,'h'>"> {1133  let ParserMatchClass = PPRVectorList<16, 2>;1134}1135 1136def PP_s : RegisterOperand<PPR2, "printTypedVectorList<0,'s'>"> {1137  let ParserMatchClass = PPRVectorList<32, 2>;1138}1139 1140def PP_d : RegisterOperand<PPR2, "printTypedVectorList<0,'d'>"> {1141  let ParserMatchClass = PPRVectorList<64, 2>;1142}1143 1144// SVE2 multiple-of-2 multi-predicate-vector operands1145def PPR2Mul2 : RegisterClass<"AArch64", [untyped], 16, (add (decimate PSeqPairs, 2))> {1146  let Size = 32;1147}1148 1149class PPRVectorListMul<int ElementWidth, int NumRegs> : PPRVectorList<ElementWidth, NumRegs> {1150  let Name = "SVEPredicateListMul" # NumRegs # "x" # ElementWidth;1151  let DiagnosticType = "Invalid" # Name;1152  let PredicateMethod =1153      "isTypedVectorListMultiple<RegKind::SVEPredicateVector, " # NumRegs # ", 0, "1154                                                                # ElementWidth #1155                                                                ", AArch64::PPRMul2RegClassID>";1156}1157 1158class PPR2MulRegOp<string Suffix, int Size, ElementSizeEnum ES>1159    : RegisterOperand<PPR2Mul2, "printTypedVectorList<0,'"#Suffix#"'>"> {1160  ElementSizeEnum ElementSize;1161  let ElementSize = ES;1162  let ParserMatchClass = PPRVectorListMul<Size, 2>;1163}1164 1165let EncoderMethod = "EncodeRegMul_MinMax<2, 0, 14>",1166    DecoderMethod = "DecodePPR2Mul2RegisterClass" in {1167 1168  def PP_b_mul_r : PPR2MulRegOp<"b", 8,  ElementSizeB>;1169  def PP_h_mul_r : PPR2MulRegOp<"h", 16, ElementSizeH>;1170  def PP_s_mul_r : PPR2MulRegOp<"s", 32, ElementSizeS>;1171  def PP_d_mul_r : PPR2MulRegOp<"d", 64, ElementSizeD>;1172 1173} // end let EncoderMethod/DecoderMethod1174 1175//===----------------------------------------------------------------------===//1176// SVE vector register classes1177class ZPRClass<int firstreg, int lastreg, int step = 1> : RegisterClass<"AArch64",1178                                            [nxv16i8, nxv8i16, nxv4i32, nxv2i64,1179                                             nxv2f16, nxv4f16, nxv8f16,1180                                             nxv2bf16, nxv4bf16, nxv8bf16,1181                                             nxv2f32, nxv4f32,1182                                             nxv2f64],1183                                            128, (sequence "Z%u", firstreg, lastreg, step)> {1184  let Size = 128;1185}1186 1187def ZPRMul2    : ZPRClass<0,  30, 2>;1188def ZPRMul4    : ZPRClass<0,  28, 4>;1189def ZPRMul2_Lo : ZPRClass<0,  14, 2>;1190def ZPRMul2_Hi : ZPRClass<16, 30, 2>;1191 1192def ZPR    : ZPRClass<0, 31> {1193  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>";1194}1195def ZPR_4b : ZPRClass<0, 15> { // Restricted 4 bit SVE vector register class.1196  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 16>";1197}1198def ZPR_3b : ZPRClass<0, 7> {  // Restricted 3 bit SVE vector register class.1199  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 8>";1200}1201 1202class ZPRAsmOperand<string name, int Width, string RegClassSuffix = "">1203    : AsmOperandClass {1204  let Name = "SVE" # name # "Reg";1205  let PredicateMethod = "isSVEDataVectorRegOfWidth<"1206                            # Width # ", AArch64::ZPR"1207                            # RegClassSuffix # "RegClassID>";1208  let RenderMethod = "addRegOperands";1209  let DiagnosticType = "InvalidZPR" # RegClassSuffix # Width;1210  let ParserMethod = "tryParseSVEDataVector<false, "1211                               # !if(!eq(Width, 0), "false", "true") # ">";1212}1213 1214def ZPRAsmOpAny : ZPRAsmOperand<"VectorAny", 0>;1215def ZPRAsmOp8   : ZPRAsmOperand<"VectorB",   8>;1216def ZPRAsmOp16  : ZPRAsmOperand<"VectorH",   16>;1217def ZPRAsmOp32  : ZPRAsmOperand<"VectorS",   32>;1218def ZPRAsmOp64  : ZPRAsmOperand<"VectorD",   64>;1219def ZPRAsmOp128 : ZPRAsmOperand<"VectorQ",   128>;1220 1221def ZPRAny  : ZPRRegOp<"",  ZPRAsmOpAny, ElementSizeNone, ZPR>;1222def ZPR8    : ZPRRegOp<"b", ZPRAsmOp8,   ElementSizeB, ZPR>;1223def ZPR16   : ZPRRegOp<"h", ZPRAsmOp16,  ElementSizeH, ZPR>;1224def ZPR32   : ZPRRegOp<"s", ZPRAsmOp32,  ElementSizeS, ZPR>;1225def ZPR64   : ZPRRegOp<"d", ZPRAsmOp64,  ElementSizeD, ZPR>;1226def ZPR128  : ZPRRegOp<"q", ZPRAsmOp128, ElementSizeQ, ZPR>;1227 1228def ZPRAsmOp3b8   : ZPRAsmOperand<"Vector3bB", 8, "_3b">;1229def ZPRAsmOp3b16  : ZPRAsmOperand<"Vector3bH", 16, "_3b">;1230def ZPRAsmOp3b32  : ZPRAsmOperand<"Vector3bS", 32, "_3b">;1231 1232def ZPR3b8  : ZPRRegOp<"b", ZPRAsmOp3b8,  ElementSizeB, ZPR_3b>;1233def ZPR3b16 : ZPRRegOp<"h", ZPRAsmOp3b16, ElementSizeH, ZPR_3b>;1234def ZPR3b32 : ZPRRegOp<"s", ZPRAsmOp3b32, ElementSizeS, ZPR_3b>;1235 1236def ZPRAsmOp4b8   : ZPRAsmOperand<"Vector4bB", 8,  "_4b">;1237def ZPRAsmOp4b16  : ZPRAsmOperand<"Vector4bH", 16, "_4b">;1238def ZPRAsmOp4b32  : ZPRAsmOperand<"Vector4bS", 32, "_4b">;1239def ZPRAsmOp4b64  : ZPRAsmOperand<"Vector4bD", 64, "_4b">;1240 1241def ZPR4b8  : ZPRRegOp<"b", ZPRAsmOp4b8,  ElementSizeB, ZPR_4b>;1242def ZPR4b16 : ZPRRegOp<"h", ZPRAsmOp4b16, ElementSizeH, ZPR_4b>;1243def ZPR4b32 : ZPRRegOp<"s", ZPRAsmOp4b32, ElementSizeS, ZPR_4b>;1244def ZPR4b64 : ZPRRegOp<"d", ZPRAsmOp4b64, ElementSizeD, ZPR_4b>;1245 1246class ZPRMul2_MinToMaxRegOp<string Suffix, AsmOperandClass C, int  Min, int Max, ElementSizeEnum  Width, RegisterClass RC>1247    : ZPRRegOp<Suffix, C, Width, RC> {1248  let EncoderMethod = "EncodeRegMul_MinMax<2," # Min # ", " # Max # ">";1249  let DecoderMethod = "DecodeZPRMul2_MinMax<" # Min # ", " # Max # ">";1250}1251 1252def ZPRMul2AsmOp8_Lo  : ZPRAsmOperand<"VectorB_Lo",  8, "Mul2_Lo">;1253def ZPRMul2AsmOp8_Hi  : ZPRAsmOperand<"VectorB_Hi",  8, "Mul2_Hi">;1254def ZPRMul2AsmOp16_Lo : ZPRAsmOperand<"VectorH_Lo", 16, "Mul2_Lo">;1255def ZPRMul2AsmOp16_Hi : ZPRAsmOperand<"VectorH_Hi", 16, "Mul2_Hi">;1256def ZPRMul2AsmOp32_Lo : ZPRAsmOperand<"VectorS_Lo", 32, "Mul2_Lo">;1257def ZPRMul2AsmOp32_Hi : ZPRAsmOperand<"VectorS_Hi", 32, "Mul2_Hi">;1258def ZPRMul2AsmOp64_Lo : ZPRAsmOperand<"VectorD_Lo", 64, "Mul2_Lo">;1259def ZPRMul2AsmOp64_Hi : ZPRAsmOperand<"VectorD_Hi", 64, "Mul2_Hi">;1260 1261def ZPR_K : RegisterClass<"AArch64", [nxv16i8], 128,1262                          (add Z20, Z21, Z22, Z23, Z28, Z29, Z30, Z31)>{1263                             let Size = 128;1264}1265 1266def ZK : RegisterOperand<ZPR_K, "printSVERegOp<>">{1267  let EncoderMethod = "EncodeZK";1268  let DecoderMethod = "DecodeZK";1269  let ParserMatchClass = ZPRAsmOperand<"Vector_20to23or28to31", 0, "_K">;1270}1271 1272def ZPR8Mul2_Lo  : ZPRMul2_MinToMaxRegOp<"b", ZPRMul2AsmOp8_Lo,   0, 14, ElementSizeB, ZPRMul2_Lo>;1273def ZPR8Mul2_Hi  : ZPRMul2_MinToMaxRegOp<"b", ZPRMul2AsmOp8_Hi,  16, 30, ElementSizeB, ZPRMul2_Hi>;1274def ZPR16Mul2_Lo : ZPRMul2_MinToMaxRegOp<"h", ZPRMul2AsmOp16_Lo,  0, 14, ElementSizeH, ZPRMul2_Lo>;1275def ZPR16Mul2_Hi : ZPRMul2_MinToMaxRegOp<"h", ZPRMul2AsmOp16_Hi, 16, 30, ElementSizeH, ZPRMul2_Hi>;1276def ZPR32Mul2_Lo : ZPRMul2_MinToMaxRegOp<"s", ZPRMul2AsmOp32_Lo,  0, 14, ElementSizeS, ZPRMul2_Lo>;1277def ZPR32Mul2_Hi : ZPRMul2_MinToMaxRegOp<"s", ZPRMul2AsmOp32_Hi, 16, 30, ElementSizeS, ZPRMul2_Hi>;1278def ZPR64Mul2_Lo : ZPRMul2_MinToMaxRegOp<"d", ZPRMul2AsmOp64_Lo,  0, 14, ElementSizeD, ZPRMul2_Lo>;1279def ZPR64Mul2_Hi : ZPRMul2_MinToMaxRegOp<"d", ZPRMul2AsmOp64_Hi, 16, 30, ElementSizeD, ZPRMul2_Hi>;1280 1281class FPRasZPR<int Width> : AsmOperandClass{1282  let Name = "FPR" # Width # "asZPR";1283  let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";1284  let RenderMethod = "addFPRasZPRRegOperands<" # Width # ">";1285}1286 1287class FPRasZPROperand<int Width> : RegisterOperand<ZPR> {1288  let ParserMatchClass = FPRasZPR<Width>;1289  let PrintMethod = "printZPRasFPR<" # Width # ">";1290}1291 1292def FPR8asZPR   : FPRasZPROperand<8>;1293def FPR16asZPR  : FPRasZPROperand<16>;1294def FPR32asZPR  : FPRasZPROperand<32>;1295def FPR64asZPR  : FPRasZPROperand<64>;1296def FPR128asZPR : FPRasZPROperand<128>;1297 1298// Pairs, triples, and quads of SVE vector registers.1299def ZSeqPairs   : RegisterTuples<[zsub0, zsub1], [(rotl ZPR, 0), (rotl ZPR, 1)]>;1300def ZSeqTriples : RegisterTuples<[zsub0, zsub1, zsub2], [(rotl ZPR, 0), (rotl ZPR, 1), (rotl ZPR, 2)]>;1301def ZSeqQuads   : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [(rotl ZPR, 0), (rotl ZPR, 1), (rotl ZPR, 2), (rotl ZPR, 3)]>;1302 1303def ZPR2   : RegisterClass<"AArch64", [untyped], 128, (add ZSeqPairs)>  {1304  let Size = 256;1305  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR2RegClassID, 0, 32>";1306}1307def ZPR3  : RegisterClass<"AArch64", [untyped], 128, (add ZSeqTriples)> {1308  let Size = 384;1309  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR3RegClassID, 0, 32>";1310}1311def ZPR4 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqQuads)> {1312  let Size = 512;1313  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR4RegClassID, 0, 32>";1314}1315 1316class ZPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass {1317  let Name = "SVEVectorList" # NumRegs # ElementWidth;1318  let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";1319  let PredicateMethod =1320      "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";1321  let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_ZReg, " # NumRegs # ">";1322}1323 1324def Z_b  : RegisterOperand<ZPR,  "printTypedVectorList<0,'b'>"> {1325  let ParserMatchClass = ZPRVectorList<8, 1>;1326}1327 1328def Z_h  : RegisterOperand<ZPR,  "printTypedVectorList<0,'h'>"> {1329  let ParserMatchClass = ZPRVectorList<16, 1>;1330}1331 1332def Z_s  : RegisterOperand<ZPR,  "printTypedVectorList<0,'s'>"> {1333  let ParserMatchClass = ZPRVectorList<32, 1>;1334}1335 1336def Z_d  : RegisterOperand<ZPR,  "printTypedVectorList<0,'d'>"> {1337  let ParserMatchClass = ZPRVectorList<64, 1>;1338}1339 1340def Z_q  : RegisterOperand<ZPR,  "printTypedVectorList<0,'q'>"> {1341  let ParserMatchClass = ZPRVectorList<128, 1>;1342}1343 1344def ZZ_Any  : RegisterOperand<ZPR2, "printTypedVectorList<0,0>"> {1345  let ParserMatchClass = ZPRVectorList<0, 2>;1346}1347 1348def ZZ_b  : RegisterOperand<ZPR2, "printTypedVectorList<0,'b'>"> {1349  let ParserMatchClass = ZPRVectorList<8, 2>;1350}1351 1352def ZZ_h  : RegisterOperand<ZPR2, "printTypedVectorList<0,'h'>"> {1353  let ParserMatchClass = ZPRVectorList<16, 2>;1354}1355 1356def ZZ_s  : RegisterOperand<ZPR2, "printTypedVectorList<0,'s'>"> {1357  let ParserMatchClass = ZPRVectorList<32, 2>;1358}1359 1360def ZZ_d  : RegisterOperand<ZPR2, "printTypedVectorList<0,'d'>"> {1361  let ParserMatchClass = ZPRVectorList<64, 2>;1362}1363 1364def ZZ_q  : RegisterOperand<ZPR2, "printTypedVectorList<0,'q'>"> {1365  let ParserMatchClass = ZPRVectorList<128, 2>;1366}1367 1368def ZZZ_Any  : RegisterOperand<ZPR3, "printTypedVectorList<0,0>"> {1369  let ParserMatchClass = ZPRVectorList<0, 3>;1370}1371 1372def ZZZ_b  : RegisterOperand<ZPR3, "printTypedVectorList<0,'b'>"> {1373  let ParserMatchClass = ZPRVectorList<8, 3>;1374}1375 1376def ZZZ_h  : RegisterOperand<ZPR3, "printTypedVectorList<0,'h'>"> {1377  let ParserMatchClass = ZPRVectorList<16, 3>;1378}1379 1380def ZZZ_s  : RegisterOperand<ZPR3, "printTypedVectorList<0,'s'>"> {1381  let ParserMatchClass = ZPRVectorList<32, 3>;1382}1383 1384def ZZZ_d  : RegisterOperand<ZPR3, "printTypedVectorList<0,'d'>"> {1385  let ParserMatchClass = ZPRVectorList<64, 3>;1386}1387 1388def ZZZ_q  : RegisterOperand<ZPR3, "printTypedVectorList<0,'q'>"> {1389  let ParserMatchClass = ZPRVectorList<128, 3>;1390}1391 1392def ZZZZ_b : RegisterOperand<ZPR4, "printTypedVectorList<0,'b'>"> {1393  let ParserMatchClass = ZPRVectorList<8, 4>;1394}1395 1396def ZZZZ_h : RegisterOperand<ZPR4, "printTypedVectorList<0,'h'>"> {1397  let ParserMatchClass = ZPRVectorList<16, 4>;1398}1399 1400def ZZZZ_s : RegisterOperand<ZPR4, "printTypedVectorList<0,'s'>"> {1401  let ParserMatchClass = ZPRVectorList<32, 4>;1402}1403 1404def ZZZZ_d : RegisterOperand<ZPR4, "printTypedVectorList<0,'d'>"> {1405  let ParserMatchClass = ZPRVectorList<64, 4>;1406}1407 1408def ZZZZ_q : RegisterOperand<ZPR4, "printTypedVectorList<0,'q'>"> {1409  let ParserMatchClass = ZPRVectorList<128, 4>;1410}1411 1412// SME2 multiple-of-2 or 4 multi-vector operands1413def ZPR2Mul2 : RegisterClass<"AArch64", [untyped], 128, (add (decimate ZSeqPairs, 2))> {1414  let Size = 256;1415}1416 1417def ZPR4Mul4 : RegisterClass<"AArch64", [untyped], 128, (add (decimate ZSeqQuads, 4))> {1418  let Size = 512;1419}1420 1421class ZPRVectorListMul<int ElementWidth, int NumRegs, string RegClassSuffix = "">1422  : ZPRVectorList<ElementWidth, NumRegs> {1423  let Name = "SVEVectorList" # NumRegs # "x" # ElementWidth # RegClassSuffix;1424  let DiagnosticType = "Invalid" # Name;1425  let PredicateMethod =1426      "isTypedVectorListMultiple<RegKind::SVEDataVector, "1427                                 # NumRegs # ", 0, "1428                                 # ElementWidth #  ", "1429                                 # "AArch64::ZPR" # RegClassSuffix # "RegClassID" # ">";1430}1431 1432let EncoderMethod = "EncodeRegMul_MinMax<2, 0, 30>",1433    DecoderMethod = "DecodeZPR2Mul2RegisterClass<0, 30>" in {1434  def ZZ_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,0>"> {1435    let ParserMatchClass = ZPRVectorListMul<0, 2, "Mul2">;1436  }1437 1438  def ZZ_b_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'b'>"> {1439    let ParserMatchClass = ZPRVectorListMul<8, 2, "Mul2">;1440  }1441 1442  def ZZ_h_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'h'>"> {1443    let ParserMatchClass = ZPRVectorListMul<16, 2, "Mul2">;1444  }1445 1446  def ZZ_s_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'s'>"> {1447    let ParserMatchClass = ZPRVectorListMul<32, 2, "Mul2">;1448  }1449 1450  def ZZ_d_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'d'>"> {1451    let ParserMatchClass = ZPRVectorListMul<64, 2, "Mul2">;1452  }1453 1454  def ZZ_q_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'q'>"> {1455    let ParserMatchClass = ZPRVectorListMul<128, 2, "Mul2">;1456  }1457} // end let EncoderMethod/DecoderMethod1458 1459let EncoderMethod = "EncodeRegMul_MinMax<4, 0, 28>",1460    DecoderMethod = "DecodeZPR4Mul4RegisterClass" in {1461  def ZZZZ_b_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'b'>"> {1462    let ParserMatchClass = ZPRVectorListMul<8, 4, "Mul4">;1463  }1464 1465  def ZZZZ_h_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'h'>"> {1466    let ParserMatchClass = ZPRVectorListMul<16, 4, "Mul4">;1467  }1468 1469  def ZZZZ_s_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'s'>"> {1470    let ParserMatchClass = ZPRVectorListMul<32, 4, "Mul4">;1471  }1472 1473  def ZZZZ_d_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'d'>"> {1474    let ParserMatchClass = ZPRVectorListMul<64, 4, "Mul4">;1475  }1476 1477  def ZZZZ_q_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'q'>"> {1478    let ParserMatchClass = ZPRVectorListMul<128, 4, "Mul4">;1479  }1480} // end let EncoderMethod/DecoderMethod1481 1482// Pairs of consecutive ZPR, starting with an even register, split into1483// Lo=0-14 and Hi=16-30.1484def ZPR2Mul2_Lo : RegisterClass<"AArch64", [untyped], 128,1485                                (trunc (decimate ZSeqPairs, 2), 8)>  {1486  let Size = 256;1487}1488 1489def ZPR2Mul2_Hi : RegisterClass<"AArch64", [untyped], 128,1490                                (trunc (rotr (decimate ZSeqPairs, 2), 8), 8)>  {1491  let Size = 256;1492}1493 1494let EncoderMethod = "EncodeRegMul_MinMax<2, 0, 14>",1495    DecoderMethod = "DecodeZPR2Mul2RegisterClass<0, 16>" in {1496  def ZZ_b_mul_r_Lo : RegisterOperand<ZPR2Mul2_Lo, "printTypedVectorList<0,'b'>"> {1497    let ParserMatchClass = ZPRVectorListMul<8, 2, "Mul2_Lo">;1498  }1499 1500  def ZZ_h_mul_r_Lo : RegisterOperand<ZPR2Mul2_Lo, "printTypedVectorList<0,'h'>"> {1501    let ParserMatchClass = ZPRVectorListMul<16, 2, "Mul2_Lo">;1502  }1503 1504  def ZZ_s_mul_r_Lo : RegisterOperand<ZPR2Mul2_Lo, "printTypedVectorList<0,'s'>"> {1505    let ParserMatchClass = ZPRVectorListMul<32, 2, "Mul2_Lo">;1506  }1507 1508  def ZZ_d_mul_r_Lo : RegisterOperand<ZPR2Mul2_Lo, "printTypedVectorList<0,'d'>"> {1509    let ParserMatchClass = ZPRVectorListMul<64, 2, "Mul2_Lo">;1510  }1511}1512 1513let EncoderMethod = "EncodeRegMul_MinMax<2, 16, 30>",1514    DecoderMethod = "DecodeZPR2Mul2RegisterClass<16, 31>" in {1515  def ZZ_b_mul_r_Hi : RegisterOperand<ZPR2Mul2_Hi, "printTypedVectorList<0,'b'>"> {1516    let ParserMatchClass = ZPRVectorListMul<8, 2, "Mul2_Hi">;1517  }1518 1519  def ZZ_h_mul_r_Hi : RegisterOperand<ZPR2Mul2_Hi, "printTypedVectorList<0,'h'>"> {1520    let ParserMatchClass = ZPRVectorListMul<16, 2, "Mul2_Hi">;1521  }1522 1523  def ZZ_s_mul_r_Hi : RegisterOperand<ZPR2Mul2_Hi, "printTypedVectorList<0,'s'>"> {1524    let ParserMatchClass = ZPRVectorListMul<32, 2, "Mul2_Hi">;1525  }1526 1527  def ZZ_d_mul_r_Hi : RegisterOperand<ZPR2Mul2_Hi, "printTypedVectorList<0,'d'>"> {1528    let ParserMatchClass = ZPRVectorListMul<64, 2, "Mul2_Hi">;1529  }1530 } // end let EncoderMethod/DecoderMethod1531 1532// SME2 strided multi-vector operands1533 1534// ZStridedPairs1535//1536// A group of two Z vectors with strided numbering consisting of:1537//   Zn+0.T and Zn+8.T1538// where n is in the range 0 to 7 and 16 to 23 inclusive, and T is one of B, H,1539// S, or D.1540 1541// Z0_Z8, Z1_Z9, Z2_Z10, Z3_Z11, Z4_Z12, Z5_Z13, Z6_Z14, Z7_Z151542def ZStridedPairsLo : RegisterTuples<[zsub0, zsub1], [1543  (trunc (rotl ZPR, 0), 8), (trunc (rotl ZPR, 8), 8)1544]>;1545 1546// Z16_Z24, Z17_Z25, Z18_Z26, Z19_Z27, Z20_Z28, Z21_Z29, Z22_Z30, Z23_Z311547def ZStridedPairsHi : RegisterTuples<[zsub0, zsub1], [1548  (trunc (rotl ZPR, 16), 8), (trunc (rotl ZPR, 24), 8)1549]>;1550 1551// ZStridedQuads1552//1553// A group of four Z vectors with strided numbering consisting of:1554//   Zn+0.T, Zn+4.T, Zn+8.T and Zn+12.T1555// where n is in the range 0 to 3 and 16 to 19 inclusive, and T is one of B, H,1556// S, or D.1557 1558// Z0_Z4_Z8_Z12, Z1_Z5_Z9_Z13, Z2_Z6_Z10_Z14, Z3_Z7_Z11_Z151559def ZStridedQuadsLo : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [1560  (trunc (rotl ZPR, 0), 4), (trunc (rotl ZPR, 4), 4),1561  (trunc (rotl ZPR, 8), 4), (trunc (rotl ZPR, 12), 4)1562]>;1563// Z16_Z20_Z24_Z28, Z17_Z21_Z25_Z29, Z18_Z22_Z26_Z30, Z19_Z23_Z27_Z311564def ZStridedQuadsHi : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [1565  (trunc (rotl ZPR, 16), 4), (trunc (rotl ZPR, 20), 4),1566  (trunc (rotl ZPR, 24), 4), (trunc (rotl ZPR, 28), 4)1567]>;1568 1569def ZPR2Strided : RegisterClass<"AArch64", [untyped], 128,1570                                (add ZStridedPairsLo, ZStridedPairsHi)>  {1571  let Size = 256;1572  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR2StridedRegClassID, 0, 16>";1573}1574def ZPR4Strided : RegisterClass<"AArch64", [untyped], 128,1575                                (add ZStridedQuadsLo, ZStridedQuadsHi)>  {1576  let Size = 512;1577  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR4StridedRegClassID, 0, 8>";1578}1579 1580def ZPR2StridedOrContiguous : RegisterClass<"AArch64", [untyped], 128,1581                                (add ZStridedPairsLo, ZStridedPairsHi,1582                                (decimate ZSeqPairs, 2))> {1583  let Size = 256;1584}1585 1586class ZPRVectorListStrided<int ElementWidth, int NumRegs, int Stride>1587    : ZPRVectorList<ElementWidth, NumRegs> {1588  let Name = "SVEVectorListStrided" # NumRegs # "x" # ElementWidth;1589  let DiagnosticType = "Invalid" # Name;1590  let PredicateMethod = "isTypedVectorListStrided<RegKind::SVEDataVector, "1591                        # NumRegs # "," # Stride # "," # ElementWidth # ">";1592  let RenderMethod = "addStridedVectorListOperands<" # NumRegs # ">";1593}1594 1595let EncoderMethod = "EncodeZPR2StridedRegisterClass",1596    DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR2StridedRegClassID, 0, 16>" in {1597  def ZZ_b_strided1598      : RegisterOperand<ZPR2Strided, "printTypedVectorList<0, 'b'>"> {1599    let ParserMatchClass = ZPRVectorListStrided<8, 2, 8>;1600  }1601 1602  def ZZ_h_strided1603      : RegisterOperand<ZPR2Strided, "printTypedVectorList<0, 'h'>"> {1604    let ParserMatchClass = ZPRVectorListStrided<16, 2, 8>;1605  }1606 1607  def ZZ_s_strided1608      : RegisterOperand<ZPR2Strided, "printTypedVectorList<0,'s'>"> {1609    let ParserMatchClass = ZPRVectorListStrided<32, 2, 8>;1610  }1611 1612  def ZZ_d_strided1613      : RegisterOperand<ZPR2Strided, "printTypedVectorList<0,'d'>"> {1614    let ParserMatchClass = ZPRVectorListStrided<64, 2, 8>;1615  }1616 1617  def ZZ_b_strided_and_contiguous1618      : RegisterOperand<ZPR2StridedOrContiguous, "printTypedVectorList<0,'b'>">;1619  def ZZ_h_strided_and_contiguous1620      : RegisterOperand<ZPR2StridedOrContiguous, "printTypedVectorList<0,'h'>">;1621  def ZZ_s_strided_and_contiguous1622      : RegisterOperand<ZPR2StridedOrContiguous, "printTypedVectorList<0,'s'>">;1623  def ZZ_d_strided_and_contiguous1624      : RegisterOperand<ZPR2StridedOrContiguous, "printTypedVectorList<0,'d'>">;1625}1626 1627def ZPR4StridedOrContiguous : RegisterClass<"AArch64", [untyped], 128,1628                                (add ZStridedQuadsLo, ZStridedQuadsHi,1629                                (decimate ZSeqQuads, 4))>  {1630  let Size = 512;1631}1632 1633let EncoderMethod = "EncodeZPR4StridedRegisterClass",1634    DecoderMethod = "DecodeSimpleRegisterClass<AArch64::ZPR4StridedRegClassID, 0, 16>" in {1635  def ZZZZ_b_strided1636      : RegisterOperand<ZPR4Strided, "printTypedVectorList<0,'b'>"> {1637    let ParserMatchClass = ZPRVectorListStrided<8, 4, 4>;1638  }1639 1640  def ZZZZ_h_strided1641      : RegisterOperand<ZPR4Strided, "printTypedVectorList<0,'h'>"> {1642    let ParserMatchClass = ZPRVectorListStrided<16, 4, 4>;1643  }1644 1645  def ZZZZ_s_strided1646      : RegisterOperand<ZPR4Strided, "printTypedVectorList<0,'s'>"> {1647    let ParserMatchClass = ZPRVectorListStrided<32, 4, 4>;1648  }1649 1650  def ZZZZ_d_strided1651      : RegisterOperand<ZPR4Strided, "printTypedVectorList<0,'d'>"> {1652    let ParserMatchClass = ZPRVectorListStrided<64, 4, 4>;1653  }1654 1655  def ZZZZ_b_strided_and_contiguous1656      : RegisterOperand<ZPR4StridedOrContiguous, "printTypedVectorList<0,'b'>">;1657  def ZZZZ_h_strided_and_contiguous1658      : RegisterOperand<ZPR4StridedOrContiguous, "printTypedVectorList<0,'h'>">;1659  def ZZZZ_s_strided_and_contiguous1660      : RegisterOperand<ZPR4StridedOrContiguous, "printTypedVectorList<0,'s'>">;1661  def ZZZZ_d_strided_and_contiguous1662      : RegisterOperand<ZPR4StridedOrContiguous, "printTypedVectorList<0,'d'>">;1663}1664 1665class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,1666                          bit ScaleAlwaysSame = 0b0> : AsmOperandClass {1667  let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale1668                         # !if(ScaleAlwaysSame, "Only", "");1669 1670  let PredicateMethod = "isSVEDataVectorRegWithShiftExtend<"1671                          # RegWidth # ", AArch64::ZPRRegClassID, "1672                          # "AArch64_AM::" # ShiftExtend # ", "1673                          # Scale # ", "1674                          # !if(ScaleAlwaysSame, "true", "false")1675                          # ">";1676  let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale;1677  let RenderMethod = "addRegOperands";1678  let ParserMethod = "tryParseSVEDataVector<true, true>";1679}1680 1681class ZPRExtendRegisterOperand<bit SignExtend, bit IsLSL, string Repr,1682                               int RegWidth, int Scale, string Suffix = "">1683    : RegisterOperand<ZPR> {1684  let ParserMatchClass =1685    !cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale # Suffix);1686  let PrintMethod = "printRegWithShiftExtend<"1687                          # !if(SignExtend, "true", "false") # ", "1688                          # Scale # ", "1689                          # !if(IsLSL, "'x'", "'w'") # ", "1690                          # !if(!eq(RegWidth, 32), "'s'", "'d'") # ">";1691}1692 1693foreach RegWidth = [32, 64] in {1694  // UXTW(8|16|32|64)1695  def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;1696  def ZPR#RegWidth#AsmOpndExtUXTW8     : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;1697  def ZPR#RegWidth#AsmOpndExtUXTW16    : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>;1698  def ZPR#RegWidth#AsmOpndExtUXTW32    : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>;1699  def ZPR#RegWidth#AsmOpndExtUXTW64    : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>;1700 1701  def ZPR#RegWidth#ExtUXTW8Only        : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8, "Only">;1702  def ZPR#RegWidth#ExtUXTW8            : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8>;1703  def ZPR#RegWidth#ExtUXTW16           : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 16>;1704  def ZPR#RegWidth#ExtUXTW32           : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 32>;1705  def ZPR#RegWidth#ExtUXTW64           : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 64>;1706 1707  // SXTW(8|16|32|64)1708  def ZPR#RegWidth#AsmOpndExtSXTW8Only : ZPRExtendAsmOperand<"SXTW", RegWidth, 8, 0b1>;1709  def ZPR#RegWidth#AsmOpndExtSXTW8     : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>;1710  def ZPR#RegWidth#AsmOpndExtSXTW16    : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>;1711  def ZPR#RegWidth#AsmOpndExtSXTW32    : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>;1712  def ZPR#RegWidth#AsmOpndExtSXTW64    : ZPRExtendAsmOperand<"SXTW", RegWidth, 64>;1713 1714  def ZPR#RegWidth#ExtSXTW8Only        : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8, "Only">;1715  def ZPR#RegWidth#ExtSXTW8            : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8>;1716  def ZPR#RegWidth#ExtSXTW16           : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 16>;1717  def ZPR#RegWidth#ExtSXTW32           : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 32>;1718  def ZPR#RegWidth#ExtSXTW64           : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 64>;1719 1720  // LSL(8|16|32|64)1721  def ZPR#RegWidth#AsmOpndExtLSL8      : ZPRExtendAsmOperand<"LSL", RegWidth, 8>;1722  def ZPR#RegWidth#AsmOpndExtLSL16     : ZPRExtendAsmOperand<"LSL", RegWidth, 16>;1723  def ZPR#RegWidth#AsmOpndExtLSL32     : ZPRExtendAsmOperand<"LSL", RegWidth, 32>;1724  def ZPR#RegWidth#AsmOpndExtLSL64     : ZPRExtendAsmOperand<"LSL", RegWidth, 64>;1725  def ZPR#RegWidth#ExtLSL8             : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 8>;1726  def ZPR#RegWidth#ExtLSL16            : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 16>;1727  def ZPR#RegWidth#ExtLSL32            : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 32>;1728  def ZPR#RegWidth#ExtLSL64            : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 64>;1729}1730 1731class GPR64ShiftExtendAsmOperand <string AsmOperandName, int Scale, string RegClass> : AsmOperandClass {1732  let Name = AsmOperandName # Scale;1733  let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";1734  let DiagnosticType = "Invalid" # AsmOperandName # Scale;1735  let RenderMethod = "addRegOperands";1736  let ParserMethod = "tryParseGPROperand<true>";1737}1738 1739class GPR64ExtendRegisterOperand<string Name, int Scale, RegisterClass RegClass> : RegisterOperand<RegClass>{1740  let ParserMatchClass = !cast<AsmOperandClass>(Name);1741  let PrintMethod = "printRegWithShiftExtend<false, " # Scale # ", 'x', 0>";1742}1743 1744foreach Scale = [8, 16, 32, 64, 128] in {1745  def GPR64shiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64shifted", Scale, "GPR64">;1746  def GPR64shifted # Scale : GPR64ExtendRegisterOperand<"GPR64shiftedAsmOpnd" # Scale, Scale, GPR64>;1747 1748  def GPR64NoXZRshiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64NoXZRshifted", Scale, "GPR64common">;1749  def GPR64NoXZRshifted # Scale : GPR64ExtendRegisterOperand<"GPR64NoXZRshiftedAsmOpnd" # Scale, Scale, GPR64common>;1750}1751 1752// Accumulator array tiles.1753def ZAQ0  : AArch64Reg<0,  "za0.q">;1754def ZAQ1  : AArch64Reg<1,  "za1.q">;1755def ZAQ2  : AArch64Reg<2,  "za2.q">;1756def ZAQ3  : AArch64Reg<3,  "za3.q">;1757def ZAQ4  : AArch64Reg<4,  "za4.q">;1758def ZAQ5  : AArch64Reg<5,  "za5.q">;1759def ZAQ6  : AArch64Reg<6,  "za6.q">;1760def ZAQ7  : AArch64Reg<7,  "za7.q">;1761def ZAQ8  : AArch64Reg<8,  "za8.q">;1762def ZAQ9  : AArch64Reg<9,  "za9.q">;1763def ZAQ10 : AArch64Reg<10, "za10.q">;1764def ZAQ11 : AArch64Reg<11, "za11.q">;1765def ZAQ12 : AArch64Reg<12, "za12.q">;1766def ZAQ13 : AArch64Reg<13, "za13.q">;1767def ZAQ14 : AArch64Reg<14, "za14.q">;1768def ZAQ15 : AArch64Reg<15, "za15.q">;1769 1770let SubRegIndices = [zasubq0, zasubq1] in {1771  def ZAD0 : AArch64Reg<0, "za0.d", [ZAQ0, ZAQ8]>;1772  def ZAD1 : AArch64Reg<1, "za1.d", [ZAQ1, ZAQ9]>;1773  def ZAD2 : AArch64Reg<2, "za2.d", [ZAQ2, ZAQ10]>;1774  def ZAD3 : AArch64Reg<3, "za3.d", [ZAQ3, ZAQ11]>;1775  def ZAD4 : AArch64Reg<4, "za4.d", [ZAQ4, ZAQ12]>;1776  def ZAD5 : AArch64Reg<5, "za5.d", [ZAQ5, ZAQ13]>;1777  def ZAD6 : AArch64Reg<6, "za6.d", [ZAQ6, ZAQ14]>;1778  def ZAD7 : AArch64Reg<7, "za7.d", [ZAQ7, ZAQ15]>;1779}1780 1781let SubRegIndices = [zasubd0, zasubd1] in {1782  def ZAS0 : AArch64Reg<0, "za0.s", [ZAD0, ZAD4]>;1783  def ZAS1 : AArch64Reg<1, "za1.s", [ZAD1, ZAD5]>;1784  def ZAS2 : AArch64Reg<2, "za2.s", [ZAD2, ZAD6]>;1785  def ZAS3 : AArch64Reg<3, "za3.s", [ZAD3, ZAD7]>;1786}1787 1788let SubRegIndices = [zasubs0, zasubs1] in {1789  def ZAH0 : AArch64Reg<0, "za0.h", [ZAS0, ZAS2]>;1790  def ZAH1 : AArch64Reg<1, "za1.h", [ZAS1, ZAS3]>;1791}1792 1793let SubRegIndices = [zasubh0, zasubh1] in {1794  def ZAB0 : AArch64Reg<0, "za0.b", [ZAH0, ZAH1]>;1795}1796 1797let SubRegIndices = [zasubb] in {1798  def ZA : AArch64Reg<0, "za", [ZAB0]>;1799}1800 1801def ZT0 : AArch64Reg<0, "zt0">;1802 1803// SME Register Classes1804 1805let isAllocatable = 0 in {1806  // Accumulator array1807  def MPR : RegisterClass<"AArch64", [untyped], 2048, (add ZA)> {1808    let Size = 2048;1809  }1810 1811  // Accumulator array as single tiles1812  def MPR8    : RegisterClass<"AArch64", [untyped], 2048, (add (sequence "ZAB%u", 0, 0))> {1813    let Size = 2048;1814  }1815  def MPR16   : RegisterClass<"AArch64", [untyped], 1024, (add (sequence "ZAH%u", 0, 1))> {1816    let Size = 1024;1817  }1818  def MPR32   : RegisterClass<"AArch64", [untyped],  512, (add (sequence "ZAS%u", 0, 3))> {1819    let Size = 512;1820  }1821  def MPR64   : RegisterClass<"AArch64", [untyped],  256, (add (sequence "ZAD%u", 0, 7))> {1822    let Size = 256;1823  }1824  def MPR128  : RegisterClass<"AArch64", [untyped],  128, (add (sequence "ZAQ%u", 0, 15))> {1825    let Size = 128;1826  }1827}1828 1829def ZTR : RegisterClass<"AArch64", [untyped], 512, (add ZT0)> {1830  let Size = 512;1831  let DiagnosticType = "InvalidLookupTable";1832}1833// SME Register Operands1834// There are three types of SME matrix register operands:1835// * Tiles:1836//1837//   These tiles make up the larger accumulator matrix. The tile representation1838//   has an element type suffix, e.g. za0.b or za15.q and can be any of the1839//   registers:1840//          ZAQ0..ZAQ151841//          ZAD0..ZAD71842//          ZAS0..ZAS31843//          ZAH0..ZAH11844//       or ZAB01845//1846// * Tile vectors:1847//1848//   Their representation is similar to regular tiles, but they have an extra1849//   'h' or 'v' to tell how the vector at [reg+offset] is laid out in the tile,1850//   horizontally or vertically.1851//1852//   e.g. za1h.h or za15v.q, which corresponds to vectors in registers ZAH1 and1853//   ZAQ15, respectively. The horizontal/vertical is more a property of the1854//   instruction, than a property of the asm-operand itself, or its register.1855//   The distinction is required for the parsing/printing of the operand,1856//   as from a compiler's perspective, the whole tile is read/written.1857//1858// * Accumulator matrix:1859//1860//   This is the entire matrix accumulator register ZA (<=> ZAB0), printed as1861//   'za'.1862 1863//1864// Tiles1865//1866 1867class MatrixTileAsmOperand<string RC, int EltSize> : AsmOperandClass {1868  let Name = "MatrixTile" # EltSize;1869  let DiagnosticType = "Invalid" # Name;1870  let ParserMethod = "tryParseMatrixRegister";1871  let RenderMethod = "addMatrixOperands";1872  let PredicateMethod = "isMatrixRegOperand<"1873                          # "MatrixKind::Tile" # ", "1874                          # EltSize # ", AArch64::" # RC # "RegClassID>";1875}1876 1877class MatrixTileOperand<int EltSize, RegisterClass RC>1878    : RegisterOperand<RC> {1879  let ParserMatchClass = MatrixTileAsmOperand<!cast<string>(RC), EltSize>;1880  let PrintMethod = "printMatrixTile";1881}1882 1883def TileOp16  : MatrixTileOperand<16, MPR16>;1884def TileOp32  : MatrixTileOperand<32, MPR32>;1885def TileOp64  : MatrixTileOperand<64, MPR64>;1886 1887//1888// Tile vectors (horizontal and vertical)1889//1890 1891class MatrixTileVectorAsmOperand<string RC, int EltSize, int IsVertical>1892    : AsmOperandClass {1893  let Name = "MatrixTileVector" # !if(IsVertical, "V", "H") # EltSize;1894  let DiagnosticType = "Invalid" # Name;1895  let ParserMethod = "tryParseMatrixRegister";1896  let RenderMethod = "addMatrixOperands";1897  let PredicateMethod = "isMatrixRegOperand<"1898                          # "MatrixKind::"1899                          # !if(IsVertical, "Col", "Row") # ", "1900                          # EltSize # ", AArch64::" # RC # "RegClassID>";1901}1902 1903class MatrixTileVectorOperand<int EltSize, RegisterClass RC, int IsVertical>1904    : RegisterOperand<RC> {1905  let ParserMatchClass = MatrixTileVectorAsmOperand<!cast<string>(RC), EltSize,1906                                                    IsVertical>;1907  let PrintMethod = "printMatrixTileVector<" # IsVertical # ">";1908}1909 1910def TileVectorOpH8   : MatrixTileVectorOperand<  8, MPR8,   0>;1911def TileVectorOpH16  : MatrixTileVectorOperand< 16, MPR16,  0>;1912def TileVectorOpH32  : MatrixTileVectorOperand< 32, MPR32,  0>;1913def TileVectorOpH64  : MatrixTileVectorOperand< 64, MPR64,  0>;1914def TileVectorOpH128 : MatrixTileVectorOperand<128, MPR128, 0>;1915 1916def TileVectorOpV8   : MatrixTileVectorOperand<  8, MPR8,   1>;1917def TileVectorOpV16  : MatrixTileVectorOperand< 16, MPR16,  1>;1918def TileVectorOpV32  : MatrixTileVectorOperand< 32, MPR32,  1>;1919def TileVectorOpV64  : MatrixTileVectorOperand< 64, MPR64,  1>;1920def TileVectorOpV128 : MatrixTileVectorOperand<128, MPR128, 1>;1921 1922//1923// Accumulator matrix1924//1925 1926class MatrixAsmOperand<string RC, int EltSize> : AsmOperandClass {1927  let Name = "Matrix" # !if(EltSize, !cast<string>(EltSize), "");1928  let DiagnosticType = "Invalid" # Name;1929  let ParserMethod = "tryParseMatrixRegister";1930  let RenderMethod = "addMatrixOperands";1931  let PredicateMethod = "isMatrixRegOperand<"1932                          # "MatrixKind::Array" # ", "1933                          # EltSize # ", AArch64::" # RC # "RegClassID>";1934}1935 1936class MatrixOperand<RegisterClass RC, int EltSize> : RegisterOperand<RC> {1937  let ParserMatchClass = MatrixAsmOperand<!cast<string>(RC), EltSize>;1938  let PrintMethod = "printMatrix<" # EltSize # ">";1939}1940 1941def MatrixOp : MatrixOperand<MPR, 0>;1942// SME2 register operands and classes1943def MatrixOp8 : MatrixOperand<MPR, 8>;1944def MatrixOp16 : MatrixOperand<MPR, 16>;1945def MatrixOp32 : MatrixOperand<MPR, 32>;1946def MatrixOp64 : MatrixOperand<MPR, 64>;1947 1948class MatrixTileListAsmOperand : AsmOperandClass {1949  let Name = "MatrixTileList";1950  let ParserMethod = "tryParseMatrixTileList";1951  let RenderMethod = "addMatrixTileListOperands";1952  let PredicateMethod = "isMatrixTileList";1953}1954 1955class MatrixTileListOperand : Operand<i8> {1956  let ParserMatchClass = MatrixTileListAsmOperand<>;1957  let DecoderMethod = "DecodeMatrixTileListRegisterClass";1958  let EncoderMethod = "EncodeMatrixTileListRegisterClass";1959  let PrintMethod = "printMatrixTileList";1960}1961 1962def MatrixTileList : MatrixTileListOperand<>;1963 1964def MatrixIndexGPR32_8_11 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 8, 11)> {1965   let DiagnosticType = "InvalidMatrixIndexGPR32_8_11";1966   let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::MatrixIndexGPR32_8_11RegClassID, 0, 4>";1967}1968def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)> {1969  let DiagnosticType = "InvalidMatrixIndexGPR32_12_15";1970  let DecoderMethod = "DecodeSimpleRegisterClass<AArch64::MatrixIndexGPR32_12_15RegClassID, 0, 4>";1971}1972def MatrixIndexGPR32Op8_11 : RegisterOperand<MatrixIndexGPR32_8_11> {1973  let EncoderMethod = "encodeMatrixIndexGPR32<AArch64::W8>";1974}1975def MatrixIndexGPR32Op12_15 : RegisterOperand<MatrixIndexGPR32_12_15> {1976  let EncoderMethod = "encodeMatrixIndexGPR32<AArch64::W12>";1977}1978 1979def SVCROperand : AsmOperandClass {1980  let Name = "SVCR";1981  let ParserMethod = "tryParseSVCR";1982  let DiagnosticType = "Invalid" # Name;1983}1984 1985def svcr_op : Operand<i32>, TImmLeaf<i32, [{1986    return AArch64SVCR::lookupSVCRByEncoding(Imm) != nullptr;1987  }]> {1988  let ParserMatchClass = SVCROperand;1989  let PrintMethod = "printSVCROp";1990  let DecoderMethod = "DecodeSVCROp";1991  let MCOperandPredicate = [{1992    if (!MCOp.isImm())1993      return false;1994    return AArch64SVCR::lookupSVCRByEncoding(MCOp.getImm()) != nullptr;1995  }];1996}1997 1998let isAllocatable = 0, GeneratePressureSet = 0 in {1999  def W_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (add (sequence "W%u_HI", 0, 30), WZR_HI, WSP_HI)>;2000  def B_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (sequence "B%u_HI", 0, 31)>;2001  def H_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (sequence "H%u_HI", 0, 31)>;2002  def S_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (sequence "S%u_HI", 0, 31)>;2003  def D_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (sequence "D%u_HI", 0, 31)>;2004  def Q_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (sequence "Q%u_HI", 0, 31)>;2005}2006 2007//===----------------------------------------------------------------------===//2008// Register categories.2009//2010 2011def GeneralPurposeRegisters : RegisterCategory<[GPR64, GPR32]>;2012 2013def FIXED_REGS : RegisterClass<"AArch64", [i64], 64, (add FP, SP, VG, FFR)>;2014def FixedRegisters : RegisterCategory<[CCR, FIXED_REGS]>;2015