1416 lines · plain
1//==- AArch64SchedCortexA320.td - ARM Cortex-A320 Scheduling Definitions -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for the ARM Cortex-A320 processor.10//11//===----------------------------------------------------------------------===//12 13// ===---------------------------------------------------------------------===//14// The following definitions describe the per-operand machine model.15// This works with MachineScheduler. See MCSchedModel.h for details.16 17// Cortex-A320 machine model for scheduling and other instruction cost heuristics.18def CortexA320Model : SchedMachineModel {19 let MicroOpBufferSize = 0; // Cortex-A320 is an in-order processor20 let IssueWidth = 1; // Cortex-A320 is a single-issue processor21 let LoadLatency = 5;22 let PostRAScheduler = 1; // Enable PostRA scheduler pass.23 let CompleteModel = 0; // Covers instructions applicable to Cortex-A320.24 25 let FullInstRWOverlapCheck = 0;26}27 28 29//===----------------------------------------------------------------------===//30// Subtarget-specific SchedWrite types31 32let SchedModel = CortexA320Model in {33 34//===----------------------------------------------------------------------===//35// Define each kind of processor resource and number available.36 37// Modeling each pipeline as a ProcResource using the BufferSize = 0 since the38// Cortex-A320 is in-order.39let BufferSize = 0 in {40 def CortexA320UnitALU : ProcResource<1>; // Int ALU41 def CortexA320UnitMAC : ProcResource<1>; // Int MAC, 64-bit wide42 def CortexA320UnitDiv : ProcResource<1>; // Int Division, not pipelined43 def CortexA320UnitLdSt : ProcResource<1>; // Load/Store shared pipe44 def CortexA320UnitB : ProcResource<1>; // Branch45 def CortexA320UnitPAC : ProcResource<1>; // Pointer Authentication (PAC) pipe46 47 // The FP DIV/SQRT instructions execute totally differently from the FP ALU48 // instructions; that's why for now we model them with 2 resources.49 def CortexA320UnitVALU : ProcResource<1>; // SIMD/FP/SVE ALU50 def CortexA320UnitVMAC : ProcResource<1>; // SIMD/FP/SVE MAC51 def CortexA320UnitVMC : ProcResource<1>; // SIMD/FP/SVE multicycle instrs (e.g Div, SQRT, cryptography)52}53 54// These latencies are modeled without taking into account forwarding paths55// (the software optimisation guide lists latencies taking into account56// typical forwarding paths).57def : WriteRes<WriteImm, [CortexA320UnitALU]> { let Latency = 1; } // MOVN, MOVZ58def : WriteRes<WriteI, [CortexA320UnitALU]> { let Latency = 1; } // ALU59def : WriteRes<WriteISReg, [CortexA320UnitALU]> { let Latency = 2; } // ALU of Shifted-Reg60def : WriteRes<WriteIEReg, [CortexA320UnitALU]> { let Latency = 2; } // ALU of Extended-Reg61def : WriteRes<WriteExtr, [CortexA320UnitALU]> { let Latency = 2; } // EXTR from a reg pair62def : WriteRes<WriteIS, [CortexA320UnitALU]> { let Latency = 2; } // Shift/Scale63 64// MAC65def : WriteRes<WriteIM32, [CortexA320UnitMAC]> { let Latency = 3; } // 32-bit Multiply66def : WriteRes<WriteIM64, [CortexA320UnitMAC]> { let Latency = 5; let ReleaseAtCycles = [2];} // 64-bit Multiply67 68// Div69def : WriteRes<WriteID32, [CortexA320UnitDiv]> {70 let Latency = 12; let ReleaseAtCycles = [12];71}72def : WriteRes<WriteID64, [CortexA320UnitDiv]> {73 let Latency = 20; let ReleaseAtCycles = [20];74}75 76//===----------------------------------------------------------------------===//77// Define customized scheduler read/write types specific to Cortex-A32078 79//===----------------------------------------------------------------------===//80class CortexA320Write<int n, ProcResourceKind res> : SchedWriteRes<[res]> {81 let Latency = n;82}83 84class CortexA320MCWrite<int n, int m, ProcResourceKind res> : SchedWriteRes<[res]> {85 let Latency = n;86 let ReleaseAtCycles = [m];87 let BeginGroup = 1;88}89 90class CortexA320MC_RC0Write<int n, ProcResourceKind res> : SchedWriteRes<[res]> {91 let Latency = n;92 let BeginGroup = 1;93}94 95//===----------------------------------------------------------------------===//96 97// Define generic 2 micro-op types98def CortexA320Write_11cyc_1VMAC_1VALU : SchedWriteRes<[CortexA320UnitVALU, CortexA320UnitVMAC]> {99 let Latency = 11;100 let NumMicroOps = 2;101}102 103def CortexA320Write_16cyc_1VMAC_1VALU : SchedWriteRes<[CortexA320UnitVALU, CortexA320UnitVMAC]> {104 let Latency = 16;105 let NumMicroOps = 2;106}107 108class CortexA320Write_PAC_B <int lat> : SchedWriteRes<[CortexA320UnitPAC, CortexA320UnitB]> {109 let Latency = lat;110 let NumMicroOps = 2;111}112 113// Load114def : WriteRes<WriteLD, [CortexA320UnitLdSt]> { let Latency = 4; }115def : WriteRes<WriteLDIdx, [CortexA320UnitLdSt]> { let Latency = 4; }116def : WriteRes<WriteLDHi, [CortexA320UnitLdSt]> { let Latency = 4; }117 118def CortexA320WriteVLD1 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 3; }119def CortexA320WriteVLD1SI : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 3; let SingleIssue = 1; }120 121def CortexA320WriteVLD2 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4;122 let ReleaseAtCycles = [2]; }123 124def CortexA320WriteVLD3 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 5;125 let ReleaseAtCycles = [3]; }126 127def CortexA320WriteVLD4 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 6;128 let ReleaseAtCycles = [4]; }129 130def CortexA320WriteVLD6 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 5;131 let ReleaseAtCycles = [3]; }132 133def CortexA320WriteVLD8 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 6;134 let ReleaseAtCycles = [4]; }135 136def CortexA320WriteLDP1 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4; }137def CortexA320WriteLDP2 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4; }138def CortexA320WriteLDP4 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4; }139 140// Pre/Post Indexing - Performed as part of address generation141def : WriteRes<WriteAdr, []> { let Latency = 0; }142 143// Store144let RetireOOO = 1 in {145def : WriteRes<WriteST, [CortexA320UnitLdSt]> { let Latency = 1; }146def : WriteRes<WriteSTP, [CortexA320UnitLdSt]> { let Latency = 1; }147def : WriteRes<WriteSTIdx, [CortexA320UnitLdSt]> { let Latency = 1; }148}149def : WriteRes<WriteSTX, [CortexA320UnitLdSt]> { let Latency = 3; }150 151// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.152def : WriteRes<WriteVST, [CortexA320UnitLdSt]> { let Latency = 5;153 let ReleaseAtCycles = [2];}154def CortexA320WriteVST1 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4; }155def CortexA320WriteVST2 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 5;156 let ReleaseAtCycles = [2]; }157def CortexA320WriteVST3 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 5;158 let ReleaseAtCycles = [3]; }159def CortexA320WriteVST4 : SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 5;160 let ReleaseAtCycles = [4]; }161 162def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }163 164// Branch165def : WriteRes<WriteBr, [CortexA320UnitB]>;166def : WriteRes<WriteBrReg, [CortexA320UnitB]>;167def : WriteRes<WriteSys, [CortexA320UnitB]>;168def : WriteRes<WriteBarrier, [CortexA320UnitB]>;169def : WriteRes<WriteHint, [CortexA320UnitB]>;170 171// FP ALU172// As WriteF result is produced in F5 and it can be mostly forwarded173// to consumer at F1, the effectively Latency is set as 4.174def : WriteRes<WriteF, [CortexA320UnitVALU]> { let Latency = 4; }175def : WriteRes<WriteFCmp, [CortexA320UnitVALU]> { let Latency = 3; }176def : WriteRes<WriteFCvt, [CortexA320UnitVALU]> { let Latency = 4; }177def : WriteRes<WriteFCopy, [CortexA320UnitVALU]> { let Latency = 3; }178def : WriteRes<WriteFImm, [CortexA320UnitVALU]> { let Latency = 3; }179 180class CortexA320VSt<int n> : SchedWriteRes<[CortexA320UnitLdSt]> {181 let RetireOOO = 1;182 let ReleaseAtCycles = [n];183}184 185def CortexA320VSt0 : SchedWriteRes<[CortexA320UnitLdSt]> {186 let RetireOOO = 1;187}188 189def : SchedAlias<WriteVd, CortexA320Write<4, CortexA320UnitVALU>>;190def : SchedAlias<WriteVq, CortexA320Write<4, CortexA320UnitVALU>>;191 192// FP ALU specific new schedwrite definitions193def CortexA320WriteFPALU_F3 : SchedWriteRes<[CortexA320UnitVALU]> { let Latency = 3;}194def CortexA320WriteFPALU_F4 : SchedWriteRes<[CortexA320UnitVALU]> { let Latency = 4;}195 196// FP Mul, Div, Sqrt. Div/Sqrt are not pipelined197def : WriteRes<WriteFMul, [CortexA320UnitVMAC]> { let Latency = 4; }198 199let RetireOOO = 1 in {200def : WriteRes<WriteFDiv, [CortexA320UnitVMC]> { let Latency = 22;201 let ReleaseAtCycles = [29]; }202def CortexA320WriteVMAC : SchedWriteRes<[CortexA320UnitVMAC]> { let Latency = 4; }203def CortexA320WriteFDivHP : SchedWriteRes<[CortexA320UnitVMC]> { let Latency = 8;204 let ReleaseAtCycles = [5]; }205def CortexA320WriteFDivSP : SchedWriteRes<[CortexA320UnitVMC]> { let Latency = 13;206 let ReleaseAtCycles = [10]; }207def CortexA320WriteFDivDP : SchedWriteRes<[CortexA320UnitVMC]> { let Latency = 22;208 let ReleaseAtCycles = [19]; }209def CortexA320WriteFSqrtHP : SchedWriteRes<[CortexA320UnitVMC]> { let Latency = 8;210 let ReleaseAtCycles = [5]; }211def CortexA320WriteFSqrtSP : SchedWriteRes<[CortexA320UnitVMC]> { let Latency = 12;212 let ReleaseAtCycles = [9]; }213def CortexA320WriteFSqrtDP : SchedWriteRes<[CortexA320UnitVMC]> { let Latency = 22;214 let ReleaseAtCycles = [19]; }215}216 217//===----------------------------------------------------------------------===//218// Subtarget-specific SchedRead types.219 220def : ReadAdvance<ReadVLD, 0>;221def : ReadAdvance<ReadExtrHi, 0>;222def : ReadAdvance<ReadAdrBase, 0>;223def : ReadAdvance<ReadST, 1>;224 225def : ReadAdvance<ReadI, 0>;226def : ReadAdvance<ReadISReg, 0>;227def : ReadAdvance<ReadIEReg, 0>;228 229 230// MUL231def : ReadAdvance<ReadIM, 0>;232def : ReadAdvance<ReadIMA, 2>;233 234// Div235def : ReadAdvance<ReadID, 0>;236 237//===----------------------------------------------------------------------===//238// Subtarget-specific InstRWs.239 240def CortexA320WriteISReg : SchedWriteVariant<[241 SchedVar<RegShiftedPred, [WriteISReg]>,242 SchedVar<NoSchedPred, [WriteI]>]>;243def : InstRW<[CortexA320WriteISReg], (instregex ".*rs$")>;244def : InstRW<[WriteIS], (instrs RBITWr, RBITXr)>;245 246// Pointer Authentication Instructions (v8.3 PAC)247// -----------------------------------------------------------------------------248 249// Authenticate data address250// Authenticate instruction address251// Compute pointer authentication code for data address252// Compute pointer authentication code, using generic key253// Compute pointer authentication code for instruction address254def : InstRW<[CortexA320Write<4, CortexA320UnitPAC>], (instregex "^AUT", "^PAC")>;255 256// Branch and link, register, with pointer authentication257// Branch, register, with pointer authentication258// Branch, return, with pointer authentication259def : InstRW<[CortexA320Write_PAC_B<1>], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA,260 BRAAZ, BRAB, BRABZ, RETAA, RETAB,261 ERETAA, ERETAB)>;262 263// Load register, with pointer authentication264def : InstRW<[CortexA320Write<2, CortexA320UnitPAC>], (instregex "^LDRA[AB](indexed|writeback)")>;265 266// Strip pointer authentication code267def : InstRW<[CortexA320Write<5, CortexA320UnitPAC>], (instrs XPACD, XPACI, XPACLRI)>;268//---269// Miscellaneous270//---271def : InstRW<[CortexA320WriteVLD1SI,CortexA320WriteLDP1], (instregex "LDPS?Wi")>;272def : InstRW<[CortexA320WriteVLD1,CortexA320WriteLDP1], (instregex "LDPSi")>;273def : InstRW<[CortexA320WriteVLD1,CortexA320WriteLDP2], (instregex "LDP(X|D)i")>;274def : InstRW<[CortexA320WriteVLD1,CortexA320WriteLDP4], (instregex "LDPQi")>;275def : InstRW<[WriteAdr, CortexA320WriteVLD1SI,CortexA320WriteLDP1], (instregex "LDPS?W(pre|post)")>;276def : InstRW<[WriteAdr, CortexA320WriteVLD1,CortexA320WriteLDP1], (instregex "LDPS(pre|post)")>;277def : InstRW<[WriteAdr, CortexA320WriteVLD1,CortexA320WriteLDP2], (instregex "LDP(X|D)(pre|post)")>;278def : InstRW<[WriteAdr, CortexA320WriteVLD1,CortexA320WriteLDP4], (instregex "LDPQ(pre|post)")>;279def : InstRW<[WriteI], (instrs COPY)>;280//---281// Vector Loads - 128-bit per cycle282//---283// 1-element structures284def CortexA320WriteVLD1Latency3: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 3; let ReleaseAtCycles = [1]; }285def CortexA320WriteVLD1Latency4: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4; let ReleaseAtCycles = [2]; }286def CortexA320WriteVLD1Latency5: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 5; let ReleaseAtCycles = [3]; }287def CortexA320WriteVLD1Latency6: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 6; let ReleaseAtCycles = [4]; }288 289def : InstRW<[CortexA320WriteVLD1Latency3], (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;290def : InstRW<[CortexA320WriteVLD1Latency3], (instregex "LD1Twov(8b|4h|2s|1d)$")>;291def : InstRW<[CortexA320WriteVLD1Latency4], (instregex "LD1Twov(16b|8h|4s|2d)$")>;292def : InstRW<[CortexA320WriteVLD1Latency4], (instregex "LD1Threev(8b|4h|2s|1d)$")>;293def : InstRW<[CortexA320WriteVLD1Latency5], (instregex "LD1Threev(16b|8h|4s|2d)$")>;294def : InstRW<[CortexA320WriteVLD1Latency4], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;295def : InstRW<[CortexA320WriteVLD1Latency6], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;296def : InstRW<[CortexA320WriteVLD1Latency3], (instregex "LD1i(8|16|32|64)$")>; // single element297def : InstRW<[CortexA320WriteVLD1Latency3], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // replicate298 299def : InstRW<[WriteAdr, CortexA320WriteVLD1Latency3], (instregex "LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;300def : InstRW<[WriteAdr, CortexA320WriteVLD1Latency3], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;301def : InstRW<[WriteAdr, CortexA320WriteVLD1Latency4], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;302def : InstRW<[WriteAdr, CortexA320WriteVLD1Latency4], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;303def : InstRW<[WriteAdr, CortexA320WriteVLD1Latency5], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;304def : InstRW<[WriteAdr, CortexA320WriteVLD1Latency4], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;305def : InstRW<[WriteAdr, CortexA320WriteVLD1Latency6], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;306def : InstRW<[WriteAdr, CortexA320WriteVLD1Latency3], (instregex "LD1i(8|16|32|64)_POST$")>; // single element307def : InstRW<[WriteAdr, CortexA320WriteVLD1Latency3], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // replicate308 309// 2-element structures310def CortexA320WriteVLD2Latency3: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 3; let ReleaseAtCycles = [2]; }311def CortexA320WriteVLD2Latency4Release1: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4; let ReleaseAtCycles = [1]; }312def CortexA320WriteVLD2Latency4Release2: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4; let ReleaseAtCycles = [2]; }313def CortexA320WriteVLD2Latency4Release6: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4; let ReleaseAtCycles = [6]; }314 315def : InstRW<[CortexA320WriteVLD2Latency4Release1], (instregex "LD2Twov(8b|4h|2s|1d)$")>;316def : InstRW<[CortexA320WriteVLD2Latency4Release2], (instregex "LD2Twov(16b|8h|4s|2d)$")>;317def : InstRW<[CortexA320WriteVLD2Latency4Release6], (instregex "LD2i(8|16|32|64)$")>;318def : InstRW<[CortexA320WriteVLD2Latency3], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;319 320def : InstRW<[WriteAdr, CortexA320WriteVLD2Latency4Release1], (instregex "LD2Twov(8b|4h|2s|1d)_POST$")>;321def : InstRW<[WriteAdr, CortexA320WriteVLD2Latency4Release2], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;322def : InstRW<[WriteAdr, CortexA320WriteVLD2Latency4Release6], (instregex "LD2i(8|16|32|64)_POST$")>;323def : InstRW<[WriteAdr, CortexA320WriteVLD2Latency3], (instregex "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;324 325// 3-element structures326def CortexA320WriteVLD3Latency4: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4; let ReleaseAtCycles = [3]; }327def CortexA320WriteVLD3Latency5Release6: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 5; let ReleaseAtCycles = [6]; }328def CortexA320WriteVLD3Latency5Release7: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 5; let ReleaseAtCycles = [7]; }329 330def : InstRW<[CortexA320WriteVLD3Latency5Release6], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;331def : InstRW<[CortexA320WriteVLD3Latency5Release7], (instregex "LD3i(8|16|32|64)$")>;332def : InstRW<[CortexA320WriteVLD3Latency4], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;333 334def : InstRW<[WriteAdr, CortexA320WriteVLD3Latency5Release6], (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;335def : InstRW<[WriteAdr, CortexA320WriteVLD3Latency5Release7], (instregex "LD3i(8|16|32|64)_POST$")>;336def : InstRW<[WriteAdr, CortexA320WriteVLD3Latency4], (instregex "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;337 338// 4-element structures339def CortexA320WriteVLD4Latency4: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 4; let ReleaseAtCycles = [4]; }340def CortexA320WriteVLD4Latency5Release7: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 5; let ReleaseAtCycles = [7]; }341def CortexA320WriteVLD4Latency5Release8: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 5; let ReleaseAtCycles = [8]; }342def CortexA320WriteVLD4Latency6: SchedWriteRes<[CortexA320UnitLdSt]> { let Latency = 6; let ReleaseAtCycles = [7]; }343 344def : InstRW<[CortexA320WriteVLD4Latency5Release7], (instregex "LD4Fourv(8b|4h|2s|1d)$")>;345def : InstRW<[CortexA320WriteVLD4Latency5Release8], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;346def : InstRW<[CortexA320WriteVLD4Latency6], (instregex "LD4i(8|16|32|64)$")>;347def : InstRW<[CortexA320WriteVLD4Latency4], (instregex "LD4Rv(8b|16b|4h|8b|2s|4s|1d|2d)$")>;348 349def : InstRW<[WriteAdr, CortexA320WriteVLD4Latency5Release7], (instregex "LD4Fourv(8b|4h|2s|1d)_POST$")>;350def : InstRW<[WriteAdr, CortexA320WriteVLD4Latency5Release8], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>; 351def : InstRW<[WriteAdr, CortexA320WriteVLD4Latency6], (instregex "LD4i(8|16|32|64)_POST$")>;352def : InstRW<[WriteAdr, CortexA320WriteVLD4Latency4], (instregex "LD4Rv(8b|16b|4h|8b|2s|4s|1d|2d)_POST$")>;353//---354// Vector Stores355//---356// 1 Element structures357def : InstRW<[CortexA320WriteVST1], (instregex "ST1i(8|16|32|64)$")>;358def : InstRW<[CortexA320WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d)$")>;359def : InstRW<[CortexA320WriteVST2], (instregex "ST1Onev(16b|8h|4s|2d)$")>;360def : InstRW<[CortexA320WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d)$")>;361def : InstRW<[CortexA320WriteVST2], (instregex "ST1Twov(16b|8h|4s|2d)$")>;362def : InstRW<[CortexA320WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;363def : InstRW<[CortexA320WriteVST4], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;364def : InstRW<[WriteAdr, CortexA320WriteVST1], (instregex "ST1i(8|16|32|64)_POST$")>;365def : InstRW<[WriteAdr, CortexA320WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;366def : InstRW<[WriteAdr, CortexA320WriteVST2], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;367def : InstRW<[WriteAdr, CortexA320WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;368def : InstRW<[WriteAdr, CortexA320WriteVST2], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;369def : InstRW<[WriteAdr, CortexA320WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;370def : InstRW<[WriteAdr, CortexA320WriteVST4], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;371 372// 2 Element structures373def : InstRW<[CortexA320WriteVST2], (instregex "ST2i(8|16|32|64)$")>;374def : InstRW<[CortexA320WriteVST2], (instregex "ST2Twov(8b|4h|2s)$")>;375def : InstRW<[CortexA320WriteVST4], (instregex "ST2Twov(16b|8h|4s|2d)$")>;376 377def : InstRW<[WriteAdr, CortexA320WriteVST2], (instregex "ST2i(8|16|32|64)_POST$")>;378def : InstRW<[WriteAdr, CortexA320WriteVST2], (instregex "ST2Twov(8b|4h|2s)_POST$")>;379def : InstRW<[WriteAdr, CortexA320WriteVST4], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;380 381// 3 Element structures382def : InstRW<[CortexA320WriteVST2], (instregex "ST3i(8|16|32|64)$")>;383def : InstRW<[CortexA320WriteVST4], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;384 385def : InstRW<[WriteAdr, CortexA320WriteVST2], (instregex "ST3i(8|16|32|64)_POST$")>;386def : InstRW<[WriteAdr, CortexA320WriteVST4], (instregex "ST3Threev(8b|4h|2s|1d|2d|16b|8h|4s|4d)_POST$")>;387 388// 4 Element structures389def : InstRW<[CortexA320WriteVST2], (instregex "ST4i(8|16|32|64)$")>;390def : InstRW<[CortexA320WriteVST4], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;391 392def : InstRW<[WriteAdr, CortexA320WriteVST2], (instregex "ST4i(8|16|32|64)_POST$")>;393def : InstRW<[WriteAdr, CortexA320WriteVST4], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;394 395//---396// Floating Point Conversions, MAC, DIV, SQRT397//---398def : InstRW<[CortexA320WriteFPALU_F3], (instregex "^DUP(v2i64|v4i32|v8i16|v16i8)")>;399def : InstRW<[CortexA320WriteFPALU_F4], (instregex "^XTN")>;400def : InstRW<[CortexA320WriteFPALU_F4], (instregex "^FCVT[ALMNPZ][SU](S|U)?(W|X)")>;401def : InstRW<[CortexA320WriteFPALU_F4], (instregex "^FCVT(X)?[ALMNPXZ](S|U|N)?v")>;402 403def : InstRW<[CortexA320WriteFPALU_F4], (instregex "^(S|U)CVTF(S|U)(W|X)(H|S|D)")>;404def : InstRW<[CortexA320WriteFPALU_F4], (instregex "^(S|U)CVTF(h|s|d)")>;405def : InstRW<[CortexA320WriteFPALU_F4], (instregex "^(S|U)CVTFv")>;406 407def : InstRW<[CortexA320WriteVMAC], (instregex "^FN?M(ADD|SUB).*")>;408def : InstRW<[CortexA320WriteVMAC], (instregex "^FML(A|S)v.*")>;409def : InstRW<[CortexA320WriteFDivHP], (instrs FDIVHrr)>;410def : InstRW<[CortexA320WriteFDivSP], (instrs FDIVSrr)>;411def : InstRW<[CortexA320WriteFDivDP], (instrs FDIVDrr)>;412def : InstRW<[CortexA320WriteFDivHP], (instregex "^FDIVv.*16$")>;413def : InstRW<[CortexA320WriteFDivSP], (instregex "^FDIVv.*32$")>;414def : InstRW<[CortexA320WriteFDivDP], (instregex "^FDIVv.*64$")>;415def : InstRW<[CortexA320WriteFSqrtHP], (instregex "^.*SQRT.*16$")>;416def : InstRW<[CortexA320WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;417def : InstRW<[CortexA320WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;418 419def : InstRW<[CortexA320WriteFPALU_F3], (instrs FCSELHrrr, FCSELSrrr, FCSELDrrr)>;420 421// Advanced SIMD integer instructions422// ASIMD absolute diff423def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU]ABDv(2i32|4i16|8i8)")>;424def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU]ABDv(16i8|4i32|8i16)")>;425// ASIMD absolute diff accum426def : InstRW<[CortexA320Write<6, CortexA320UnitVALU>], (instregex "[SU]ABAL?v")>;427// ASIMD absolute diff long428def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU]ABDLv")>;429// ASIMD arith #1430def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "(ADD|SUB|NEG)v",431 "[SU]R?HADDv", "[SU]HSUBv")>;432// ASIMD arith #2433def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "ABSv(1i64|2i32|4i16|8i8)$",434 "[SU]ADDLPv(2i32_v1i64|4i16_v2i32|8i8_v4i16)$",435 "ADDPv(2i32|4i16|8i8)$")>;436def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "([SU]QADD|[SU]QSUB|SQNEG|SUQADD|USQADD)v(1i16|1i32|1i64|1i8|2i32|4i16|8i8)$")>;437def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "ABSv(2i64|4i32|8i16|16i8)$",438 "[SU]ADDLPv(16i8_v8i16|4i32_v2i64|8i16_v4i32)$",439 "ADDPv(16i8|2i64|4i32|8i16)$")>;440def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "([SU]QADD|[SU]QSUB|SQNEG|SUQADD|USQADD)v(16i8|2i64|4i32|8i16)$")>;441// ASIMD arith #3442def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "SADDLv", "UADDLv", "SADDWv",443 "UADDWv", "SSUBLv", "USUBLv", "SSUBWv", "USUBWv")>;444def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "ADDHNv", "SUBHNv")>;445// ASIMD arith #5446def : InstRW<[CortexA320Write<8, CortexA320UnitVALU>], (instregex "RADDHNv", "RSUBHNv")>;447// ASIMD arith, reduce448def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "ADDVv")>;449def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "SADDLVv", "UADDLVv")>;450// ASIMD compare #1451def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "CM(EQ|GE|GT|HI|HS|LE|LT)v(1i64|2i32|4i16|8i8)")>;452def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "CM(EQ|GE|GT|HI|HS|LE|LT)v(2i64|4i32|8i16|16i8)")>;453// ASIMD compare #2454def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "CMTSTv(1i64|2i32|4i16|8i8)")>;455def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "CMTSTv(2i64|4i32|8i16|16i8)")>;456// ASIMD logical $1457def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "(AND|EOR|NOT|ORN)v8i8",458 "(ORR|BIC)v(2i32|4i16|8i8)$", "MVNIv(2i|2s|4i16)")>;459def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "(AND|EOR|NOT|ORN)v16i8",460 "(ORR|BIC)v(16i8|4i32|8i16)$", "MVNIv(4i32|4s|8i16)")>;461// ASIMD max/min, basic462def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU](MIN|MAX)P?v(2i32|4i16|8i8)")>;463def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU](MIN|MAX)P?v(16i8|4i132|8i16)")>;464// SIMD max/min, reduce465def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "[SU](MAX|MIN)Vv")>;466// ASIMD multiply, by element467def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "MULv(2i32|4i16|4i32|8i16)_indexed$",468 "SQR?DMULHv(1i16|1i32|2i32|4i16|4i32|8i16)_indexed$")>;469// ASIMD multiply470def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instrs PMULv8i8)>;471def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instrs PMULv16i8)>;472// ASIMD multiply accumulate473def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "ML[AS]v(2i32|4i16|8i8)$")>;474def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "ML[AS]v(16i8|4i32|8i16)$")>;475def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "ML[AS]v(2i32|4i16|4i32|8i16)_indexed$")>;476// ASIMD multiply accumulate half477def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "SQRDML[AS]H[vi]")>;478// ASIMD multiply accumulate long479def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "[SU]ML[AS]Lv")>;480// ASIMD multiply accumulate long #2481def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "SQDML[AS]L[iv]")>;482// ASIMD dot product483def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "[SU]DOTv8i8")>;484def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "[SU]DOTv16i8")>;485// ASIMD dot product, by scalar486def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "[SU]DOTlanev")>;487// ASIMD multiply long488def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "[SU]MULLv", "SQDMULL[iv]")>;489// ASIMD polynomial (8x8) multiply long490def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instrs PMULLv8i8, PMULLv16i8)>;491// ASIMD pairwise add and accumulate492def : InstRW<[CortexA320MCWrite<7, 2, CortexA320UnitVALU>], (instregex "[SU]ADALPv")>;493// ASIMD shift accumulate494def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU]SRA(d|v2i32|v4i16|v8i8)")>;495def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU]SRAv(16i8|2i64|4i32|8i16)")>;496// ASIMD shift accumulate #2497def : InstRW<[CortexA320MCWrite<7, 2, CortexA320UnitVALU>], (instregex "[SU]RSRA[vd]")>;498// ASIMD shift by immed499def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "SHLd$", "SHLv",500 "SLId$", "SRId$", "[SU]SHR[vd]", "SHRNv")>;501// ASIMD shift by immed502// SXTL and UXTL are aliases for SHLL503def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[US]?SHLLv")>;504// ASIMD shift by immed #2505def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU]RSHR(d|v2i32|v4i16|v8i8)",506 "[SU]RSHRv(16i8|2i64|4i32|8i16)")>;507def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "RSHRNv(2i32|4i16|8i8)",508 "RSHRNv(16i8|4i32|8i16)")>;509// ASIMD shift by register510def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU]SHLv(1i64|2i32|4i16|8i8)")>;511def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU]SHLv(2i64|4i32|8i16|16i8)")>;512// ASIMD shift by register #2513def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU]RSHLv(1i64|2i32|4i16|8i8)")>;514def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "[SU]RSHLv(2i64|4i32|8i16|16i8)")>;515 516def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "[SU]QSHLv(1i64|2i32|4i16|8i8)")>;517def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "[SU]QSHLv(2i64|4i32|8i16|16i8)")>;518 519def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "[SU]QRSHLv(1i64|2i32|4i16|8i8)")>;520def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "[SU]QRSHLv(2i64|4i32|8i16|16i8)")>;521 522// Cryptography extensions523// -----------------------------------------------------------------------------524 525// Crypto AES ops526def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;527 528// Crypto polynomial (64x64) multiply long529def : InstRW<[CortexA320MCWrite<4, 0, CortexA320UnitVMC>], (instrs PMULLv1i64, PMULLv2i64)>;530 531// Crypto SHA1 hash acceleration op532// Crypto SHA1 schedule acceleration ops533def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^SHA1(H|SU0|SU1)")>;534 535// Crypto SHA1 hash acceleration ops536// Crypto SHA256 hash acceleration ops537def : InstRW<[CortexA320MCWrite<4, 0, CortexA320UnitVMC>], (instregex "^SHA1[CMP]", "^SHA256H2?")>;538 539// Crypto SHA256 schedule acceleration ops540def : InstRW<[CortexA320MCWrite<4, 0, CortexA320UnitVMC>], (instregex "^SHA256SU[01]")>;541 542// Crypto SHA512 hash acceleration ops543def : InstRW<[CortexA320MCWrite<9, 0, CortexA320UnitVMC>], (instregex "^SHA512(H|H2|SU0|SU1)")>;544 545// Crypto SHA3 ops546def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instrs BCAX, EOR3)>;547def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instrs XAR)>;548def : InstRW<[CortexA320MCWrite<9, 0, CortexA320UnitVMC>], (instrs RAX1)>;549 550 551// Crypto SM3 ops552def : InstRW<[CortexA320MCWrite<9, 0, CortexA320UnitVMC>], (instregex "^SM3PARTW[12]$", "^SM3SS1$",553 "^SM3TT[12][AB]$")>;554 555// Crypto SM4 ops556def : InstRW<[CortexA320MCWrite<9, 0, CortexA320UnitVMC>], (instrs SM4E, SM4ENCKEY)>;557 558// CRC559// -----------------------------------------------------------------------------560 561def : InstRW<[CortexA320MCWrite<2, 0, CortexA320UnitMAC>], (instregex "^CRC32")>;562 563// SVE Predicate instructions564 565// Loop control, based on predicate566def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs BRKA_PPmP, BRKA_PPzP,567 BRKB_PPmP, BRKB_PPzP)>;568 569// Loop control, based on predicate and flag setting570def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs BRKAS_PPzP, BRKBS_PPzP)>;571 572// Loop control, propagating573def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs BRKN_PPzP, BRKPA_PPzPP, BRKPB_PPzPP)>;574 575// Loop control, propagating and flag setting576def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs BRKNS_PPzP)>;577def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs BRKPAS_PPzPP, BRKPBS_PPzPP)>;578 579 580// Loop control, based on GPR581def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>],582 (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]")>;583 584def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^WHILE(RW|WR)_PXX_[BHSD]")>;585 586// Loop terminate587def : InstRW<[CortexA320Write<1, CortexA320UnitALU>], (instregex "^CTERM(EQ|NE)_(WW|XX)")>;588 589// Predicate counting scalar590def : InstRW<[CortexA320Write<1, CortexA320UnitALU>], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;591 592def : InstRW<[CortexA320Write<3, CortexA320UnitALU>],593 (instregex "^CNT[BHWD]_XPiI")>;594 595def : InstRW<[CortexA320Write<3, CortexA320UnitALU>],596 (instregex "^(INC|DEC)[BHWD]_XPiI")>;597 598def : InstRW<[CortexA320Write<5, CortexA320UnitALU>],599 (instregex "^(SQINC|SQDEC|UQINC|UQDEC)[BHWD]_[XW]Pi(Wd)?I")>;600 601// Predicate counting scalar, active predicate602def : InstRW<[CortexA320Write<1, CortexA320UnitVALU>],603 (instregex "^CNTP_XPP_[BHSD]")>;604 605def : InstRW<[CortexA320Write<1, CortexA320UnitVALU>],606 (instregex "^(DEC|INC)P_XP_[BHSD]")>;607 608def : InstRW<[CortexA320Write<9, CortexA320UnitVALU>],609 (instregex "^(SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]",610 "^(UQDEC|UQINC)P_WP_[BHSD]",611 "^(SQDEC|SQINC|UQDEC|UQINC)P_XPWd_[BHSD]")>;612 613 614// Predicate counting vector, active predicate615def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>],616 (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]")>;617 618// Predicate logical619def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>],620 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP")>;621 622// Predicate logical, flag setting623def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>],624 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;625 626// Predicate reverse627def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^REV_PP_[BHSD]")>;628 629// Predicate select630def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs SEL_PPPP)>;631 632// Predicate set633def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;634 635// Predicate set/initialize, set flags636def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^PTRUES_[BHSD]")>;637 638// Predicate find first/next639def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;640 641// Predicate test642def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs PTEST_PP)>;643 644// Predicate transpose645def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^TRN[12]_PPP_[BHSDQ]")>;646 647// Predicate unpack and widen648def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs PUNPKHI_PP, PUNPKLO_PP)>;649 650// Predicate zip/unzip651def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^(ZIP|UZP)[12]_PPP_[BHSDQ]")>;652 653 654// SVE integer instructions655// -----------------------------------------------------------------------------656// Arithmetic, absolute diff657def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^[SU]ABD_(ZPmZ|ZPZZ)_[BHSD]")>;658 659// Arithmetic, absolute diff accum660def : InstRW<[CortexA320MCWrite<6, 2, CortexA320UnitVALU>], (instregex "^[SU]ABA_ZZZ_[BHSD]")>;661 662// Arithmetic, absolute diff accum long663def : InstRW<[CortexA320MCWrite<6, 2, CortexA320UnitVALU>], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]")>;664 665// Arithmetic, absolute diff long666def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]")>;667 668// Arithmetic, basic669def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>],670 (instregex "^(ABS|CNOT|NEG)_ZPmZ_[BHSD]",671 "^(ADD|SUB|SUBR)_ZPmZ_[BHSD]",672 "^(ADD|SUB|SUBR)_ZPZZ_[BHSD]",673 "^(ADD|SUB)_ZZZ_[BHSD]",674 "^(ADD|SUB|SUBR)_ZI_[BHSD]",675 "^ADR_[SU]XTW_ZZZ_D_[0123]",676 "^ADR_LSL_ZZZ_[SD]_[0123]",677 "^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]")>;678def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],679 (instregex "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",680 "^SADDLBT_ZZZ_[HSD]",681 "^SSUBL(BT|TB)_ZZZ_[HSD]")>;682 683// Arithmetic, complex684def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],685 (instregex "^SQ(ABS|NEG)_ZPmZ_[BHSD]",686 "^SQ(ADD|SUB|SUBR)_ZPmZ_?[BHSD]",687 "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]",688 "^[SU]Q(ADD|SUB)_ZI_[BHSD]",689 "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]",690 "^(UQSUB|UQSUBR)_ZPmZ_[BHSD]")>;691def : InstRW<[CortexA320Write<8, CortexA320UnitVALU>],692 (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]")>;693 694// Arithmetic, large integer695def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]")>;696 697// Arithmetic, pairwise add698def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^ADDP_ZPmZ_[BHSD]")>;699 700// Arithmetic, pairwise add and accum long701def : InstRW<[CortexA320MCWrite<7, 2, CortexA320UnitVALU>], (instregex "^[SU]ADALP_ZPmZ_[HSD]")>;702 703// Arithmetic, shift704def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>],705 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",706 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",707 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",708 "^(ASR|LSL|LSR)_ZPZI_[BHSD]",709 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",710 "^(ASR|LSL|LSR)_ZPZZ_[BHSD]",711 "^(ASR|LSL|LSR)_ZZI_[BHSD]",712 "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>;713// Arithmetic, shift right for divide714def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],715 (instregex "^ASRD_ZPmI_[BHSD]",716 "^ASRD_ZPZI_[BHSD]")>;717 718// Arithmetic, shift and accumulate719def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],720 (instregex "^(SSRA|USRA)_ZZI_[BHSD]")>;721 722def : InstRW<[CortexA320MCWrite<7, 2, CortexA320UnitVALU>],723 (instregex "^(SRSRA|URSRA)_ZZI_[BHSD]")>;724 725 726// Arithmetic, shift by immediate727// Arithmetic, shift by immediate and insert728def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>],729 (instregex "^(SHRNB|SHRNT|SSHLLB|SSHLLT|USHLLB|USHLLT|SLI|SRI)_ZZI_[BHSD]")>;730 731// Arithmetic, shift complex732def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],733 (instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]",734 "^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_(ZPmZ|ZPZZ)_[BHSD]",735 "^(SQSHL|SQSHLU|UQSHL)_(ZPmI|ZPZI)_[BHSD]",736 "^SQSHRU?N[BT]_ZZI_[BHS]",737 "^UQR?SHRN[BT]_ZZI_[BHS]")>;738 739// Arithmetic, shift rounding740def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],741 (instregex "^(SRSHL|SRSHR|SRSHLR|URSHL|URSHLR|URSHR)_(ZPmZ|ZPZZ|ZPZI)_[BHSD]",742 "^[SU]RSHR_ZPmI_[BHSD]")>;743 744// Bit manipulation745def : InstRW<[CortexA320MCWrite<13, 12, CortexA320UnitVMC>],746 (instregex "^(BDEP|BEXT|BGRP)_ZZZ_B")>;747 748def : InstRW<[CortexA320MCWrite<21, 20, CortexA320UnitVMC>],749 (instregex "^(BDEP|BEXT|BGRP)_ZZZ_H")>;750 751def : InstRW<[CortexA320MCWrite<37, 36, CortexA320UnitVMC>],752 (instregex "^(BDEP|BEXT|BGRP)_ZZZ_S")>;753 754def : InstRW<[CortexA320MCWrite<68, 67, CortexA320UnitVMC>],755 (instregex "^(BDEP|BEXT|BGRP)_ZZZ_D")>;756 757 758// Bitwise select759def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ")>;760 761// Count/reverse bits762def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^(CLS|CLZ|RBIT)_ZPmZ_[BHSD]")>;763def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^CNT_ZPmZ_[BH]")>;764def : InstRW<[CortexA320Write<8, CortexA320UnitVALU>], (instregex "^CNT_ZPmZ_S")>;765def : InstRW<[CortexA320Write<12, CortexA320UnitVALU>], (instregex "^CNT_ZPmZ_D")>;766// Broadcast logical bitmask immediate to vector767def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instrs DUPM_ZI)>;768 769// Compare and set flags770def : InstRW<[CortexA320Write<5, CortexA320UnitVALU>],771 (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]",772 "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]")>;773 774// Complex add775def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^CADD_ZZI_[BHSD]")>;776 777def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^SQCADD_ZZI_[BHSD]")>;778 779// Complex dot product 8-bit element780def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;781 782// Complex dot product 16-bit element783def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;784 785// Complex multiply-add B, H, S element size786def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^CMLA_ZZZ_[BHS]",787 "^CMLA_ZZZI_[HS]")>;788 789// Complex multiply-add D element size790def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instrs CMLA_ZZZ_D)>;791 792// Conditional extract operations, scalar form793def : InstRW<[CortexA320MCWrite<8, 2, CortexA320UnitVALU>], (instregex "^CLAST[AB]_RPZ_[BHSD]")>;794 795// Conditional extract operations, SIMD&FP scalar and vector forms796def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]",797 "^COMPACT_ZPZ_[SD]",798 "^SPLICE_ZPZZ?_[BHSD]")>;799 800// Convert to floating point, 64b to float or convert to double801def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU]CVTF_ZPmZ_Dto[SD]")>;802 803// Convert to floating point, 64b to half804def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU]CVTF_ZPmZ_DtoH")>;805 806// Convert to floating point, 32b to single or half807def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;808 809// Convert to floating point, 32b to double810def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU]CVTF_ZPmZ_StoD")>;811 812// Convert to floating point, 16b to half813def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;814 815// Copy, scalar816def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>],(instregex "^CPY_ZPmR_[BHSD]")>;817 818// Copy, scalar SIMD&FP or imm819def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^CPY_ZPm[IV]_[BHSD]",820 "^CPY_ZPzI_[BHSD]")>;821 822// Divides, 32 bit823def : InstRW<[CortexA320MCWrite<15, 12, CortexA320UnitVMC>], (instregex "^[SU]DIVR?_(ZPmZ|ZPZZ)_S")>;824 825// Divides, 64 bit826def : InstRW<[CortexA320MCWrite<26, 23, CortexA320UnitVMC>], (instregex "^[SU]DIVR?_(ZPmZ|ZPZZ)_D")>;827 828// Dot product, 8 bit829def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^[SU]DOT_ZZZI?_BtoS")>;830 831// Dot product, 8 bit, using signed and unsigned integers832def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;833 834// Dot product, 16 bit835def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^[SU]DOT_ZZZI?_HtoD")>;836 837// Duplicate, immediate and indexed form838def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^DUP_ZI_[BHSD]",839 "^DUP_ZZI_[BHSDQ]")>;840 841// Duplicate, scalar form842def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^DUP_ZR_[BHSD]")>;843 844// Extend, sign or zero845def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^[SU]XTB_ZPmZ_[HSD]",846 "^[SU]XTH_ZPmZ_[SD]",847 "^[SU]XTW_ZPmZ_[D]")>;848 849// Extract850def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;851 852// Extract narrow saturating853def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]",854 "^SQXTUN[BT]_ZZ_[BHS]")>;855 856// Extract/insert operation, SIMD and FP scalar form857def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^LAST[AB]_VPZ_[BHSD]",858 "^INSR_ZV_[BHSD]")>;859 860// Extract/insert operation, scalar861def : InstRW<[CortexA320MCWrite<8, 2, CortexA320UnitVALU>], (instregex "^LAST[AB]_RPZ_[BHSD]",862 "^INSR_ZR_[BHSD]")>;863 864// Histogram operations865def : InstRW<[CortexA320MCWrite<8, 2, CortexA320UnitVALU>], (instregex "^HISTCNT_ZPzZZ_[SD]",866 "^HISTSEG_ZZZ")>;867 868// Horizontal operations, B, H, S form, immediate operands only869def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^INDEX_II_[BHS]")>;870 871// Horizontal operations, B, H, S form, scalar, immediate operands/ scalar872// operands only / immediate, scalar operands873def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^INDEX_(IR|RI|RR)_[BHS]")>;874 875// Horizontal operations, D form, immediate operands only876def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instrs INDEX_II_D)>;877 878// Horizontal operations, D form, scalar, immediate operands)/ scalar operands879// only / immediate, scalar operands880def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^INDEX_(IR|RI|RR)_D")>;881 882// Logical883def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>],884 (instregex "^(AND|EOR|ORR)_ZI",885 "^(AND|BIC|EOR|EOR|ORR)_ZZZ",886 "^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]",887 "^(AND|BIC|EOR|NOT|ORR)_ZPZZ_[BHSD]")>;888 889def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],890 (instregex "^EOR(BT|TB)_ZZZ_[BHSD]")>;891 892// Max/min, basic and pairwise893def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",894 "^[SU](MAX|MIN)P?_(ZPmZ|ZPZZ)_[BHSD]")>;895 896// Matching operations897def : InstRW<[CortexA320MCWrite<9, 2, CortexA320UnitVALU>], (instregex "^N?MATCH_PPzZZ_[BH]")>;898 899// Matrix multiply-accumulate900def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;901 902// Move prefix903def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]",904 "^MOVPRFX_ZZ")>;905 906// Multiply, B, H, S element size907def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ|ZPZZ)_[BHS]",908 "^[SU]MULH_(ZPmZ|ZZZ|ZPZZ)_[BHS]")>;909 910// Multiply, D element size911def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ|ZPZZ)_D",912 "^[SU]MULH_(ZPmZ|ZZZ|ZPZZ)_D")>;913 914// Multiply long915def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^[SU]MULL[BT]_ZZZI_[SD]",916 "^[SU]MULL[BT]_ZZZ_[HSD]")>;917 918// Multiply accumulate, B, H, S element size919def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^ML[AS]_(ZZZI|ZPZZZ)_[BHS]",920 "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>;921 922// Multiply accumulate, D element size923def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^ML[AS]_(ZZZI|ZPZZZ)_D",924 "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;925 926// Multiply accumulate long927def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]",928 "^[SU]ML[AS]L[BT]_ZZZI_[SD]")>;929 930// Multiply accumulate saturating doubling long regular931def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^SQDML[AS](LB|LT|LBT)_ZZZ_[HSD]",932 "^SQDML[AS](LB|LT)_ZZZI_[SD]")>;933 934// Multiply saturating doubling high, B, H, S element size935def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^SQDMULH_ZZZ_[BHS]",936 "^SQDMULH_ZZZI_[HS]")>;937 938// Multiply saturating doubling high, D element size939def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>;940 941// Multiply saturating doubling long942def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^SQDMULL[BT]_ZZZ_[HSD]",943 "^SQDMULL[BT]_ZZZI_[SD]")>;944 945// Multiply saturating rounding doubling regular/complex accumulate, B, H, S946// element size947def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^SQRDML[AS]H_ZZZ_[BHS]",948 "^SQRDCMLAH_ZZZ_[BHS]",949 "^SQRDML[AS]H_ZZZI_[HS]",950 "^SQRDCMLAH_ZZZI_[HS]")>;951 952// Multiply saturating rounding doubling regular/complex accumulate, D element953// size954def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^SQRDML[AS]H_ZZZI?_D",955 "^SQRDCMLAH_ZZZ_D")>;956 957// Multiply saturating rounding doubling regular/complex, B, H, S element size958def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^SQRDMULH_ZZZ_[BHS]",959 "^SQRDMULH_ZZZI_[HS]")>;960 961// Multiply saturating rounding doubling regular/complex, D element size962def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^SQRDMULH_ZZZI?_D")>;963 964// Multiply/multiply long, (8x8) polynomial965def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^PMUL_ZZZ_B")>;966 967def : InstRW<[CortexA320Write<9, CortexA320UnitVMC>], (instregex "^PMULL[BT]_ZZZ_[HDQ]")>;968 969 970// Predicate counting vector971def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>],972 (instregex "^(DEC|INC)[HWD]_ZPiI")>;973def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],974 (instregex "^(SQDEC|SQINC|UQDEC|UQINC)[HWD]_ZPiI")>;975 976// Reciprocal estimate977def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;978 979// Reduction, arithmetic, B form980def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;981 982// Reduction, arithmetic, H form983def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;984 985// Reduction, arithmetic, S form986def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;987 988// Reduction, arithmetic, D form989def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;990 991// Reduction, logical992def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^(ANDV|EORV|ORV)_VPZ_[BHSD]")>;993 994// Reverse, vector995def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^REV_ZZ_[BHSD]",996 "^REVB_ZPmZ_[HSD]",997 "^REVH_ZPmZ_[SD]",998 "^REVW_ZPmZ_D")>;999 1000// Select, vector form1001def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^SEL_ZPZZ_[BHSD]")>;1002 1003// Table lookup1004def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^TBL_ZZZZ?_[BHSD]")>;1005 1006// Table lookup extension1007def : InstRW<[CortexA320Write<8, CortexA320UnitVALU>], (instregex "^TBX_ZZZ_[BHSD]")>;1008 1009// Transpose, vector form1010def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^TRN[12]_ZZZ_[BHSDQ]")>;1011 1012// Unpack and extend1013def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]")>;1014 1015// Zip/unzip1016def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]")>;1017 1018// SVE floating-point instructions1019// -----------------------------------------------------------------------------1020 1021// Floating point absolute value/difference1022def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^FAB[SD]_ZPmZ_[HSD]",1023 "^FAB[SD]_ZPZZ_[HSD]")>;1024 1025// Floating point arithmetic1026def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ|ZPZI|ZPZZ)_[HSD]",1027 "^FADDP_ZPmZZ_[HSD]",1028 "^FNEG_ZPmZ_[HSD]",1029 "^FSUBR_(ZPm[IZ]|ZPZ[IZ])_[HSD]")>;1030 1031// Floating point associative add, F161032def : InstRW<[CortexA320MCWrite<32, 29, CortexA320UnitVALU>], (instrs FADDA_VPZ_H)>;1033 1034// Floating point associative add, F321035def : InstRW<[CortexA320MCWrite<16, 13, CortexA320UnitVALU>], (instrs FADDA_VPZ_S)>;1036 1037// Floating point associative add, F641038def : InstRW<[CortexA320MCWrite<8, 5, CortexA320UnitVALU>], (instrs FADDA_VPZ_D)>;1039 1040// Floating point compare1041def : InstRW<[CortexA320Write<5, CortexA320UnitVALU>], (instregex "^FACG[ET]_PPzZZ_[HSD]",1042 "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]",1043 "^FCM(LE|LT)_PPzZ0_[HSD]",1044 "^FCMUO_PPzZZ_[HSD]")>;1045 1046// Floating point complex add1047def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^FCADD_ZPmZ_[HSD]")>;1048 1049// Floating point complex multiply add1050def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^FCMLA_ZPmZZ_[HSD]",1051 "^FCMLA_ZZZI_[HS]")>;1052 1053// Floating point convert, long or narrow (F16 to F32 or F32 to F16)1054def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",1055 "^FCVTLT_ZPmZ_HtoS",1056 "^FCVTNT_ZPmZ_StoH")>;1057 1058// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F321059// or F64 to F16)1060def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",1061 "^FCVTLT_ZPmZ_StoD",1062 "^FCVTNT_ZPmZ_DtoS")>;1063 1064// Floating point convert, round to odd1065def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^FCVTX_ZPmZ_DtoS", "FCVTXNT_ZPmZ_DtoS")>;1066 1067// Floating point base2 log, F161068def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;1069 1070// Floating point base2 log, F321071def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;1072 1073// Floating point base2 log, F641074def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;1075 1076// Floating point convert to integer, F161077def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;1078 1079// Floating point convert to integer, F321080def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;1081 1082// Floating point convert to integer, F641083def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],1084 (instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>;1085 1086// Floating point copy1087def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^FCPY_ZPmI_[HSD]",1088 "^FDUP_ZI_[HSD]")>;1089 1090// Floating point divide, F161091def : InstRW<[CortexA320MCWrite<8, 5, CortexA320UnitVMC>], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;1092 1093// Floating point divide, F321094def : InstRW<[CortexA320MCWrite<13, 10, CortexA320UnitVMC>], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;1095 1096// Floating point divide, F641097def : InstRW<[CortexA320MCWrite<22, 19, CortexA320UnitVMC>], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;1098 1099// Floating point min/max pairwise1100def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;1101 1102// Floating point min/max1103def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^F(MAX|MIN)(NM)?_(ZPm[IZ]|ZPZZ|ZPZI)_[HSD]")>;1104 1105// Floating point multiply1106def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^(FSCALE|FMULX)_(ZPmZ|ZPZZ)_[HSD]",1107 "^FMUL_(ZPm[IZ]|ZZZI?|ZPZI|ZPZZ)_[HSD]")>;1108 1109// Floating point multiply accumulate1110def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>],1111 (instregex "^FML[AS]_(ZPmZZ|ZZZI|ZPZZZ)_[HSD]",1112 "^(FMAD|FNMAD|FNML[AS]|FN?MSB)_(ZPmZZ|ZPZZZ)_[HSD]")>;1113 1114// Floating point multiply add/sub accumulate long1115def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^FML[AS]L[BT]_ZZZI?_SHH")>;1116 1117// Floating point reciprocal estimate, F161118def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^FRECPE_ZZ_H", "^FRECPX_ZPmZ_H",1119 "^FRSQRTE_ZZ_H")>;1120 1121// Floating point reciprocal estimate, F321122def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^FRECPE_ZZ_S", "^FRECPX_ZPmZ_S",1123 "^FRSQRTE_ZZ_S")>;1124// Floating point reciprocal estimate, F641125def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>],(instregex "^FRECPE_ZZ_D", "^FRECPX_ZPmZ_D",1126 "^FRSQRTE_ZZ_D")>;1127 1128// Floating point reciprocal step1129def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]")>;1130 1131// Floating point reduction, F161132def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],1133 (instregex "^(FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_[HSD]")>;1134 1135// Floating point reduction, F321136def : InstRW<[CortexA320MCWrite<12, 11, CortexA320UnitVALU>],1137 (instregex "^FADDV_VPZ_H")>;1138 1139def : InstRW<[CortexA320MCWrite<8, 5, CortexA320UnitVALU>],1140 (instregex "^FADDV_VPZ_S")>;1141 1142def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>],1143 (instregex "^FADDV_VPZ_D")>;1144 1145 1146// Floating point round to integral, F161147def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;1148 1149// Floating point round to integral, F321150def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;1151 1152// Floating point round to integral, F641153def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;1154 1155// Floating point square root, F161156def : InstRW<[CortexA320MCWrite<11, 5, CortexA320UnitVMC>], (instregex "^FSQRT_ZPmZ_H")>;1157 1158// Floating point square root, F321159def : InstRW<[CortexA320MCWrite<14, 9, CortexA320UnitVMC>], (instregex "^FSQRT_ZPmZ_S")>;1160 1161// Floating point square root, F641162def : InstRW<[CortexA320MCWrite<25, 19, CortexA320UnitVMC>], (instregex "^FSQRT_ZPmZ_D")>;1163 1164// Floating point trigonometric exponentiation1165def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^FEXPA_ZZ_[HSD]")>;1166 1167// Floating point trigonometric multiply add1168def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^FTMAD_ZZI_[HSD]")>;1169 1170// Floating point trigonometric, miscellaneous1171def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^FTSMUL_ZZZ_[HSD]")>;1172def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^FTSSEL_ZZZ_[HSD]")>;1173 1174 1175// SVE BFloat16 (BF16) instructions1176// -----------------------------------------------------------------------------1177 1178// Convert, F32 to BF161179def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;1180 1181// Dot product1182def : InstRW<[CortexA320Write_11cyc_1VMAC_1VALU], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;1183 1184// Matrix multiply accumulate1185def : InstRW<[CortexA320Write_16cyc_1VMAC_1VALU], (instrs BFMMLA_ZZZ_HtoS)>;1186 1187// Multiply accumulate long1188def : InstRW<[CortexA320Write<4, CortexA320UnitVMAC>], (instregex "^BFMLAL[BT]_ZZZ(I)?")>;1189 1190// SVE Load instructions1191// -----------------------------------------------------------------------------1192 1193// Load vector1194def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instrs LDR_ZXI)>;1195 1196// Load predicate1197def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instrs LDR_PXI)>;1198 1199// Contiguous load, scalar + imm1200def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instregex "^LD1[BHWD]_IMM$",1201 "^LD1S?B_[HSD]_IMM$",1202 "^LD1S?H_[SD]_IMM$",1203 "^LD1S?W_D_IMM$" )>;1204// Contiguous load, scalar + scalar1205def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instregex "^LD1[BHWD]$",1206 "^LD1S?B_[HSD]$",1207 "^LD1S?H_[SD]$",1208 "^LD1S?W_D$" )>;1209 1210// Contiguous load broadcast, scalar + imm1211def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instregex "^LD1R[BHWD]_IMM$",1212 "^LD1RSW_IMM$",1213 "^LD1RS?B_[HSD]_IMM$",1214 "^LD1RS?H_[SD]_IMM$",1215 "^LD1RS?W_D_IMM$",1216 "^LD1RQ_[BHWD]_IMM$")>;1217 1218// Contiguous load broadcast, scalar + scalar1219def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instregex "^LD1RQ_[BHWD]$")>;1220 1221// Non temporal load, scalar + imm1222def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instregex "^LDNT1[BHWD]_ZRI$")>;1223 1224// Non temporal load, scalar + scalar1225def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instregex "^LDNT1[BHWD]_ZRR$")>;1226 1227// Non temporal gather load, vector + scalar 32-bit element size1228def : InstRW<[CortexA320MCWrite<9, 9, CortexA320UnitLdSt>], (instregex "^LDNT1[BHW]_ZZR_S$",1229 "^LDNT1S[BH]_ZZR_S$")>;1230 1231// Non temporal gather load, vector + scalar 64-bit element size1232def : InstRW<[CortexA320MCWrite<7, 7, CortexA320UnitLdSt>], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;1233def : InstRW<[CortexA320MCWrite<7, 7, CortexA320UnitLdSt>], (instrs LDNT1D_ZZR_D)>;1234 1235// Contiguous first faulting load, scalar + scalar1236def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instregex "^LDFF1[BHWD]$",1237 "^LDFF1S?B_[HSD]$",1238 "^LDFF1S?H_[SD]$",1239 "^LDFF1S?W_D$")>;1240 1241// Contiguous non faulting load, scalar + imm1242def : InstRW<[CortexA320Write<3, CortexA320UnitLdSt>], (instregex "^LDNF1[BHWD]_IMM$",1243 "^LDNF1S?B_[HSD]_IMM$",1244 "^LDNF1S?H_[SD]_IMM$",1245 "^LDNF1S?W_D_IMM$")>;1246 1247// Contiguous Load two structures to two vectors, scalar + imm1248def : InstRW<[CortexA320MCWrite<3, 1, CortexA320UnitLdSt>], (instregex "^LD2[BHWD]_IMM$")>;1249 1250// Contiguous Load two structures to two vectors, scalar + scalar1251def : InstRW<[CortexA320MCWrite<3, 2, CortexA320UnitLdSt>], (instregex "^LD2[BHWD]$")>;1252 1253// Contiguous Load three structures to three vectors, scalar + imm1254def : InstRW<[CortexA320MCWrite<5, 3, CortexA320UnitLdSt>], (instregex "^LD3[BHWD]_IMM$")>;1255 1256// Contiguous Load three structures to three vectors, scalar + scalar1257def : InstRW<[CortexA320MCWrite<5, 3, CortexA320UnitLdSt>], (instregex "^LD3[BHWD]$")>;1258 1259// Contiguous Load four structures to four vectors, scalar + imm1260def : InstRW<[CortexA320MCWrite<5, 3, CortexA320UnitLdSt>], (instregex "^LD4[BHWD]_IMM$")>;1261 1262// Contiguous Load four structures to four vectors, scalar + scalar1263def : InstRW<[CortexA320MCWrite<5, 3, CortexA320UnitLdSt>], (instregex "^LD4[BHWD]$")>;1264 1265// Gather load, vector + imm, 32-bit element size1266def : InstRW<[CortexA320MCWrite<9, 9, CortexA320UnitLdSt>], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",1267 "^GLD(FF)?1W_IMM$")>;1268 1269// Gather load, vector + imm, 64-bit element size1270def : InstRW<[CortexA320MCWrite<7, 7, CortexA320UnitLdSt>], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",1271 "^GLD(FF)?1D_IMM$")>;1272 1273// Gather load, 64-bit element size1274def : InstRW<[CortexA320MCWrite<7, 7, CortexA320UnitLdSt>],1275 (instregex "^GLD(FF)?1S?[BHW]_D_[SU]XTW(_SCALED)?$",1276 "^GLD(FF)?1S?[BHW]_D(_SCALED)?$",1277 "^GLD(FF)?1D_[SU]XTW(_SCALED)?$",1278 "^GLD(FF)?1D(_SCALED)?$")>;1279 1280// Gather load, 32-bit scaled offset1281def : InstRW<[CortexA320MCWrite<7, 7, CortexA320UnitLdSt>],1282 (instregex "^GLD(FF)?1S?[HW]_S_[SU]XTW_SCALED$",1283 "^GLD(FF)?1W_[SU]XTW_SCALED")>;1284 1285// Gather load, 32-bit unpacked unscaled offset1286def : InstRW<[CortexA320MCWrite<7, 7, CortexA320UnitLdSt>], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",1287 "^GLD(FF)?1W_[SU]XTW$")>;1288 1289def : InstRW<[CortexA320Write<0, CortexA320UnitVALU>], (instregex "^PRF(B|H|W|D).*")>;1290// SVE Store instructions1291// -----------------------------------------------------------------------------1292 1293// Store from predicate reg1294def : InstRW<[CortexA320VSt0], (instrs STR_PXI)>;1295 1296// Store from vector reg1297def : InstRW<[CortexA320VSt0], (instrs STR_ZXI)>;1298 1299// Contiguous store, scalar + imm1300def : InstRW<[CortexA320VSt0], (instregex "^ST1[BHWD]_IMM$",1301 "^ST1B_[HSD]_IMM$",1302 "^ST1H_[SD]_IMM$",1303 "^ST1W_D_IMM$")>;1304 1305// Contiguous store, scalar + scalar1306def : InstRW<[CortexA320VSt0], (instregex "^ST1H(_[SD])?$")>;1307def : InstRW<[CortexA320VSt0], (instregex "^ST1[BWD]$",1308 "^ST1B_[HSD]$",1309 "^ST1W_D$")>;1310 1311// Contiguous store two structures from two vectors, scalar + imm1312def : InstRW<[CortexA320VSt<11>], (instregex "^ST2[BHWD]_IMM$")>;1313 1314// Contiguous store two structures from two vectors, scalar + scalar1315def : InstRW<[CortexA320VSt<11>], (instrs ST2H)>;1316 1317// Contiguous store two structures from two vectors, scalar + scalar1318def : InstRW<[CortexA320VSt<11>], (instregex "^ST2[BWD]$")>;1319 1320// Contiguous store three structures from three vectors, scalar + imm1321def : InstRW<[CortexA320VSt<25>], (instregex "^ST3[BHW]_IMM$")>;1322def : InstRW<[CortexA320VSt<14>], (instregex "^ST3D_IMM$")>;1323 1324// Contiguous store three structures from three vectors, scalar + scalar1325def : InstRW<[CortexA320VSt<25>], (instregex "^ST3[BHW]$")>;1326def : InstRW<[CortexA320VSt<14>], (instregex "^ST3D$")>;1327 1328// Contiguous store four structures from four vectors, scalar + imm1329def : InstRW<[CortexA320VSt<50>], (instregex "^ST4[BHW]_IMM$")>;1330def : InstRW<[CortexA320VSt<25>], (instregex "^ST4D_IMM$")>;1331 1332// Contiguous store four structures from four vectors, scalar + scalar1333def : InstRW<[CortexA320VSt<50>], (instregex "^ST4[BHW]$")>;1334 1335// Contiguous store four structures from four vectors, scalar + scalar1336def : InstRW<[CortexA320VSt<25>], (instregex "^ST4D$")>;1337 1338// Non temporal store, scalar + imm1339def : InstRW<[CortexA320VSt0], (instregex "^STNT1[BHWD]_ZRI$")>;1340 1341// Non temporal store, scalar + scalar1342def : InstRW<[CortexA320VSt0], (instrs STNT1H_ZRR)>;1343def : InstRW<[CortexA320VSt0], (instregex "^STNT1[BWD]_ZRR$")>;1344 1345// Scatter non temporal store, vector + scalar 32-bit element size1346def : InstRW<[CortexA320VSt<9>], (instregex "^STNT1[BHW]_ZZR_S")>;1347 1348// Scatter non temporal store, vector + scalar 64-bit element size1349def : InstRW<[CortexA320VSt<7>], (instregex "^STNT1[BHWD]_ZZR_D")>;1350 1351// Scatter store vector + imm 32-bit element size1352def : InstRW<[CortexA320VSt<9>], (instregex "^SST1[BH]_S_IMM$",1353 "^SST1W_IMM$")>;1354 1355// Scatter store vector + imm 64-bit element size1356def : InstRW<[CortexA320VSt<7>], (instregex "^SST1[BHW]_D_IMM$",1357 "^SST1D_IMM$")>;1358 1359// Scatter store, 32-bit scaled offset1360def : InstRW<[CortexA320VSt<8>],1361 (instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>;1362 1363// Scatter store, 32-bit unpacked unscaled offset1364def : InstRW<[CortexA320VSt<8>], (instregex "^SST1[BHW]_D_[SU]XTW$",1365 "^SST1D_[SU]XTW$")>;1366 1367// Scatter store, 32-bit unpacked scaled offset1368def : InstRW<[CortexA320VSt<8>], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",1369 "^SST1D_[SU]XTW_SCALED$")>;1370 1371// Scatter store, 32-bit unscaled offset1372def : InstRW<[CortexA320VSt<8>], (instregex "^SST1[BH]_S_[SU]XTW$",1373 "^SST1W_[SU]XTW$")>;1374 1375// Scatter store, 64-bit scaled offset1376def : InstRW<[CortexA320VSt<8>], (instregex "^SST1[HW]_D_SCALED$",1377 "^SST1D_SCALED$")>;1378 1379// Scatter store, 64-bit unscaled offset1380def : InstRW<[CortexA320VSt<8>], (instregex "^SST1[BHW]_D$",1381 "^SST1D$")>;1382 1383// SVE Miscellaneous instructions1384// -----------------------------------------------------------------------------1385 1386// Read first fault register, unpredicated1387def : InstRW<[CortexA320Write<1, CortexA320UnitALU>], (instrs RDFFR_P)>;1388 1389// Read first fault register, predicated1390def : InstRW<[CortexA320Write<3, CortexA320UnitALU>], (instrs RDFFR_PPz)>;1391 1392// Read first fault register and set flags1393def : InstRW<[CortexA320Write<3, CortexA320UnitALU>], (instrs RDFFRS_PPz)>;1394 1395// Set first fault register1396// Write to first fault register1397def : InstRW<[CortexA320Write<1, CortexA320UnitALU>], (instrs SETFFR, WRFFR)>;1398 1399// SVE Cryptographic instructions1400// -----------------------------------------------------------------------------1401 1402// Crypto AES ops1403def : InstRW<[CortexA320Write<3, CortexA320UnitVALU>], (instregex "^AES[DE]_ZZZ_B$",1404 "^AESI?MC_ZZ_B$")>;1405 1406// Crypto SHA3 ops1407def : InstRW<[CortexA320Write<4, CortexA320UnitVALU>], (instregex "^(BCAX|EOR3)_ZZZZ$",1408 "^XAR_ZZZI_[BHSD]$")>;1409 1410def : InstRW<[CortexA320MC_RC0Write<9, CortexA320UnitVMC>], (instregex "^RAX1_ZZZ_D$")>;1411 1412// Crypto SM4 ops1413def : InstRW<[CortexA320MC_RC0Write<9, CortexA320UnitVMC>], (instregex "^SM4E(KEY)?_ZZZ_S$")>;1414 1415}1416