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1//==- AArch64SchedCortexA55.td - ARM Cortex-A55 Scheduling Definitions -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for the ARM Cortex-A55 processors. Note10// that this schedule is currently used as the default for -mcpu=generic. As a11// result, some of the modelling decision made do not precisely model the12// Cortex-A55, instead aiming to be a good compromise between different cpus.13//14//===----------------------------------------------------------------------===//15 16// ===---------------------------------------------------------------------===//17// The following definitions describe the per-operand machine model.18// This works with MachineScheduler. See MCSchedModel.h for details.19 20// Cortex-A55 machine model for scheduling and other instruction cost heuristics.21def CortexA55Model : SchedMachineModel {22 let MicroOpBufferSize = 0; // The Cortex-A55 is an in-order processor23 let IssueWidth = 2; // It dual-issues under most circumstances24 let LoadLatency = 4; // Cycles for loads to access the cache. The25 // optimisation guide shows that most loads have26 // a latency of 3, but some have a latency of 427 // or 5. Setting it 4 looked to be good trade-off.28 let MispredictPenalty = 8; // A branch direction mispredict.29 let PostRAScheduler = 1; // Enable PostRA scheduler pass.30 let CompleteModel = 0; // Covers instructions applicable to Cortex-A55.31 32 list<Predicate> UnsupportedFeatures = [HasSVE, HasMTE];33 34 // FIXME: Remove when all errors have been fixed.35 let FullInstRWOverlapCheck = 0;36}37 38//===----------------------------------------------------------------------===//39// Define each kind of processor resource and number available.40 41// Modeling each pipeline as a ProcResource using the BufferSize = 0 since the42// Cortex-A55 is in-order.43 44def CortexA55UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU45def CortexA55UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC, 64-bi wide46def CortexA55UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division, not pipelined47def CortexA55UnitLd : ProcResource<1> { let BufferSize = 0; } // Load pipe48def CortexA55UnitSt : ProcResource<1> { let BufferSize = 0; } // Store pipe49def CortexA55UnitB : ProcResource<1> { let BufferSize = 0; } // Branch50 51// The FP DIV/SQRT instructions execute totally differently from the FP ALU52// instructions, which can mostly be dual-issued; that's why for now we model53// them with 2 resources.54def CortexA55UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU55def CortexA55UnitFPMAC : ProcResource<2> { let BufferSize = 0; } // FP MAC56def CortexA55UnitFPDIV : ProcResource<1> { let BufferSize = 0; } // FP Div/SQRT, 64/12857 58//===----------------------------------------------------------------------===//59// Subtarget-specific SchedWrite types60 61let SchedModel = CortexA55Model in {62 63// These latencies are modeled without taking into account forwarding paths64// (the software optimisation guide lists latencies taking into account65// typical forwarding paths).66def : WriteRes<WriteImm, [CortexA55UnitALU]> { let Latency = 3; } // MOVN, MOVZ67def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU68def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg69def : WriteRes<WriteIEReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Extended-Reg70def : WriteRes<WriteExtr, [CortexA55UnitALU]> { let Latency = 3; } // EXTR from a reg pair71def : WriteRes<WriteIS, [CortexA55UnitALU]> { let Latency = 3; } // Shift/Scale72 73// MAC74def : WriteRes<WriteIM32, [CortexA55UnitMAC]> { let Latency = 4; } // 32-bit Multiply75def : WriteRes<WriteIM64, [CortexA55UnitMAC]> { let Latency = 4; } // 64-bit Multiply76 77// Div78def : WriteRes<WriteID32, [CortexA55UnitDiv]> {79 let Latency = 8; let ReleaseAtCycles = [8];80}81def : WriteRes<WriteID64, [CortexA55UnitDiv]> {82 let Latency = 8; let ReleaseAtCycles = [8];83}84 85// Load86def : WriteRes<WriteLD, [CortexA55UnitLd]> { let Latency = 3; }87def : WriteRes<WriteLDIdx, [CortexA55UnitLd]> { let Latency = 4; }88def : WriteRes<WriteLDHi, [CortexA55UnitLd]> { let Latency = 5; }89 90// Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd91// below, choosing the median of 3 which makes the latency 6.92// An extra cycle is needed to get the swizzling right.93def : WriteRes<WriteVLD, [CortexA55UnitLd]> { let Latency = 6;94 let ReleaseAtCycles = [3]; }95def CortexA55WriteVLD1 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; }96def CortexA55WriteVLD1SI : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; let SingleIssue = 1; }97def CortexA55WriteVLD2 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 5;98 let ReleaseAtCycles = [2]; }99def CortexA55WriteVLD3 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 6;100 let ReleaseAtCycles = [3]; }101def CortexA55WriteVLD4 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 7;102 let ReleaseAtCycles = [4]; }103def CortexA55WriteVLD5 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 8;104 let ReleaseAtCycles = [5]; }105def CortexA55WriteVLD6 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 9;106 let ReleaseAtCycles = [6]; }107def CortexA55WriteVLD7 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 10;108 let ReleaseAtCycles = [7]; }109def CortexA55WriteVLD8 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 11;110 let ReleaseAtCycles = [8]; }111 112def CortexA55WriteLDP1 : SchedWriteRes<[]> { let Latency = 4; }113def CortexA55WriteLDP2 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 5; }114def CortexA55WriteLDP4 : SchedWriteRes<[CortexA55UnitLd, CortexA55UnitLd, CortexA55UnitLd, CortexA55UnitLd, CortexA55UnitLd]> { let Latency = 6; }115 116// Pre/Post Indexing - Performed as part of address generation117def : WriteRes<WriteAdr, []> { let Latency = 0; }118 119// Store120let RetireOOO = 1 in {121def : WriteRes<WriteST, [CortexA55UnitSt]> { let Latency = 1; }122def : WriteRes<WriteSTP, [CortexA55UnitSt]> { let Latency = 1; }123def : WriteRes<WriteSTIdx, [CortexA55UnitSt]> { let Latency = 1; }124}125def : WriteRes<WriteSTX, [CortexA55UnitSt]> { let Latency = 4; }126 127// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.128def : WriteRes<WriteVST, [CortexA55UnitSt]> { let Latency = 5;129 let ReleaseAtCycles = [2];}130def CortexA55WriteVST1 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 4; }131def CortexA55WriteVST2 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;132 let ReleaseAtCycles = [2]; }133def CortexA55WriteVST3 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 6;134 let ReleaseAtCycles = [3]; }135def CortexA55WriteVST4 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;136 let ReleaseAtCycles = [4]; }137 138def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }139 140// Branch141def : WriteRes<WriteBr, [CortexA55UnitB]>;142def : WriteRes<WriteBrReg, [CortexA55UnitB]>;143def : WriteRes<WriteSys, [CortexA55UnitB]>;144def : WriteRes<WriteBarrier, [CortexA55UnitB]>;145def : WriteRes<WriteHint, [CortexA55UnitB]>;146 147// FP ALU148// As WriteF result is produced in F5 and it can be mostly forwarded149// to consumer at F1, the effectively latency is set as 4.150def : WriteRes<WriteF, [CortexA55UnitFPALU]> { let Latency = 4; }151def : WriteRes<WriteFCmp, [CortexA55UnitFPALU]> { let Latency = 3; }152def : WriteRes<WriteFCvt, [CortexA55UnitFPALU]> { let Latency = 4; }153def : WriteRes<WriteFCopy, [CortexA55UnitFPALU]> { let Latency = 3; }154def : WriteRes<WriteFImm, [CortexA55UnitFPALU]> { let Latency = 3; }155 156// NEON157class CortexA55WriteVd<int n, ProcResourceKind res> : SchedWriteRes<[res]> {158 let Latency = n;159}160class CortexA55WriteVq<int n, ProcResourceKind res> : SchedWriteRes<[res, res]> {161 let Latency = n;162 let BeginGroup = 1;163}164def CortexA55WriteDotScVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;165def CortexA55WriteDotVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;166def CortexA55WriteDotVd_4 : CortexA55WriteVd<4, CortexA55UnitFPALU>;167def CortexA55WriteMlaLVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;168def CortexA55WriteMlaIxVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;169def CortexA55WriteMlaVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;170def CortexA55WriteMlaVd_4 : CortexA55WriteVd<4, CortexA55UnitFPALU>;171def CortexA55WriteAluVq_4 : CortexA55WriteVq<4, CortexA55UnitFPALU>;172def CortexA55WriteAluVd_3 : CortexA55WriteVd<3, CortexA55UnitFPALU>;173def CortexA55WriteAluVq_3 : CortexA55WriteVq<3, CortexA55UnitFPALU>;174def CortexA55WriteAluVd_2 : CortexA55WriteVd<2, CortexA55UnitFPALU>;175def CortexA55WriteAluVq_2 : CortexA55WriteVq<2, CortexA55UnitFPALU>;176def CortexA55WriteAluVd_1 : CortexA55WriteVd<1, CortexA55UnitFPALU>;177def CortexA55WriteAluVq_1 : CortexA55WriteVq<1, CortexA55UnitFPALU>;178def : SchedAlias<WriteVd, CortexA55WriteVd<4, CortexA55UnitFPALU>>;179def : SchedAlias<WriteVq, CortexA55WriteVq<4, CortexA55UnitFPALU>>;180 181// FP ALU specific new schedwrite definitions182def CortexA55WriteFPALU_F2 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 2;}183def CortexA55WriteFPALU_F3 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 3;}184def CortexA55WriteFPALU_F4 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 4;}185def CortexA55WriteFPALU_F5 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 5;}186 187// FP Mul, Div, Sqrt. Div/Sqrt are not pipelined188def : WriteRes<WriteFMul, [CortexA55UnitFPMAC]> { let Latency = 4; }189 190let RetireOOO = 1 in {191def : WriteRes<WriteFDiv, [CortexA55UnitFPDIV]> { let Latency = 22;192 let ReleaseAtCycles = [29]; }193def CortexA55WriteFMAC : SchedWriteRes<[CortexA55UnitFPMAC]> { let Latency = 4; }194def CortexA55WriteFDivHP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 8;195 let ReleaseAtCycles = [5]; }196def CortexA55WriteFDivSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 13;197 let ReleaseAtCycles = [10]; }198def CortexA55WriteFDivDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;199 let ReleaseAtCycles = [19]; }200def CortexA55WriteFSqrtHP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 8;201 let ReleaseAtCycles = [5]; }202def CortexA55WriteFSqrtSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 12;203 let ReleaseAtCycles = [9]; }204def CortexA55WriteFSqrtDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;205 let ReleaseAtCycles = [19]; }206}207//===----------------------------------------------------------------------===//208// Subtarget-specific SchedRead types.209 210def : ReadAdvance<ReadVLD, 0>;211def : ReadAdvance<ReadExtrHi, 1>;212def : ReadAdvance<ReadAdrBase, 1>;213def : ReadAdvance<ReadST, 1>;214 215// ALU - ALU input operands are generally needed in EX1. An operand produced in216// in say EX2 can be forwarded for consumption to ALU in EX1, thereby217// allowing back-to-back ALU operations such as add. If an operand requires218// a shift, it will, however, be required in ISS stage.219def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,220 WriteISReg, WriteIEReg,WriteIS,221 WriteID32,WriteID64,222 WriteIM32,WriteIM64]>;223// Shifted operand224def CortexA55ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,225 WriteISReg, WriteIEReg,WriteIS,226 WriteID32,WriteID64,227 WriteIM32,WriteIM64]>;228def CortexA55ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,229 WriteISReg, WriteIEReg,WriteIS,230 WriteID32,WriteID64,231 WriteIM32,WriteIM64]>;232def CortexA55ReadISReg : SchedReadVariant<[233 SchedVar<RegShiftedPred, [CortexA55ReadShifted]>,234 SchedVar<NoSchedPred, [CortexA55ReadNotShifted]>]>;235def : SchedAlias<ReadISReg, CortexA55ReadISReg>;236 237def CortexA55ReadIEReg : SchedReadVariant<[238 SchedVar<RegExtendedPred, [CortexA55ReadShifted]>,239 SchedVar<NoSchedPred, [CortexA55ReadNotShifted]>]>;240def : SchedAlias<ReadIEReg, CortexA55ReadIEReg>;241 242// MUL243def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,244 WriteISReg, WriteIEReg,WriteIS,245 WriteID32,WriteID64,246 WriteIM32,WriteIM64]>;247def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,248 WriteISReg, WriteIEReg,WriteIS,249 WriteID32,WriteID64,250 WriteIM32,WriteIM64]>;251 252// Div253def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,254 WriteISReg, WriteIEReg,WriteIS,255 WriteID32,WriteID64,256 WriteIM32,WriteIM64]>;257 258//===----------------------------------------------------------------------===//259// Subtarget-specific InstRWs.260 261//---262// Miscellaneous263//---264def : InstRW<[CortexA55WriteVLD1SI,CortexA55WriteLDP1], (instregex "LDPS?Wi")>;265def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP1], (instregex "LDPSi")>;266def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP2], (instregex "LDP(X|D)i")>;267def : InstRW<[CortexA55WriteVLD1,CortexA55WriteLDP4], (instregex "LDPQi")>;268def : InstRW<[WriteAdr, CortexA55WriteVLD1SI,CortexA55WriteLDP1], (instregex "LDPS?W(pre|post)")>;269def : InstRW<[WriteAdr, CortexA55WriteVLD1,CortexA55WriteLDP1], (instregex "LDPS(pre|post)")>;270def : InstRW<[WriteAdr, CortexA55WriteVLD1,CortexA55WriteLDP2], (instregex "LDP(X|D)(pre|post)")>;271def : InstRW<[WriteAdr, CortexA55WriteVLD1,CortexA55WriteLDP4], (instregex "LDPQ(pre|post)")>;272def : InstRW<[WriteI], (instrs COPY)>;273//---274// Vector Loads - 64-bit per cycle275//---276// 1-element structures277def : InstRW<[CortexA55WriteVLD1], (instregex "LD1i(8|16|32|64)$")>; // single element278def : InstRW<[CortexA55WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // replicate279def : InstRW<[CortexA55WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d)$")>;280def : InstRW<[CortexA55WriteVLD2], (instregex "LD1Onev(16b|8h|4s|2d)$")>;281def : InstRW<[CortexA55WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d)$")>; // multiple structures282def : InstRW<[CortexA55WriteVLD4], (instregex "LD1Twov(16b|8h|4s|2d)$")>;283def : InstRW<[CortexA55WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d)$")>;284def : InstRW<[CortexA55WriteVLD6], (instregex "LD1Threev(16b|8h|4s|2d)$")>;285def : InstRW<[CortexA55WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;286def : InstRW<[CortexA55WriteVLD8], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;287 288def : InstRW<[WriteAdr, CortexA55WriteVLD1], (instregex "LD1i(8|16|32|64)_POST$")>;289def : InstRW<[WriteAdr, CortexA55WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;290def : InstRW<[WriteAdr, CortexA55WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;291def : InstRW<[WriteAdr, CortexA55WriteVLD2], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;292def : InstRW<[WriteAdr, CortexA55WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;293def : InstRW<[WriteAdr, CortexA55WriteVLD4], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;294def : InstRW<[WriteAdr, CortexA55WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;295def : InstRW<[WriteAdr, CortexA55WriteVLD6], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;296def : InstRW<[WriteAdr, CortexA55WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;297def : InstRW<[WriteAdr, CortexA55WriteVLD8], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;298 299// 2-element structures300def : InstRW<[CortexA55WriteVLD2], (instregex "LD2i(8|16|32|64)$")>;301def : InstRW<[CortexA55WriteVLD2], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;302def : InstRW<[CortexA55WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;303def : InstRW<[CortexA55WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;304 305def : InstRW<[WriteAdr, CortexA55WriteVLD2], (instregex "LD2i(8|16|32|64)(_POST)?$")>;306def : InstRW<[WriteAdr, CortexA55WriteVLD2], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;307def : InstRW<[WriteAdr, CortexA55WriteVLD2], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;308def : InstRW<[WriteAdr, CortexA55WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;309 310// 3-element structures311def : InstRW<[CortexA55WriteVLD2], (instregex "LD3i(8|16|32|64)$")>;312def : InstRW<[CortexA55WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;313def : InstRW<[CortexA55WriteVLD3], (instregex "LD3Threev(8b|4h|2s|1d)$")>;314def : InstRW<[CortexA55WriteVLD6], (instregex "LD3Threev(16b|8h|4s|2d)$")>;315 316def : InstRW<[WriteAdr, CortexA55WriteVLD2], (instregex "LD3i(8|16|32|64)_POST$")>;317def : InstRW<[WriteAdr, CortexA55WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;318def : InstRW<[WriteAdr, CortexA55WriteVLD3], (instregex "LD3Threev(8b|4h|2s|1d)_POST$")>;319def : InstRW<[WriteAdr, CortexA55WriteVLD6], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;320 321// 4-element structures322def : InstRW<[CortexA55WriteVLD2], (instregex "LD4i(8|16|32|64)$")>; // load single 4-el structure to one lane of 4 regs.323def : InstRW<[CortexA55WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // load single 4-el structure, replicate to all lanes of 4 regs.324def : InstRW<[CortexA55WriteVLD4], (instregex "LD4Fourv(8b|4h|2s|1d)$")>; // load multiple 4-el structures to 4 regs.325def : InstRW<[CortexA55WriteVLD8], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;326 327def : InstRW<[WriteAdr, CortexA55WriteVLD2], (instregex "LD4i(8|16|32|64)_POST$")>;328def : InstRW<[WriteAdr, CortexA55WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;329def : InstRW<[WriteAdr, CortexA55WriteVLD4], (instregex "LD4Fourv(8b|4h|2s|1d)_POST$")>;330def : InstRW<[WriteAdr, CortexA55WriteVLD8], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;331 332//---333// Vector Stores334//---335def : InstRW<[CortexA55WriteVST1], (instregex "ST1i(8|16|32|64)$")>;336def : InstRW<[CortexA55WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;337def : InstRW<[CortexA55WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;338def : InstRW<[CortexA55WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;339def : InstRW<[CortexA55WriteVST4], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;340def : InstRW<[WriteAdr, CortexA55WriteVST1], (instregex "ST1i(8|16|32|64)_POST$")>;341def : InstRW<[WriteAdr, CortexA55WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;342def : InstRW<[WriteAdr, CortexA55WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;343def : InstRW<[WriteAdr, CortexA55WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;344def : InstRW<[WriteAdr, CortexA55WriteVST4], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;345 346def : InstRW<[CortexA55WriteVST2], (instregex "ST2i(8|16|32|64)$")>;347def : InstRW<[CortexA55WriteVST2], (instregex "ST2Twov(8b|4h|2s)$")>;348def : InstRW<[CortexA55WriteVST4], (instregex "ST2Twov(16b|8h|4s|2d)$")>;349def : InstRW<[WriteAdr, CortexA55WriteVST2], (instregex "ST2i(8|16|32|64)_POST$")>;350def : InstRW<[WriteAdr, CortexA55WriteVST2], (instregex "ST2Twov(8b|4h|2s)_POST$")>;351def : InstRW<[WriteAdr, CortexA55WriteVST4], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;352 353def : InstRW<[CortexA55WriteVST2], (instregex "ST3i(8|16|32|64)$")>;354def : InstRW<[CortexA55WriteVST4], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;355def : InstRW<[WriteAdr, CortexA55WriteVST2], (instregex "ST3i(8|16|32|64)_POST$")>;356def : InstRW<[WriteAdr, CortexA55WriteVST4], (instregex "ST3Threev(8b|4h|2s|1d|2d|16b|8h|4s|4d)_POST$")>;357 358def : InstRW<[CortexA55WriteVST2], (instregex "ST4i(8|16|32|64)$")>;359def : InstRW<[CortexA55WriteVST4], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;360def : InstRW<[WriteAdr, CortexA55WriteVST2], (instregex "ST4i(8|16|32|64)_POST$")>;361def : InstRW<[WriteAdr, CortexA55WriteVST4], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;362 363//---364// Floating Point Conversions, MAC, DIV, SQRT365//---366def : InstRW<[CortexA55WriteFPALU_F2], (instregex "^DUP(v2i64|v4i32|v8i16|v16i8)")>;367def : InstRW<[CortexA55WriteFPALU_F2], (instregex "^XTN")>;368def : InstRW<[CortexA55WriteFPALU_F3], (instregex "^FCVT[ALMNPZ][SU](S|U)?(W|X)")>;369def : InstRW<[CortexA55WriteFPALU_F4], (instregex "^FCVT(X)?[ALMNPXZ](S|U|N)?v")>;370 371def : InstRW<[CortexA55WriteFPALU_F4], (instregex "^(S|U)CVTF(S|U)(W|X)(H|S|D)")>;372def : InstRW<[CortexA55WriteFPALU_F4], (instregex "^(S|U)CVTF(h|s|d)")>;373def : InstRW<[CortexA55WriteFPALU_F4], (instregex "^(S|U)CVTFv")>;374 375def : InstRW<[CortexA55WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>;376def : InstRW<[CortexA55WriteFMAC], (instregex "^FML(A|S).*")>;377def : InstRW<[CortexA55WriteFDivHP], (instrs FDIVHrr)>;378def : InstRW<[CortexA55WriteFDivSP], (instrs FDIVSrr)>;379def : InstRW<[CortexA55WriteFDivDP], (instrs FDIVDrr)>;380def : InstRW<[CortexA55WriteFDivHP], (instregex "^FDIVv.*16$")>;381def : InstRW<[CortexA55WriteFDivSP], (instregex "^FDIVv.*32$")>;382def : InstRW<[CortexA55WriteFDivDP], (instregex "^FDIVv.*64$")>;383def : InstRW<[CortexA55WriteFSqrtHP], (instregex "^.*SQRT.*16$")>;384def : InstRW<[CortexA55WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;385def : InstRW<[CortexA55WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;386 387// 4.15. Advanced SIMD integer instructions388// ASIMD absolute diff389def : InstRW<[CortexA55WriteAluVd_3], (instregex "[SU]ABDv(2i32|4i16|8i8)")>;390def : InstRW<[CortexA55WriteAluVq_3], (instregex "[SU]ABDv(16i8|4i32|8i16)")>;391// ASIMD absolute diff accum392def : InstRW<[CortexA55WriteAluVq_4], (instregex "[SU]ABAL?v")>;393// ASIMD absolute diff long394def : InstRW<[CortexA55WriteAluVq_3], (instregex "[SU]ABDLv")>;395// ASIMD arith #1396def : InstRW<[CortexA55WriteAluVd_2], (instregex "(ADD|SUB|NEG)v(1i64|2i32|4i16|8i8)",397 "[SU]R?HADDv(2i32|4i16|8i8)", "[SU]HSUBv(2i32|4i16|8i8)")>;398def : InstRW<[CortexA55WriteAluVq_2], (instregex "(ADD|SUB|NEG)v(2i64|4i32|8i16|16i8)",399 "[SU]R?HADDv(8i16|4i32|16i8)", "[SU]HSUBv(8i16|4i32|16i8)")>;400// ASIMD arith #2401def : InstRW<[CortexA55WriteAluVd_3], (instregex "ABSv(1i64|2i32|4i16|8i8)$",402 "[SU]ADDLPv(2i32_v1i64|4i16_v2i32|8i8_v4i16)$", 403 "([SU]QADD|[SU]QSUB|SQNEG|SUQADD|USQADD)v(1i16|1i32|1i64|1i8|2i32|4i16|8i8)$",404 "ADDPv(2i32|4i16|8i8)$")>;405def : InstRW<[CortexA55WriteAluVq_3], (instregex "ABSv(2i64|4i32|8i16|16i8)$",406 "[SU]ADDLPv(16i8_v8i16|4i32_v2i64|8i16_v4i32)$", 407 "([SU]QADD|[SU]QSUB|SQNEG|SUQADD|USQADD)v(16i8|2i64|4i32|8i16)$",408 "ADDPv(16i8|2i64|4i32|8i16)$")>;409// ASIMD arith #3410def : InstRW<[CortexA55WriteAluVq_3], (instregex "SADDLv", "UADDLv", "SADDWv",411 "UADDWv", "SSUBLv", "USUBLv", "SSUBWv", "USUBWv", "ADDHNv", "SUBHNv")>;412// ASIMD arith #5413def : InstRW<[CortexA55WriteAluVq_4], (instregex "RADDHNv", "RSUBHNv")>;414// ASIMD arith, reduce415def : InstRW<[CortexA55WriteAluVq_3], (instregex "ADDVv", "SADDLVv", "UADDLVv")>;416// ASIMD compare #1417def : InstRW<[CortexA55WriteAluVd_2], (instregex "CM(EQ|GE|GT|HI|HS|LE|LT)v(1i64|2i32|4i16|8i8)")>;418def : InstRW<[CortexA55WriteAluVq_2], (instregex "CM(EQ|GE|GT|HI|HS|LE|LT)v(2i64|4i32|8i16|16i8)")>;419// ASIMD compare #2420def : InstRW<[CortexA55WriteAluVd_3], (instregex "CMTSTv(1i64|2i32|4i16|8i8)")>;421def : InstRW<[CortexA55WriteAluVq_3], (instregex "CMTSTv(2i64|4i32|8i16|16i8)")>;422// ASIMD logical $1423def : InstRW<[CortexA55WriteAluVd_1], (instregex "(AND|EOR|NOT|ORN)v8i8",424 "(ORR|BIC)v(2i32|4i16|8i8)$", "MVNIv(2i|2s|4i16)")>;425def : InstRW<[CortexA55WriteAluVq_1], (instregex "(AND|EOR|NOT|ORN)v16i8",426 "(ORR|BIC)v(16i8|4i32|8i16)$", "MVNIv(4i32|4s|8i16)")>;427// ASIMD max/min, basic428def : InstRW<[CortexA55WriteAluVd_2], (instregex "[SU](MIN|MAX)P?v(2i32|4i16|8i8)")>;429def : InstRW<[CortexA55WriteAluVq_2], (instregex "[SU](MIN|MAX)P?v(16i8|4i132|8i16)")>;430// SIMD max/min, reduce431def : InstRW<[CortexA55WriteAluVq_4], (instregex "[SU](MAX|MIN)Vv")>;432// ASIMD multiply, by element433def : InstRW<[CortexA55WriteAluVq_4], (instregex "MULv(2i32|4i16|4i32|8i16)_indexed$",434 "SQR?DMULHv(1i16|1i32|2i32|4i16|4i32|8i16)_indexed$")>;435// ASIMD multiply436def : InstRW<[CortexA55WriteAluVd_3], (instrs PMULv8i8)>;437def : InstRW<[CortexA55WriteAluVq_3], (instrs PMULv16i8)>;438// ASIMD multiply accumulate439def : InstRW<[CortexA55WriteMlaVd_4], (instregex "ML[AS]v(2i32|4i16|8i8)$")>;440def : InstRW<[CortexA55WriteMlaVq_4], (instregex "ML[AS]v(16i8|4i32|8i16)$")>;441def : InstRW<[CortexA55WriteMlaIxVq_4], (instregex "ML[AS]v(2i32|4i16|4i32|8i16)_indexed$")>;442// ASIMD multiply accumulate half443def : InstRW<[CortexA55WriteAluVq_4], (instregex "SQRDML[AS]H[vi]")>;444// ASIMD multiply accumulate long445def : InstRW<[CortexA55WriteMlaLVq_4], (instregex "[SU]ML[AS]Lv")>;446// ASIMD multiply accumulate long #2447def : InstRW<[CortexA55WriteAluVq_4], (instregex "SQDML[AS]L[iv]")>;448// ASIMD dot product449def : InstRW<[CortexA55WriteDotVd_4], (instregex "[SU]DOTv8i8")>;450def : InstRW<[CortexA55WriteDotVq_4], (instregex "[SU]DOTv16i8")>;451// ASIMD dot product, by scalar452def : InstRW<[CortexA55WriteDotScVq_4], (instregex "[SU]DOTlanev")>;453// ASIMD multiply long454def : InstRW<[CortexA55WriteAluVq_4], (instregex "[SU]MULLv", "SQDMULL[iv]")>;455// ASIMD polynomial (8x8) multiply long456def : InstRW<[CortexA55WriteAluVq_3], (instrs PMULLv8i8, PMULLv16i8)>;457// ASIMD pairwise add and accumulate458def : InstRW<[CortexA55WriteAluVq_4], (instregex "[SU]ADALPv")>;459// ASIMD shift accumulate460def : InstRW<[CortexA55WriteAluVd_3], (instregex "[SU]SRA(d|v2i32|v4i16|v8i8)")>;461def : InstRW<[CortexA55WriteAluVq_3], (instregex "[SU]SRAv(16i8|2i64|4i32|8i16)")>;462// ASIMD shift accumulate #2463def : InstRW<[CortexA55WriteAluVq_4], (instregex "[SU]RSRA[vd]")>;464// ASIMD shift by immed465def : InstRW<[CortexA55WriteAluVd_2], (instregex "SHLd$", "SHLv",466 "SLId$", "SRId$", "[SU]SHR[vd]", "SHRNv")>;467// ASIMD shift by immed468// SXTL and UXTL are aliases for SHLL469def : InstRW<[CortexA55WriteAluVq_2], (instregex "[US]?SHLLv")>;470// ASIMD shift by immed #2471def : InstRW<[CortexA55WriteAluVd_3], (instregex "[SU]RSHR(d|v2i32|v4i16|v8i8)",472 "RSHRNv(2i32|4i16|8i8)")>;473def : InstRW<[CortexA55WriteAluVq_3], (instregex "[SU]RSHRv(16i8|2i64|4i32|8i16)",474 "RSHRNv(16i8|4i32|8i16)")>;475// ASIMD shift by register476def : InstRW<[CortexA55WriteAluVd_2], (instregex "[SU]SHLv(1i64|2i32|4i16|8i8)")>;477def : InstRW<[CortexA55WriteAluVq_2], (instregex "[SU]SHLv(2i64|4i32|8i16|16i8)")>;478// ASIMD shift by register #2479def : InstRW<[CortexA55WriteAluVd_3], (instregex "[SU]RSHLv(1i64|2i32|4i16|8i8)")>;480def : InstRW<[CortexA55WriteAluVq_3], (instregex "[SU]RSHLv(2i64|4i32|8i16|16i8)")>;481 482}483