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1//=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// Contains all of the Cortex-A57 specific SchedWriteRes types. The approach10// below is to define a generic SchedWriteRes for every combination of11// latency and microOps. The naming conventions is to use a prefix, one field12// for latency, and one or more microOp count/type designators.13// Prefix: A57Write14// Latency: #cyc15// MicroOp Count/Types: #(B|I|M|L|S|X|W|V)16// Postfix (optional): (XYZ)_Forward17//18// The postfix is added to differentiate SchedWriteRes that are used in19// subsequent SchedReadAdvances.20//21// e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are22// 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes.23//24//===----------------------------------------------------------------------===//25 26//===----------------------------------------------------------------------===//27// Define Generic 1 micro-op types28 29def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }30def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }31def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }32def A57Write_5cyc_1V_FP_Forward : SchedWriteRes<[A57UnitV]> { let Latency = 5; }33def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }34def A57Write_5cyc_1W_Mul_Forward : SchedWriteRes<[A57UnitW]> { let Latency = 5; }35def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }36def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;37 let ReleaseAtCycles = [17]; }38def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;39 let ReleaseAtCycles = [19]; }40def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }41def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }42def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }43def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }44def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;45 let ReleaseAtCycles = [32]; }46def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;47 let ReleaseAtCycles = [35]; }48def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }49def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }50def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }51def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }52def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; }53def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }54def A57Write_4cyc_1X_NonMul_Forward : SchedWriteRes<[A57UnitX]> { let Latency = 4; }55def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }56def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }57def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }58 59 60//===----------------------------------------------------------------------===//61// Define Generic 2 micro-op types62 63def A57Write_64cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {64 let Latency = 64;65 let NumMicroOps = 2;66 let ReleaseAtCycles = [32, 32];67}68def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,69 A57UnitL]> {70 let Latency = 6;71 let NumMicroOps = 2;72}73def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,74 A57UnitX]> {75 let Latency = 7;76 let NumMicroOps = 2;77}78def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL,79 A57UnitV]> {80 let Latency = 8;81 let NumMicroOps = 2;82}83def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {84 let Latency = 9;85 let NumMicroOps = 2;86}87def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {88 let Latency = 8;89 let NumMicroOps = 2;90}91def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> {92 let Latency = 6;93 let NumMicroOps = 2;94}95def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {96 let Latency = 6;97 let NumMicroOps = 2;98}99def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {100 let Latency = 6;101 let NumMicroOps = 2;102}103def A57Write_6cyc_2W_Mul_Forward : SchedWriteRes<[A57UnitW, A57UnitW]> {104 let Latency = 6;105 let NumMicroOps = 2;106}107def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI,108 A57UnitL]> {109 let Latency = 5;110 let NumMicroOps = 2;111}112def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {113 let Latency = 5;114 let NumMicroOps = 2;115}116def A57Write_5cyc_2V_FP_Forward : SchedWriteRes<[A57UnitV, A57UnitV]> {117 let Latency = 5;118 let NumMicroOps = 2;119}120def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {121 let Latency = 5;122 let NumMicroOps = 2;123}124def A57Write_5cyc_2X_NonMul_Forward : SchedWriteRes<[A57UnitX, A57UnitX]> {125 let Latency = 5;126 let NumMicroOps = 2;127}128def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,129 A57UnitV]> {130 let Latency = 10;131 let NumMicroOps = 2;132}133def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {134 let Latency = 10;135 let NumMicroOps = 2;136}137def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB,138 A57UnitI]> {139 let Latency = 1;140 let NumMicroOps = 2;141}142def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI,143 A57UnitS]> {144 let Latency = 1;145 let NumMicroOps = 2;146}147def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB,148 A57UnitI]> {149 let Latency = 2;150 let NumMicroOps = 2;151}152def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> {153 let Latency = 2;154 let NumMicroOps = 2;155}156def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {157 let Latency = 2;158 let NumMicroOps = 2;159}160def A57Write_34cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {161 let Latency = 34;162 let NumMicroOps = 2;163 let ReleaseAtCycles = [17, 17];164}165def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,166 A57UnitM]> {167 let Latency = 3;168 let NumMicroOps = 2;169}170def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,171 A57UnitS]> {172 let Latency = 3;173 let NumMicroOps = 2;174}175def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,176 A57UnitV]> {177 let Latency = 3;178 let NumMicroOps = 2;179}180def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {181 let Latency = 3;182 let NumMicroOps = 2;183}184def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI,185 A57UnitL]> {186 let Latency = 4;187 let NumMicroOps = 2;188}189def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {190 let Latency = 4;191 let NumMicroOps = 2;192}193 194 195//===----------------------------------------------------------------------===//196// Define Generic 3 micro-op types197 198def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {199 let Latency = 10;200 let NumMicroOps = 3;201}202def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI,203 A57UnitS, A57UnitS]> {204 let Latency = 2;205 let NumMicroOps = 3;206}207def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI,208 A57UnitS,209 A57UnitV]> {210 let Latency = 3;211 let NumMicroOps = 3;212}213def A57Write_3cyc_1M_2S : SchedWriteRes<[A57UnitM,214 A57UnitS, A57UnitS]> {215 let Latency = 3;216 let NumMicroOps = 3;217}218def A57Write_3cyc_3S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> {219 let Latency = 3;220 let NumMicroOps = 3;221}222def A57Write_3cyc_2S_1V : SchedWriteRes<[A57UnitS, A57UnitS,223 A57UnitV]> {224 let Latency = 3;225 let NumMicroOps = 3;226}227def A57Write_5cyc_1I_2L : SchedWriteRes<[A57UnitI,228 A57UnitL, A57UnitL]> {229 let Latency = 5;230 let NumMicroOps = 3;231}232def A57Write_6cyc_1I_2L : SchedWriteRes<[A57UnitI,233 A57UnitL, A57UnitL]> {234 let Latency = 6;235 let NumMicroOps = 3;236}237def A57Write_6cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {238 let Latency = 6;239 let NumMicroOps = 3;240}241def A57Write_7cyc_3L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> {242 let Latency = 7;243 let NumMicroOps = 3;244}245def A57Write_8cyc_1I_1L_1V : SchedWriteRes<[A57UnitI,246 A57UnitL,247 A57UnitV]> {248 let Latency = 8;249 let NumMicroOps = 3;250}251def A57Write_8cyc_1L_2V : SchedWriteRes<[A57UnitL,252 A57UnitV, A57UnitV]> {253 let Latency = 8;254 let NumMicroOps = 3;255}256def A57Write_8cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {257 let Latency = 8;258 let NumMicroOps = 3;259}260def A57Write_9cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {261 let Latency = 9;262 let NumMicroOps = 3;263}264 265 266//===----------------------------------------------------------------------===//267// Define Generic 4 micro-op types268 269def A57Write_2cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI,270 A57UnitS, A57UnitS]> {271 let Latency = 2;272 let NumMicroOps = 4;273}274def A57Write_3cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI,275 A57UnitS, A57UnitS]> {276 let Latency = 3;277 let NumMicroOps = 4;278}279def A57Write_3cyc_1I_3S : SchedWriteRes<[A57UnitI,280 A57UnitS, A57UnitS, A57UnitS]> {281 let Latency = 3;282 let NumMicroOps = 4;283}284def A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI,285 A57UnitS, A57UnitS,286 A57UnitV]> {287 let Latency = 3;288 let NumMicroOps = 4;289}290def A57Write_4cyc_4S : SchedWriteRes<[A57UnitS, A57UnitS,291 A57UnitS, A57UnitS]> {292 let Latency = 4;293 let NumMicroOps = 4;294}295def A57Write_7cyc_1I_3L : SchedWriteRes<[A57UnitI,296 A57UnitL, A57UnitL, A57UnitL]> {297 let Latency = 7;298 let NumMicroOps = 4;299}300def A57Write_5cyc_2I_2L : SchedWriteRes<[A57UnitI, A57UnitI,301 A57UnitL, A57UnitL]> {302 let Latency = 5;303 let NumMicroOps = 4;304}305def A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI,306 A57UnitL,307 A57UnitV, A57UnitV]> {308 let Latency = 8;309 let NumMicroOps = 4;310}311def A57Write_8cyc_4L : SchedWriteRes<[A57UnitL, A57UnitL,312 A57UnitL, A57UnitL]> {313 let Latency = 8;314 let NumMicroOps = 4;315}316def A57Write_9cyc_2L_2V : SchedWriteRes<[A57UnitL, A57UnitL,317 A57UnitV, A57UnitV]> {318 let Latency = 9;319 let NumMicroOps = 4;320}321def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL,322 A57UnitV, A57UnitV, A57UnitV]> {323 let Latency = 9;324 let NumMicroOps = 4;325}326def A57Write_12cyc_4V : SchedWriteRes<[A57UnitV, A57UnitV,327 A57UnitV, A57UnitV]> {328 let Latency = 12;329 let NumMicroOps = 4;330}331 332 333//===----------------------------------------------------------------------===//334// Define Generic 5 micro-op types335 336def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,337 A57UnitV, A57UnitV]> {338 let Latency = 3;339 let NumMicroOps = 5;340}341def A57Write_8cyc_1I_4L : SchedWriteRes<[A57UnitI,342 A57UnitL, A57UnitL,343 A57UnitL, A57UnitL]> {344 let Latency = 8;345 let NumMicroOps = 5;346}347def A57Write_4cyc_1I_4S : SchedWriteRes<[A57UnitI,348 A57UnitS, A57UnitS,349 A57UnitS, A57UnitS]> {350 let Latency = 4;351 let NumMicroOps = 5;352}353def A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI,354 A57UnitL, A57UnitL,355 A57UnitV, A57UnitV]> {356 let Latency = 9;357 let NumMicroOps = 5;358}359def A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI,360 A57UnitL,361 A57UnitV, A57UnitV, A57UnitV]> {362 let Latency = 9;363 let NumMicroOps = 5;364}365def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL,366 A57UnitV, A57UnitV, A57UnitV]> {367 let Latency = 9;368 let NumMicroOps = 5;369}370def A57Write_9cyc_5V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,371 A57UnitV, A57UnitV]> {372 let Latency = 9;373 let NumMicroOps = 5;374}375 376 377//===----------------------------------------------------------------------===//378// Define Generic 6 micro-op types379 380def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI,381 A57UnitS, A57UnitS, A57UnitS,382 A57UnitV, A57UnitV]> {383 let Latency = 3;384 let NumMicroOps = 6;385}386def A57Write_4cyc_2I_4S : SchedWriteRes<[A57UnitI, A57UnitI,387 A57UnitS, A57UnitS,388 A57UnitS, A57UnitS]> {389 let Latency = 4;390 let NumMicroOps = 6;391}392def A57Write_4cyc_4S_2V : SchedWriteRes<[A57UnitS, A57UnitS,393 A57UnitS, A57UnitS,394 A57UnitV, A57UnitV]> {395 let Latency = 4;396 let NumMicroOps = 6;397}398def A57Write_6cyc_6S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,399 A57UnitS, A57UnitS, A57UnitS]> {400 let Latency = 6;401 let NumMicroOps = 6;402}403def A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI,404 A57UnitL, A57UnitL,405 A57UnitV, A57UnitV, A57UnitV]> {406 let Latency = 9;407 let NumMicroOps = 6;408}409def A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI,410 A57UnitL,411 A57UnitV, A57UnitV,412 A57UnitV, A57UnitV]> {413 let Latency = 9;414 let NumMicroOps = 6;415}416def A57Write_9cyc_2L_4V : SchedWriteRes<[A57UnitL, A57UnitL,417 A57UnitV, A57UnitV,418 A57UnitV, A57UnitV]> {419 let Latency = 9;420 let NumMicroOps = 6;421}422 423 424//===----------------------------------------------------------------------===//425// Define Generic 7 micro-op types426 427def A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL,428 A57UnitV, A57UnitV,429 A57UnitV, A57UnitV]> {430 let Latency = 10;431 let NumMicroOps = 7;432}433def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI,434 A57UnitS, A57UnitS,435 A57UnitS, A57UnitS,436 A57UnitV, A57UnitV]> {437 let Latency = 4;438 let NumMicroOps = 7;439}440def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI,441 A57UnitS, A57UnitS, A57UnitS,442 A57UnitS, A57UnitS, A57UnitS]> {443 let Latency = 6;444 let NumMicroOps = 7;445}446def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI,447 A57UnitL, A57UnitL,448 A57UnitV, A57UnitV,449 A57UnitV, A57UnitV]> {450 let Latency = 9;451 let NumMicroOps = 7;452}453def A57Write_12cyc_7V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,454 A57UnitV, A57UnitV,455 A57UnitV, A57UnitV]> {456 let Latency = 12;457 let NumMicroOps = 7;458}459 460 461//===----------------------------------------------------------------------===//462// Define Generic 8 micro-op types463 464def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI,465 A57UnitL, A57UnitL, A57UnitL,466 A57UnitV, A57UnitV,467 A57UnitV, A57UnitV]> {468 let Latency = 10;469 let NumMicroOps = 8;470}471def A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL,472 A57UnitL, A57UnitL,473 A57UnitV, A57UnitV,474 A57UnitV, A57UnitV]> {475 let Latency = 11;476 let NumMicroOps = 8;477}478def A57Write_8cyc_8S : SchedWriteRes<[A57UnitS, A57UnitS,479 A57UnitS, A57UnitS,480 A57UnitS, A57UnitS,481 A57UnitS, A57UnitS]> {482 let Latency = 8;483 let NumMicroOps = 8;484}485 486 487//===----------------------------------------------------------------------===//488// Define Generic 9 micro-op types489 490def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI,491 A57UnitS, A57UnitS,492 A57UnitS, A57UnitS,493 A57UnitS, A57UnitS,494 A57UnitS, A57UnitS]> {495 let Latency = 8;496 let NumMicroOps = 9;497}498def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI,499 A57UnitL, A57UnitL,500 A57UnitL, A57UnitL,501 A57UnitV, A57UnitV,502 A57UnitV, A57UnitV]> {503 let Latency = 11;504 let NumMicroOps = 9;505}506def A57Write_15cyc_9V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,507 A57UnitV, A57UnitV, A57UnitV,508 A57UnitV, A57UnitV, A57UnitV]> {509 let Latency = 15;510 let NumMicroOps = 9;511}512 513 514//===----------------------------------------------------------------------===//515// Define Generic 10 micro-op types516 517def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,518 A57UnitS, A57UnitS, A57UnitS,519 A57UnitV, A57UnitV,520 A57UnitV, A57UnitV]> {521 let Latency = 6;522 let NumMicroOps = 10;523}524 525 526//===----------------------------------------------------------------------===//527// Define Generic 11 micro-op types528 529def A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI,530 A57UnitS, A57UnitS, A57UnitS,531 A57UnitS, A57UnitS, A57UnitS,532 A57UnitV, A57UnitV,533 A57UnitV, A57UnitV]> {534 let Latency = 6;535 let NumMicroOps = 11;536}537 538 539//===----------------------------------------------------------------------===//540// Define Generic 12 micro-op types541 542def A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS,543 A57UnitS, A57UnitS, A57UnitS, A57UnitS,544 A57UnitV, A57UnitV,545 A57UnitV, A57UnitV]> {546 let Latency = 8;547 let NumMicroOps = 12;548}549 550//===----------------------------------------------------------------------===//551// Define Generic 13 micro-op types552 553def A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI,554 A57UnitS, A57UnitS, A57UnitS,555 A57UnitS, A57UnitS, A57UnitS,556 A57UnitS, A57UnitS,557 A57UnitV, A57UnitV,558 A57UnitV, A57UnitV]> {559 let Latency = 8;560 let NumMicroOps = 13;561}562 563