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1//==- AArch64SchedFalkor.td - Falkor Scheduling Definitions -*- tablegen -*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for Qualcomm Falkor to support10// instruction scheduling and other instruction cost heuristics.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// Define the SchedMachineModel and provide basic properties for coarse grained16// instruction cost model.17 18def FalkorModel : SchedMachineModel {19 let IssueWidth = 8; // 8 uops are dispatched per cycle.20 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.21 let LoopMicroOpBufferSize = 16;22 let LoadLatency = 3; // Optimistic load latency.23 let MispredictPenalty = 11; // Minimum branch misprediction penalty.24 let CompleteModel = 1;25 26 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,27 PAUnsupported.F,28 SMEUnsupported.F,29 [HasMTE, HasCSSC]);30 // FIXME: Remove when all errors have been fixed.31 let FullInstRWOverlapCheck = 0;32}33 34//===----------------------------------------------------------------------===//35// Define each kind of processor resource and number available on Falkor.36 37let SchedModel = FalkorModel in {38 39 def FalkorUnitB : ProcResource<1>; // Branch40 def FalkorUnitLD : ProcResource<1>; // Load pipe41 def FalkorUnitSD : ProcResource<1>; // Store data42 def FalkorUnitST : ProcResource<1>; // Store pipe43 def FalkorUnitX : ProcResource<1>; // Complex arithmetic44 def FalkorUnitY : ProcResource<1>; // Simple arithmetic45 def FalkorUnitZ : ProcResource<1>; // Simple arithmetic46 47 def FalkorUnitVSD : ProcResource<1>; // Vector store data48 def FalkorUnitVX : ProcResource<1>; // Vector X-pipe49 def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe50 51 def FalkorUnitGTOV : ProcResource<1>; // Scalar to Vector52 def FalkorUnitVTOG : ProcResource<1>; // Vector to Scalar53 54 // Define the resource groups.55 def FalkorUnitXY : ProcResGroup<[FalkorUnitX, FalkorUnitY]>;56 def FalkorUnitXYZ : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ]>;57 def FalkorUnitXYZB : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ,58 FalkorUnitB]>;59 def FalkorUnitZB : ProcResGroup<[FalkorUnitZ, FalkorUnitB]>;60 def FalkorUnitVXVY : ProcResGroup<[FalkorUnitVX, FalkorUnitVY]>;61 62}63 64//===----------------------------------------------------------------------===//65// Map the target-defined scheduler read/write resources and latency for66// Falkor.67 68let SchedModel = FalkorModel in {69 70// These WriteRes entries are not used in the Falkor sched model.71def : WriteRes<WriteImm, []> { let Unsupported = 1; }72def : WriteRes<WriteI, []> { let Unsupported = 1; }73def : WriteRes<WriteISReg, []> { let Unsupported = 1; }74def : WriteRes<WriteIEReg, []> { let Unsupported = 1; }75def : WriteRes<WriteExtr, []> { let Unsupported = 1; }76def : WriteRes<WriteIS, []> { let Unsupported = 1; }77def : WriteRes<WriteID32, []> { let Unsupported = 1; }78def : WriteRes<WriteID64, []> { let Unsupported = 1; }79def : WriteRes<WriteIM32, []> { let Unsupported = 1; }80def : WriteRes<WriteIM64, []> { let Unsupported = 1; }81def : WriteRes<WriteBr, []> { let Unsupported = 1; }82def : WriteRes<WriteBrReg, []> { let Unsupported = 1; }83def : WriteRes<WriteLD, []> { let Unsupported = 1; }84def : WriteRes<WriteST, []> { let Unsupported = 1; }85def : WriteRes<WriteSTP, []> { let Unsupported = 1; }86def : WriteRes<WriteAdr, []> { let Unsupported = 1; }87def : WriteRes<WriteLDIdx, []> { let Unsupported = 1; }88def : WriteRes<WriteSTIdx, []> { let Unsupported = 1; }89def : WriteRes<WriteF, []> { let Unsupported = 1; }90def : WriteRes<WriteFCmp, []> { let Unsupported = 1; }91def : WriteRes<WriteFCvt, []> { let Unsupported = 1; }92def : WriteRes<WriteFCopy, []> { let Unsupported = 1; }93def : WriteRes<WriteFImm, []> { let Unsupported = 1; }94def : WriteRes<WriteFMul, []> { let Unsupported = 1; }95def : WriteRes<WriteFDiv, []> { let Unsupported = 1; }96def : WriteRes<WriteVd, []> { let Unsupported = 1; }97def : WriteRes<WriteVq, []> { let Unsupported = 1; }98def : WriteRes<WriteVLD, []> { let Unsupported = 1; }99def : WriteRes<WriteVST, []> { let Unsupported = 1; }100def : WriteRes<WriteSys, []> { let Unsupported = 1; }101def : WriteRes<WriteBarrier, []> { let Unsupported = 1; }102def : WriteRes<WriteHint, []> { let Unsupported = 1; }103def : WriteRes<WriteLDHi, []> { let Unsupported = 1; }104def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }105 106// These ReadAdvance entries are not used in the Falkor sched model.107def : ReadAdvance<ReadI, 0>;108def : ReadAdvance<ReadISReg, 0>;109def : ReadAdvance<ReadIEReg, 0>;110def : ReadAdvance<ReadIM, 0>;111def : ReadAdvance<ReadIMA, 0>;112def : ReadAdvance<ReadID, 0>;113def : ReadAdvance<ReadExtrHi, 0>;114def : ReadAdvance<ReadAdrBase, 0>;115def : ReadAdvance<ReadVLD, 0>;116def : ReadAdvance<ReadST, 0>;117 118// Detailed Refinements119// -----------------------------------------------------------------------------120include "AArch64SchedFalkorDetails.td"121 122}123