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1//==- AArch64SchedKryo.td - Qualcomm Kryo Scheduling Defs ---*- tablegen -*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for Qualcomm Kryo to support10// instruction scheduling and other instruction cost heuristics.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// The issue width is set to five, matching the five issue queues for expanded16// uops. Now, the latency spreadsheet has information based on fragmented uops,17// but these do not actually take up an issue queue.18 19def KryoModel : SchedMachineModel {20 let IssueWidth = 5; // 5-wide issue for expanded uops21 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer22 let LoadLatency = 4; // Optimistic load latency23 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch24 25 // Enable partial & runtime unrolling. The magic number is chosen based on26 // experiments and benchmarking data.27 let LoopMicroOpBufferSize = 16;28 let CompleteModel = 1;29 30 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,31 PAUnsupported.F,32 SMEUnsupported.F,33 [HasMTE, HasCSSC]);34 // FIXME: Remove when all errors have been fixed.35 let FullInstRWOverlapCheck = 0;36}37 38//===----------------------------------------------------------------------===//39// Define each kind of processor resource and number available on Kryo.40 41let SchedModel = KryoModel in {42 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops43 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops44 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops45 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops46 def KryoUnitX : ProcResGroup<[KryoUnitXA, // Type X micro-ops47 KryoUnitXB]>;48 def KryoUnitY : ProcResGroup<[KryoUnitYA, // Type Y micro-ops49 KryoUnitYB]>;50 def KryoUnitXY : ProcResGroup<[KryoUnitXA, // Type XY micro-ops51 KryoUnitXB,52 KryoUnitYA,53 KryoUnitYB]>;54 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops55 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops56 def KryoUnitLS : ProcResGroup<[KryoUnitLSA, // Type LS micro-ops57 KryoUnitLSB]>;58}59 60let SchedModel = KryoModel in {61 62//===----------------------------------------------------------------------===//63// Map the target-defined scheduler read/write resources and latency for64// Kryo.65 66def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }67def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }68def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]>69 { let Latency = 2; let NumMicroOps = 2; }70def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]>71 { let Latency = 2; let NumMicroOps = 2; }72def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]>73 { let Latency = 2; let NumMicroOps = 2; }74def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }75def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]>76 { let Latency = 8; let NumMicroOps = 1; } // Fragent -177def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]>78 { let Latency = 8; let NumMicroOps = 1; } // Fragent -179def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }80def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; }81def : WriteRes<WriteBr, [KryoUnitXY]> { let Latency = 1; }82def : WriteRes<WriteBrReg, [KryoUnitXY]> { let Latency = 1; }83def : WriteRes<WriteLD, [KryoUnitLS]> { let Latency = 4; }84def : WriteRes<WriteST, [KryoUnitLS]> { let Latency = 4; }85def : WriteRes<WriteSTP, [KryoUnitLS]> { let Latency = 4; }86def : WriteRes<WriteAdr, [KryoUnitXY]> { let Latency = 6; }87def : WriteRes<WriteLDIdx, [KryoUnitLS]> { let Latency = 4; }88def : WriteRes<WriteSTIdx, [KryoUnitLS]> { let Latency = 4; }89def : WriteRes<WriteF, [KryoUnitXY, KryoUnitXY]>90 { let Latency = 3; let NumMicroOps = 2; }91def : WriteRes<WriteFCmp, [KryoUnitXY]> { let Latency = 2; }92def : WriteRes<WriteFCvt, [KryoUnitX]> { let Latency = 4; }93def : WriteRes<WriteFCopy, [KryoUnitXY]> { let Latency = 6; }94def : WriteRes<WriteFImm, [KryoUnitXY]> { let Latency = 6; }95def : WriteRes<WriteFMul, [KryoUnitX, KryoUnitX]>96 { let Latency = 6; let NumMicroOps = 2; }97def : WriteRes<WriteFDiv, [KryoUnitXA, KryoUnitY]>98 { let Latency = 12; let NumMicroOps = 2; } // Fragent -1 / NoRSV +199def : WriteRes<WriteVd, [KryoUnitXY]> { let Latency = 6; }100def : WriteRes<WriteVq, [KryoUnitXY]> { let Latency = 6; }101def : WriteRes<WriteVLD, [KryoUnitLS]> { let Latency = 4; }102def : WriteRes<WriteVST, [KryoUnitLS]> { let Latency = 4; }103 104def : WriteRes<WriteSys, []> { let Latency = 1; }105def : WriteRes<WriteBarrier, []> { let Latency = 1; }106def : WriteRes<WriteHint, []> { let Latency = 1; }107 108def : WriteRes<WriteLDHi, []> { let Latency = 4; }109 110def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }111 112// No forwarding logic is modelled yet.113def : ReadAdvance<ReadI, 0>;114def : ReadAdvance<ReadISReg, 0>;115def : ReadAdvance<ReadIEReg, 0>;116def : ReadAdvance<ReadIM, 0>;117def : ReadAdvance<ReadIMA, 0>;118def : ReadAdvance<ReadID, 0>;119def : ReadAdvance<ReadExtrHi, 0>;120def : ReadAdvance<ReadAdrBase, 0>;121def : ReadAdvance<ReadVLD, 0>;122def : ReadAdvance<ReadST, 0>;123 124 125//===----------------------------------------------------------------------===//126// Specialize the coarse model by associating instruction groups with the127// subtarget-defined types. As the modeled is refined, this will override most128// of the above SchedWriteRes and SchedAlias mappings.129 130// Miscellaneous131// -----------------------------------------------------------------------------132 133def : InstRW<[WriteI], (instrs COPY)>;134 135 136// Detailed Refinedments137// -----------------------------------------------------------------------------138include "AArch64SchedKryoDetails.td"139 140 141} // SchedModel = KryoModel142