brintos / llvm-project-archived public Read only

1//=- AArch64SchedKryoDetails.td - QC Kryo Scheduling Defs ----*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the uop and latency details for the machine model for the10// Qualcomm Kryo subtarget.11//12//===----------------------------------------------------------------------===//13 14def KryoWrite_3cyc_X_noRSV_138ln :15	SchedWriteRes<[KryoUnitX]> {16    let Latency = 3; let NumMicroOps = 2;17}18def : InstRW<[KryoWrite_3cyc_X_noRSV_138ln],19    (instregex "(S|U)R?SRA(d|(v2i32|v4i16|v8i8)_shift)")>;20 21def KryoWrite_3cyc_X_X_139ln :22	SchedWriteRes<[KryoUnitX, KryoUnitX]> {23    let Latency = 3; let NumMicroOps = 2;24}25def : InstRW<[KryoWrite_3cyc_X_X_139ln],26    (instregex "(S|U)R?SRA(v2i64|v4i32|v8i16|v16i8)_shift")>;27 28def KryoWrite_4cyc_XY_XY_noRSV_172ln :29    SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {30    let Latency = 4; let NumMicroOps = 3;31}32def : InstRW<[KryoWrite_4cyc_XY_XY_noRSV_172ln],33	(instregex "(S|U)ABA(v8i8|v4i16|v2i32)")>;34def KryoWrite_4cyc_XY_XY_XY_XY_178ln :35    SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY, KryoUnitXY]> {36    let Latency = 4; let NumMicroOps = 4;37}38def : InstRW<[KryoWrite_4cyc_XY_XY_XY_XY_178ln],39	(instregex "(S|U)ABA(v16i8|v8i16|v4i32)")>;40def KryoWrite_3cyc_XY_XY_XY_XY_177ln :41	SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY, KryoUnitXY]> {42    let Latency = 3; let NumMicroOps = 4;43}44def : InstRW<[KryoWrite_3cyc_XY_XY_XY_XY_177ln],45	(instregex "(S|U)ABALv.*")>;46def KryoWrite_3cyc_XY_XY_166ln :47	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {48    let Latency = 3; let NumMicroOps = 2;49}50def : InstRW<[KryoWrite_3cyc_XY_XY_166ln],51	(instregex "(S|U)(ABD|QSUB|RHADD)(v16i8|v8i16|v4i32|v2i64)")>;52def KryoWrite_3cyc_XY_noRSV_159ln :53	SchedWriteRes<[KryoUnitXY]> {54    let Latency = 3; let NumMicroOps = 2;55}56def : InstRW<[KryoWrite_3cyc_XY_noRSV_159ln],57	(instregex "(S|U)(ABD|RHADD)(v8i8|v4i16|v2i32)")>;58def KryoWrite_3cyc_XY_XY_165ln :59	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {60    let Latency = 3; let NumMicroOps = 2;61}62def : InstRW<[KryoWrite_3cyc_XY_XY_165ln],63	(instregex "(S|U)ABDLv.*")>;64def KryoWrite_3cyc_X_noRSV_154ln :65	SchedWriteRes<[KryoUnitX]> {66let Latency = 3; let NumMicroOps = 2;67}68def : InstRW<[KryoWrite_3cyc_X_noRSV_154ln],69	(instregex "(S|U)ADALP(v8i8|v4i16|v2i32)_v.*")>;70def KryoWrite_3cyc_X_X_155ln :71	SchedWriteRes<[KryoUnitX, KryoUnitX]> {72	let Latency = 3; let NumMicroOps = 2;73}74def : InstRW<[KryoWrite_3cyc_X_X_155ln],75	(instregex "(S|U)ADALP(v16i8|v8i16|v4i32)_v.*")>;76def KryoWrite_2cyc_XY_XY_151ln :77	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {78	let Latency = 2; let NumMicroOps = 2;79}80def : InstRW<[KryoWrite_2cyc_XY_XY_151ln],81	(instregex "(S|U)(ADD|SUB)Lv.*")>;82def KryoWrite_2cyc_XY_noRSV_148ln :83	SchedWriteRes<[KryoUnitXY]> {84	let Latency = 2; let NumMicroOps = 2;85}86def : InstRW<[KryoWrite_2cyc_XY_noRSV_148ln],87	(instregex "((S|U)ADDLP|ABS)(v2i32|v4i16|v8i8)(_v.*)?")>;88def KryoWrite_2cyc_XY_XY_150ln :89	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {90	let Latency = 2; let NumMicroOps = 2;91}92def : InstRW<[KryoWrite_2cyc_XY_XY_150ln],93	(instregex "((S|U)ADDLP|ABS)(v2i64|v4i32|v8i16|v16i8)(_v.*)?")>;94def KryoWrite_3cyc_XY_XY_XY_noRSV_179ln :95	SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY]> {96	let Latency = 3; let NumMicroOps = 4;97}98def : InstRW<[KryoWrite_3cyc_XY_XY_XY_noRSV_179ln],99	(instrs SADDLVv4i32v, UADDLVv4i32v)>;100def KryoWrite_5cyc_XY_XY_XY_noRSV_180ln :101	SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY]> {102	let Latency = 5; let NumMicroOps = 4;103}104def : InstRW<[KryoWrite_5cyc_XY_XY_XY_noRSV_180ln],105	(instrs SADDLVv8i16v, UADDLVv8i16v)>;106def KryoWrite_6cyc_XY_XY_X_noRSV_181ln :107	SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitX]> {108	let Latency = 6; let NumMicroOps = 4;109}110def : InstRW<[KryoWrite_6cyc_XY_XY_X_noRSV_181ln],111	(instrs SADDLVv16i8v, UADDLVv16i8v)>;112def KryoWrite_3cyc_XY_noRSV_158ln :113	SchedWriteRes<[KryoUnitXY]> {114	let Latency = 3; let NumMicroOps = 2;115}116def : InstRW<[KryoWrite_3cyc_XY_noRSV_158ln],117	(instrs SADDLVv4i16v, UADDLVv4i16v, ADDVv4i16v)>;118def KryoWrite_4cyc_X_noRSV_169ln :119	SchedWriteRes<[KryoUnitX]> {120	let Latency = 4; let NumMicroOps = 2;121}122def : InstRW<[KryoWrite_4cyc_X_noRSV_169ln],123	(instrs SADDLVv8i8v, UADDLVv8i8v, ADDVv8i8v)>;124def KryoWrite_2cyc_XY_XY_XY_XY_176ln :125	SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY, KryoUnitXY]> {126	let Latency = 2; let NumMicroOps = 4;127}128def : InstRW<[KryoWrite_2cyc_XY_XY_XY_XY_176ln],129	(instregex "(S|U)(ADDW|SUBW)v.*")>;130def KryoWrite_4cyc_X_noRSV_40ln :131	SchedWriteRes<[KryoUnitX]> {132	let Latency = 4; let NumMicroOps = 2;133}134def : InstRW<[KryoWrite_4cyc_X_noRSV_40ln],135	(instregex "(S|U)CVTFS(W|X)(D|S)ri")>;136def KryoWrite_4cyc_X_noRSV_97ln :137	SchedWriteRes<[KryoUnitX]> {138	let Latency = 4; let NumMicroOps = 2;139}140def : InstRW<[KryoWrite_4cyc_X_noRSV_97ln],141	(instregex "(S|U)CVTFU(W|X)(D|S)ri")>;142def KryoWrite_4cyc_X_noRSV_110ln :143	SchedWriteRes<[KryoUnitX]> {144	let Latency = 4; let NumMicroOps = 2;145}146def : InstRW<[KryoWrite_4cyc_X_noRSV_110ln],147	(instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;148def KryoWrite_4cyc_X_X_114ln :149	SchedWriteRes<[KryoUnitX, KryoUnitX]> {150	let Latency = 4; let NumMicroOps = 2;151}152def : InstRW<[KryoWrite_4cyc_X_X_114ln],153	(instregex "(S|U)CVTF(v2i64|v4i32|v2f64|v4f32)(_shift)?")>;154def KryoWrite_1cyc_XA_Y_98ln :155	SchedWriteRes<[KryoUnitXA, KryoUnitY]> {156	let Latency = 1; let NumMicroOps = 2;157}158def : InstRW<[KryoWrite_1cyc_XA_Y_98ln],159	(instregex "(S|U)DIV(_Int)?(W|X)r")>;160def KryoWrite_2cyc_XY_XY_152ln :161	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {162	let Latency = 2; let NumMicroOps = 2;163}164def : InstRW<[KryoWrite_2cyc_XY_XY_152ln],165	(instregex "(S|U)H(ADD|SUB)(v16i8|v8i16|v4i32)")>;166def KryoWrite_2cyc_XY_noRSV_149ln :167	SchedWriteRes<[KryoUnitXY]> {168	let Latency = 2; let NumMicroOps = 2;169}170def : InstRW<[KryoWrite_2cyc_XY_noRSV_149ln],171	(instregex "((S|U)H(ADD|SUB)|ADDP)(v8i8|v4i16|v2i32)")>;172def KryoWrite_4cyc_X_70ln :173	SchedWriteRes<[KryoUnitX]> {174	let Latency = 4; let NumMicroOps = 1;175}176def : InstRW<[KryoWrite_4cyc_X_70ln],177	(instregex "(S|U)(MADDL|MSUBL)rrr")>;178def KryoWrite_4cyc_X_X_191ln :179	SchedWriteRes<[KryoUnitX, KryoUnitX]> {180	let Latency = 4; let NumMicroOps = 2;181}182def : InstRW<[KryoWrite_4cyc_X_X_191ln],183	(instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>;184def KryoWrite_1cyc_XY_195ln :185	SchedWriteRes<[KryoUnitXY]> {186	let Latency = 1; let NumMicroOps = 1;187}188def : InstRW<[KryoWrite_1cyc_XY_195ln],189	(instregex "(S|U)MOVv.*")>;190def KryoWrite_5cyc_X_71ln :191	SchedWriteRes<[KryoUnitX]> {192	let Latency = 5; let NumMicroOps = 1;193}194def : InstRW<[KryoWrite_5cyc_X_71ln],195	(instrs SMULHrr, UMULHrr)>;196def KryoWrite_3cyc_XY_noRSV_186ln :197	SchedWriteRes<[KryoUnitXY]> {198	let Latency = 3; let NumMicroOps = 2;199}200def : InstRW<[KryoWrite_3cyc_XY_noRSV_186ln],201	(instregex "^(S|U)QADD(v8i8|v4i16|v2i32)")>;202def KryoWrite_3cyc_XY_XY_187ln :203	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {204	let Latency = 3; let NumMicroOps = 2;205}206def : InstRW<[KryoWrite_3cyc_XY_XY_187ln],207	(instregex "^(S|U)QADD(v16i8|v8i16|v4i32|v2i64)")>;208def KryoWrite_3cyc_XY_noRSV_69ln :209	SchedWriteRes<[KryoUnitXY]> {210	let Latency = 3; let NumMicroOps = 2;211}212def : InstRW<[KryoWrite_3cyc_XY_noRSV_69ln],213	(instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;214def KryoWrite_3cyc_XY_noRSV_248ln :215	SchedWriteRes<[KryoUnitXY]> {216	let Latency = 3; let NumMicroOps = 2;217}218def : InstRW<[KryoWrite_3cyc_XY_noRSV_248ln],219	(instregex "(S|U)QSHLU?(d|s|h|b|(v8i8|v4i16|v2i32)_shift)$")>;220def KryoWrite_3cyc_XY_XY_250ln :221	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {222	let Latency = 3; let NumMicroOps = 2;223}224def : InstRW<[KryoWrite_3cyc_XY_XY_250ln],225	(instregex "(S|U)(QSHLU?|RSHR)(v16i8|v8i16|v4i32|v2i64)_shift$")>;226def KryoWrite_3cyc_XY_noRSV_246ln :227	SchedWriteRes<[KryoUnitXY]> {228	let Latency = 3; let NumMicroOps = 2;229}230def : InstRW<[KryoWrite_3cyc_XY_noRSV_246ln],231	(instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;232def KryoWrite_3cyc_XY_XY_251ln :233	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {234	let Latency = 3; let NumMicroOps = 2;235}236def : InstRW<[KryoWrite_3cyc_XY_XY_251ln],237	(instregex "(S|U)(QSHL|RSHL|QRSHL)(v16i8|v8i16|v4i32|v2i64)$")>;238def KryoWrite_6cyc_XY_X_238ln :239	SchedWriteRes<[KryoUnitXY, KryoUnitX]> {240	let Latency = 6; let NumMicroOps = 2;241}242def : InstRW<[KryoWrite_6cyc_XY_X_238ln],243	(instregex "((S|U)QR?SHRN|SQR?SHRUN)(v16i8|v8i16|v4i32)_shift$")>;244def KryoWrite_3cyc_XY_noRSV_249ln :245	SchedWriteRes<[KryoUnitXY]> {246	let Latency = 3; let NumMicroOps = 2;247}248def : InstRW<[KryoWrite_3cyc_XY_noRSV_249ln],249	(instregex "((S|U)QR?SHRN|SQR?SHRUN)(s|h|b)?")>;250def KryoWrite_6cyc_XY_X_noRSV_252ln :251	SchedWriteRes<[KryoUnitXY, KryoUnitX]> {252	let Latency = 6; let NumMicroOps = 3;253}254def : InstRW<[KryoWrite_6cyc_XY_X_noRSV_252ln],255	(instregex "((S|U)QR?SHRN|SQR?SHRUN)(v8i8|v4i16|v2i32)_shift?")>;256def KryoWrite_3cyc_XY_noRSV_161ln :257	SchedWriteRes<[KryoUnitXY]> {258	let Latency = 3; let NumMicroOps = 2;259}260def : InstRW<[KryoWrite_3cyc_XY_noRSV_161ln],261	(instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;262def KryoWrite_3cyc_XY_noRSV_163ln :263	SchedWriteRes<[KryoUnitXY]> {264	let Latency = 3; let NumMicroOps = 2;265}266def : InstRW<[KryoWrite_3cyc_XY_noRSV_163ln],267	(instregex "(S|U)QXTU?N(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)")>;268def KryoWrite_3cyc_XY_noRSV_162ln :269	SchedWriteRes<[KryoUnitXY]> {270	let Latency = 3; let NumMicroOps = 2;271}272def : InstRW<[KryoWrite_3cyc_XY_noRSV_162ln],273	(instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>;274def KryoWrite_3cyc_XY_noRSV_247ln :275	SchedWriteRes<[KryoUnitXY]> {276	let Latency = 3; let NumMicroOps = 2;277}278def : InstRW<[KryoWrite_3cyc_XY_noRSV_247ln],279	(instregex "(S|U)RSHR(d|(v8i8|v4i16|v2i32)_shift)$")>;280def KryoWrite_2cyc_XY_noRSV_239ln :281	SchedWriteRes<[KryoUnitXY]> {282	let Latency = 2; let NumMicroOps = 2;283}284def : InstRW<[KryoWrite_2cyc_XY_noRSV_239ln],285	(instregex "(S|U)SHL(d|v8i8|v4i16|v2i32|v1i64)$")>;286def KryoWrite_2cyc_XY_XY_243ln :287	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {288	let Latency = 2; let NumMicroOps = 2;289}290def : InstRW<[KryoWrite_2cyc_XY_XY_243ln],291	(instregex "(S|U)SHL(v16i8|v8i16|v4i32|v2i64)$")>;292def KryoWrite_2cyc_XY_XY_241ln :293	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {294	let Latency = 2; let NumMicroOps = 2;295}296def : InstRW<[KryoWrite_2cyc_XY_XY_241ln],297	(instregex "(S|U)?SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>;298def KryoWrite_2cyc_XY_noRSV_240ln :299	SchedWriteRes<[KryoUnitXY]> {300	let Latency = 2; let NumMicroOps = 2;301}302def : InstRW<[KryoWrite_2cyc_XY_noRSV_240ln],303	(instregex "((S|U)SHR|SHL)(d|(v8i8|v4i16|v2i32)_shift)$")>;304def KryoWrite_2cyc_XY_XY_242ln :305	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {306	let Latency = 2; let NumMicroOps = 2;307}308def : InstRW<[KryoWrite_2cyc_XY_XY_242ln],309	(instregex "((S|U)SHR|SHL)(v16i8|v8i16|v4i32|v2i64)_shift$")>;310def KryoWrite_2cyc_XY_XY_183ln :311	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {312	let Latency = 2; let NumMicroOps = 2;313}314def : InstRW<[KryoWrite_2cyc_XY_XY_183ln],315	(instregex "(S|U)(MAX|MIN)P?(v16i8|v8i16|v4i32)")>;316def KryoWrite_2cyc_XY_noRSV_182ln :317	SchedWriteRes<[KryoUnitXY]> {318	let Latency = 2; let NumMicroOps = 2;319}320def : InstRW<[KryoWrite_2cyc_XY_noRSV_182ln],321	(instregex "(S|U)(MAX|MIN)P?(v8i8|v4i16|v2i32)")>;322def KryoWrite_3cyc_XY_noRSV_184ln :323	SchedWriteRes<[KryoUnitXY]> {324	let Latency = 3; let NumMicroOps = 2;325}326def : InstRW<[KryoWrite_3cyc_XY_noRSV_184ln],327	(instregex "(S|U)(MAX|MIN)V(v4i16v|v8i8v|v4i32)")>;328def KryoWrite_4cyc_X_noRSV_185ln :329	SchedWriteRes<[KryoUnitX]> {330	let Latency = 4; let NumMicroOps = 2;331}332def : InstRW<[KryoWrite_4cyc_X_noRSV_185ln],333	(instregex "(S|U)(MAX|MIN)V(v16i8v|v8i16v)")>;334def KryoWrite_2cyc_XY_noRSV_67ln :335	SchedWriteRes<[KryoUnitXY]> {336	let Latency = 2; let NumMicroOps = 2;337}338def : InstRW<[KryoWrite_2cyc_XY_noRSV_67ln],339	(instrs ABSv1i64)>;340def KryoWrite_1cyc_XY_63ln :341	SchedWriteRes<[KryoUnitXY]> {342	let Latency = 1; let NumMicroOps = 1;343}344def : InstRW<[KryoWrite_1cyc_XY_63ln, ReadI, ReadI],345	(instregex "ADC.*")>;346def KryoWrite_1cyc_XY_63_1ln :347	SchedWriteRes<[KryoUnitXY]> {348	let Latency = 1; let NumMicroOps = 1;349}350def : InstRW<[KryoWrite_1cyc_XY_63_1ln],351	(instregex "ADR.*")>;352def KryoWrite_1cyc_XY_62ln :353	SchedWriteRes<[KryoUnitXY]> {354	let Latency = 1; let NumMicroOps = 1;355}356def : InstRW<[KryoWrite_1cyc_XY_62ln, ReadI],357	(instregex "ADDS?(W|X)ri")>;358def KryoWrite_2cyc_XY_XY_64ln :359	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {360	let Latency = 2; let NumMicroOps = 2;361}362def : InstRW<[KryoWrite_2cyc_XY_XY_64ln, ReadI, ReadI],363	(instregex "ADDS?(W|X)r(r|s|x)(64)?")>;364def KryoWrite_1cyc_XY_noRSV_65ln :365	SchedWriteRes<[KryoUnitXY]> {366	let Latency = 1; let NumMicroOps = 2;367}368def : InstRW<[KryoWrite_1cyc_XY_noRSV_65ln],369	(instrs ADDv1i64)>;370def KryoWrite_1cyc_XY_noRSV_144ln :371	SchedWriteRes<[KryoUnitXY]> {372	let Latency = 1; let NumMicroOps = 2;373}374def : InstRW<[KryoWrite_1cyc_XY_noRSV_144ln],375	(instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;376def KryoWrite_1cyc_XY_XY_146ln :377	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {378	let Latency = 1; let NumMicroOps = 2;379}380def : InstRW<[KryoWrite_1cyc_XY_XY_146ln],381	(instregex "(ADD|SUB)(v16i8|v8i16|v4i32|v2i64)")>;382def KryoWrite_4cyc_XY_X_noRSV_171ln :383	SchedWriteRes<[KryoUnitXY, KryoUnitX]> {384	let Latency = 4; let NumMicroOps = 3;385}386def : InstRW<[KryoWrite_4cyc_XY_X_noRSV_171ln],387	(instregex "(ADD|SUB)HNv.*")>;388def KryoWrite_1cyc_XY_noRSV_66ln :389	SchedWriteRes<[KryoUnitXY]> {390	let Latency = 1; let NumMicroOps = 2;391}392def : InstRW<[KryoWrite_1cyc_XY_noRSV_66ln],393	(instrs ADDPv2i64p)>;394def KryoWrite_2cyc_XY_XY_153ln :395	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {396	let Latency = 2; let NumMicroOps = 2;397}398def : InstRW<[KryoWrite_2cyc_XY_XY_153ln],399	(instregex "ADDP(v16i8|v8i16|v4i32|v2i64)")>;400def KryoWrite_3cyc_XY_XY_noRSV_170ln :401	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {402	let Latency = 3; let NumMicroOps = 3;403}404def : InstRW<[KryoWrite_3cyc_XY_XY_noRSV_170ln],405	(instrs ADDVv4i32v)>;406def KryoWrite_4cyc_XY_XY_noRSV_173ln :407	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {408	let Latency = 4; let NumMicroOps = 3;409}410def : InstRW<[KryoWrite_4cyc_XY_XY_noRSV_173ln],411	(instrs ADDVv8i16v)>;412def KryoWrite_5cyc_XY_X_noRSV_174ln :413	SchedWriteRes<[KryoUnitXY, KryoUnitX]> {414	let Latency = 5; let NumMicroOps = 3;415}416def : InstRW<[KryoWrite_5cyc_XY_X_noRSV_174ln],417	(instrs ADDVv16i8v)>;418def KryoWrite_3cyc_XY_XY_X_X_27ln :419	SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitX, KryoUnitX]> {420	let Latency = 3; let NumMicroOps = 4;421}422def : InstRW<[KryoWrite_3cyc_XY_XY_X_X_27ln],423	(instrs AESDrr, AESErr)>;424def KryoWrite_2cyc_X_X_22ln :425	SchedWriteRes<[KryoUnitX, KryoUnitX]> {426	let Latency = 2; let NumMicroOps = 2;427}428def : InstRW<[KryoWrite_2cyc_X_X_22ln],429	(instrs AESIMCrr, AESMCrr)>;430def KryoWrite_1cyc_XY_noRSV_76ln :431	SchedWriteRes<[KryoUnitXY]> {432	let Latency = 1; let NumMicroOps = 2;433}434def : InstRW<[KryoWrite_1cyc_XY_noRSV_76ln],435	(instregex "((AND|ORN|EOR|EON)S?(Wr[rsi]|v8i8|v4i16|v2i32)|(ORR|BIC)S?(Wr[rs]|v8i8|v4i16|v2i32))")>;436def KryoWrite_1cyc_XY_XY_79ln :437	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {438	let Latency = 1; let NumMicroOps = 2;439}440def : InstRW<[KryoWrite_1cyc_XY_XY_79ln],441	(instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>;442def KryoWrite_1cyc_X_72ln :443	SchedWriteRes<[KryoUnitX]> {444	let Latency = 1; let NumMicroOps = 1;445}446def : InstRW<[KryoWrite_1cyc_X_72ln],447	(instregex "(S|U)?BFM.*")>;448def KryoWrite_1cyc_XY_noRSV_77ln :449	SchedWriteRes<[KryoUnitXY]> {450	let Latency = 1; let NumMicroOps = 2;451}452def : InstRW<[KryoWrite_1cyc_XY_noRSV_77ln],453	(instregex "(BIC|ORR)S?Wri")>;454def KryoWrite_1cyc_XY_XY_78ln :455	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {456	let Latency = 1; let NumMicroOps = 2;457}458def : InstRW<[KryoWrite_1cyc_XY_XY_78ln],459	(instregex "(BIC|ORR)S?Xri")>;460def KryoWrite_1cyc_X_noRSV_74ln :461	SchedWriteRes<[KryoUnitX]> {462	let Latency = 1; let NumMicroOps = 2;463}464def : InstRW<[KryoWrite_1cyc_X_noRSV_74ln],465	(instrs BIFv8i8, BITv8i8, BSLv8i8, BSPv8i8)>;466def KryoWrite_1cyc_X_X_75ln :467	SchedWriteRes<[KryoUnitX, KryoUnitX]> {468	let Latency = 1; let NumMicroOps = 2;469}470def : InstRW<[KryoWrite_1cyc_X_X_75ln],471	(instrs BIFv16i8, BITv16i8, BSLv16i8, BSPv16i8)>;472def KryoWrite_0cyc_noRSV_11ln :473	SchedWriteRes<[]> {474	let Latency = 0; let NumMicroOps = 1;475}476def : InstRW<[KryoWrite_0cyc_noRSV_11ln],477	(instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;478def KryoWrite_0cyc_XY_16ln :479	SchedWriteRes<[KryoUnitXY]> {480	let Latency = 0; let NumMicroOps = 1;481}482def : InstRW<[KryoWrite_0cyc_XY_16ln, ReadI],483	(instregex "(CCMN|CCMP)(W|X)i")>;484def KryoWrite_0cyc_XY_16_1ln :485	SchedWriteRes<[KryoUnitXY]> {486	let Latency = 0; let NumMicroOps = 1;487}488def : InstRW<[KryoWrite_0cyc_XY_16_1ln, ReadI, ReadI],489	(instregex "(CCMN|CCMP)(W|X)r")>;490def KryoWrite_2cyc_XY_3ln :491	SchedWriteRes<[KryoUnitXY]> {492	let Latency = 2; let NumMicroOps = 1;493}494def : InstRW<[KryoWrite_2cyc_XY_3ln, ReadI],495	(instregex "(CLS|CLZ)(W|X)r")>;496def KryoWrite_2cyc_XY_noRSV_7ln :497	SchedWriteRes<[KryoUnitXY]> {498	let Latency = 2; let NumMicroOps = 2;499}500def : InstRW<[KryoWrite_2cyc_XY_noRSV_7ln],501	(instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;502def KryoWrite_2cyc_XY_XY_8ln :503	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {504	let Latency = 2; let NumMicroOps = 2;505}506def : InstRW<[KryoWrite_2cyc_XY_XY_8ln],507	(instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>;508def KryoWrite_2cyc_XY_noRSV_80ln :509	SchedWriteRes<[KryoUnitXY]> {510	let Latency = 2; let NumMicroOps = 2;511}512def : InstRW<[KryoWrite_2cyc_XY_noRSV_80ln],513	(instregex "CM(EQ|GE|HS|GT|HI|TST)(v8i8|v4i16|v2i32|v1i64)$")>;514def KryoWrite_2cyc_XY_XY_83ln :515	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {516	let Latency = 2; let NumMicroOps = 2;517}518def : InstRW<[KryoWrite_2cyc_XY_XY_83ln],519	(instregex "CM(EQ|GE|HS|GT|HI|TST)(v16i8|v8i16|v4i32|v2i64)$")>;520def KryoWrite_2cyc_XY_noRSV_81ln :521	SchedWriteRes<[KryoUnitXY]> {522	let Latency = 2; let NumMicroOps = 2;523}524def : InstRW<[KryoWrite_2cyc_XY_noRSV_81ln],525	(instregex "CM(EQ|LE|GE|GT|LT)(v8i8|v4i16|v2i32|v1i64)rz$")>;526def KryoWrite_2cyc_XY_XY_82ln :527	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {528	let Latency = 2; let NumMicroOps = 2;529}530def : InstRW<[KryoWrite_2cyc_XY_XY_82ln],531	(instregex "CM(EQ|LE|GE|GT|LT)(v16i8|v8i16|v4i32|v2i64)rz$")>;532def KryoWrite_3cyc_XY_4ln :533	SchedWriteRes<[KryoUnitXY]> {534	let Latency = 3; let NumMicroOps = 1;535}536def : InstRW<[KryoWrite_3cyc_XY_4ln, ReadI, ReadISReg],537	(instregex "CRC32.*")>;538def KryoWrite_1cyc_XY_20ln :539	SchedWriteRes<[KryoUnitXY]> {540	let Latency = 1; let NumMicroOps = 1;541}542def : InstRW<[KryoWrite_1cyc_XY_20ln, ReadI, ReadI],543	(instregex "CSEL(W|X)r")>;544def KryoWrite_1cyc_X_17ln :545	SchedWriteRes<[KryoUnitX]> {546	let Latency = 1; let NumMicroOps = 1;547}548def : InstRW<[KryoWrite_1cyc_X_17ln, ReadI, ReadI],549	(instregex "(CSINC|CSNEG)(W|X)r")>;550def KryoWrite_1cyc_XY_18ln :551	SchedWriteRes<[KryoUnitXY]> {552	let Latency = 1; let NumMicroOps = 1;553}554def : InstRW<[KryoWrite_1cyc_XY_18ln, ReadI, ReadI],555	(instregex "(CSINV)(W|X)r")>;556def KryoWrite_3cyc_LS_X_13ln :557	SchedWriteRes<[KryoUnitLS, KryoUnitX]> {558	let Latency = 3; let NumMicroOps = 2;559}560def : InstRW<[KryoWrite_3cyc_LS_X_13ln],561	(instrs DRPS)>;562def KryoWrite_0cyc_LS_10ln :563	SchedWriteRes<[KryoUnitLS]> {564	let Latency = 0; let NumMicroOps = 1;565}566def : InstRW<[KryoWrite_0cyc_LS_10ln],567	(instrs DSB, DMB, CLREX)>;568def KryoWrite_1cyc_X_noRSV_196ln :569	SchedWriteRes<[KryoUnitX]> {570	let Latency = 1; let NumMicroOps = 2;571}572def : InstRW<[KryoWrite_1cyc_X_noRSV_196ln],573	(instregex "DUP(v8i8|v4i16|v2i32)(gpr|lane)")>;574def KryoWrite_1cyc_X_X_197ln :575	SchedWriteRes<[KryoUnitX, KryoUnitX]> {576	let Latency = 1; let NumMicroOps = 2;577}578def : InstRW<[KryoWrite_1cyc_X_X_197ln],579	(instregex "DUP(v16i8|v8i16|v4i32|v2i64)(gpr|lane)")>;580def KryoWrite_3cyc_LS_LS_X_15ln :581	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX]> {582	let Latency = 3; let NumMicroOps = 3;583}584def : InstRW<[KryoWrite_3cyc_LS_LS_X_15ln],585	(instrs ERET)>;586def KryoWrite_1cyc_X_noRSV_207ln :587	SchedWriteRes<[KryoUnitX]> {588	let Latency = 1; let NumMicroOps = 2;589}590def : InstRW<[KryoWrite_1cyc_X_noRSV_207ln],591	(instrs EXTv8i8)>;592def KryoWrite_1cyc_X_X_212ln :593	SchedWriteRes<[KryoUnitX, KryoUnitX]> {594	let Latency = 1; let NumMicroOps = 2;595}596def : InstRW<[KryoWrite_1cyc_X_X_212ln],597	(instrs EXTv16i8)>;598def KryoWrite_2cyc_XY_X_136ln :599	SchedWriteRes<[KryoUnitXY, KryoUnitX]> {600	let Latency = 2; let NumMicroOps = 2;601}602def : InstRW<[KryoWrite_2cyc_XY_X_136ln],603	(instrs EXTRWrri, EXTRXrri)>;604def KryoWrite_2cyc_XY_noRSV_35ln :605	SchedWriteRes<[KryoUnitXY]> {606	let Latency = 2; let NumMicroOps = 2;607}608def : InstRW<[KryoWrite_2cyc_XY_noRSV_35ln],609	(instregex "F(MAX|MIN)(NM)?P?(D|S)rr")>;610def KryoWrite_2cyc_XY_XY_106ln :611	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {612	let Latency = 2; let NumMicroOps = 2;613}614def : InstRW<[KryoWrite_2cyc_XY_XY_106ln],615	(instregex "(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2i64p|v2f64|v4f32)")>;616def KryoWrite_2cyc_XY_noRSV_104ln :617	SchedWriteRes<[KryoUnitXY]> {618	let Latency = 2; let NumMicroOps = 2;619}620def : InstRW<[KryoWrite_2cyc_XY_noRSV_104ln],621	(instregex "(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2f32|v2i32p)")>;622def KryoWrite_3cyc_XY_noRSV_107ln :623	SchedWriteRes<[KryoUnitXY]> {624	let Latency = 3; let NumMicroOps = 2;625}626def : InstRW<[KryoWrite_3cyc_XY_noRSV_107ln],627	(instregex "F(MAX|MIN)(NM)?Vv4i32v")>;628def KryoWrite_3cyc_XY_noRSV_101ln :629	SchedWriteRes<[KryoUnitXY]> {630	let Latency = 3; let NumMicroOps = 2;631}632def : InstRW<[KryoWrite_3cyc_XY_noRSV_101ln],633	(instregex "FABD(32|64|v2f32)")>;634def KryoWrite_3cyc_XY_XY_103ln :635	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {636	let Latency = 3; let NumMicroOps = 2;637}638def : InstRW<[KryoWrite_3cyc_XY_XY_103ln],639	(instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>;640def KryoWrite_1cyc_XY_noRSV_48ln :641	SchedWriteRes<[KryoUnitXY]> {642	let Latency = 1; let NumMicroOps = 2;643}644def : InstRW<[KryoWrite_1cyc_XY_noRSV_48ln],645	(instregex "F(ABS|NEG)(D|S)r")>;646def KryoWrite_1cyc_XY_noRSV_124ln :647	SchedWriteRes<[KryoUnitXY]> {648	let Latency = 1; let NumMicroOps = 2;649}650def : InstRW<[KryoWrite_1cyc_XY_noRSV_124ln],651	(instregex "F(ABS|NEG)v2f32")>;652def KryoWrite_1cyc_XY_XY_125ln :653	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {654	let Latency = 1; let NumMicroOps = 2;655}656def : InstRW<[KryoWrite_1cyc_XY_XY_125ln],657	(instregex "F(ABS|NEG)(v2f64|v4f32)")>;658def KryoWrite_2cyc_XY_noRSV_33ln :659	SchedWriteRes<[KryoUnitXY]> {660	let Latency = 2; let NumMicroOps = 2;661}662def : InstRW<[KryoWrite_2cyc_XY_noRSV_33ln],663	(instregex "(FAC(GE|GT)|FCM(EQ|GE|GT))(32|64)")>;664def KryoWrite_3cyc_XY_noRSV_30ln :665	SchedWriteRes<[KryoUnitXY]> {666	let Latency = 3; let NumMicroOps = 2;667}668def : InstRW<[KryoWrite_3cyc_XY_noRSV_30ln],669	(instregex "(FADD|FSUB)(D|S)rr")>;670def KryoWrite_3cyc_XY_noRSV_100ln :671	SchedWriteRes<[KryoUnitXY]> {672	let Latency = 3; let NumMicroOps = 2;673}674def : InstRW<[KryoWrite_3cyc_XY_noRSV_100ln],675	(instregex "(FADD|FSUB|FADDP)v2f32")>;676def KryoWrite_3cyc_XY_noRSV_29ln :677	SchedWriteRes<[KryoUnitXY]> {678	let Latency = 3; let NumMicroOps = 2;679}680def : InstRW<[KryoWrite_3cyc_XY_noRSV_29ln],681	(instregex "FADDP(v2i32p|v2i64p)")>;682def KryoWrite_0cyc_XY_31ln :683	SchedWriteRes<[KryoUnitXY]> {684	let Latency = 0; let NumMicroOps = 1;685}686def : InstRW<[KryoWrite_0cyc_XY_31ln],687	(instregex "FCCMPE?(D|S)rr")>;688def KryoWrite_2cyc_XY_noRSV_34ln :689	SchedWriteRes<[KryoUnitXY]> {690	let Latency = 2; let NumMicroOps = 2;691}692def : InstRW<[KryoWrite_2cyc_XY_noRSV_34ln],693	(instregex "FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64)rz")>;694def KryoWrite_2cyc_XY_XY_36ln :695	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {696	let Latency = 2; let NumMicroOps = 2;697}698def : InstRW<[KryoWrite_2cyc_XY_XY_36ln],699	(instregex "FCM(EQ|LE|GE|GT|LT)(v2i64|v4i32)rz")>;700def KryoWrite_2cyc_XY_noRSV_105ln :701	SchedWriteRes<[KryoUnitXY]> {702	let Latency = 2; let NumMicroOps = 2;703}704def : InstRW<[KryoWrite_2cyc_XY_noRSV_105ln],705	(instregex "FCM(EQ|LE|GE|GT|LT)v2i32rz")>;706def KryoWrite_0cyc_XY_32ln :707	SchedWriteRes<[KryoUnitXY]> {708	let Latency = 0; let NumMicroOps = 1;709}710def : InstRW<[KryoWrite_0cyc_XY_32ln],711	(instregex "FCMPE?(D|S)r(r|i)")>;712def KryoWrite_1cyc_XY_noRSV_49ln :713	SchedWriteRes<[KryoUnitXY]> {714	let Latency = 1; let NumMicroOps = 2;715}716def : InstRW<[KryoWrite_1cyc_XY_noRSV_49ln],717	(instrs FCSELDrrr, FCSELSrrr)>;718def KryoWrite_4cyc_X_noRSV_41ln :719	SchedWriteRes<[KryoUnitX]> {720	let Latency = 4; let NumMicroOps = 2;721}722def : InstRW<[KryoWrite_4cyc_X_noRSV_41ln],723	(instrs FCVTDHr, FCVTDSr, FCVTHDr, FCVTHSr, FCVTSDr, FCVTSHr)>;724def KryoWrite_4cyc_X_38ln :725	SchedWriteRes<[KryoUnitX]> {726	let Latency = 4; let NumMicroOps = 1;727}728def : InstRW<[KryoWrite_4cyc_X_38ln],729	(instregex "FCVT(((A|N|M|P)(S|U)(S|U)|Z(S|U)_Int(S|U))(W|X)(D|S)ri?|Z(S|U)(d|s))$")>;730def KryoWrite_4cyc_X_noRSV_113ln :731	SchedWriteRes<[KryoUnitX]> {732	let Latency = 4; let NumMicroOps = 2;733}734def : InstRW<[KryoWrite_4cyc_X_noRSV_113ln],735	(instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;736def KryoWrite_4cyc_X_X_117ln :737	SchedWriteRes<[KryoUnitX, KryoUnitX]> {738	let Latency = 4; let NumMicroOps = 2;739}740def : InstRW<[KryoWrite_4cyc_X_X_117ln],741	(instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v4f32|v2f64)$")>;742def KryoWrite_5cyc_X_X_XY_noRSV_119ln :743	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitXY]> {744	let Latency = 5; let NumMicroOps = 4;745}746def : InstRW<[KryoWrite_5cyc_X_X_XY_noRSV_119ln],747	(instregex "FCVTX?N(v2f32|v4f32|v2i32|v4i16|v4i32|v8i16)$")>;748def KryoWrite_4cyc_X_X_116ln :749	SchedWriteRes<[KryoUnitX, KryoUnitX]> {750	let Latency = 4; let NumMicroOps = 2;751}752def : InstRW<[KryoWrite_4cyc_X_X_116ln],753	(instregex "FCVTL(v2i32|v4i16|v4i32|v8i16)$")>;754def KryoWrite_4cyc_X_noRSV_112ln :755	SchedWriteRes<[KryoUnitX]> {756	let Latency = 4; let NumMicroOps = 2;757}758def : InstRW<[KryoWrite_4cyc_X_noRSV_112ln],759	(instrs FCVTXNv1i64)>;760def KryoWrite_4cyc_X_37ln :761	SchedWriteRes<[KryoUnitX]> {762	let Latency = 4; let NumMicroOps = 1;763}764def : InstRW<[KryoWrite_4cyc_X_37ln],765	(instregex "FCVTZ(S|U)(S|U)(W|X)(D|S)ri?$")>;766def KryoWrite_4cyc_X_noRSV_111ln :767	SchedWriteRes<[KryoUnitX]> {768	let Latency = 4; let NumMicroOps = 2;769}770def : InstRW<[KryoWrite_4cyc_X_noRSV_111ln],771	(instregex "FCVTZ(S|U)(v2f32|v1i32|v1i64|v2i32(_shift)?)$")>;772def KryoWrite_4cyc_X_X_115ln :773	SchedWriteRes<[KryoUnitX, KryoUnitX]> {774	let Latency = 4; let NumMicroOps = 2;775}776def : InstRW<[KryoWrite_4cyc_X_X_115ln],777	(instregex "FCVTZ(S|U)(v2f64|v4f32|(v2i64|v4i32)(_shift)?)$")>;778def KryoWrite_10cyc_XA_Y_noRSV_43ln :779	SchedWriteRes<[KryoUnitXA, KryoUnitY]> {780	let Latency = 10; let NumMicroOps = 3;781}782def : InstRW<[KryoWrite_10cyc_XA_Y_noRSV_43ln],783	(instrs FDIVSrr)>;784def KryoWrite_14cyc_XA_Y_noRSV_43ln :785	SchedWriteRes<[KryoUnitXA, KryoUnitY]> {786	let Latency = 14; let NumMicroOps = 3;787}788def : InstRW<[KryoWrite_14cyc_XA_Y_noRSV_43ln],789	(instrs FDIVDrr)>;790def KryoWrite_10cyc_XA_Y_noRSV_121ln :791	SchedWriteRes<[KryoUnitXA, KryoUnitY]> {792	let Latency = 10; let NumMicroOps = 3;793}794def : InstRW<[KryoWrite_10cyc_XA_Y_noRSV_121ln],795	(instrs FDIVv2f32)>;796def KryoWrite_14cyc_XA_Y_XA_Y_123ln :797	SchedWriteRes<[KryoUnitXA, KryoUnitY, KryoUnitXA, KryoUnitY]> {798	let Latency = 14; let NumMicroOps = 4;799}800def : InstRW<[KryoWrite_14cyc_XA_Y_XA_Y_123ln],801	(instrs FDIVv2f64, FDIVv4f32)>;802def KryoWrite_5cyc_X_noRSV_55ln :803	SchedWriteRes<[KryoUnitX]> {804	let Latency = 5; let NumMicroOps = 2;805}806def : InstRW<[KryoWrite_5cyc_X_noRSV_55ln],807	(instregex "FN?M(ADD|SUB)Srrr")>;808def KryoWrite_6cyc_X_noRSV_57ln :809	SchedWriteRes<[KryoUnitX]> {810	let Latency = 6; let NumMicroOps = 2;811}812def : InstRW<[KryoWrite_6cyc_X_noRSV_57ln],813	(instregex "FN?M(ADD|SUB)Drrr")>;814def KryoWrite_5cyc_X_noRSV_51ln :815	SchedWriteRes<[KryoUnitX]> {816	let Latency = 5; let NumMicroOps = 2;817}818def : InstRW<[KryoWrite_5cyc_X_noRSV_51ln],819	(instrs FMLAv2f32, FMLSv2f32, FMLAv1i32_indexed, FMLSv1i32_indexed)>;820def KryoWrite_5cyc_X_X_56ln :821	SchedWriteRes<[KryoUnitX, KryoUnitX]> {822	let Latency = 5; let NumMicroOps = 2;823}824def : InstRW<[KryoWrite_5cyc_X_X_56ln],825	(instrs FMLAv4f32, FMLSv4f32)>;826def KryoWrite_6cyc_X_X_61ln :827	SchedWriteRes<[KryoUnitX, KryoUnitX]> {828	let Latency = 6; let NumMicroOps = 2;829}830def : InstRW<[KryoWrite_6cyc_X_X_61ln],831	(instrs FMLAv2f64, FMLSv2f64)>;832def KryoWrite_5cyc_X_noRSV_128ln :833	SchedWriteRes<[KryoUnitX]> {834	let Latency = 5; let NumMicroOps = 2;835}836def : InstRW<[KryoWrite_5cyc_X_noRSV_128ln],837	(instrs FMLAv2i32_indexed, FMLSv2i32_indexed)>;838def KryoWrite_5cyc_X_X_131ln :839	SchedWriteRes<[KryoUnitX, KryoUnitX]> {840	let Latency = 5; let NumMicroOps = 2;841}842def : InstRW<[KryoWrite_5cyc_X_X_131ln],843	(instrs FMLAv4i32_indexed, FMLSv4i32_indexed)>;844def KryoWrite_6cyc_X_X_134ln :845	SchedWriteRes<[KryoUnitX, KryoUnitX]> {846	let Latency = 6; let NumMicroOps = 2;847}848def : InstRW<[KryoWrite_6cyc_X_X_134ln],849	(instrs FMLAv2i64_indexed, FMLSv2i64_indexed)>;850def KryoWrite_6cyc_X_noRSV_60ln :851	SchedWriteRes<[KryoUnitX]> {852	let Latency = 6; let NumMicroOps = 2;853}854def : InstRW<[KryoWrite_6cyc_X_noRSV_60ln],855	(instrs FMLAv1i64_indexed, FMLSv1i64_indexed, FMULv1i64_indexed, FMULXv1i64_indexed)>;856def KryoWrite_1cyc_XY_45ln :857	SchedWriteRes<[KryoUnitXY]> {858	let Latency = 1; let NumMicroOps = 1;859}860def : InstRW<[KryoWrite_1cyc_XY_45ln],861	(instregex "FMOV(XDHigh|DXHigh|DX)r")>;862def KryoWrite_1cyc_XY_noRSV_47ln :863	SchedWriteRes<[KryoUnitXY]> {864	let Latency = 1; let NumMicroOps = 2;865}866def : InstRW<[KryoWrite_1cyc_XY_noRSV_47ln],867	(instregex "FMOV(Di|Dr|Si|Sr|SWr|WSr|XDr|v.*_ns)")>;868def KryoWrite_5cyc_X_noRSV_53ln :869	SchedWriteRes<[KryoUnitX]> {870	let Latency = 5; let NumMicroOps = 2;871}872def : InstRW<[KryoWrite_5cyc_X_noRSV_53ln],873	(instrs FMULv1i32_indexed, FMULXv1i32_indexed)>;874def KryoWrite_5cyc_X_noRSV_127ln :875	SchedWriteRes<[KryoUnitX]> {876	let Latency = 5; let NumMicroOps = 2;877}878def : InstRW<[KryoWrite_5cyc_X_noRSV_127ln],879	(instrs FMULv2f32, FMULXv2f32, FMULv2i32_indexed, FMULXv2i32_indexed)>;880def KryoWrite_5cyc_X_X_130ln :881	SchedWriteRes<[KryoUnitX, KryoUnitX]> {882	let Latency = 5; let NumMicroOps = 2;883}884def : InstRW<[KryoWrite_5cyc_X_X_130ln],885	(instrs FMULv4f32, FMULXv4f32, FMULv4i32_indexed, FMULXv4i32_indexed)>;886def KryoWrite_6cyc_X_X_133ln :887	SchedWriteRes<[KryoUnitX, KryoUnitX]> {888	let Latency = 6; let NumMicroOps = 2;889}890def : InstRW<[KryoWrite_6cyc_X_X_133ln],891	(instrs FMULv2f64, FMULXv2f64, FMULv2i64_indexed, FMULXv2i64_indexed)>;892def KryoWrite_5cyc_X_noRSV_54ln :893	SchedWriteRes<[KryoUnitX]> {894	let Latency = 5; let NumMicroOps = 2;895}896def : InstRW<[KryoWrite_5cyc_X_noRSV_54ln],897	(instrs FMULSrr, FNMULSrr, FMULX32)>;898def KryoWrite_6cyc_X_noRSV_59ln :899	SchedWriteRes<[KryoUnitX]> {900	let Latency = 6; let NumMicroOps = 2;901}902def : InstRW<[KryoWrite_6cyc_X_noRSV_59ln],903	(instrs FMULDrr, FNMULDrr, FMULX64)>;904def KryoWrite_3cyc_XY_noRSV_28ln :905	SchedWriteRes<[KryoUnitXY]> {906	let Latency = 3; let NumMicroOps = 2;907}908def : InstRW<[KryoWrite_3cyc_XY_noRSV_28ln],909	(instrs FRECPEv1i32, FRECPEv1i64, FRSQRTEv1i32, FRSQRTEv1i64 )>;910def KryoWrite_3cyc_XY_noRSV_99ln :911	SchedWriteRes<[KryoUnitXY]> {912	let Latency = 3; let NumMicroOps = 2;913}914def : InstRW<[KryoWrite_3cyc_XY_noRSV_99ln],915	(instrs FRECPEv2f32, FRSQRTEv2f32)>;916def KryoWrite_3cyc_XY_XY_102ln :917	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {918	let Latency = 3; let NumMicroOps = 2;919}920def : InstRW<[KryoWrite_3cyc_XY_XY_102ln],921	(instrs FRECPEv2f64, FRECPEv4f32, FRSQRTEv2f64, FRSQRTEv4f32)>;922def KryoWrite_5cyc_X_noRSV_52ln :923	SchedWriteRes<[KryoUnitX]> {924	let Latency = 5; let NumMicroOps = 2;925}926def : InstRW<[KryoWrite_5cyc_X_noRSV_52ln],927	(instrs FRECPS32, FRSQRTS32)>;928def KryoWrite_6cyc_X_noRSV_58ln :929	SchedWriteRes<[KryoUnitX]> {930	let Latency = 6; let NumMicroOps = 2;931}932def : InstRW<[KryoWrite_6cyc_X_noRSV_58ln],933	(instrs FRECPS64, FRSQRTS64)>;934def KryoWrite_5cyc_X_noRSV_126ln :935	SchedWriteRes<[KryoUnitX]> {936	let Latency = 5; let NumMicroOps = 2;937}938def : InstRW<[KryoWrite_5cyc_X_noRSV_126ln],939	(instrs FRECPSv2f32, FRSQRTSv2f32)>;940def KryoWrite_5cyc_X_X_129ln :941	SchedWriteRes<[KryoUnitX, KryoUnitX]> {942	let Latency = 5; let NumMicroOps = 2;943}944def : InstRW<[KryoWrite_5cyc_X_X_129ln],945	(instrs FRECPSv4f32, FRSQRTSv4f32)>;946def KryoWrite_6cyc_X_X_132ln :947	SchedWriteRes<[KryoUnitX, KryoUnitX]> {948	let Latency = 6; let NumMicroOps = 2;949}950def : InstRW<[KryoWrite_6cyc_X_X_132ln],951	(instrs FRECPSv2f64, FRSQRTSv2f64)>;952def KryoWrite_3cyc_XY_noRSV_50ln :953	SchedWriteRes<[KryoUnitXY]> {954	let Latency = 3; let NumMicroOps = 2;955}956def : InstRW<[KryoWrite_3cyc_XY_noRSV_50ln],957	(instrs FRECPXv1i32, FRECPXv1i64)>;958def KryoWrite_2cyc_XY_noRSV_39ln :959	SchedWriteRes<[KryoUnitXY]> {960	let Latency = 2; let NumMicroOps = 2;961}962def : InstRW<[KryoWrite_2cyc_XY_noRSV_39ln],963	(instregex "FRINT(A|I|M|N|P|X|Z)(S|D)r")>;964def KryoWrite_2cyc_XY_noRSV_108ln :965	SchedWriteRes<[KryoUnitXY]> {966	let Latency = 2; let NumMicroOps = 2;967}968def : InstRW<[KryoWrite_2cyc_XY_noRSV_108ln],969	(instregex "FRINT(A|I|M|N|P|X|Z)v2f32")>;970def KryoWrite_2cyc_XY_XY_109ln :971	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {972	let Latency = 2; let NumMicroOps = 2;973}974def : InstRW<[KryoWrite_2cyc_XY_XY_109ln],975	(instregex "FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)")>;976def KryoWrite_12cyc_XA_Y_noRSV_42ln :977	SchedWriteRes<[KryoUnitXA, KryoUnitY]> {978	let Latency = 12; let NumMicroOps = 3;979}980def : InstRW<[KryoWrite_12cyc_XA_Y_noRSV_42ln],981	(instrs FSQRTSr)>;982def KryoWrite_21cyc_XA_Y_noRSV_42ln :983	SchedWriteRes<[KryoUnitXA, KryoUnitY]> {984	let Latency = 21; let NumMicroOps = 3;985}986def : InstRW<[KryoWrite_21cyc_XA_Y_noRSV_42ln],987	(instrs FSQRTDr)>;988def KryoWrite_12cyc_XA_Y_noRSV_120ln :989	SchedWriteRes<[KryoUnitXA, KryoUnitY]> {990	let Latency = 12; let NumMicroOps = 3;991}992def : InstRW<[KryoWrite_12cyc_XA_Y_noRSV_120ln],993	(instrs FSQRTv2f32)>;994def KryoWrite_21cyc_XA_Y_XA_Y_122ln :995	SchedWriteRes<[KryoUnitXA, KryoUnitY, KryoUnitXA, KryoUnitY]> {996	let Latency = 21; let NumMicroOps = 4;997}998def : InstRW<[KryoWrite_21cyc_XA_Y_XA_Y_122ln],999	(instrs FSQRTv4f32)>;1000def KryoWrite_36cyc_XA_Y_XA_Y_122ln :1001	SchedWriteRes<[KryoUnitXA, KryoUnitY, KryoUnitXA, KryoUnitY]> {1002	let Latency = 36; let NumMicroOps = 4;1003}1004def : InstRW<[KryoWrite_36cyc_XA_Y_XA_Y_122ln],1005	(instrs FSQRTv2f64)>;1006def KryoWrite_1cyc_X_201ln :1007	SchedWriteRes<[KryoUnitX]> {1008	let Latency = 1; let NumMicroOps = 1;1009}1010def : InstRW<[KryoWrite_1cyc_X_201ln],1011	(instregex "INSv.*")>;1012def KryoWrite_3cyc_LS_255ln :1013	SchedWriteRes<[KryoUnitLS]> {1014	let Latency = 3; let NumMicroOps = 1;1015}1016def : InstRW<[KryoWrite_3cyc_LS_255ln],1017	(instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)$")>;1018def KryoWrite_4cyc_LS_X_270ln :1019	SchedWriteRes<[KryoUnitLS, KryoUnitX]> {1020	let Latency = 4; let NumMicroOps = 2;1021}1022def : InstRW<[KryoWrite_4cyc_LS_X_270ln],1023	(instregex "LD1(i8|i16|i32)$")>;1024def KryoWrite_3cyc_LS_noRSV_285ln :1025	SchedWriteRes<[KryoUnitLS]> {1026	let Latency = 3; let NumMicroOps = 2;1027}1028def : InstRW<[KryoWrite_3cyc_LS_noRSV_285ln],1029	(instregex "LD1One(v8b|v4h|v2s|v1d)$")>;1030def KryoWrite_3cyc_LS_XY_289ln :1031	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1032	let Latency = 3; let NumMicroOps = 2;1033}1034def : InstRW<[KryoWrite_3cyc_LS_XY_289ln, WriteAdr],1035	(instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)_POST$")>;1036def KryoWrite_4cyc_LS_XY_X_298ln :1037	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX]> {1038	let Latency = 4; let NumMicroOps = 3;1039}1040def : InstRW<[KryoWrite_4cyc_LS_XY_X_298ln, WriteAdr],1041	(instregex "LD1(i8|i16|i32)_POST$")>;1042def KryoWrite_3cyc_LS_LS_LS_308ln :1043	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS]> {1044	let Latency = 3; let NumMicroOps = 3;1045}1046def : InstRW<[KryoWrite_3cyc_LS_LS_LS_308ln],1047	(instregex "LD1Three(v16b|v8h|v4s|v2d)$")>;1048def KryoWrite_3cyc_LS_XY_noRSV_317ln :1049	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1050	let Latency = 3; let NumMicroOps = 3;1051}1052def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_317ln, WriteAdr],1053	(instregex "LD1One(v8b|v4h|v2s|v1d)_POST$")>;1054def KryoWrite_3cyc_LS_LS_LS_LS_328ln :1055	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {1056	let Latency = 3; let NumMicroOps = 4;1057}1058def : InstRW<[KryoWrite_3cyc_LS_LS_LS_LS_328ln, WriteAdr],1059	(instregex "LD1Four(v16b|v8h|v4s|v2d)_POST$")>;1060def KryoWrite_3cyc_LS_XY_LS_LS_332ln :1061	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS]> {1062	let Latency = 3; let NumMicroOps = 4;1063}1064def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_332ln, WriteAdr],1065	(instregex "LD1Three(v16b|v8h|v4s|v2d)_POST$")>;1066def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_348ln :1067	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1068	let Latency = 3; let NumMicroOps = 5;1069}1070def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_348ln],1071	(instregex "LD1Three(v8b|v4h|v2s|v1d)$")>;1072def KryoWrite_3cyc_LS_XY_LS_LS_LS_351ln :1073	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {1074	let Latency = 3; let NumMicroOps = 5;1075}1076def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_LS_351ln],1077	(instregex "LD1Four(v16b|v8h|v4s|v2d)$")>;1078def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_358ln :1079	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1080	let Latency = 3; let NumMicroOps = 6;1081}1082def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_358ln],1083	(instregex "LD1Four(v8b|v4h|v2s|v1d)$")>;1084def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_360ln :1085	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {1086	let Latency = 3; let NumMicroOps = 6;1087}1088def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_360ln, WriteAdr],1089	(instregex "LD1Three(v8b|v4h|v2s|v1d)_POST$")>;1090def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_368ln :1091	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {1092	let Latency = 3; let NumMicroOps = 7;1093}1094def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_368ln, WriteAdr],1095	(instregex "LD1Four(v8b|v4h|v2s|v1d)_POST$")>;1096def KryoWrite_3cyc_LS_LS_281ln :1097	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1098	let Latency = 3; let NumMicroOps = 2;1099}1100def : InstRW<[KryoWrite_3cyc_LS_LS_281ln],1101	(instregex "LD(1|2)Two(v16b|v8h|v4s|v2d)$")>;1102def KryoWrite_3cyc_LS_noRSV_noRSV_311ln :1103	SchedWriteRes<[KryoUnitLS]> {1104	let Latency = 3; let NumMicroOps = 3;1105}1106def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_311ln],1107	(instregex "LD(1|2)Two(v8b|v4h|v2s|v1d)$")>;1108def KryoWrite_3cyc_LS_XY_LS_313ln :1109	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {1110	let Latency = 3; let NumMicroOps = 3;1111}1112def : InstRW<[KryoWrite_3cyc_LS_XY_LS_313ln, WriteAdr],1113	(instregex "LD(1|2)Two(v16b|v8h|v4s|v2d)_POST$")>;1114def KryoWrite_3cyc_LS_XY_noRSV_noRSV_334ln :1115	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1116	let Latency = 3; let NumMicroOps = 4;1117}1118def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_noRSV_334ln, WriteAdr],1119	(instregex "LD(1|2)Two(v8b|v4h|v2s|v1d)_POST$")>;1120def KryoWrite_3cyc_LS_256ln :1121	SchedWriteRes<[KryoUnitLS]> {1122	let Latency = 3; let NumMicroOps = 1;1123}1124def : InstRW<[KryoWrite_3cyc_LS_256ln],1125	(instregex "LD1R(v16b|v8h|v4s|v2d)$")>;1126def KryoWrite_3cyc_LS_noRSV_286ln :1127	SchedWriteRes<[KryoUnitLS]> {1128	let Latency = 3; let NumMicroOps = 2;1129}1130def : InstRW<[KryoWrite_3cyc_LS_noRSV_286ln],1131	(instregex "LD1R(v8b|v4h|v2s|v1d)$")>;1132def KryoWrite_3cyc_LS_XY_290ln :1133	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1134	let Latency = 3; let NumMicroOps = 2;1135}1136def : InstRW<[KryoWrite_3cyc_LS_XY_290ln, WriteAdr],1137	(instregex "LD1R(v16b|v8h|v4s|v2d)_POST$")>;1138def KryoWrite_3cyc_LS_XY_noRSV_318ln :1139	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1140	let Latency = 3; let NumMicroOps = 3;1141}1142def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_318ln, WriteAdr],1143	(instregex "LD1R(v8b|v4h|v2s|v1d)_POST$")>;1144def KryoWrite_3cyc_LS_257ln :1145	SchedWriteRes<[KryoUnitLS]> {1146	let Latency = 3; let NumMicroOps = 1;1147}1148def : InstRW<[KryoWrite_3cyc_LS_257ln],1149	(instregex "LD2i64$")>;1150def KryoWrite_3cyc_LS_XY_291ln :1151	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1152	let Latency = 3; let NumMicroOps = 2;1153}1154def : InstRW<[KryoWrite_3cyc_LS_XY_291ln, WriteAdr],1155	(instregex "LD2i64_POST$")>;1156def KryoWrite_4cyc_LS_X_X_296ln :1157	SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitX]> {1158	let Latency = 4; let NumMicroOps = 3;1159}1160def : InstRW<[KryoWrite_4cyc_LS_X_X_296ln],1161	(instregex "LD2(i8|i16|i32)$")>;1162def KryoWrite_4cyc_LS_XY_X_X_321ln :1163	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX, KryoUnitX]> {1164	let Latency = 4; let NumMicroOps = 4;1165}1166def : InstRW<[KryoWrite_4cyc_LS_XY_X_X_321ln, WriteAdr],1167	(instregex "LD2(i8|i16|i32)_POST$")>;1168def KryoWrite_3cyc_LS_LS_282ln :1169	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1170	let Latency = 3; let NumMicroOps = 2;1171}1172def : InstRW<[KryoWrite_3cyc_LS_LS_282ln],1173	(instregex "LD2R(v16b|v8h|v4s|v2d)$")>;1174def KryoWrite_3cyc_LS_noRSV_noRSV_312ln :1175	SchedWriteRes<[KryoUnitLS]> {1176	let Latency = 3; let NumMicroOps = 3;1177}1178def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_312ln],1179	(instregex "LD2R(v8b|v4h|v2s|v1d)$")>;1180def KryoWrite_3cyc_LS_XY_LS_314ln :1181	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {1182	let Latency = 3; let NumMicroOps = 3;1183}1184def : InstRW<[KryoWrite_3cyc_LS_XY_LS_314ln, WriteAdr],1185	(instregex "LD2R(v16b|v8h|v4s|v2d)_POST$")>;1186def KryoWrite_3cyc_LS_XY_noRSV_noRSV_335ln :1187	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1188	let Latency = 3; let NumMicroOps = 4;1189}1190def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_noRSV_335ln, WriteAdr],1191	(instregex "LD2R(v8b|v4h|v2s|v1d)_POST$")>;1192def KryoWrite_3cyc_LS_LS_283ln :1193	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1194	let Latency = 3; let NumMicroOps = 2;1195}1196def : InstRW<[KryoWrite_3cyc_LS_LS_283ln],1197	(instregex "LD3i64$")>;1198def KryoWrite_3cyc_LS_LS_LS_309ln :1199	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS]> {1200	let Latency = 3; let NumMicroOps = 3;1201}1202def : InstRW<[KryoWrite_3cyc_LS_LS_LS_309ln],1203	(instregex "LD3Threev2d$")>;1204def KryoWrite_3cyc_LS_XY_LS_315ln :1205	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {1206	let Latency = 3; let NumMicroOps = 3;1207}1208def : InstRW<[KryoWrite_3cyc_LS_XY_LS_315ln, WriteAdr],1209	(instregex "LD3i64_POST$")>;1210def KryoWrite_4cyc_LS_X_X_X_320ln :1211	SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> {1212	let Latency = 4; let NumMicroOps = 4;1213}1214def : InstRW<[KryoWrite_4cyc_LS_X_X_X_320ln],1215	(instregex "LD3(i8|i16|i32)$")>;1216def KryoWrite_3cyc_LS_XY_LS_LS_331ln :1217	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS]> {1218	let Latency = 3; let NumMicroOps = 4;1219}1220def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_331ln, WriteAdr],1221	(instregex "LD3Threev2d_POST$")>;1222def KryoWrite_4cyc_LS_XY_X_X_X_338ln :1223	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX]> {1224	let Latency = 4; let NumMicroOps = 5;1225}1226def : InstRW<[KryoWrite_4cyc_LS_XY_X_X_X_338ln, WriteAdr],1227	(instregex "LD3(i8|i16|i32)_POST$")>;1228def KryoWrite_4cyc_LS_LS_X_X_X_noRSV_noRSV_noRSV_373ln :1229	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> {1230	let Latency = 4; let NumMicroOps = 8;1231}1232def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_noRSV_noRSV_noRSV_373ln],1233	(instregex "LD3Three(v8b|v4h|v2s)$")>;1234def KryoWrite_4cyc_LS_XY_LS_X_X_X_noRSV_noRSV_noRSV_380ln :1235	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX, KryoUnitX,1236                   KryoUnitX]> {1237	let Latency = 4; let NumMicroOps = 9;1238}1239def : InstRW<[KryoWrite_4cyc_LS_XY_LS_X_X_X_noRSV_noRSV_noRSV_380ln, WriteAdr],1240	(instregex "LD3Three(v8b|v4h|v2s)_POST$")>;1241def KryoWrite_4cyc_LS_LS_X_X_X_LS_LS_X_X_X_381ln :1242	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX,1243                   KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> {1244	let Latency = 4; let NumMicroOps = 10;1245}1246def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_LS_LS_X_X_X_381ln],1247	(instregex "LD3Three(v16b|v8h|v4s)$")>;1248def KryoWrite_4cyc_LS_LS_X_X_X_LS_XY_LS_X_X_X_383ln :1249	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX,1250                   KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX, KryoUnitX,1251                   KryoUnitX]> {1252	let Latency = 4; let NumMicroOps = 11;1253}1254def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_LS_XY_LS_X_X_X_383ln, WriteAdr],1255	(instregex "LD3Three(v16b|v8h|v4s)_POST$")>;1256def KryoWrite_3cyc_LS_LS_LS_310ln :1257	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS]> {1258	let Latency = 3; let NumMicroOps = 3;1259}1260def : InstRW<[KryoWrite_3cyc_LS_LS_LS_310ln],1261	(instregex "LD3R(v16b|v8h|v4s|v2d)$")>;1262def KryoWrite_3cyc_LS_XY_LS_LS_333ln :1263	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS]> {1264	let Latency = 3; let NumMicroOps = 4;1265}1266def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_333ln, WriteAdr],1267	(instregex "LD3R(v16b|v8h|v4s|v2d)_POST$")>;1268def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_349ln :1269	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1270	let Latency = 3; let NumMicroOps = 5;1271}1272def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_349ln],1273	(instregex "LD3R(v8b|v4h|v2s|v1d)$")>;1274def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_361ln :1275	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {1276	let Latency = 3; let NumMicroOps = 6;1277}1278def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_361ln, WriteAdr],1279	(instregex "LD3R(v8b|v4h|v2s|v1d)_POST$")>;1280def KryoWrite_3cyc_LS_LS_284ln :1281	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1282	let Latency = 3; let NumMicroOps = 2;1283}1284def : InstRW<[KryoWrite_3cyc_LS_LS_284ln],1285	(instregex "LD4i64$")>;1286def KryoWrite_3cyc_LS_XY_LS_316ln :1287	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {1288	let Latency = 3; let NumMicroOps = 3;1289}1290def : InstRW<[KryoWrite_3cyc_LS_XY_LS_316ln, WriteAdr],1291	(instregex "LD4i64_POST$")>;1292def KryoWrite_3cyc_LS_LS_LS_LS_329ln :1293	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {1294	let Latency = 3; let NumMicroOps = 4;1295}1296def : InstRW<[KryoWrite_3cyc_LS_LS_LS_LS_329ln],1297	(instregex "LD4Four(v2d)$")>;1298def KryoWrite_4cyc_LS_X_X_X_X_337ln :1299	SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> {1300	let Latency = 4; let NumMicroOps = 5;1301}1302def : InstRW<[KryoWrite_4cyc_LS_X_X_X_X_337ln],1303	(instregex "LD4(i8|i16|i32)$")>;1304def KryoWrite_3cyc_LS_XY_LS_LS_LS_350ln :1305	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {1306	let Latency = 3; let NumMicroOps = 5;1307}1308def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_LS_350ln, WriteAdr],1309	(instregex "LD4Four(v2d)_POST$")>;1310def KryoWrite_4cyc_LS_XY_X_X_X_X_355ln :1311	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX,1312                   KryoUnitX]> {1313	let Latency = 4; let NumMicroOps = 6;1314}1315def : InstRW<[KryoWrite_4cyc_LS_XY_X_X_X_X_355ln, WriteAdr],1316	(instregex "LD4(i8|i16|i32)_POST$")>;1317def KryoWrite_4cyc_LS_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_382ln :1318	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX,1319                   KryoUnitX]> {1320	let Latency = 4; let NumMicroOps = 10;1321}1322def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_382ln],1323	(instregex "LD4Four(v8b|v4h|v2s)$")>;1324def KryoWrite_4cyc_LS_XY_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_384ln :1325	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX, KryoUnitX,1326                   KryoUnitX, KryoUnitX]> {1327	let Latency = 4; let NumMicroOps = 11;1328}1329def : InstRW<[KryoWrite_4cyc_LS_XY_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_384ln, WriteAdr],1330	(instregex "LD4Four(v8b|v4h|v2s)_POST$")>;1331def KryoWrite_4cyc_LS_LS_X_X_X_X_LS_LS_X_X_X_X_386ln :1332	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX,1333                   KryoUnitX, KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX,1334                   KryoUnitX, KryoUnitX]> {1335	let Latency = 4; let NumMicroOps = 12;1336}1337def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_X_LS_LS_X_X_X_X_386ln],1338	(instregex "LD4Four(v16b|v8h|v4s)$")>;1339def KryoWrite_4cyc_LS_LS_X_X_X_X_LS_XY_LS_X_X_X_X_389ln :1340	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX,1341                   KryoUnitX, KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX,1342                   KryoUnitX, KryoUnitX, KryoUnitX]> {1343	let Latency = 4; let NumMicroOps = 13;1344}1345def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_X_LS_XY_LS_X_X_X_X_389ln, WriteAdr],1346	(instregex "LD4Four(v16b|v8h|v4s)_POST$")>;1347def KryoWrite_3cyc_LS_LS_LS_LS_330ln :1348	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {1349	let Latency = 3; let NumMicroOps = 4;1350}1351def : InstRW<[KryoWrite_3cyc_LS_LS_LS_LS_330ln],1352	(instregex "LD4R(v16b|v8h|v4s|v2d)$")>;1353def KryoWrite_3cyc_LS_XY_LS_LS_LS_352ln :1354	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS, KryoUnitLS]> {1355	let Latency = 3; let NumMicroOps = 5;1356}1357def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_LS_352ln, WriteAdr],1358	(instregex "LD4R(v16b|v8h|v4s|v2d)_POST$")>;1359def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_359ln :1360	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1361	let Latency = 3; let NumMicroOps = 6;1362}1363def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_359ln],1364	(instregex "LD4R(v8b|v4h|v2s|v1d)$")>;1365def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_369ln :1366	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {1367	let Latency = 3; let NumMicroOps = 7;1368}1369def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_369ln, WriteAdr],1370	(instregex "LD4R(v8b|v4h|v2s|v1d)_POST$")>;1371def KryoWrite_3cyc_LS_LS_400ln :1372	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1373	let Latency = 3; let NumMicroOps = 2;1374}1375def : InstRW<[KryoWrite_3cyc_LS_LS_400ln],1376	(instregex "LDAX?R(B|H|W|X)")>;1377def : InstRW<[KryoWrite_3cyc_LS_LS_400ln, WriteLDHi],1378	(instregex "LDAXP(W|X)")>;1379def KryoWrite_3cyc_LS_LS_401ln :1380	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1381	let Latency = 3; let NumMicroOps = 2;1382}1383def : InstRW<[KryoWrite_3cyc_LS_LS_401ln, WriteLDHi],1384	(instrs LDNPQi)>;1385def KryoWrite_3cyc_LS_noRSV_noRSV_408ln :1386	SchedWriteRes<[KryoUnitLS]> {1387	let Latency = 3; let NumMicroOps = 3;1388}1389def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_408ln, WriteLDHi],1390	(instrs LDNPDi, LDNPSi)>;1391def KryoWrite_3cyc_LS_394ln :1392	SchedWriteRes<[KryoUnitLS]> {1393	let Latency = 3; let NumMicroOps = 1;1394}1395def : InstRW<[KryoWrite_3cyc_LS_394ln, WriteLDHi],1396	(instrs LDNPWi, LDNPXi)>;1397def KryoWrite_3cyc_LS_LS_402ln :1398	SchedWriteRes<[KryoUnitLS, KryoUnitLS]> {1399	let Latency = 3; let NumMicroOps = 2;1400}1401def : InstRW<[KryoWrite_3cyc_LS_LS_402ln, WriteLDHi],1402	(instrs LDPQi)>;1403def KryoWrite_3cyc_LS_noRSV_noRSV_409ln :1404	SchedWriteRes<[KryoUnitLS]> {1405	let Latency = 3; let NumMicroOps = 3;1406}1407def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_409ln, WriteLDHi],1408	(instrs LDPDi, LDPSi)>;1409def KryoWrite_3cyc_LS_XY_LS_410ln :1410	SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> {1411	let Latency = 3; let NumMicroOps = 3;1412}1413def : InstRW<[KryoWrite_3cyc_LS_XY_LS_410ln, WriteLDHi, WriteAdr],1414	(instregex "LDPQ(post|pre)")>;1415def KryoWrite_3cyc_LS_XY_noRSV_noRSV_411ln :1416	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1417	let Latency = 3; let NumMicroOps = 4;1418}1419def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_noRSV_411ln, WriteLDHi, WriteAdr],1420	(instregex "LDP(D|S)(post|pre)")>;1421def KryoWrite_3cyc_LS_393ln :1422	SchedWriteRes<[KryoUnitLS]> {1423	let Latency = 3; let NumMicroOps = 1;1424}1425def : InstRW<[KryoWrite_3cyc_LS_393ln, WriteLDHi],1426	(instrs LDPWi, LDPXi)>;1427def KryoWrite_3cyc_LS_XY_403ln :1428	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1429	let Latency = 3; let NumMicroOps = 2;1430}1431def : InstRW<[KryoWrite_3cyc_LS_XY_403ln, WriteLDHi, WriteAdr],1432	(instregex "LDP(W|X)(post|pre)")>;1433def KryoWrite_4cyc_LS_395ln :1434	SchedWriteRes<[KryoUnitLS]> {1435	let Latency = 4; let NumMicroOps = 1;1436}1437def : InstRW<[KryoWrite_4cyc_LS_395ln, WriteLDHi],1438	(instrs LDPSWi)>;1439def KryoWrite_4cyc_LS_XY_405ln :1440	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1441	let Latency = 4; let NumMicroOps = 2;1442}1443def : InstRW<[KryoWrite_4cyc_LS_XY_405ln, WriteLDHi, WriteAdr],1444	(instrs LDPSWpost, LDPSWpre)>;1445def KryoWrite_3cyc_LS_264ln :1446	SchedWriteRes<[KryoUnitLS]> {1447	let Latency = 3; let NumMicroOps = 1;1448}1449def : InstRW<[KryoWrite_3cyc_LS_264ln],1450	(instrs LDRQui, LDRQl)>;1451def KryoWrite_4cyc_X_LS_271ln :1452	SchedWriteRes<[KryoUnitX, KryoUnitLS]> {1453	let Latency = 4; let NumMicroOps = 2;1454}1455def : InstRW<[KryoWrite_4cyc_X_LS_271ln],1456	(instrs LDRQroW, LDRQroX)>;1457def KryoWrite_3cyc_LS_noRSV_287ln :1458	SchedWriteRes<[KryoUnitLS]> {1459	let Latency = 3; let NumMicroOps = 2;1460}1461def : InstRW<[KryoWrite_3cyc_LS_noRSV_287ln],1462	(instregex "LDR((D|S)l|(D|S|H|B)ui)")>;1463def KryoWrite_3cyc_LS_XY_293ln :1464	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1465	let Latency = 3; let NumMicroOps = 2;1466}1467def : InstRW<[KryoWrite_3cyc_LS_XY_293ln, WriteAdr],1468	(instrs LDRQpost, LDRQpre)>;1469def KryoWrite_4cyc_X_LS_noRSV_297ln :1470	SchedWriteRes<[KryoUnitX, KryoUnitLS]> {1471	let Latency = 4; let NumMicroOps = 3;1472}1473def : InstRW<[KryoWrite_4cyc_X_LS_noRSV_297ln],1474	(instregex "LDR(D|S|H|B)ro(W|X)")>;1475def KryoWrite_3cyc_LS_XY_noRSV_319ln :1476	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1477	let Latency = 3; let NumMicroOps = 3;1478}1479def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_319ln, WriteAdr],1480	(instregex "LDR(D|S|H|B)(post|pre)")>;1481def KryoWrite_3cyc_LS_261ln :1482	SchedWriteRes<[KryoUnitLS]> {1483	let Latency = 3; let NumMicroOps = 1;1484}1485def : InstRW<[KryoWrite_3cyc_LS_261ln],1486	(instregex "LDR(BB|HH|W|X)ui")>;1487def KryoWrite_3cyc_LS_XY_292ln :1488	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1489	let Latency = 3; let NumMicroOps = 2;1490}1491def : InstRW<[KryoWrite_3cyc_LS_XY_292ln, WriteAdr],1492	(instregex "LDR(BB|HH|W|X)(post|pre)")>;1493def KryoWrite_4cyc_X_LS_272ln :1494	SchedWriteRes<[KryoUnitX, KryoUnitLS]> {1495	let Latency = 4; let NumMicroOps = 2;1496}1497def : InstRW<[KryoWrite_4cyc_X_LS_272ln],1498	(instregex "(LDR(BB|HH|W|X)ro(W|X)|PRFMro(W|X))")>;1499def KryoWrite_3cyc_LS_262ln :1500	SchedWriteRes<[KryoUnitLS]> {1501	let Latency = 3; let NumMicroOps = 1;1502}1503def : InstRW<[KryoWrite_3cyc_LS_262ln],1504	(instrs LDRWl, LDRXl)>;1505def KryoWrite_4cyc_LS_268ln :1506	SchedWriteRes<[KryoUnitLS]> {1507	let Latency = 4; let NumMicroOps = 1;1508}1509def : InstRW<[KryoWrite_4cyc_LS_268ln],1510	(instregex "LDRS(BW|BX|HW|HX|W)ui")>;1511def KryoWrite_5cyc_X_LS_273ln :1512	SchedWriteRes<[KryoUnitX, KryoUnitLS]> {1513	let Latency = 5; let NumMicroOps = 2;1514}1515def : InstRW<[KryoWrite_5cyc_X_LS_273ln],1516	(instregex "LDRS(BW|BX|HW|HX|W)ro(W|X)")>;1517def KryoWrite_4cyc_LS_XY_294ln :1518	SchedWriteRes<[KryoUnitLS, KryoUnitXY]> {1519	let Latency = 4; let NumMicroOps = 2;1520}1521def : InstRW<[KryoWrite_4cyc_LS_XY_294ln, WriteAdr],1522	(instregex "LDRS(BW|BX|HW|HX|W)(post|pre)")>;1523def KryoWrite_4cyc_LS_269ln :1524	SchedWriteRes<[KryoUnitLS]> {1525	let Latency = 4; let NumMicroOps = 1;1526}1527def : InstRW<[KryoWrite_4cyc_LS_269ln],1528	(instrs LDRSWl)>;1529def KryoWrite_3cyc_LS_260ln :1530	SchedWriteRes<[KryoUnitLS]> {1531	let Latency = 3; let NumMicroOps = 1;1532}1533def : InstRW<[KryoWrite_3cyc_LS_260ln],1534	(instregex "LDTR(B|H|W|X)i")>;1535def KryoWrite_4cyc_LS_267ln :1536	SchedWriteRes<[KryoUnitLS]> {1537	let Latency = 4; let NumMicroOps = 1;1538}1539def : InstRW<[KryoWrite_4cyc_LS_267ln],1540	(instregex "LDTRS(BW|BX|HW|HX|W)i")>;1541def KryoWrite_3cyc_LS_263ln :1542	SchedWriteRes<[KryoUnitLS]> {1543	let Latency = 3; let NumMicroOps = 1;1544}1545def : InstRW<[KryoWrite_3cyc_LS_263ln],1546	(instrs LDURQi)>;1547def KryoWrite_3cyc_LS_noRSV_288ln :1548	SchedWriteRes<[KryoUnitLS]> {1549	let Latency = 3; let NumMicroOps = 2;1550}1551def : InstRW<[KryoWrite_3cyc_LS_noRSV_288ln],1552	(instregex "LDUR(D|S|H|B)i")>;1553def KryoWrite_3cyc_LS_259ln :1554	SchedWriteRes<[KryoUnitLS]> {1555	let Latency = 3; let NumMicroOps = 1;1556}1557def : InstRW<[KryoWrite_3cyc_LS_259ln],1558	(instregex "LDUR(BB|HH|W|X)i")>;1559def KryoWrite_4cyc_LS_266ln :1560	SchedWriteRes<[KryoUnitLS]> {1561	let Latency = 4; let NumMicroOps = 1;1562}1563def : InstRW<[KryoWrite_4cyc_LS_266ln],1564	(instregex "LDURS(B|H)?(W|X)i")>;1565def KryoWrite_3cyc_LS_258ln :1566	SchedWriteRes<[KryoUnitLS]> {1567	let Latency = 3; let NumMicroOps = 1;1568}1569def : InstRW<[KryoWrite_3cyc_LS_258ln, WriteLDHi],1570	(instregex "LDXP(W|X)")>;1571def KryoWrite_3cyc_LS_258_1ln :1572	SchedWriteRes<[KryoUnitLS]> {1573	let Latency = 3; let NumMicroOps = 1;1574}1575def : InstRW<[KryoWrite_3cyc_LS_258_1ln],1576	(instregex "LDXR(B|H|W|X)")>;1577def KryoWrite_2cyc_XY_XY_137ln :1578	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {1579	let Latency = 2; let NumMicroOps = 2;1580}1581def : InstRW<[KryoWrite_2cyc_XY_XY_137ln],1582	(instrs LSLVWr, LSLVXr)>;1583def KryoWrite_1cyc_XY_135ln :1584	SchedWriteRes<[KryoUnitXY]> {1585	let Latency = 1; let NumMicroOps = 1;1586}1587def : InstRW<[KryoWrite_1cyc_XY_135ln],1588	(instregex "(LS|AS|RO)RV(W|X)r")>;1589def KryoWrite_4cyc_X_84ln :1590	SchedWriteRes<[KryoUnitX]> {1591	let Latency = 4; let NumMicroOps = 1;1592}1593def : InstRW<[KryoWrite_4cyc_X_84ln],1594	(instrs MADDWrrr, MSUBWrrr)>;1595def KryoWrite_5cyc_X_85ln :1596	SchedWriteRes<[KryoUnitX]> {1597	let Latency = 5; let NumMicroOps = 1;1598}1599def : InstRW<[KryoWrite_5cyc_X_85ln],1600	(instrs MADDXrrr, MSUBXrrr)>;1601def KryoWrite_4cyc_X_noRSV_188ln :1602	SchedWriteRes<[KryoUnitX]> {1603	let Latency = 4; let NumMicroOps = 2;1604}1605def : InstRW<[KryoWrite_4cyc_X_noRSV_188ln],1606	(instregex "(MLA|MLS|MUL)(v8i8|v4i16|v2i32)(_indexed)?")>;1607def KryoWrite_4cyc_X_X_192ln :1608	SchedWriteRes<[KryoUnitX, KryoUnitX]> {1609	let Latency = 4; let NumMicroOps = 2;1610}1611def : InstRW<[KryoWrite_4cyc_X_X_192ln],1612	(instregex "(MLA|MLS|MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?")>;1613def KryoWrite_1cyc_XY_noRSV_198ln :1614	SchedWriteRes<[KryoUnitXY]> {1615	let Latency = 1; let NumMicroOps = 2;1616}1617def : InstRW<[KryoWrite_1cyc_XY_noRSV_198ln],1618	(instregex "(MOVI|MVNI)(D|v8b_ns|v2i32|v4i16|v2s_msl)")>;1619def KryoWrite_1cyc_XY_XY_199ln :1620	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {1621	let Latency = 1; let NumMicroOps = 2;1622}1623def : InstRW<[KryoWrite_1cyc_XY_XY_199ln],1624	(instregex "(MOVI|MVNI)(v2d_ns|v16b_ns|v4i32|v8i16|v4s_msl)")>;1625def KryoWrite_1cyc_X_89ln :1626	SchedWriteRes<[KryoUnitX]> {1627	let Latency = 1; let NumMicroOps = 1;1628}1629def : InstRW<[KryoWrite_1cyc_X_89ln],1630	(instrs MOVKWi, MOVKXi)>;1631def KryoWrite_1cyc_XY_91ln :1632	SchedWriteRes<[KryoUnitXY]> {1633	let Latency = 1; let NumMicroOps = 1;1634}1635def : InstRW<[KryoWrite_1cyc_XY_91ln],1636	(instrs MOVNWi, MOVNXi)>;1637def KryoWrite_1cyc_XY_90ln :1638	SchedWriteRes<[KryoUnitXY]> {1639	let Latency = 1; let NumMicroOps = 1;1640}1641def : InstRW<[KryoWrite_1cyc_XY_90ln],1642	(instrs MOVZWi, MOVZXi)>;1643def KryoWrite_2cyc_XY_93ln :1644	SchedWriteRes<[KryoUnitXY]> {1645	let Latency = 2; let NumMicroOps = 1;1646}1647def : InstRW<[KryoWrite_2cyc_XY_93ln],1648	(instrs MRS)>;1649def KryoWrite_0cyc_X_87ln :1650	SchedWriteRes<[KryoUnitX]> {1651	let Latency = 0; let NumMicroOps = 1;1652}1653def : InstRW<[KryoWrite_0cyc_X_87ln],1654	(instrs MSRpstateImm4)>;1655def : InstRW<[KryoWrite_0cyc_X_87ln],1656	(instrs MSRpstateImm1)>;1657def KryoWrite_0cyc_XY_88ln :1658	SchedWriteRes<[KryoUnitXY]> {1659	let Latency = 0; let NumMicroOps = 1;1660}1661def : InstRW<[KryoWrite_0cyc_XY_88ln],1662	(instrs MSR)>;1663def KryoWrite_1cyc_XY_noRSV_143ln :1664	SchedWriteRes<[KryoUnitXY]> {1665	let Latency = 1; let NumMicroOps = 2;1666}1667def : InstRW<[KryoWrite_1cyc_XY_noRSV_143ln],1668	(instregex "NEG(v8i8|v4i16|v2i32|v1i64)")>;1669def KryoWrite_1cyc_XY_XY_145ln :1670	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {1671	let Latency = 1; let NumMicroOps = 2;1672}1673def : InstRW<[KryoWrite_1cyc_XY_XY_145ln],1674	(instregex "NEG(v16i8|v8i16|v4i32|v2i64)")>;1675def KryoWrite_1cyc_XY_noRSV_193ln :1676	SchedWriteRes<[KryoUnitXY]> {1677	let Latency = 1; let NumMicroOps = 2;1678}1679def : InstRW<[KryoWrite_1cyc_XY_noRSV_193ln],1680	(instrs NOTv8i8)>;1681def KryoWrite_1cyc_XY_XY_194ln :1682	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {1683	let Latency = 1; let NumMicroOps = 2;1684}1685def : InstRW<[KryoWrite_1cyc_XY_XY_194ln],1686	(instrs NOTv16i8)>;1687def KryoWrite_2cyc_XY_noRSV_234ln :1688	SchedWriteRes<[KryoUnitXY]> {1689	let Latency = 2; let NumMicroOps = 2;1690}1691def : InstRW<[KryoWrite_2cyc_XY_noRSV_234ln],1692	(instrs PMULv8i8)>;1693def KryoWrite_2cyc_XY_XY_236ln :1694	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {1695	let Latency = 2; let NumMicroOps = 2;1696}1697def : InstRW<[KryoWrite_2cyc_XY_XY_236ln],1698	(instrs PMULv16i8)>;1699def KryoWrite_2cyc_XY_XY_235ln :1700	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {1701	let Latency = 2; let NumMicroOps = 2;1702}1703def : InstRW<[KryoWrite_2cyc_XY_XY_235ln],1704	(instrs PMULLv8i8, PMULLv16i8)>;1705def KryoWrite_3cyc_XY_XY_237ln :1706	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {1707	let Latency = 3; let NumMicroOps = 2;1708}1709def : InstRW<[KryoWrite_3cyc_XY_XY_237ln],1710	(instrs PMULLv1i64, PMULLv2i64)>;1711def KryoWrite_0cyc_LS_254ln :1712	SchedWriteRes<[KryoUnitLS]> {1713	let Latency = 0; let NumMicroOps = 1;1714}1715def : InstRW<[KryoWrite_0cyc_LS_254ln],1716	(instrs PRFMl, PRFMui)>;1717def KryoWrite_0cyc_LS_253ln :1718	SchedWriteRes<[KryoUnitLS]> {1719	let Latency = 0; let NumMicroOps = 1;1720}1721def : InstRW<[KryoWrite_0cyc_LS_253ln],1722	(instrs PRFUMi)>;1723def KryoWrite_6cyc_XY_X_noRSV_175ln :1724	SchedWriteRes<[KryoUnitXY, KryoUnitX]> {1725	let Latency = 6; let NumMicroOps = 3;1726}1727def : InstRW<[KryoWrite_6cyc_XY_X_noRSV_175ln],1728	(instregex "R(ADD|SUB)HNv.*")>;1729def KryoWrite_2cyc_XY_204ln :1730	SchedWriteRes<[KryoUnitXY]> {1731	let Latency = 2; let NumMicroOps = 1;1732}1733def : InstRW<[KryoWrite_2cyc_XY_204ln],1734	(instrs RBITWr, RBITXr)>;1735def KryoWrite_2cyc_XY_noRSV_218ln :1736	SchedWriteRes<[KryoUnitXY]> {1737	let Latency = 2; let NumMicroOps = 2;1738}1739def : InstRW<[KryoWrite_2cyc_XY_noRSV_218ln],1740	(instrs RBITv8i8)>;1741def KryoWrite_2cyc_XY_XY_219ln :1742	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {1743	let Latency = 2; let NumMicroOps = 2;1744}1745def : InstRW<[KryoWrite_2cyc_XY_XY_219ln],1746	(instrs RBITv16i8)>;1747def KryoWrite_1cyc_X_202ln :1748	SchedWriteRes<[KryoUnitX]> {1749	let Latency = 1; let NumMicroOps = 1;1750}1751def : InstRW<[KryoWrite_1cyc_X_202ln],1752	(instregex "REV(16|32)?(W|X)r")>;1753def KryoWrite_1cyc_XY_noRSV_214ln :1754	SchedWriteRes<[KryoUnitXY]> {1755	let Latency = 1; let NumMicroOps = 2;1756}1757def : InstRW<[KryoWrite_1cyc_XY_noRSV_214ln],1758	(instregex "REV(16|32|64)(v8i8|v4i16|v2i32)")>;1759def KryoWrite_1cyc_XY_XY_216ln :1760	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {1761	let Latency = 1; let NumMicroOps = 2;1762}1763def : InstRW<[KryoWrite_1cyc_XY_XY_216ln],1764	(instregex "REV(16|32|64)(v16i8|v8i16|v4i32)")>;1765def KryoWrite_3cyc_X_noRSV_244ln :1766	SchedWriteRes<[KryoUnitX]> {1767	let Latency = 3; let NumMicroOps = 2;1768}1769def : InstRW<[KryoWrite_3cyc_X_noRSV_244ln],1770	(instregex "S(L|R)I(d|(v8i8|v4i16|v2i32)_shift)")>;1771def KryoWrite_3cyc_X_X_245ln :1772	SchedWriteRes<[KryoUnitX, KryoUnitX]> {1773	let Latency = 3; let NumMicroOps = 2;1774}1775def : InstRW<[KryoWrite_3cyc_X_X_245ln],1776	(instregex "S(L|R)I(v16i8|v8i16|v4i32|v2i64)_shift")>;1777def KryoWrite_1cyc_XY_2ln :1778	SchedWriteRes<[KryoUnitXY]> {1779	let Latency = 1; let NumMicroOps = 1;1780}1781def : InstRW<[KryoWrite_1cyc_XY_2ln, ReadI, ReadI],1782	(instregex "SBCS?(W|X)r")>;1783def KryoWrite_2cyc_XA_XA_XA_24ln :1784	SchedWriteRes<[KryoUnitXA, KryoUnitXA, KryoUnitXA]> {1785	let Latency = 2; let NumMicroOps = 3;1786}1787def : InstRW<[KryoWrite_2cyc_XA_XA_XA_24ln],1788	(instrs SHA1Crrr, SHA1Mrrr, SHA1Prrr)>;1789def KryoWrite_1cyc_XY_noRSV_21ln :1790	SchedWriteRes<[KryoUnitXY]> {1791	let Latency = 1; let NumMicroOps = 2;1792}1793def : InstRW<[KryoWrite_1cyc_XY_noRSV_21ln],1794	(instrs SHA1Hrr)>;1795def KryoWrite_2cyc_X_X_23ln :1796	SchedWriteRes<[KryoUnitX, KryoUnitX]> {1797	let Latency = 2; let NumMicroOps = 2;1798}1799def : InstRW<[KryoWrite_2cyc_X_X_23ln],1800	(instrs SHA1SU0rrr, SHA1SU1rr, SHA256SU0rr)>;1801def KryoWrite_4cyc_XA_XA_XA_25ln :1802	SchedWriteRes<[KryoUnitXA, KryoUnitXA, KryoUnitXA]> {1803	let Latency = 4; let NumMicroOps = 3;1804}1805def : InstRW<[KryoWrite_4cyc_XA_XA_XA_25ln],1806	(instrs SHA256Hrrr, SHA256H2rrr)>;1807def KryoWrite_3cyc_XY_XY_X_X_26ln :1808	SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitX, KryoUnitX]> {1809	let Latency = 3; let NumMicroOps = 4;1810}1811def : InstRW<[KryoWrite_3cyc_XY_XY_X_X_26ln],1812	(instrs SHA256SU1rrr)>;1813def KryoWrite_4cyc_X_noRSV_189ln :1814	SchedWriteRes<[KryoUnitX]> {1815	let Latency = 4; let NumMicroOps = 2;1816}1817def : InstRW<[KryoWrite_4cyc_X_noRSV_189ln],1818	(instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>;1819def KryoWrite_3cyc_XY_noRSV_68ln :1820	SchedWriteRes<[KryoUnitXY]> {1821	let Latency = 3; let NumMicroOps = 2;1822}1823def : InstRW<[KryoWrite_3cyc_XY_noRSV_68ln],1824	(instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;1825def KryoWrite_3cyc_XY_noRSV_157ln :1826	SchedWriteRes<[KryoUnitXY]> {1827	let Latency = 3; let NumMicroOps = 2;1828}1829def : InstRW<[KryoWrite_3cyc_XY_noRSV_157ln],1830	(instregex "SQ(ABS|NEG)(v8i8|v4i16|v2i32)")>;1831def KryoWrite_3cyc_XY_XY_164ln :1832	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {1833	let Latency = 3; let NumMicroOps = 2;1834}1835def : InstRW<[KryoWrite_3cyc_XY_XY_164ln],1836	(instregex "SQ(ABS|NEG)(v16i8|v8i16|v4i32|v2i64)")>;1837def KryoWrite_4cyc_X_noRSV_190ln :1838	SchedWriteRes<[KryoUnitX]> {1839	let Latency = 4; let NumMicroOps = 2;1840}1841def : InstRW<[KryoWrite_4cyc_X_noRSV_190ln],1842	(instregex "SQD(MLAL|MLSL|MULL)(i16|i32)")>;1843def KryoWrite_0cyc_LS_Y_274ln :1844	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {1845	let Latency = 0; let NumMicroOps = 2;1846}1847def : InstRW<[KryoWrite_0cyc_LS_Y_274ln],1848	(instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))$")>;1849def KryoWrite_1cyc_LS_Y_X_301ln :1850	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX]> {1851	let Latency = 1; let NumMicroOps = 3;1852}1853def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_301ln],1854	(instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))_POST$")>;1855def KryoWrite_1cyc_LS_Y_XY_305ln :1856	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY]> {1857	let Latency = 1; let NumMicroOps = 3;1858}1859def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_305ln],1860	(instregex "ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;1861def KryoWrite_0cyc_LS_Y_LS_Y_323ln :1862	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {1863	let Latency = 0; let NumMicroOps = 4;1864}1865def : InstRW<[WriteAdr, KryoWrite_0cyc_LS_Y_LS_Y_323ln],1866	(instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;1867def KryoWrite_1cyc_LS_Y_XY_LS_Y_345ln :1868	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> {1869	let Latency = 1; let NumMicroOps = 5;1870}1871def : InstRW<[KryoWrite_1cyc_LS_Y_XY_LS_Y_345ln],1872	(instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;1873def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_356ln :1874	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS,1875                   KryoUnitY]> {1876	let Latency = 0; let NumMicroOps = 6;1877}1878def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_356ln],1879	(instregex "ST1Three(v16b|v8h|v4s|v2d)$")>;1880def KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_366ln :1881	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY,1882                   KryoUnitLS, KryoUnitY]> {1883	let Latency = 1; let NumMicroOps = 7;1884}1885def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_366ln],1886	(instregex "ST1Three(v16b|v8h|v4s|v2d)_POST$")>;1887def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_371ln :1888	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS,1889                   KryoUnitY, KryoUnitLS, KryoUnitY]> {1890	let Latency = 0; let NumMicroOps = 8;1891}1892def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_371ln],1893	(instregex "ST1Four(v16b|v8h|v4s|v2d)$")>;1894def KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_377ln :1895	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitXY,1896                   KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {1897	let Latency = 0; let NumMicroOps = 9;1898}1899def : InstRW<[WriteAdr, KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_377ln],1900	(instregex "ST1Four(v16b|v8h|v4s|v2d)_POST$")>;1901def KryoWrite_0cyc_LS_Y_275ln :1902	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {1903	let Latency = 0; let NumMicroOps = 2;1904}1905def : InstRW<[KryoWrite_0cyc_LS_Y_275ln],1906	(instregex "ST2(Two(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64))$")>;1907def KryoWrite_1cyc_LS_Y_XY_306ln :1908	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY]> {1909	let Latency = 1; let NumMicroOps = 3;1910}1911def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_306ln],1912	(instregex "ST2(Two(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64))_POST$")>;1913def KryoWrite_0cyc_LS_Y_LS_Y_322ln :1914	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {1915	let Latency = 0; let NumMicroOps = 4;1916}1917def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_322ln],1918	(instregex "ST2Two(v16b|v8h|v4s|v2d)$")>;1919def KryoWrite_1cyc_LS_Y_XY_LS_Y_344ln :1920	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> {1921	let Latency = 1; let NumMicroOps = 5;1922}1923def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_344ln],1924	(instregex "ST2Two(v16b|v8h|v4s|v2d)_POST$")>;1925def KryoWrite_0cyc_LS_Y_LS_Y_324ln :1926	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {1927	let Latency = 0; let NumMicroOps = 4;1928}1929def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_324ln],1930	(instregex "ST3(Threev1d|(i8|i16|i32|i64))$")>;1931def KryoWrite_1cyc_LS_Y_XY_LS_Y_346ln :1932	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> {1933	let Latency = 1; let NumMicroOps = 5;1934}1935def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_346ln],1936	(instregex "ST3(Threev1d|(i8|i16|i32|i64))_POST$")>;1937def KryoWrite_1cyc_X_X_LS_Y_LS_Y_353ln :1938	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitLS,1939                   KryoUnitY]> {1940	let Latency = 1; let NumMicroOps = 6;1941}1942def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_LS_Y_353ln],1943	(instregex "ST3Three(v8b|v4h|v2s)$")>;1944def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_357ln :1945	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS,1946                   KryoUnitY]> {1947	let Latency = 0; let NumMicroOps = 6;1948}1949def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_357ln],1950	(instregex "ST3Threev2d$")>;1951def KryoWrite_1cyc_X_X_LS_Y_XY_LS_Y_363ln :1952	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY,1953                   KryoUnitLS, KryoUnitY]> {1954	let Latency = 1; let NumMicroOps = 7;1955}1956def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_XY_LS_Y_363ln],1957	(instregex "ST3Three(v8b|v4h|v2s)_POST$")>;1958def KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_367ln :1959	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY,1960                   KryoUnitLS, KryoUnitY]> {1961	let Latency = 1; let NumMicroOps = 7;1962}1963def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_367ln],1964	(instregex "ST3Threev2d_POST$")>;1965def KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_LS_Y_385ln :1966	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitLS,1967                   KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY,1968                   KryoUnitLS, KryoUnitY]> {1969	let Latency = 1; let NumMicroOps = 12;1970}1971def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_LS_Y_385ln],1972	(instregex "ST3Three(v16b|v8h|v4s)$")>;1973def KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_XY_LS_Y_388ln :1974	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitLS,1975                   KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY,1976                   KryoUnitXY, KryoUnitLS, KryoUnitY]> {1977	let Latency = 1; let NumMicroOps = 13;1978}1979def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_XY_LS_Y_388ln],1980	(instregex "ST3Three(v16b|v8h|v4s)_POST$")>;1981def KryoWrite_0cyc_LS_Y_LS_Y_325ln :1982	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {1983	let Latency = 0; let NumMicroOps = 4;1984}1985def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_325ln],1986	(instregex "ST4(Fourv1d|(i8|i16|i32|i64))$")>;1987def KryoWrite_1cyc_LS_Y_XY_LS_Y_347ln :1988	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> {1989	let Latency = 1; let NumMicroOps = 5;1990}1991def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_347ln],1992	(instregex "ST4(Fourv1d|(i8|i16|i32|i64))_POST$")>;1993def KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_370ln :1994	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX,1995                   KryoUnitX, KryoUnitLS, KryoUnitY]> {1996	let Latency = 1; let NumMicroOps = 8;1997}1998def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_370ln],1999	(instregex "ST4Four(v8b|v4h|v2s)$")>;2000def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_372ln :2001	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS,2002                   KryoUnitY, KryoUnitLS, KryoUnitY]> {2003	let Latency = 0; let NumMicroOps = 8;2004}2005def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_372ln],2006	(instregex "ST4Fourv2d$")>;2007def KryoWrite_1cyc_X_X_LS_Y_XY_X_X_LS_Y_375ln :2008	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY,2009                   KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY]> {2010	let Latency = 1; let NumMicroOps = 9;2011}2012def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_XY_X_X_LS_Y_375ln],2013	(instregex "ST4Four(v8b|v4h|v2s)_POST$")>;2014def KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_379ln :2015	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitXY,2016                   KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {2017	let Latency = 0; let NumMicroOps = 9;2018}2019def : InstRW<[WriteAdr, KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_379ln],2020	(instregex "ST4Fourv2d_POST$")>;2021def KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_390ln :2022	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX,2023                   KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX,2024                   KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS,2025                   KryoUnitY]> {2026	let Latency = 1; let NumMicroOps = 16;2027}2028def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_390ln],2029	(instregex "ST4Four(v16b|v8h|v4s)$")>;2030def KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_XY_X_X_LS_Y_392ln :2031	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX,2032                   KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX,2033                   KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitX, KryoUnitX,2034                   KryoUnitLS, KryoUnitY]> {2035	let Latency = 1; let NumMicroOps = 17;2036}2037def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_XY_X_X_LS_Y_392ln],2038	(instregex "ST4Four(v16b|v8h|v4s)_POST$")>;2039def KryoWrite_0cyc_LS_LS_Y_299ln :2040	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitY]> {2041	let Latency = 0; let NumMicroOps = 3;2042}2043def : InstRW<[KryoWrite_0cyc_LS_LS_Y_299ln],2044	(instregex "STLR(B|H|W|X)")>;2045def KryoWrite_3cyc_LS_LS_Y_307ln :2046	SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitY]> {2047	let Latency = 3; let NumMicroOps = 3;2048}2049def : InstRW<[KryoWrite_3cyc_LS_LS_Y_307ln],2050	(instregex "STLX(P(W|X)|R(B|H|W|X))")>;2051def KryoWrite_0cyc_LS_Y_276ln :2052	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {2053	let Latency = 0; let NumMicroOps = 2;2054}2055def : InstRW<[KryoWrite_0cyc_LS_Y_276ln],2056	(instrs STNPDi, STNPSi)>;2057def KryoWrite_0cyc_LS_Y_LS_Y_326ln :2058	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {2059	let Latency = 0; let NumMicroOps = 4;2060}2061def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_326ln],2062	(instrs STNPQi)>;2063def KryoWrite_0cyc_LS_Y_280ln :2064	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {2065	let Latency = 0; let NumMicroOps = 2;2066}2067def : InstRW<[KryoWrite_0cyc_LS_Y_280ln],2068	(instrs STNPWi, STNPXi)>;2069def KryoWrite_0cyc_LS_Y_277ln :2070	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {2071	let Latency = 0; let NumMicroOps = 2;2072}2073def : InstRW<[KryoWrite_0cyc_LS_Y_277ln],2074	(instregex "STP(D|S)i")>;2075def KryoWrite_1cyc_LS_Y_X_303ln :2076	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX]> {2077	let Latency = 1; let NumMicroOps = 3;2078}2079def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_303ln],2080	(instregex "STP(D|S)(post|pre)")>;2081def KryoWrite_0cyc_LS_Y_LS_Y_327ln :2082	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> {2083	let Latency = 0; let NumMicroOps = 4;2084}2085def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_327ln],2086	(instrs STPQi)>;2087def KryoWrite_1cyc_LS_Y_X_LS_Y_343ln :2088	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitLS, KryoUnitY]> {2089	let Latency = 1; let NumMicroOps = 5;2090}2091def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_LS_Y_343ln],2092	(instrs STPQpost, STPQpre)>;2093def KryoWrite_0cyc_LS_Y_279ln :2094	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {2095	let Latency = 0; let NumMicroOps = 2;2096}2097def : InstRW<[KryoWrite_0cyc_LS_Y_279ln],2098	(instregex "STP(W|X)i")>;2099def KryoWrite_1cyc_LS_X_Y_300ln :2100	SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitY]> {2101	let Latency = 1; let NumMicroOps = 3;2102}2103def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_X_Y_300ln],2104	(instregex "STP(W|X)(post|pre)")>;2105def KryoWrite_0cyc_LS_Y_278ln :2106	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {2107	let Latency = 0; let NumMicroOps = 2;2108}2109def : InstRW<[KryoWrite_0cyc_LS_Y_278ln],2110	(instregex "STR(Q|D|S|H|B)ui")>;2111def KryoWrite_1cyc_X_LS_Y_295ln :2112	SchedWriteRes<[KryoUnitX, KryoUnitLS, KryoUnitY]> {2113	let Latency = 1; let NumMicroOps = 3;2114}2115def : InstRW<[KryoWrite_1cyc_X_LS_Y_295ln],2116	(instregex "STR(D|S|H|B)ro(W|X)")>;2117def KryoWrite_1cyc_LS_Y_X_304ln :2118	SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX]> {2119	let Latency = 1; let NumMicroOps = 3;2120}2121def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_304ln],2122	(instregex "STR(Q|D|S|H|B)(post|pre)")>;2123def KryoWrite_2cyc_X_LS_Y_XY_LS_Y_354ln :2124	SchedWriteRes<[KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS,2125                   KryoUnitY]> {2126	let Latency = 2; let NumMicroOps = 6;2127}2128def : InstRW<[KryoWrite_2cyc_X_LS_Y_XY_LS_Y_354ln],2129	(instregex "STRQro(W|X)")>;2130def KryoWrite_0cyc_LS_Y_399ln :2131	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {2132	let Latency = 0; let NumMicroOps = 2;2133}2134def : InstRW<[KryoWrite_0cyc_LS_Y_399ln],2135	(instregex "STR(BB|HH|W|X)ui")>;2136def KryoWrite_1cyc_X_LS_Y_406ln :2137	SchedWriteRes<[KryoUnitX, KryoUnitLS, KryoUnitY]> {2138	let Latency = 1; let NumMicroOps = 3;2139}2140def : InstRW<[KryoWrite_1cyc_X_LS_Y_406ln],2141	(instregex "STR(BB|HH|W|X)ro(W|X)")>;2142def KryoWrite_1cyc_LS_X_Y_407ln :2143	SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitY]> {2144	let Latency = 1; let NumMicroOps = 3;2145}2146def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_X_Y_407ln],2147	(instregex "STR(BB|HH|W|X)(post|pre)")>;2148def KryoWrite_0cyc_LS_Y_398ln :2149	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {2150	let Latency = 0; let NumMicroOps = 2;2151}2152def : InstRW<[KryoWrite_0cyc_LS_Y_398ln],2153	(instregex "STTR(B|H|W|X)i")>;2154def KryoWrite_0cyc_LS_Y_396ln :2155	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {2156	let Latency = 0; let NumMicroOps = 2;2157}2158def : InstRW<[KryoWrite_0cyc_LS_Y_396ln],2159	(instregex "STUR(Q|D|S|H|B)i")>;2160def KryoWrite_0cyc_LS_Y_397ln :2161	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {2162	let Latency = 0; let NumMicroOps = 2;2163}2164def : InstRW<[KryoWrite_0cyc_LS_Y_397ln],2165	(instregex "STUR(BB|HH|W|X)i")>;2166def KryoWrite_3cyc_LS_Y_404ln :2167	SchedWriteRes<[KryoUnitLS, KryoUnitY]> {2168	let Latency = 3; let NumMicroOps = 2;2169}2170def : InstRW<[KryoWrite_3cyc_LS_Y_404ln],2171	(instregex "STX(P(W|X)|R(B|H|W|X))")>;2172def KryoWrite_3cyc_XY_noRSV_160ln :2173	SchedWriteRes<[KryoUnitXY]> {2174	let Latency = 3; let NumMicroOps = 2;2175}2176def : InstRW<[KryoWrite_3cyc_XY_noRSV_160ln],2177	(instregex "^(SU|US)QADD(v8i8|v4i16|v2i32)")>;2178def KryoWrite_3cyc_XY_XY_167ln :2179	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {2180	let Latency = 3; let NumMicroOps = 2;2181}2182def : InstRW<[KryoWrite_3cyc_XY_XY_167ln],2183	(instregex "^(SU|US)QADD(v16i8|v8i16|v4i32|v2i64)")>;2184def KryoWrite_1cyc_XY_1ln :2185	SchedWriteRes<[KryoUnitXY]> {2186	let Latency = 1; let NumMicroOps = 1;2187}2188def : InstRW<[KryoWrite_1cyc_XY_1ln, ReadI],2189	(instregex "SUBS?(W|X)ri")>;2190def KryoWrite_2cyc_XY_XY_5ln :2191	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {2192	let Latency = 2; let NumMicroOps = 2;2193}2194def : InstRW<[KryoWrite_2cyc_XY_XY_5ln, ReadI, ReadIEReg],2195	(instregex "SUBS?(W|X)rx")>;2196def KryoWrite_2cyc_XY_XY_5_1ln :2197	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {2198	let Latency = 2; let NumMicroOps = 2;2199}2200def : InstRW<[KryoWrite_2cyc_XY_XY_5_1ln, ReadI, ReadISReg],2201	(instregex "SUBS?(W|X)rs")>;2202def KryoWrite_1cyc_XY_noRSV_6ln :2203	SchedWriteRes<[KryoUnitXY]> {2204	let Latency = 1; let NumMicroOps = 2;2205}2206def : InstRW<[KryoWrite_1cyc_XY_noRSV_6ln, ReadI, ReadI],2207	(instregex "SUBS?(W|X)rr")>;2208def KryoWrite_0cyc_LS_9ln :2209	SchedWriteRes<[KryoUnitLS]> {2210	let Latency = 0; let NumMicroOps = 1;2211}2212def : InstRW<[KryoWrite_0cyc_LS_9ln],2213	(instregex "SYSL?xt")>;2214def KryoWrite_1cyc_X_noRSV_205ln :2215	SchedWriteRes<[KryoUnitX]> {2216	let Latency = 1; let NumMicroOps = 2;2217}2218def : InstRW<[KryoWrite_1cyc_X_noRSV_205ln],2219	(instrs TBLv8i8One)>;2220def KryoWrite_1cyc_X_X_208ln :2221	SchedWriteRes<[KryoUnitX, KryoUnitX]> {2222	let Latency = 1; let NumMicroOps = 2;2223}2224def : InstRW<[KryoWrite_1cyc_X_X_208ln],2225	(instrs TBLv16i8One)>;2226def KryoWrite_2cyc_X_X_X_noRSV_222ln :2227	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX]> {2228	let Latency = 2; let NumMicroOps = 4;2229}2230def : InstRW<[KryoWrite_2cyc_X_X_X_noRSV_222ln],2231	(instrs TBLv8i8Two)>;2232def KryoWrite_2cyc_X_X_X_X_X_X_224ln :2233	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2234                   KryoUnitX]> {2235	let Latency = 2; let NumMicroOps = 6;2236}2237def : InstRW<[KryoWrite_2cyc_X_X_X_X_X_X_224ln],2238	(instrs TBLv16i8Two)>;2239def KryoWrite_3cyc_X_X_X_X_X_noRSV_225ln :2240	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> {2241	let Latency = 3; let NumMicroOps = 6;2242}2243def : InstRW<[KryoWrite_3cyc_X_X_X_X_X_noRSV_225ln],2244	(instrs TBLv8i8Three)>;2245def KryoWrite_3cyc_X_X_X_X_X_X_X_noRSV_228ln :2246	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2247                   KryoUnitX, KryoUnitX]> {2248	let Latency = 3; let NumMicroOps = 8;2249}2250def : InstRW<[KryoWrite_3cyc_X_X_X_X_X_X_X_noRSV_228ln],2251	(instrs TBLv8i8Four)>;2252def KryoWrite_4cyc_X_X_X_X_X_X_X_X_XY_X_X_230ln :2253	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2254                   KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitXY, KryoUnitX,2255                   KryoUnitX]> {2256	let Latency = 4; let NumMicroOps = 11;2257}2258def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_X_X_XY_X_X_230ln],2259	(instrs TBLv16i8Three)>;2260def KryoWrite_4cyc_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_232ln :2261	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2262                   KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2263                   KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> {2264	let Latency = 4; let NumMicroOps = 15;2265}2266def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_232ln],2267	(instrs TBLv16i8Four)>;2268def KryoWrite_2cyc_X_X_noRSV_220ln :2269	SchedWriteRes<[KryoUnitX, KryoUnitX]> {2270	let Latency = 2; let NumMicroOps = 3;2271}2272def : InstRW<[KryoWrite_2cyc_X_X_noRSV_220ln],2273	(instrs TBXv8i8One)>;2274def KryoWrite_2cyc_X_X_X_X_221ln :2275	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> {2276	let Latency = 2; let NumMicroOps = 4;2277}2278def : InstRW<[KryoWrite_2cyc_X_X_X_X_221ln],2279	(instrs TBXv16i8One)>;2280def KryoWrite_3cyc_X_X_X_X_noRSV_223ln :2281	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> {2282	let Latency = 3; let NumMicroOps = 5;2283}2284def : InstRW<[KryoWrite_3cyc_X_X_X_X_noRSV_223ln],2285	(instrs TBXv8i8Two)>;2286def KryoWrite_4cyc_X_X_X_X_X_X_noRSV_226ln :2287	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2288                   KryoUnitX]> {2289	let Latency = 4; let NumMicroOps = 7;2290}2291def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_noRSV_226ln],2292	(instrs TBXv8i8Three)>;2293def KryoWrite_3cyc_X_X_X_X_X_X_X_X_227ln :2294	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2295                   KryoUnitX, KryoUnitX, KryoUnitX]> {2296	let Latency = 3; let NumMicroOps = 8;2297}2298def : InstRW<[KryoWrite_3cyc_X_X_X_X_X_X_X_X_227ln],2299	(instrs TBXv16i8Two)>;2300def KryoWrite_4cyc_X_X_X_X_X_X_X_X_noRSV_229ln :2301	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2302                   KryoUnitX, KryoUnitX, KryoUnitX]> {2303	let Latency = 4; let NumMicroOps = 9;2304}2305def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_X_X_noRSV_229ln],2306	(instrs TBXv8i8Four)>;2307def KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_XY_X_X_X_231ln :2308	SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2309                   KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitXY,2310                   KryoUnitX, KryoUnitX, KryoUnitX]> {2311	let Latency = 5; let NumMicroOps = 13;2312}2313def : InstRW<[KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_XY_X_X_X_231ln],2314	(instrs TBXv16i8Three)>;2315def KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_X_233ln :2316    SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2317                   KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX,2318                   KryoUnitX, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX,2319                   KryoUnitX, KryoUnitX]> {2320	let Latency = 5; let NumMicroOps = 17;2321}2322def : InstRW<[KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_X_233ln],2323	(instrs TBXv16i8Four)>;2324def KryoWrite_1cyc_XY_XY_217ln :2325	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {2326	let Latency = 1; let NumMicroOps = 2;2327}2328def : InstRW<[KryoWrite_1cyc_XY_XY_217ln],2329	(instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;2330def KryoWrite_1cyc_X_X_211ln :2331	SchedWriteRes<[KryoUnitX, KryoUnitX]> {2332	let Latency = 1; let NumMicroOps = 2;2333}2334def : InstRW<[KryoWrite_1cyc_X_X_211ln],2335	(instregex "(TRN1|TRN2)(v4i32|v8i16|v16i8)")>;2336def KryoWrite_1cyc_X_XY_213ln :2337	SchedWriteRes<[KryoUnitX, KryoUnitXY]> {2338	let Latency = 1; let NumMicroOps = 2;2339}2340def : InstRW<[KryoWrite_1cyc_X_XY_213ln],2341	(instregex "(TRN1|TRN2)(v2i32|v4i16|v8i8)")>;2342def KryoWrite_3cyc_XY_noRSV_156ln :2343	SchedWriteRes<[KryoUnitXY]> {2344	let Latency = 3; let NumMicroOps = 2;2345}2346def : InstRW<[KryoWrite_3cyc_XY_noRSV_156ln],2347	(instrs URECPEv2i32, URSQRTEv2i32)>;2348def KryoWrite_3cyc_XY_XY_168ln :2349	SchedWriteRes<[KryoUnitXY, KryoUnitXY]> {2350	let Latency = 3; let NumMicroOps = 2;2351}2352def : InstRW<[KryoWrite_3cyc_XY_XY_168ln],2353	(instrs URECPEv4i32, URSQRTEv4i32)>;2354def KryoWrite_1cyc_X_X_210ln :2355	SchedWriteRes<[KryoUnitX, KryoUnitX]> {2356	let Latency = 1; let NumMicroOps = 2;2357}2358def : InstRW<[KryoWrite_1cyc_X_X_210ln],2359	(instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>;2360def KryoWrite_1cyc_X_noRSV_206ln :2361	SchedWriteRes<[KryoUnitX]> {2362	let Latency = 1; let NumMicroOps = 2;2363}2364def : InstRW<[KryoWrite_1cyc_X_noRSV_206ln],2365	(instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;2366def KryoWrite_1cyc_XY_noRSV_215ln :2367	SchedWriteRes<[KryoUnitXY]> {2368	let Latency = 1; let NumMicroOps = 2;2369}2370def : InstRW<[KryoWrite_1cyc_XY_noRSV_215ln],2371	(instregex "XTNv.*")>;2372def KryoWrite_1cyc_X_X_209ln :2373	SchedWriteRes<[KryoUnitX, KryoUnitX]> {2374	let Latency = 1; let NumMicroOps = 2;2375}2376def : InstRW<[KryoWrite_1cyc_X_X_209ln],2377	(instregex "ZIP1(v4i32|v8i16|v16i8)")>;2378