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1//=- AArch64SchedNeoverseN1.td - NeoverseN1 Scheduling Model -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the scheduling model for the Arm Neoverse N1 processors.10//11// References:12// - "Arm Neoverse N1 Software Optimization Guide"13// - https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_n114//15//===----------------------------------------------------------------------===//16 17def NeoverseN1Model : SchedMachineModel {18 let IssueWidth = 3; // This value comes from the decode bandwidth19 // and empirical measurements showed that this20 // value is better.21 let MicroOpBufferSize = 128; // NOTE: Copied from Cortex-A76.22 let LoadLatency = 4; // Optimistic load latency.23 let MispredictPenalty = 11; // Cycles cost of branch mispredicted.24 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.25 let CompleteModel = 1;26 27 list<Predicate> UnsupportedFeatures = !listconcat(PAUnsupported.F,28 SMEUnsupported.F,29 SVEUnsupported.F,30 [HasMTE, HasCSSC]);31}32 33//===----------------------------------------------------------------------===//34// Define each kind of processor resource and number available on Neoverse N1.35// Instructions are first fetched and then decoded into internal macro-ops36// (MOPs). From there, the MOPs proceed through register renaming and dispatch37// stages. A MOP can be split into one or more micro-ops further down the38// pipeline, after the decode stage. Once dispatched, micro-ops wait for their39// operands and issue out-of-order to one of the issue pipelines. Each issue40// pipeline can accept one micro-op per cycle.41 42let SchedModel = NeoverseN1Model in {43 44// Define the issue ports.45def N1UnitB : ProcResource<1>; // Branch46def N1UnitS : ProcResource<2>; // Integer single cycle 0/147def N1UnitM : ProcResource<1>; // Integer multicycle48def N1UnitL : ProcResource<2>; // Load/Store 0/149def N1UnitD : ProcResource<2>; // Store data 0/150def N1UnitV0 : ProcResource<1>; // FP/ASIMD 051def N1UnitV1 : ProcResource<1>; // FP/ASIMD 152 53def N1UnitI : ProcResGroup<[N1UnitS, N1UnitM]>; // Integer units54def N1UnitV : ProcResGroup<[N1UnitV0, N1UnitV1]>; // FP/ASIMD units55 56// Define commonly used read types.57 58// No generic forwarding is provided for these types.59def : ReadAdvance<ReadI, 0>;60def : ReadAdvance<ReadISReg, 0>;61def : ReadAdvance<ReadIEReg, 0>;62def : ReadAdvance<ReadIM, 0>;63def : ReadAdvance<ReadIMA, 0>;64def : ReadAdvance<ReadID, 0>;65def : ReadAdvance<ReadExtrHi, 0>;66def : ReadAdvance<ReadAdrBase, 0>;67def : ReadAdvance<ReadST, 0>;68def : ReadAdvance<ReadVLD, 0>;69 70def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }71def : WriteRes<WriteBarrier, []> { let Latency = 1; }72def : WriteRes<WriteHint, []> { let Latency = 1; }73 74 75//===----------------------------------------------------------------------===//76// Define generic 0 micro-op types77 78let Latency = 0, NumMicroOps = 0 in79def N1Write_0c_0Z : SchedWriteRes<[]>;80 81//===----------------------------------------------------------------------===//82// Define generic 1 micro-op types83 84def N1Write_1c_1B : SchedWriteRes<[N1UnitB]> { let Latency = 1; }85def N1Write_1c_1I : SchedWriteRes<[N1UnitI]> { let Latency = 1; }86def N1Write_2c_1M : SchedWriteRes<[N1UnitM]> { let Latency = 2; }87def N1Write_3c_1M : SchedWriteRes<[N1UnitM]> { let Latency = 3; }88def N1Write_4c3_1M : SchedWriteRes<[N1UnitM]> { let Latency = 4;89 let ReleaseAtCycles = [3]; }90def N1Write_5c3_1M : SchedWriteRes<[N1UnitM]> { let Latency = 5;91 let ReleaseAtCycles = [3]; }92def N1Write_12c5_1M : SchedWriteRes<[N1UnitM]> { let Latency = 12;93 let ReleaseAtCycles = [5]; }94def N1Write_20c5_1M : SchedWriteRes<[N1UnitM]> { let Latency = 20;95 let ReleaseAtCycles = [5]; }96def N1Write_4c_1L : SchedWriteRes<[N1UnitL]> { let Latency = 4; }97def N1Write_5c_1L : SchedWriteRes<[N1UnitL]> { let Latency = 5; }98def N1Write_7c_1L : SchedWriteRes<[N1UnitL]> { let Latency = 7; }99def N1Write_2c_1V : SchedWriteRes<[N1UnitV]> { let Latency = 2; }100def N1Write_3c_1V : SchedWriteRes<[N1UnitV]> { let Latency = 3; }101def N1Write_4c_1V : SchedWriteRes<[N1UnitV]> { let Latency = 4; }102def N1Write_5c_1V : SchedWriteRes<[N1UnitV]> { let Latency = 5; }103def N1Write_2c_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 2; }104def N1Write_3c_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 3; }105def N1Write_4c_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 4; }106def N1Write_7c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 7;107 let ReleaseAtCycles = [7]; }108def N1Write_10c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 10;109 let ReleaseAtCycles = [7]; }110def N1Write_13c10_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 13;111 let ReleaseAtCycles = [10]; }112def N1Write_15c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 15;113 let ReleaseAtCycles = [7]; }114def N1Write_17c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 17;115 let ReleaseAtCycles = [7]; }116def N1Write_2c_1V1 : SchedWriteRes<[N1UnitV1]> { let Latency = 2; }117def N1Write_3c_1V1 : SchedWriteRes<[N1UnitV1]> { let Latency = 3; }118def N1Write_4c_1V1 : SchedWriteRes<[N1UnitV1]> { let Latency = 4; }119 120//===----------------------------------------------------------------------===//121// Define generic 2 micro-op types122 123let Latency = 1, NumMicroOps = 2 in124def N1Write_1c_1B_1I : SchedWriteRes<[N1UnitB, N1UnitI]>;125let Latency = 3, NumMicroOps = 2 in126def N1Write_3c_1I_1M : SchedWriteRes<[N1UnitI, N1UnitM]>;127let Latency = 2, NumMicroOps = 2 in128def N1Write_2c_1I_1L : SchedWriteRes<[N1UnitI, N1UnitL]>;129let Latency = 5, NumMicroOps = 2 in130def N1Write_5c_1I_1L : SchedWriteRes<[N1UnitI, N1UnitL]>;131let Latency = 6, NumMicroOps = 2 in132def N1Write_6c_1I_1L : SchedWriteRes<[N1UnitI, N1UnitL]>;133let Latency = 7, NumMicroOps = 2 in134def N1Write_7c_1I_1L : SchedWriteRes<[N1UnitI, N1UnitL]>;135let Latency = 5, NumMicroOps = 2 in136def N1Write_5c_1M_1V : SchedWriteRes<[N1UnitM, N1UnitV]>;137let Latency = 6, NumMicroOps = 2 in138def N1Write_6c_1M_1V0 : SchedWriteRes<[N1UnitM, N1UnitV0]>;139let Latency = 5, NumMicroOps = 2 in140def N1Write_5c_2L : SchedWriteRes<[N1UnitL, N1UnitL]>;141let Latency = 1, NumMicroOps = 2 in142def N1Write_1c_1L_1D : SchedWriteRes<[N1UnitL, N1UnitD]>;143let Latency = 2, NumMicroOps = 2 in144def N1Write_2c_1L_1V : SchedWriteRes<[N1UnitL, N1UnitV]>;145let Latency = 4, NumMicroOps = 2 in146def N1Write_4c_1L_1V : SchedWriteRes<[N1UnitL, N1UnitV]>;147let Latency = 7, NumMicroOps = 2 in148def N1Write_7c_1L_1V : SchedWriteRes<[N1UnitL, N1UnitV]>;149let Latency = 4, NumMicroOps = 2 in150def N1Write_4c_1V0_1V1 : SchedWriteRes<[N1UnitV0, N1UnitV1]>;151let Latency = 4, NumMicroOps = 2 in152def N1Write_4c_2V0 : SchedWriteRes<[N1UnitV0, N1UnitV0]>;153let Latency = 5, NumMicroOps = 2 in154def N1Write_5c_2V0 : SchedWriteRes<[N1UnitV0, N1UnitV0]>;155let Latency = 6, NumMicroOps = 2 in156def N1Write_6c_2V1 : SchedWriteRes<[N1UnitV1, N1UnitV1]>;157let Latency = 5, NumMicroOps = 2 in158def N1Write_5c_1V1_1V : SchedWriteRes<[N1UnitV1, N1UnitV]>;159 160//===----------------------------------------------------------------------===//161// Define generic 3 micro-op types162 163let Latency = 7, NumMicroOps = 3 in164def N1Write_2c_1I_1L_1V : SchedWriteRes<[N1UnitI, N1UnitL, N1UnitV]>;165let Latency = 1, NumMicroOps = 3 in166def N1Write_1c_2L_1D : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitD]>;167let Latency = 2, NumMicroOps = 3 in168def N1Write_2c_1L_2V : SchedWriteRes<[N1UnitL, N1UnitV, N1UnitV]>;169let Latency = 6, NumMicroOps = 3 in170def N1Write_6c_3L : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL]>;171let Latency = 4, NumMicroOps = 3 in172def N1Write_4c_3V : SchedWriteRes<[N1UnitV, N1UnitV, N1UnitV]>;173let Latency = 6, NumMicroOps = 3 in174def N1Write_6c_3V : SchedWriteRes<[N1UnitV, N1UnitV, N1UnitV]>;175let Latency = 8, NumMicroOps = 3 in176def N1Write_8c_3V : SchedWriteRes<[N1UnitV, N1UnitV, N1UnitV]>;177 178//===----------------------------------------------------------------------===//179// Define generic 4 micro-op types180 181let Latency = 2, NumMicroOps = 4 in182def N1Write_2c_2I_2L : SchedWriteRes<[N1UnitI, N1UnitI, N1UnitL, N1UnitL]>;183let Latency = 6, NumMicroOps = 4 in184def N1Write_6c_4L : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL, N1UnitL]>;185let Latency = 2, NumMicroOps = 4 in186def N1Write_2c_2L_2V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitV, N1UnitV]>;187let Latency = 2, NumMicroOps = 4 in188def N1Write_3c_2L_2V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitV, N1UnitV]>;189let Latency = 5, NumMicroOps = 4 in190def N1Write_5c_2L_2V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitV, N1UnitV]>;191let Latency = 7, NumMicroOps = 4 in192def N1Write_7c_2L_2V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitV, N1UnitV]>;193let Latency = 4, NumMicroOps = 4 in194def N1Write_4c_4V : SchedWriteRes<[N1UnitV, N1UnitV, N1UnitV, N1UnitV]>;195let Latency = 6, NumMicroOps = 4 in196def N1Write_6c_4V0 : SchedWriteRes<[N1UnitV0, N1UnitV0, N1UnitV0, N1UnitV0]>;197 198//===----------------------------------------------------------------------===//199// Define generic 5 micro-op types200 201let Latency = 3, NumMicroOps = 5 in202def N1Write_3c_2L_3V : SchedWriteRes<[N1UnitL, N1UnitL,203 N1UnitV, N1UnitV, N1UnitV]>;204let Latency = 7, NumMicroOps = 5 in205def N1Write_7c_2L_3V : SchedWriteRes<[N1UnitL, N1UnitL,206 N1UnitV, N1UnitV, N1UnitV]>;207let Latency = 6, NumMicroOps = 5 in208def N1Write_6c_5V : SchedWriteRes<[N1UnitV, N1UnitV, N1UnitV, N1UnitV, N1UnitV]>;209 210//===----------------------------------------------------------------------===//211// Define generic 6 micro-op types212 213let Latency = 3, NumMicroOps = 6 in214def N1Write_3c_4L_2V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL, N1UnitL,215 N1UnitV, N1UnitV]>;216let Latency = 4, NumMicroOps = 6 in217def N1Write_4c_3L_3V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL,218 N1UnitV, N1UnitV, N1UnitV]>;219let Latency = 5, NumMicroOps = 6 in220def N1Write_5c_3L_3V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL,221 N1UnitV, N1UnitV, N1UnitV]>;222let Latency = 6, NumMicroOps = 6 in223def N1Write_6c_3L_3V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL,224 N1UnitV, N1UnitV, N1UnitV]>;225let Latency = 7, NumMicroOps = 6 in226def N1Write_7c_3L_3V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL,227 N1UnitV, N1UnitV, N1UnitV]>;228let Latency = 8, NumMicroOps = 6 in229def N1Write_8c_3L_3V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL,230 N1UnitV, N1UnitV, N1UnitV]>;231 232//===----------------------------------------------------------------------===//233// Define generic 7 micro-op types234 235let Latency = 8, NumMicroOps = 7 in236def N1Write_8c_3L_4V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL,237 N1UnitV, N1UnitV, N1UnitV, N1UnitV]>;238 239//===----------------------------------------------------------------------===//240// Define generic 8 micro-op types241 242let Latency = 5, NumMicroOps = 8 in243def N1Write_5c_4L_4V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL, N1UnitL, 244 N1UnitV, N1UnitV, N1UnitV, N1UnitV]>;245let Latency = 6, NumMicroOps = 8 in246def N1Write_6c_4L_4V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL, N1UnitL, 247 N1UnitV, N1UnitV, N1UnitV, N1UnitV]>;248let Latency = 8, NumMicroOps = 8 in249def N1Write_8c_4L_4V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL, N1UnitL,250 N1UnitV, N1UnitV, N1UnitV, N1UnitV]>;251let Latency = 10, NumMicroOps = 8 in252def N1Write_10c_4L_4V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL, N1UnitL,253 N1UnitV, N1UnitV, N1UnitV, N1UnitV]>;254 255//===----------------------------------------------------------------------===//256// Define generic 12 micro-op types257 258let Latency = 9, NumMicroOps = 12 in259def N1Write_9c_6L_6V : SchedWriteRes<[N1UnitL, N1UnitL, N1UnitL,260 N1UnitL, N1UnitL, N1UnitL, 261 N1UnitV, N1UnitV, N1UnitV,262 N1UnitV, N1UnitV, N1UnitV]>;263 264 265// Miscellaneous Instructions266// -----------------------------------------------------------------------------267 268def : InstRW<[WriteI], (instrs COPY)>;269 270// Convert floating-point condition flags271// Flag manipulation instructions272def : WriteRes<WriteSys, []> { let Latency = 1; }273 274 275// Branch Instructions276// -----------------------------------------------------------------------------277 278// Branch, immed279// Compare and branch280def : SchedAlias<WriteBr, N1Write_1c_1B>;281 282// Branch, register283def : SchedAlias<WriteBrReg, N1Write_1c_1B>;284 285// Branch and link, immed286// Branch and link, register287def : InstRW<[N1Write_1c_1B_1I], (instrs BL, BLR)>;288 289// Compare and branch290def : InstRW<[N1Write_1c_1B], (instregex "^[CT]BN?Z[XW]$")>;291 292 293// Arithmetic and Logical Instructions294// -----------------------------------------------------------------------------295 296// ALU, basic297// ALU, basic, flagset298// Conditional compare299// Conditional select300// Logical, basic301// Address generation302// Count leading303// Reverse bits/bytes304// Move immediate305def : SchedAlias<WriteI, N1Write_1c_1I>;306 307// ALU, extend and shift308def : SchedAlias<WriteIEReg, N1Write_2c_1M>;309 310// Arithmetic, LSL shift, shift <= 4311// Arithmetic, flagset, LSL shift, shift <= 4312// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4313def N1WriteISReg : SchedWriteVariant<[314 SchedVar<IsCheapLSL, [N1Write_1c_1I]>,315 SchedVar<NoSchedPred, [N1Write_2c_1M]>]>;316def : SchedAlias<WriteISReg, N1WriteISReg>;317 318// Logical, shift, no flagset319def : InstRW<[N1Write_1c_1I],320 (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;321 322// Logical, shift, flagset323def : InstRW<[N1Write_2c_1M], (instregex "^(AND|BIC)S[WX]rs$")>;324 325 326// Divide and multiply instructions327// -----------------------------------------------------------------------------328 329// Divide330def : SchedAlias<WriteID32, N1Write_12c5_1M>;331def : SchedAlias<WriteID64, N1Write_20c5_1M>;332 333// Multiply accumulate334// Multiply accumulate, long335def : SchedAlias<WriteIM32, N1Write_2c_1M>;336def : SchedAlias<WriteIM64, N1Write_4c3_1M>;337 338// Multiply high339def : InstRW<[N1Write_5c3_1M, ReadIM, ReadIM], (instrs SMULHrr, UMULHrr)>;340 341 342// Miscellaneous data-processing instructions343// -----------------------------------------------------------------------------344 345// Bitfield extract, one reg346// Bitfield extract, two regs347def N1WriteExtr : SchedWriteVariant<[348 SchedVar<IsRORImmIdiomPred, [N1Write_1c_1I]>,349 SchedVar<NoSchedPred, [N1Write_3c_1I_1M]>]>;350def : SchedAlias<WriteExtr, N1WriteExtr>;351 352// Bitfield move, basic353// Variable shift354def : SchedAlias<WriteIS, N1Write_1c_1I>;355 356// Bitfield move, insert357def : InstRW<[N1Write_2c_1M], (instregex "^BFM[WX]ri$")>;358 359// Move immediate360def : SchedAlias<WriteImm, N1Write_1c_1I>;361 362// Load instructions363// -----------------------------------------------------------------------------364 365// Load register, immed offset366def : SchedAlias<WriteLD, N1Write_4c_1L>;367 368// Load register, immed offset, index369def : SchedAlias<WriteLDIdx, N1Write_4c_1L>;370def : SchedAlias<WriteAdr, N1Write_1c_1I>;371 372// Load pair, immed offset373def : SchedAlias<WriteLDHi, N1Write_4c_1L>;374 375// Load pair, immed offset, W-form376def : InstRW<[N1Write_4c_1L, N1Write_0c_0Z], (instrs LDPWi, LDNPWi)>;377 378// Load pair, signed immed offset, signed words379def : InstRW<[N1Write_5c_1I_1L, N1Write_0c_0Z], (instrs LDPSWi)>;380 381// Load pair, immed post or pre-index, signed words382def : InstRW<[WriteAdr, N1Write_5c_1I_1L, N1Write_0c_0Z],383 (instrs LDPSWpost, LDPSWpre)>;384 385 386// Store instructions387// -----------------------------------------------------------------------------388 389// Store register, immed offset390def : SchedAlias<WriteST, N1Write_1c_1L_1D>;391 392// Store register, immed offset, index393def : SchedAlias<WriteSTIdx, N1Write_1c_1L_1D>;394 395// Store pair, immed offset396def : SchedAlias<WriteSTP, N1Write_1c_2L_1D>;397 398// Store pair, immed offset, W-form399def : InstRW<[N1Write_1c_1L_1D], (instrs STPWi)>;400 401 402// FP data processing instructions403// -----------------------------------------------------------------------------404 405// FP absolute value406// FP arithmetic407// FP min/max408// FP negate409// FP select410def : SchedAlias<WriteF, N1Write_2c_1V>;411 412// FP compare413def : SchedAlias<WriteFCmp, N1Write_2c_1V0>;414 415// FP divide416// FP square root417def : SchedAlias<WriteFDiv, N1Write_10c7_1V0>;418 419// FP divide, H-form420// FP square root, H-form421def : InstRW<[N1Write_7c7_1V0], (instrs FDIVHrr, FSQRTHr)>;422 423// FP divide, S-form424// FP square root, S-form425def : InstRW<[N1Write_10c7_1V0], (instrs FDIVSrr, FSQRTSr)>;426 427// FP divide, D-form428def : InstRW<[N1Write_15c7_1V0], (instrs FDIVDrr)>;429 430// FP square root, D-form431def : InstRW<[N1Write_17c7_1V0], (instrs FSQRTDr)>;432 433// FP multiply434def : SchedAlias<WriteFMul, N1Write_3c_1V>;435 436// FP multiply accumulate437def : InstRW<[N1Write_4c_1V], (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;438 439// FP round to integral440def : InstRW<[N1Write_3c_1V0], (instregex "^FRINT[AIMNPXZ][HSD]r$",441 "^FRINT(32|64)[XZ][SD]r$")>;442 443 444// FP miscellaneous instructions445// -----------------------------------------------------------------------------446 447// FP convert, from vec to vec reg448// FP convert, Javascript from vec to gen reg449def : SchedAlias<WriteFCvt, N1Write_3c_1V>;450 451// FP convert, from gen to vec reg452def : InstRW<[N1Write_6c_1M_1V0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;453 454// FP convert, from vec to gen reg455def : InstRW<[N1Write_4c_1V0_1V1], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>;456 457// FP move, immed458def : SchedAlias<WriteFImm, N1Write_2c_1V>;459 460// FP move, register461def : InstRW<[N1Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>;462 463// FP transfer, from gen to low half of vec reg464// FP transfer, from gen to high half of vec reg465def : InstRW<[N1Write_3c_1M], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr,466 FMOVXDHighr)>;467 468// FP transfer, from vec to gen reg469def : SchedAlias<WriteFCopy, N1Write_2c_1V1>;470 471 472// FP load instructions473// -----------------------------------------------------------------------------474 475// Load vector reg, literal, S/D/Q forms476// Load vector reg, unscaled immed477def : InstRW<[N1Write_5c_1L, ReadAdrBase], (instregex "^LDR[SDQ]l$",478 "^LDUR[BHSDQ]i$")>;479 480// Load vector reg, immed post-index481// Load vector reg, immed pre-index482def : InstRW<[WriteAdr, N1Write_5c_1L],483 (instregex "^LDR[BHSDQ](post|pre)$")>;484 485// Load vector reg, unsigned immed486def : InstRW<[N1Write_5c_1I_1L], (instregex "^LDR[BHSDQ]ui$")>;487 488// Load vector reg, register offset, basic489// Load vector reg, register offset, scale, S/D-form490// Load vector reg, register offset, extend491// Load vector reg, register offset, extend, scale, S/D-form492def : InstRW<[N1Write_5c_1I_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>;493 494// Load vector reg, register offset, scale, H/Q-form495// Load vector reg, register offset, extend, scale, H/Q-form496def : InstRW<[N1Write_6c_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>;497 498// Load vector pair, immed offset, S/D-form499def : InstRW<[N1Write_5c_1I_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>;500 501// Load vector pair, immed offset, H/Q-form502def : InstRW<[N1Write_7c_1I_1L, WriteLDHi], (instregex "^LDPN?[HQ]i$")>;503 504// Load vector pair, immed post-index, S/D-form505// Load vector pair, immed pre-index, S/D-form506def : InstRW<[WriteAdr, N1Write_5c_1L, WriteLDHi],507 (instregex "^LDP[SD](pre|post)$")>;508 509// Load vector pair, immed post-index, Q-form510// Load vector pair, immed pre-index, Q-form511def : InstRW<[WriteAdr, N1Write_7c_1L, WriteLDHi],512 (instrs LDPQpost, LDPQpre)>;513 514 515// FP store instructions516// -----------------------------------------------------------------------------517 518// Store vector reg, unscaled immed, B/H/S/D-form519def : InstRW<[N1Write_2c_1I_1L], (instregex "^STUR[BHSD]i$")>;520 521// Store vector reg, unscaled immed, Q-form522def : InstRW<[N1Write_2c_2I_2L], (instrs STURQi)>;523 524// Store vector reg, immed post-index, B/H/S/D-form525// Store vector reg, immed pre-index, B/H/S/D-form526def : InstRW<[WriteAdr, N1Write_2c_1L_1V], (instregex "^STR[BHSD](pre|post)$")>;527 528// Store vector reg, immed pre-index, Q-form529// Store vector reg, immed post-index, Q-form530def : InstRW<[WriteAdr, N1Write_2c_2L_2V], (instrs STRQpre, STRQpost)>;531 532// Store vector reg, unsigned immed, B/H/S/D-form533def : InstRW<[N1Write_2c_1L_1V], (instregex "^STR[BHSD]ui$")>;534 535// Store vector reg, unsigned immed, Q-form536def : InstRW<[N1Write_2c_2L_2V], (instrs STRQui)>;537 538// Store vector reg, register offset, basic, B/S/D-form539// Store vector reg, register offset, scale, B/S/D-form540// Store vector reg, register offset, extend, B/S/D-form541// Store vector reg, register offset, extend, scale, B/S/D-form542def : InstRW<[N1Write_2c_1L_1V, ReadAdrBase], (instregex "^STR[BSD]ro[WX]$")>;543 544// Store vector reg, register offset, basic, H-form545// Store vector reg, register offset, scale, H-form546// Store vector reg, register offset, extend, H-form547// Store vector reg, register offset, extend, scale, H-form548def : InstRW<[N1Write_2c_1I_1L_1V, ReadAdrBase], (instregex "^STRHro[WX]$")>;549 550// Store vector reg, register offset, basic, Q-form551// Store vector reg, register offset, scale, Q-form552// Store vector reg, register offset, extend, Q-form553// Store vector reg, register offset, extend, scale, Q-form554def : InstRW<[N1Write_2c_2L_2V, ReadAdrBase], (instregex "^STRQro[WX]$")>;555 556// Store vector pair, immed offset, S-form557def : InstRW<[N1Write_2c_1L_1V], (instrs STPSi, STNPSi)>;558 559// Store vector pair, immed offset, D-form560def : InstRW<[N1Write_2c_2L_2V], (instrs STPDi, STNPDi)>;561 562// Store vector pair, immed offset, Q-form563def : InstRW<[N1Write_3c_4L_2V], (instrs STPQi, STNPQi)>;564 565// Store vector pair, immed post-index, S-form566// Store vector pair, immed pre-index, S-form567def : InstRW<[WriteAdr, N1Write_2c_1L_1V], (instrs STPSpre, STPSpost)>;568 569// Store vector pair, immed post-index, D-form570// Store vector pair, immed pre-index, D-form571def : InstRW<[WriteAdr, N1Write_2c_2L_2V], (instrs STPDpre, STPDpost)>;572 573// Store vector pair, immed post-index, Q-form574// Store vector pair, immed pre-index, Q-form575def : InstRW<[WriteAdr, N1Write_3c_4L_2V], (instrs STPQpre, STPQpost)>;576 577 578// ASIMD integer instructions579// -----------------------------------------------------------------------------580 581// ASIMD absolute diff582// ASIMD absolute diff long583// ASIMD arith, basic584// ASIMD arith, complex585// ASIMD arith, pair-wise586// ASIMD compare587// ASIMD logical588// ASIMD max/min, basic and pair-wise589def : SchedAlias<WriteVd, N1Write_2c_1V>;590def : SchedAlias<WriteVq, N1Write_2c_1V>;591 592// ASIMD absolute diff accum593// ASIMD absolute diff accum long594def : InstRW<[N1Write_4c_1V1], (instregex "^[SU]ABAL?v")>;595 596// ASIMD arith, reduce, 4H/4S597def : InstRW<[N1Write_3c_1V1], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>;598 599// ASIMD arith, reduce, 8B/8H600def : InstRW<[N1Write_5c_1V1_1V], (instregex "^(ADDV|[SU]ADDLV)v8(i8|i16)v$")>;601 602// ASIMD arith, reduce, 16B603def : InstRW<[N1Write_6c_2V1], (instregex "^(ADDV|[SU]ADDLV)v16i8v$")>;604 605// ASIMD max/min, reduce, 4H/4S606def : InstRW<[N1Write_3c_1V1], (instregex "^[SU](MAX|MIN)Vv4(i16|i32)v$")>;607 608// ASIMD max/min, reduce, 8B/8H609def : InstRW<[N1Write_5c_1V1_1V], (instregex "^[SU](MAX|MIN)Vv8(i8|i16)v$")>;610 611// ASIMD max/min, reduce, 16B612def : InstRW<[N1Write_6c_2V1], (instregex "[SU](MAX|MIN)Vv16i8v$")>;613 614// ASIMD multiply, D-form615// ASIMD multiply accumulate, D-form616// ASIMD multiply accumulate high, D-form617// ASIMD multiply accumulate saturating long618// ASIMD multiply long619// ASIMD multiply accumulate long620def : InstRW<[N1Write_4c_1V0], (instregex "^MUL(v[14]i16|v[12]i32)$",621 "^ML[AS](v[14]i16|v[12]i32)$",622 "^SQ(R)?DMULH(v[14]i16|v[12]i32)$",623 "^SQRDML[AS]H(v[14]i16|v[12]i32)$",624 "^SQDML[AS]Lv",625 "^([SU]|SQD)MULLv",626 "^[SU]ML[AS]Lv")>;627 628// ASIMD multiply, Q-form629// ASIMD multiply accumulate, Q-form630// ASIMD multiply accumulate high, Q-form631def : InstRW<[N1Write_5c_2V0], (instregex "^MUL(v8i16|v4i32)$",632 "^ML[AS](v8i16|v4i32)$",633 "^SQ(R)?DMULH(v8i16|v4i32)$",634 "^SQRDML[AS]H(v8i16|v4i32)$")>;635 636// ASIMD multiply/multiply long (8x8) polynomial, D-form637def : InstRW<[N1Write_3c_1V0], (instrs PMULv8i8, PMULLv8i8)>;638 639// ASIMD multiply/multiply long (8x8) polynomial, Q-form640def : InstRW<[N1Write_4c_2V0], (instrs PMULv16i8, PMULLv16i8)>;641 642// ASIMD pairwise add and accumulate long643def : InstRW<[N1Write_4c_1V1], (instregex "^[SU]ADALPv")>;644 645// ASIMD shift accumulate646def : InstRW<[N1Write_4c_1V1], (instregex "^[SU]R?SRAv")>;647 648// ASIMD shift by immed, basic649// ASIMD shift by immed and insert, basic650// ASIMD shift by register, basic651def : InstRW<[N1Write_2c_1V1], (instregex "^SHLL?v", "^SHRNv", "^[SU]SHLLv",652 "^[SU]SHRv", "^S[LR]Iv", "^[SU]SHLv")>;653 654// ASIMD shift by immed, complex655// ASIMD shift by register, complex656def : InstRW<[N1Write_4c_1V1],657 (instregex "^RSHRNv", "^SQRSHRU?Nv", "^(SQSHLU?|UQSHL)[bhsd]$",658 "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",659 "^SQSHU?RNv", "^[SU]RSHRv", "^UQR?SHRNv", 660 "^[SU]Q?RSHLv", "^[SU]QSHLv")>;661 662 663// ASIMD FP instructions664// -----------------------------------------------------------------------------665 666// ASIMD FP absolute value/difference667// ASIMD FP arith, normal668// ASIMD FP compare669// ASIMD FP max/min, normal670// ASIMD FP max/min, pairwise671// ASIMD FP negate672// Covered by "SchedAlias (WriteV[dq]...)" above673 674// ASIMD FP convert, long (F16 to F32)675def : InstRW<[N1Write_4c_2V0], (instregex "^FCVTL(v4|v8)i16$")>;676 677// ASIMD FP convert, long (F32 to F64)678def : InstRW<[N1Write_3c_1V0], (instregex "^FCVTL(v2|v4)i32$")>;679 680// ASIMD FP convert, narrow (F32 to F16)681def : InstRW<[N1Write_4c_2V0], (instregex "^FCVTN(v4|v8)i16$")>;682 683// ASIMD FP convert, narrow (F64 to F32)684def : InstRW<[N1Write_3c_1V0], (instregex "^FCVTN(v2|v4)i32$",685 "^FCVTXN(v2|v4)f32$")>;686 687// ASIMD FP convert, other, D-form F32 and Q-form F64688def : InstRW<[N1Write_3c_1V0], (instregex "^[FSU]CVT[AMNPZ][SU]v2f(32|64)$",689 "^[SU]CVTFv2f(32|64)$")>;690 691// ASIMD FP convert, other, D-form F16 and Q-form F32692def : InstRW<[N1Write_4c_2V0], (instregex "^[FSU]CVT[AMNPZ][SU]v4f(16|32)$",693 "^[SU]CVTFv4f(16|32)$")>;694 695// ASIMD FP convert, other, Q-form F16696def : InstRW<[N1Write_6c_4V0], (instregex "^[FSU]CVT[AMNPZ][SU]v8f16$",697 "^[SU]CVTFv8f16$")>;698 699// ASIMD FP divide, D-form, F16700// ASIMD FP square root, D-form, F16701def : InstRW<[N1Write_7c7_1V0], (instrs FDIVv4f16, FSQRTv4f16)>;702 703// ASIMD FP divide, D-form, F32704// ASIMD FP square root, D-form, F32705def : InstRW<[N1Write_10c7_1V0], (instrs FDIVv2f32, FSQRTv2f32)>;706 707// ASIMD FP divide, Q-form, F16708// ASIMD FP square root, Q-form, F16709def : InstRW<[N1Write_13c10_1V0], (instrs FDIVv8f16, FSQRTv8f16)>;710 711// ASIMD FP divide, Q-form, F32712// ASIMD FP square root, Q-form, F32713def : InstRW<[N1Write_10c7_1V0], (instrs FDIVv4f32, FSQRTv4f32)>;714 715// ASIMD FP divide, Q-form, F64716def : InstRW<[N1Write_15c7_1V0], (instrs FDIVv2f64)>;717 718// ASIMD FP square root, Q-form, F64719def : InstRW<[N1Write_17c7_1V0], (instrs FSQRTv2f64)>;720 721// ASIMD FP max/min, reduce, F32 and D-form F16722def : InstRW<[N1Write_5c_1V], (instregex "^F(MAX|MIN)(NM)?Vv4(i16|i32)v$")>;723 724// ASIMD FP max/min, reduce, Q-form F16725def : InstRW<[N1Write_8c_3V], (instregex "^F(MAX|MIN)(NM)?Vv8i16v$")>;726 727// ASIMD FP multiply728def : InstRW<[N1Write_3c_1V], (instregex "^FMULX?v")>;729 730// ASIMD FP multiply accumulate731def : InstRW<[N1Write_4c_1V], (instregex "^FML[AS]v")>;732 733// ASIMD FP multiply accumulate long734def : InstRW<[N1Write_5c_1V], (instregex "^FML[AS]L2?v")>;735 736// ASIMD FP round, D-form F32 and Q-form F64737def : InstRW<[N1Write_3c_1V0], (instregex "^FRINT[AIMNPXZ]v2f(32|64)$")>;738 739// ASIMD FP round, D-form F16 and Q-form F32740def : InstRW<[N1Write_4c_2V0], (instregex "^FRINT[AIMNPXZ]v4f(16|32)$")>;741 742// ASIMD FP round, Q-form F16743def : InstRW<[N1Write_6c_4V0], (instregex "^FRINT[AIMNPXZ]v8f16$")>;744 745 746// ASIMD miscellaneous instructions747// -----------------------------------------------------------------------------748 749// ASIMD bit reverse750// ASIMD bitwise insert751// ASIMD count752// ASIMD duplicate, element753// ASIMD extract754// ASIMD extract narrow755// ASIMD insert, element to element756// ASIMD move, FP immed757// ASIMD move, integer immed758// ASIMD reverse759// ASIMD table lookup, 1 or 2 table regs760// ASIMD table lookup extension, 1 table reg761// ASIMD transfer, element to gen reg762// ASIMD transpose763// ASIMD unzip/zip764// Covered by "SchedAlias (WriteV[dq]...)" above765 766// ASIMD duplicate, gen reg767def : InstRW<[N1Write_3c_1M],768 (instregex "^DUP((v16|v8)i8|(v8|v4)i16|(v4|v2)i32|v2i64)gpr$")>;769 770// ASIMD extract narrow, saturating771def : InstRW<[N1Write_4c_1V1], (instregex "^[SU]QXTNv", "^SQXTUNv")>;772 773// ASIMD reciprocal and square root estimate, D-form F32 and F64774def : InstRW<[N1Write_3c_1V0], (instrs FRECPEv1i32, FRECPEv2f32, FRECPEv1i64,775 FRECPXv1i32, FRECPXv1i64,776 URECPEv2i32,777 FRSQRTEv1i32, FRSQRTEv2f32, FRSQRTEv1i64,778 URSQRTEv2i32)>;779 780// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32781def : InstRW<[N1Write_4c_2V0], (instrs FRECPEv1f16, FRECPEv4f16, FRECPEv4f32,782 FRECPXv1f16,783 URECPEv4i32,784 FRSQRTEv1f16, FRSQRTEv4f16, FRSQRTEv4f32,785 URSQRTEv4i32)>;786 787// ASIMD reciprocal and square root estimate, Q-form F16788def : InstRW<[N1Write_6c_4V0], (instrs FRECPEv8f16,789 FRSQRTEv8f16)>;790 791// ASIMD reciprocal step792def : InstRW<[N1Write_4c_1V], (instregex "^FRECPS(16|32|64)$", "^FRECPSv",793 "^FRSQRTS(16|32|64)$", "^FRSQRTSv")>;794 795// ASIMD table lookup, 3 table regs796// ASIMD table lookup extension, 2 table reg797def : InstRW<[N1Write_4c_4V], (instrs TBLv8i8Three, TBLv16i8Three,798 TBXv8i8Two, TBXv16i8Two)>;799 800// ASIMD table lookup, 4 table regs801def : InstRW<[N1Write_4c_3V], (instrs TBLv8i8Four, TBLv16i8Four)>;802 803// ASIMD table lookup extension, 3 table reg804def : InstRW<[N1Write_6c_3V], (instrs TBXv8i8Three, TBXv16i8Three)>;805 806// ASIMD table lookup extension, 4 table reg807def : InstRW<[N1Write_6c_5V], (instrs TBXv8i8Four, TBXv16i8Four)>;808 809// ASIMD transfer, element to gen reg810def : InstRW<[N1Write_2c_1V1], (instregex "^SMOVvi(((8|16)to(32|64))|32to64)$",811 "^UMOVvi(8|16|32|64)$")>;812 813// ASIMD transfer, gen reg to element814def : InstRW<[N1Write_5c_1M_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;815 816 817// ASIMD load instructions818// -----------------------------------------------------------------------------819 820// ASIMD load, 1 element, multiple, 1 reg821def : InstRW<[N1Write_5c_1L],822 (instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;823def : InstRW<[WriteAdr, N1Write_5c_1L],824 (instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;825 826// ASIMD load, 1 element, multiple, 2 reg827def : InstRW<[N1Write_5c_2L],828 (instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;829def : InstRW<[WriteAdr, N1Write_5c_2L],830 (instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;831 832// ASIMD load, 1 element, multiple, 3 reg833def : InstRW<[N1Write_6c_3L],834 (instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;835def : InstRW<[WriteAdr, N1Write_6c_3L],836 (instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;837 838// ASIMD load, 1 element, multiple, 4 reg839def : InstRW<[N1Write_6c_4L],840 (instregex "^LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;841def : InstRW<[WriteAdr, N1Write_6c_4L],842 (instregex "^LD1Fourv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;843 844// ASIMD load, 1 element, one lane845// ASIMD load, 1 element, all lanes846def : InstRW<[N1Write_7c_1L_1V],847 (instregex "LD1(i|Rv)(8|16|32|64)$",848 "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;849def : InstRW<[WriteAdr, N1Write_7c_1L_1V],850 (instregex "LD1i(8|16|32|64)_POST$",851 "LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;852 853// ASIMD load, 2 element, multiple854// ASIMD load, 2 element, one lane855// ASIMD load, 2 element, all lanes856def : InstRW<[N1Write_7c_2L_2V],857 (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)$",858 "LD2i(8|16|32|64)$",859 "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;860def : InstRW<[WriteAdr, N1Write_7c_2L_2V],861 (instregex "LD2Twov(8b|16b|4h|8h|2s|4s|2d)_POST$",862 "LD2i(8|16|32|64)_POST$",863 "LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;864 865// ASIMD load, 3 element, multiple866def : InstRW<[N1Write_8c_3L_3V],867 (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)$")>;868def : InstRW<[WriteAdr, N1Write_8c_3L_3V],869 (instregex "LD3Threev(8b|16b|4h|8h|2s|4s|2d)_POST$")>;870 871// ASIMD load, 3 element, one lane872// ASIMD load, 3 element, all lanes873def : InstRW<[N1Write_7c_2L_3V],874 (instregex "LD3i(8|16|32|64)$",875 "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;876def : InstRW<[WriteAdr, N1Write_7c_2L_3V],877 (instregex "LD3i(8|16|32|64)_POST$",878 "LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;879 880// ASIMD load, 4 element, multiple, D-form881def : InstRW<[N1Write_8c_3L_4V],882 (instregex "LD4Fourv(8b|4h|2s)$")>;883def : InstRW<[WriteAdr, N1Write_8c_3L_4V],884 (instregex "LD4Fourv(8b|4h|2s)_POST$")>;885 886// ASIMD load, 4 element, multiple, Q-form887def : InstRW<[N1Write_10c_4L_4V],888 (instregex "LD4Fourv(16b|8h|4s|2d)$")>;889def : InstRW<[WriteAdr, N1Write_10c_4L_4V],890 (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;891 892// ASIMD load, 4 element, one lane893// ASIMD load, 4 element, all lanes894def : InstRW<[N1Write_8c_4L_4V],895 (instregex "LD4i(8|16|32|64)$",896 "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;897def : InstRW<[WriteAdr, N1Write_8c_4L_4V],898 (instregex "LD4i(8|16|32|64)_POST$",899 "LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;900 901 902// ASIMD store instructions903// -----------------------------------------------------------------------------904 905// ASIMD store, 1 element, multiple, 1 reg, D-form906def : InstRW<[N1Write_2c_1L_1V],907 (instregex "ST1Onev(8b|4h|2s|1d)$")>;908def : InstRW<[WriteAdr, N1Write_2c_1L_1V],909 (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;910 911// ASIMD store, 1 element, multiple, 1 reg, Q-form912def : InstRW<[N1Write_2c_1L_1V],913 (instregex "ST1Onev(16b|8h|4s|2d)$")>;914def : InstRW<[WriteAdr, N1Write_2c_1L_1V],915 (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;916 917// ASIMD store, 1 element, multiple, 2 reg, D-form918def : InstRW<[N1Write_2c_1L_2V],919 (instregex "ST1Twov(8b|4h|2s|1d)$")>;920def : InstRW<[WriteAdr, N1Write_2c_1L_2V],921 (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;922 923// ASIMD store, 1 element, multiple, 2 reg, Q-form924def : InstRW<[N1Write_3c_2L_2V],925 (instregex "ST1Twov(16b|8h|4s|2d)$")>;926def : InstRW<[WriteAdr, N1Write_3c_2L_2V],927 (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;928 929// ASIMD store, 1 element, multiple, 3 reg, D-form930def : InstRW<[N1Write_3c_2L_3V], 931 (instregex "ST1Threev(8b|4h|2s|1d)$")>;932def : InstRW<[WriteAdr, N1Write_3c_2L_3V],933 (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;934 935// ASIMD store, 1 element, multiple, 3 reg, Q-form936def : InstRW<[N1Write_4c_3L_3V],937 (instregex "ST1Threev(16b|8h|4s|2d)$")>;938def : InstRW<[WriteAdr, N1Write_4c_3L_3V],939 (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;940 941// ASIMD store, 1 element, multiple, 4 reg, D-form942def : InstRW<[N1Write_3c_2L_2V],943 (instregex "ST1Fourv(8b|4h|2s|1d)$")>;944def : InstRW<[WriteAdr, N1Write_3c_2L_2V],945 (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;946 947// ASIMD store, 1 element, multiple, 4 reg, Q-form948def : InstRW<[N1Write_5c_4L_4V],949 (instregex "ST1Fourv(16b|8h|4s|2d)$")>;950def : InstRW<[WriteAdr, N1Write_5c_4L_4V],951 (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;952 953// ASIMD store, 1 element, one lane954def : InstRW<[N1Write_4c_1L_1V],955 (instregex "ST1i(8|16|32|64)$")>;956def : InstRW<[WriteAdr, N1Write_4c_1L_1V],957 (instregex "ST1i(8|16|32|64)_POST$")>;958 959// ASIMD store, 2 element, multiple, D-form, B/H/S960def : InstRW<[N1Write_4c_1L_1V],961 (instregex "ST2Twov(8b|4h|2s)$")>;962def : InstRW<[WriteAdr, N1Write_4c_1L_1V],963 (instregex "ST2Twov(8b|4h|2s)_POST$")>;964 965// ASIMD store, 2 element, multiple, Q-form966def : InstRW<[N1Write_5c_2L_2V],967 (instregex "ST2Twov(16b|8h|4s|2d)$")>;968def : InstRW<[WriteAdr, N1Write_5c_2L_2V],969 (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;970 971// ASIMD store, 2 element, one lane972def : InstRW<[N1Write_4c_1L_1V],973 (instregex "ST2i(8|16|32|64)$")>;974def : InstRW<[WriteAdr, N1Write_4c_1L_1V],975 (instregex "ST2i(8|16|32|64)_POST$")>;976 977// ASIMD store, 3 element, multiple, D-form, B/H/S978def : InstRW<[N1Write_5c_2L_2V],979 (instregex "ST3Threev(8b|4h|2s)$")>;980def : InstRW<[WriteAdr, N1Write_5c_2L_2V],981 (instregex "ST3Threev(8b|4h|2s)_POST$")>;982 983// ASIMD store, 3 element, multiple, Q-form984def : InstRW<[N1Write_6c_3L_3V],985 (instregex "ST3Threev(16b|8h|4s|2d)$")>;986def : InstRW<[WriteAdr, N1Write_6c_3L_3V],987 (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;988 989// ASIMD store, 3 element, one lane, B/H/S990def : InstRW<[N1Write_4c_3L_3V],991 (instregex "ST3i(8|16|32)$")>;992def : InstRW<[WriteAdr, N1Write_4c_3L_3V],993 (instregex "ST3i(8|16|32)_POST$")>;994 995// ASIMD store, 3 element, one lane, D996def : InstRW<[N1Write_5c_3L_3V],997 (instrs ST3i64)>;998def : InstRW<[WriteAdr, N1Write_5c_3L_3V],999 (instrs ST3i64_POST)>;1000 1001// ASIMD store, 4 element, multiple, D-form, B/H/S1002def : InstRW<[N1Write_7c_3L_3V],1003 (instregex "ST4Fourv(8b|4h|2s)$")>;1004def : InstRW<[WriteAdr, N1Write_7c_3L_3V],1005 (instregex "ST4Fourv(8b|4h|2s)_POST$")>;1006 1007// ASIMD store, 4 element, multiple, Q-form, B/H/S1008def : InstRW<[N1Write_9c_6L_6V],1009 (instregex "ST4Fourv(16b|8h|4s)$")>;1010def : InstRW<[WriteAdr, N1Write_9c_6L_6V],1011 (instregex "ST4Fourv(16b|8h|4s)_POST$")>;1012 1013// ASIMD store, 4 element, multiple, Q-form, D1014def : InstRW<[N1Write_6c_4L_4V],1015 (instrs ST4Fourv2d)>;1016def : InstRW<[WriteAdr, N1Write_6c_4L_4V],1017 (instrs ST4Fourv2d_POST)>;1018 1019// ASIMD store, 4 element, one lane, B/H/S1020def : InstRW<[N1Write_5c_3L_3V],1021 (instregex "ST4i(8|16|32)$")>;1022def : InstRW<[WriteAdr, N1Write_5c_3L_3V],1023 (instregex "ST4i(8|16|32)_POST$")>;1024 1025// ASIMD store, 4 element, one lane, D1026def : InstRW<[N1Write_4c_3L_3V],1027 (instrs ST4i64)>;1028def : InstRW<[WriteAdr, N1Write_4c_3L_3V],1029 (instrs ST4i64_POST)>;1030 1031 1032// Cryptography extensions1033// -----------------------------------------------------------------------------1034 1035// Crypto AES ops1036def N1WriteVC : WriteSequence<[N1Write_2c_1V0]>;1037def N1ReadVC : SchedReadAdvance<2, [N1WriteVC]>;1038def : InstRW<[N1WriteVC], (instrs AESDrr, AESErr)>;1039def : InstRW<[N1Write_2c_1V0, N1ReadVC], (instrs AESMCrr, AESIMCrr)>;1040 1041// Crypto polynomial (64x64) multiply long1042// Crypto SHA1 hash acceleration op1043// Crypto SHA1 schedule acceleration ops1044// Crypto SHA256 schedule acceleration ops1045def : InstRW<[N1Write_2c_1V0], (instregex "^PMULLv[12]i64$",1046 "^SHA1(H|SU0|SU1)rr",1047 "^SHA256SU[01]rr")>;1048 1049// Crypto SHA1 hash acceleration ops1050// Crypto SHA256 hash acceleration ops1051def : InstRW<[N1Write_4c_1V0], (instregex "^SHA1[CMP]rrr$",1052 "^SHA256H2?rrr$")>;1053 1054 1055// CRC1056// -----------------------------------------------------------------------------1057 1058// CRC checksum ops1059def : InstRW<[N1Write_2c_1M], (instregex "^CRC32C?[BHWX]rr$")>;1060 1061 1062}1063