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1//=- AArch64SchedNeoverseN2.td - NeoverseN2 Scheduling Defs --*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the scheduling model for the Arm Neoverse N2 processors.10//11//===----------------------------------------------------------------------===//12 13def NeoverseN2Model : SchedMachineModel {14 let IssueWidth = 5; // Micro-ops dispatched at a time.15 let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer.16 let LoadLatency = 4; // Optimistic load latency.17 let MispredictPenalty = 10; // Extra cycles for mispredicted branch.18 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.19 let CompleteModel = 1;20 21 list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,22 [HasSVE2p1, HasSVEB16B16, HasPAuthLR, HasCPA, HasCSSC]);23}24 25//===----------------------------------------------------------------------===//26// Define each kind of processor resource and number available on Neoverse N2.27// Instructions are first fetched and then decoded into internal macro-ops28// (MOPs). From there, the MOPs proceed through register renaming and dispatch29// stages. A MOP can be split into two micro-ops further down the pipeline30// after the decode stage. Once dispatched, micro-ops wait for their operands31// and issue out-of-order to one of thirteen issue pipelines. Each issue32// pipeline can accept one micro-op per cycle.33 34let SchedModel = NeoverseN2Model in {35 36// Define the (13) issue ports.37def N2UnitB : ProcResource<2>; // Branch 0/138def N2UnitS : ProcResource<2>; // Integer single Cycle 0/139def N2UnitM0 : ProcResource<1>; // Integer multicycle 040def N2UnitM1 : ProcResource<1>; // Integer multicycle 141def N2UnitL01 : ProcResource<2>; // Load/Store 0/142def N2UnitL2 : ProcResource<1>; // Load 243def N2UnitD : ProcResource<2>; // Store data 0/144def N2UnitV0 : ProcResource<1>; // FP/ASIMD 045def N2UnitV1 : ProcResource<1>; // FP/ASIMD 146 47def N2UnitV : ProcResGroup<[N2UnitV0, N2UnitV1]>; // FP/ASIMD 0/148def N2UnitM : ProcResGroup<[N2UnitM0, N2UnitM1]>; // Integer single/multicycle 0/149def N2UnitL : ProcResGroup<[N2UnitL01, N2UnitL2]>; // Load/Store 0/1 and Load 250def N2UnitI : ProcResGroup<[N2UnitS, N2UnitM0, N2UnitM1]>; // Integer single cycle 0/1 and single/multicycle 0/151 52// Define commonly used read types.53 54// No forwarding is provided for these types.55def : ReadAdvance<ReadI, 0>;56def : ReadAdvance<ReadISReg, 0>;57def : ReadAdvance<ReadIEReg, 0>;58def : ReadAdvance<ReadIM, 0>;59def : ReadAdvance<ReadIMA, 0>;60def : ReadAdvance<ReadID, 0>;61def : ReadAdvance<ReadExtrHi, 0>;62def : ReadAdvance<ReadAdrBase, 0>;63def : ReadAdvance<ReadST, 0>;64def : ReadAdvance<ReadVLD, 0>;65 66def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }67def : WriteRes<WriteBarrier, []> { let Latency = 1; }68def : WriteRes<WriteHint, []> { let Latency = 1; }69def : WriteRes<WriteLDHi, []> { let Latency = 4; }70 71//===----------------------------------------------------------------------===//72// Define customized scheduler read/write types specific to the Neoverse N2.73 74//===----------------------------------------------------------------------===//75 76// Define generic 0 micro-op types77def N2Write_0c : SchedWriteRes<[]> { let Latency = 0; }78 79// Define generic 1 micro-op types80 81def N2Write_1c_1B : SchedWriteRes<[N2UnitB]> { let Latency = 1; }82def N2Write_1c_1I : SchedWriteRes<[N2UnitI]> { let Latency = 1; }83def N2Write_1c_1M : SchedWriteRes<[N2UnitM]> { let Latency = 1; }84def N2Write_1c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 1; }85def N2Write_1c_1L01 : SchedWriteRes<[N2UnitL01]> { let Latency = 1; }86def N2Write_2c_1M : SchedWriteRes<[N2UnitM]> { let Latency = 2; }87def N2Write_3c_1M : SchedWriteRes<[N2UnitM]> { let Latency = 3; }88def N2Write_2c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 2;89 let ReleaseAtCycles = [2]; }90def N2Write_3c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 3;91 let ReleaseAtCycles = [3]; }92def N2Write_5c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 5;93 let ReleaseAtCycles = [5]; }94def N2Write_12c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 12;95 let ReleaseAtCycles = [12]; }96def N2Write_20c_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 20;97 let ReleaseAtCycles = [20]; }98def N2Write_4c_1L : SchedWriteRes<[N2UnitL]> { let Latency = 4; }99def N2Write_6c_1L : SchedWriteRes<[N2UnitL]> { let Latency = 6; }100def N2Write_2c_1V : SchedWriteRes<[N2UnitV]> { let Latency = 2; }101def N2Write_3c_1V : SchedWriteRes<[N2UnitV]> { let Latency = 3; }102def N2Write_4c_1V : SchedWriteRes<[N2UnitV]> { let Latency = 4; }103def N2Write_5c_1V : SchedWriteRes<[N2UnitV]> { let Latency = 5; }104def N2Write_12c_1V : SchedWriteRes<[N2UnitV]> { let Latency = 12; }105def N2Write_2c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 2; }106def N2Write_3c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 3; }107def N2Write_4c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 4; }108def N2Write_7c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 7;109 let ReleaseAtCycles = [7]; }110def N2Write_9c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 9; }111def N2Write_10c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 10; }112def N2Write_12c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 12; }113def N2Write_13c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 13; }114def N2Write_15c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 15; }115def N2Write_16c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 16; }116def N2Write_20c_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 20; }117def N2Write_2c_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 2; }118def N2Write_3c_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 3; }119def N2Write_4c_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 4; }120def N2Write_6c_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 6; }121def N2Write_10c_1V1 : SchedWriteRes<[N2UnitV1]> { let Latency = 10; }122def N2Write_6c_1L01 : SchedWriteRes<[N2UnitL01]> { let Latency = 6; }123 124//===----------------------------------------------------------------------===//125// Define generic 2 micro-op types126 127def N2Write_1c_1B_1S : SchedWriteRes<[N2UnitB, N2UnitS]> {128 let Latency = 1;129 let NumMicroOps = 2;130}131 132def N2Write_6c_1M0_1B : SchedWriteRes<[N2UnitM0, N2UnitB]> {133 let Latency = 6;134 let NumMicroOps = 2;135}136 137def N2Write_9c_1M0_1L : SchedWriteRes<[N2UnitM0, N2UnitL]> {138 let Latency = 9;139 let NumMicroOps = 2;140}141 142def N2Write_3c_1I_1M : SchedWriteRes<[N2UnitI, N2UnitM]> {143 let Latency = 3;144 let NumMicroOps = 2;145}146 147def N2Write_4c_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {148 let Latency = 4;149 let NumMicroOps = 2;150}151 152def N2Write_5c_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {153 let Latency = 5;154 let NumMicroOps = 2;155}156 157def N2Write_6c_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {158 let Latency = 6;159 let NumMicroOps = 2;160}161 162def N2Write_7c_1I_1L : SchedWriteRes<[N2UnitI, N2UnitL]> {163 let Latency = 7;164 let NumMicroOps = 2;165}166 167def N2Write_1c_1L01_1D : SchedWriteRes<[N2UnitL01, N2UnitD]> {168 let Latency = 1;169 let NumMicroOps = 2;170}171 172def N2Write_5c_1M0_1V : SchedWriteRes<[N2UnitM0, N2UnitV]> {173 let Latency = 5;174 let NumMicroOps = 2;175}176 177def N2Write_2c_1L01_1V : SchedWriteRes<[N2UnitL01, N2UnitV]> {178 let Latency = 2;179 let NumMicroOps = 2;180}181 182def N2Write_4c_1V1_1V : SchedWriteRes<[N2UnitV1, N2UnitV]> {183 let Latency = 4;184 let NumMicroOps = 2;185}186 187def N2Write_4c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {188 let Latency = 4;189 let NumMicroOps = 2;190}191 192def N2Write_10c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {193 let Latency = 10;194 let NumMicroOps = 2;195 let ReleaseAtCycles = [5, 5];196}197 198def N2Write_13c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {199 let Latency = 13;200 let NumMicroOps = 2;201 let ReleaseAtCycles = [6, 7];202}203 204def N2Write_15c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {205 let Latency = 15;206 let NumMicroOps = 2;207 let ReleaseAtCycles = [7, 8];208}209 210def N2Write_16c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {211 let Latency = 16;212 let NumMicroOps = 2;213 let ReleaseAtCycles = [8, 8];214}215 216def N2Write_4c_2V : SchedWriteRes<[N2UnitV, N2UnitV]> {217 let Latency = 4;218 let NumMicroOps = 2;219}220 221def N2Write_6c_2V : SchedWriteRes<[N2UnitV, N2UnitV]> {222 let Latency = 6;223 let NumMicroOps = 2;224}225 226def N2Write_6c_2L : SchedWriteRes<[N2UnitL, N2UnitL]> {227 let Latency = 6;228 let NumMicroOps = 2;229}230 231def N2Write_8c_1L_1V : SchedWriteRes<[N2UnitL, N2UnitV]> {232 let Latency = 8;233 let NumMicroOps = 2;234}235 236def N2Write_4c_1L01_1V : SchedWriteRes<[N2UnitL01, N2UnitV]> {237 let Latency = 4;238 let NumMicroOps = 2;239}240 241def N2Write_3c_1M0_1M : SchedWriteRes<[N2UnitM0, N2UnitM]> {242 let Latency = 3;243 let NumMicroOps = 2;244}245 246def N2Write_2c_1M0_1M : SchedWriteRes<[N2UnitM0, N2UnitM]> {247 let Latency = 2;248 let NumMicroOps = 2;249}250 251def N2Write_6c_2V1 : SchedWriteRes<[N2UnitV1, N2UnitV1]> {252 let Latency = 6;253 let NumMicroOps = 2;254}255 256def N2Write_4c_1V0_1M : SchedWriteRes<[N2UnitV0, N2UnitM]> {257 let Latency = 4;258 let NumMicroOps = 2;259}260 261def N2Write_5c_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {262 let Latency = 5;263 let NumMicroOps = 2;264}265 266def N2Write_5c_1V1_1M0 : SchedWriteRes<[N2UnitV1, N2UnitM0]> {267 let Latency = 5;268 let NumMicroOps = 2;269}270 271def N2Write_7c_1M0_1V0 : SchedWriteRes<[N2UnitM0, N2UnitV0]> {272 let Latency = 7;273 let NumMicroOps = 2;274}275 276def N2Write_2c_1V0_1M : SchedWriteRes<[N2UnitV0, N2UnitM]> {277 let Latency = 2;278 let NumMicroOps = 2;279}280 281def N2Write_6c_1V_1V1 : SchedWriteRes<[N2UnitV, N2UnitV1]> {282 let Latency = 6;283 let NumMicroOps = 2;284}285 286def N2Write_6c_1L_1M : SchedWriteRes<[N2UnitL, N2UnitM]> {287 let Latency = 6;288 let NumMicroOps = 2;289}290 291def N2Write_6c_1L_1S : SchedWriteRes<[N2UnitL, N2UnitS]> {292 let Latency = 6;293 let NumMicroOps = 2;294}295 296def N2Write_9c_1L_1V : SchedWriteRes<[N2UnitL, N2UnitV]> {297 let Latency = 9;298 let NumMicroOps = 2;299}300 301def N2Write_4c_2V1 : SchedWriteRes<[N2UnitV1, N2UnitV1]> {302 let Latency = 4;303 let NumMicroOps = 2;304}305 306//===----------------------------------------------------------------------===//307// Define generic 3 micro-op types308 309def N2Write_1c_1L01_1D_1I : SchedWriteRes<[N2UnitL01, N2UnitD, N2UnitI]> {310 let Latency = 1;311 let NumMicroOps = 3;312}313 314def N2Write_2c_1L01_1V_1I : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitI]> {315 let Latency = 2;316 let NumMicroOps = 3;317}318 319def N2Write_2c_1L01_2V : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitV]> {320 let Latency = 2;321 let NumMicroOps = 3;322}323 324def N2Write_7c_1M_1M0_1V : SchedWriteRes<[N2UnitM, N2UnitM0, N2UnitV]> {325 let Latency = 7;326 let NumMicroOps = 3;327}328 329def N2Write_8c_1M0_1V1_1V : SchedWriteRes<[N2UnitM0, N2UnitV1, N2UnitV]> {330 let Latency = 8;331 let NumMicroOps = 3;332}333 334def N2Write_10c_1V_1L_1S : SchedWriteRes<[N2UnitV, N2UnitL, N2UnitL]> {335 let Latency = 10;336 let NumMicroOps = 3;337}338 339def N2Write_2c_1L01_1S_1V : SchedWriteRes<[N2UnitL01, N2UnitS, N2UnitV]> {340 let Latency = 2;341 let NumMicroOps = 3;342}343 344def N2Write_4c_1L01_1S_1V : SchedWriteRes<[N2UnitL01, N2UnitS, N2UnitV]> {345 let Latency = 4;346 let NumMicroOps = 3;347}348 349def N2Write_6c_3L : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL]> {350 let Latency = 6;351 let NumMicroOps = 3;352}353 354def N2Write_8c_1L_2V : SchedWriteRes<[N2UnitL, N2UnitV, N2UnitV]> {355 let Latency = 8;356 let NumMicroOps = 3;357}358 359//===----------------------------------------------------------------------===//360// Define generic 4 micro-op types361 362def N2Write_2c_1L01_2V_1I : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitV,363 N2UnitI]> {364 let Latency = 2;365 let NumMicroOps = 4;366}367 368def N2Write_6c_4V0 : SchedWriteRes<[N2UnitV0, N2UnitV0, N2UnitV0, N2UnitV0]> {369 let Latency = 6;370 let NumMicroOps = 4;371}372 373def N2Write_4c_4V : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {374 let Latency = 4;375 let NumMicroOps = 4;376}377 378def N2Write_6c_4V : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {379 let Latency = 6;380 let NumMicroOps = 4;381}382 383def N2Write_8c_2L_2V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV]> {384 let Latency = 8;385 let NumMicroOps = 4;386}387 388def N2Write_9c_2L_2V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV]> {389 let Latency = 9;390 let NumMicroOps = 4;391}392 393def N2Write_2c_2L01_2V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitV,394 N2UnitV]> {395 let Latency = 2;396 let NumMicroOps = 4;397}398 399def N2Write_4c_2L01_2V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitV,400 N2UnitV]> {401 let Latency = 4;402 let NumMicroOps = 4;403}404 405def N2Write_5c_2L01_2V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitV,406 N2UnitV]> {407 let Latency = 5;408 let NumMicroOps = 4;409}410 411def N2Write_8c_2M0_2V0 : SchedWriteRes<[N2UnitM0, N2UnitM0, N2UnitV0,412 N2UnitV0]> {413 let Latency = 8;414 let NumMicroOps = 4;415}416 417def N2Write_11c_2V_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,418 N2UnitV1]> {419 let Latency = 11;420 let NumMicroOps = 4;421}422 423def N2Write_9c_2V_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,424 N2UnitV1]> {425 let Latency = 9;426 let NumMicroOps = 4;427}428 429def N2Write_8c_2V_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,430 N2UnitV1]> {431 let Latency = 8;432 let NumMicroOps = 4;433}434 435def N2Write_10c_2L_2V1 : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV1,436 N2UnitV1]> {437 let Latency = 10;438 let NumMicroOps = 4;439}440 441def N2Write_10c_2L_2V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV]> {442 let Latency = 10;443 let NumMicroOps = 4;444}445 446def N2Write_4c_2M0_2M : SchedWriteRes<[N2UnitM0, N2UnitM0, N2UnitM,447 N2UnitM]> {448 let Latency = 4;449 let NumMicroOps = 4;450}451 452def N2Write_6c_2I_2L : SchedWriteRes<[N2UnitI, N2UnitI, N2UnitL, N2UnitL]> {453 let Latency = 6;454 let NumMicroOps = 4;455}456 457def N2Write_7c_4L : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL]> {458 let Latency = 7;459 let NumMicroOps = 4;460}461 462//===----------------------------------------------------------------------===//463// Define generic 5 micro-op types464 465def N2Write_2c_1L01_2V_2I : SchedWriteRes<[N2UnitL01, N2UnitV, N2UnitV,466 N2UnitI, N2UnitI]> {467 let Latency = 2;468 let NumMicroOps = 5;469}470 471def N2Write_8c_2L_3V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV,472 N2UnitV]> {473 let Latency = 8;474 let NumMicroOps = 5;475}476 477//===----------------------------------------------------------------------===//478// Define generic 6 micro-op types479 480def N2Write_8c_3L_3V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL,481 N2UnitV, N2UnitV, N2UnitV]> {482 let Latency = 8;483 let NumMicroOps = 6;484}485 486def N2Write_2c_3L01_3V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,487 N2UnitV, N2UnitV, N2UnitV]> {488 let Latency = 2;489 let NumMicroOps = 6;490}491 492def N2Write_6c_3L01_3V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,493 N2UnitV, N2UnitV, N2UnitV]> {494 let Latency = 6;495 let NumMicroOps = 6;496}497 498def N2Write_4c_3L01_3V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,499 N2UnitV, N2UnitV, N2UnitV]> {500 let Latency = 4;501 let NumMicroOps = 6;502}503 504def N2Write_10c_2L_2V_2S : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitV, N2UnitV,505 N2UnitS, N2UnitS]> {506 let Latency = 10;507 let NumMicroOps = 6;508}509 510//===----------------------------------------------------------------------===//511// Define generic 7 micro-op types512 513def N2Write_8c_3L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL,514 N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {515 let Latency = 8;516 let NumMicroOps = 7;517}518 519def N2Write_7c_7V0 : SchedWriteRes<[N2UnitV0]> {520 let Latency = 7;521 let NumMicroOps = 7;522 let ReleaseAtCycles = [7];523}524 525//===----------------------------------------------------------------------===//526// Define generic 8 micro-op types527 528def N2Write_6c_8V : SchedWriteRes<[N2UnitV, N2UnitV, N2UnitV, N2UnitV,529 N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {530 let Latency = 6;531 let NumMicroOps = 8;532}533 534def N2Write_2c_4L01_4V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,535 N2UnitL01, N2UnitV, N2UnitV, N2UnitV,536 N2UnitV]> {537 let Latency = 2;538 let NumMicroOps = 8;539}540 541def N2Write_5c_4L01_4V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,542 N2UnitL01, N2UnitV, N2UnitV, N2UnitV,543 N2UnitV]> {544 let Latency = 5;545 let NumMicroOps = 8;546}547 548def N2Write_8c_4L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL,549 N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {550 let Latency = 8;551 let NumMicroOps = 8;552}553 554def N2Write_9c_4L_4V : SchedWriteRes<[N2UnitL, N2UnitL, N2UnitL, N2UnitL,555 N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {556 let Latency = 9;557 let NumMicroOps = 8;558}559 560//===----------------------------------------------------------------------===//561// Define generic 9 micro-op types562 563def N2Write_9c_9V0 : SchedWriteRes<[N2UnitV0]> {564 let Latency = 9;565 let NumMicroOps = 9;566 let ReleaseAtCycles = [9];567}568 569//===----------------------------------------------------------------------===//570// Define generic 10 micro-op types571 572def N2Write_7c_5L01_5V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,573 N2UnitL01, N2UnitL01, N2UnitV,574 N2UnitV, N2UnitV, N2UnitV, N2UnitV]> {575 let Latency = 7;576 let NumMicroOps = 10;577}578 579def N2Write_10c_10V0 : SchedWriteRes<[N2UnitV0]> {580 let Latency = 10;581 let NumMicroOps = 10;582 let ReleaseAtCycles = [10];583}584 585//===----------------------------------------------------------------------===//586// Define generic 12 micro-op types587 588def N2Write_7c_6L01_6V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,589 N2UnitL01, N2UnitL01, N2UnitL01,590 N2UnitV, N2UnitV, N2UnitV, N2UnitV,591 N2UnitV, N2UnitV]> {592 let Latency = 7;593 let NumMicroOps = 12;594}595 596//===----------------------------------------------------------------------===//597// Define generic 15 micro-op types598 599def N2Write_7c_5L01_5S_5V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,600 N2UnitL01, N2UnitL01, N2UnitS,601 N2UnitS, N2UnitS, N2UnitS,602 N2UnitS, N2UnitV, N2UnitV,603 N2UnitV, N2UnitV, N2UnitV]> {604 let Latency = 7;605 let NumMicroOps = 15;606}607 608def N2Write_15c_15V0 : SchedWriteRes<[N2UnitV0]> {609 let Latency = 15;610 let NumMicroOps = 15;611 let ReleaseAtCycles = [15];612}613 614//===----------------------------------------------------------------------===//615// Define generic 16 micro-op types616 617def N2Write_16c_16V0 : SchedWriteRes<[N2UnitV0]> {618 let Latency = 16;619 let NumMicroOps = 16;620 let ReleaseAtCycles = [16];621}622 623//===----------------------------------------------------------------------===//624// Define generic 18 micro-op types625 626def N2Write_11c_9L01_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,627 N2UnitL01, N2UnitL01, N2UnitL01,628 N2UnitL01, N2UnitL01, N2UnitL01,629 N2UnitV, N2UnitV, N2UnitV,630 N2UnitV, N2UnitV, N2UnitV,631 N2UnitV, N2UnitV, N2UnitV]> {632 let Latency = 11;633 let NumMicroOps = 18;634}635 636//===----------------------------------------------------------------------===//637// Define generic 27 micro-op types638 639def N2Write_11c_9L01_9S_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,640 N2UnitL01, N2UnitL01, N2UnitL01,641 N2UnitL01, N2UnitL01, N2UnitL01,642 N2UnitS, N2UnitS, N2UnitS,643 N2UnitS, N2UnitS, N2UnitS,644 N2UnitS, N2UnitS, N2UnitS,645 N2UnitV, N2UnitV, N2UnitV,646 N2UnitV, N2UnitV, N2UnitV,647 N2UnitV, N2UnitV, N2UnitV]> {648 let Latency = 11;649 let NumMicroOps = 27;650}651 652//===----------------------------------------------------------------------===//653// Define predicate-controlled types654 655def N2Write_0or1c_1I : SchedWriteVariant<[656 SchedVar<NeoverseZeroMove, [N2Write_0c]>,657 SchedVar<NoSchedPred, [N2Write_1c_1I]>]>;658 659def N2Write_0or2c_1V : SchedWriteVariant<[660 SchedVar<NeoverseZeroMove, [N2Write_0c]>,661 SchedVar<NoSchedPred, [N2Write_2c_1V]>]>;662 663def N2Write_0or3c_1M0 : SchedWriteVariant<[664 SchedVar<NeoverseZeroMove, [N2Write_0c]>,665 SchedVar<NoSchedPred, [N2Write_3c_1M0]>]>;666 667//===----------------------------------------------------------------------===//668// Define types for arithmetic and logical ops with short shifts669def N2Write_Arith : SchedWriteVariant<[670 SchedVar<IsCheapLSL, [N2Write_1c_1I]>,671 SchedVar<NoSchedPred, [N2Write_2c_1M]>]>;672 673def N2Write_Logical: SchedWriteVariant<[674 SchedVar<NeoverseNoLSL, [N2Write_1c_1I]>,675 SchedVar<NoSchedPred, [N2Write_2c_1M]>]>;676 677// Miscellaneous678// -----------------------------------------------------------------------------679 680def : InstRW<[WriteI], (instrs COPY)>;681 682// Branch Instructions683// -----------------------------------------------------------------------------684 685// Branch, immed686// Compare and branch687def : SchedAlias<WriteBr, N2Write_1c_1B>;688 689// Branch, register690def : SchedAlias<WriteBrReg, N2Write_1c_1B>;691 692// Branch and link, immed693// Branch and link, register694def : InstRW<[N2Write_1c_1B_1S], (instrs BL, BLR)>;695 696// Arithmetic and Logical Instructions697// -----------------------------------------------------------------------------698 699// ALU, basic700// ALU, basic, flagset701def : SchedAlias<WriteI, N2Write_1c_1I>;702def : InstRW<[N2Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>;703 704// ALU, extend and shift705def : SchedAlias<WriteIEReg, N2Write_2c_1M>;706 707// Arithmetic, LSL shift, shift <= 4708// Arithmetic, flagset, LSL shift, shift <= 4709// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4710def : SchedAlias<WriteISReg, N2Write_Arith>;711 712// Logical, shift, no flagset713def : InstRW<[N2Write_1c_1I],714 (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;715def : InstRW<[N2Write_0or1c_1I], (instregex "^ORR[WX]rs$")>;716 717// Logical, shift, flagset718def : InstRW<[N2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;719 720// Arithmetic, immediate to logical address tag721def : InstRW<[N2Write_2c_1M], (instrs ADDG, SUBG)>;722 723// Convert floating-point condition flags724// Flag manipulation instructions725def : WriteRes<WriteSys, []> { let Latency = 1; }726 727// Insert Random Tags728def : InstRW<[N2Write_2c_1M], (instrs IRG, IRGstack)>;729 730// Insert Tag Mask731// Subtract Pointer732// Subtract Pointer, flagset733def : InstRW<[N2Write_1c_1I], (instrs GMI, SUBP, SUBPS)>;734 735// Move and shift instructions736// -----------------------------------------------------------------------------737 738def : SchedAlias<WriteImm, N2Write_1c_1I>;739 740// Divide and Multiply Instructions741// -----------------------------------------------------------------------------742 743// SDIV, UDIV744def : SchedAlias<WriteID32, N2Write_12c_1M0>;745def : SchedAlias<WriteID64, N2Write_20c_1M0>;746 747def : WriteRes<WriteIM32, [N2UnitM]> { let Latency = 2; }748def : WriteRes<WriteIM64, [N2UnitM]> { let Latency = 2; }749 750// Multiply high751def : InstRW<[N2Write_3c_1M], (instrs SMULHrr, UMULHrr)>;752 753// Pointer Authentication Instructions (v8.3 PAC)754// -----------------------------------------------------------------------------755 756// Authenticate data address757// Authenticate instruction address758// Compute pointer authentication code for data address759// Compute pointer authentication code, using generic key760// Compute pointer authentication code for instruction address761def : InstRW<[N2Write_5c_1M0], (instregex "^AUT", "^PAC")>;762 763// Branch and link, register, with pointer authentication764// Branch, register, with pointer authentication765// Branch, return, with pointer authentication766def : InstRW<[N2Write_6c_1M0_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA,767 BRAAZ, BRAB, BRABZ, RETAA, RETAB,768 ERETAA, ERETAB)>;769 770 771// Load register, with pointer authentication772def : InstRW<[N2Write_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;773 774// Strip pointer authentication code775def : InstRW<[N2Write_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;776 777// Miscellaneous data-processing instructions778// -----------------------------------------------------------------------------779 780// Bitfield extract, one reg781// Bitfield extract, two regs782// NOTE: We don't model the difference between EXTR where both operands are the783// same (one reg).784def : SchedAlias<WriteExtr, N2Write_3c_1I_1M>;785def : InstRW<[N2Write_3c_1I_1M], (instrs EXTRWrri, EXTRXrri)>;786 787// Bitfield move, basic788def : SchedAlias<WriteIS, N2Write_1c_1I>;789 790// Bitfield move, insert791def : InstRW<[N2Write_2c_1M], (instregex "^BFM[WX]ri$")>;792 793// Load instructions794// -----------------------------------------------------------------------------795 796def : SchedAlias<WriteLD, N2Write_4c_1L>;797def : SchedAlias<WriteLDIdx, N2Write_4c_1I_1L>;798 799// Load pair, signed immed offset, signed words800def : InstRW<[N2Write_5c_1M0, WriteLDHi], (instrs LDPSWi)>;801// Load pair, immed post-index or immed pre-index, signed words802def : InstRW<[WriteAdr, N2Write_5c_1M0, WriteLDHi],803 (instregex "^LDPSW(post|pre)$")>;804 805// Store instructions806// -----------------------------------------------------------------------------807 808def : SchedAlias<WriteST, N2Write_1c_1L01_1D>;809def : SchedAlias<WriteSTIdx, N2Write_1c_1L01_1D_1I>;810def : SchedAlias<WriteSTP, N2Write_1c_1L01_1D>;811def : SchedAlias<WriteAdr, N2Write_1c_1I>; // copied from A57.812 813// Tag load instructions814// -----------------------------------------------------------------------------815 816// Load allocation tag817// Load multiple allocation tags818def : InstRW<[N2Write_4c_1L], (instrs LDG, LDGM)>;819 820// Tag store instructions821// -----------------------------------------------------------------------------822 823// Store allocation tags to one or two granules, post-index824// Store allocation tags to one or two granules, pre-index825// Store allocation tag to one or two granules, zeroing, post-index826// Store Allocation Tag to one or two granules, zeroing, pre-index827// Store allocation tag and reg pair to memory, post-Index828// Store allocation tag and reg pair to memory, pre-Index829def : InstRW<[N2Write_1c_1L01_1D_1I], (instrs STGPreIndex, STGPostIndex,830 ST2GPreIndex, ST2GPostIndex,831 STZGPreIndex, STZGPostIndex,832 STZ2GPreIndex, STZ2GPostIndex,833 STGPpre, STGPpost)>;834 835// Store allocation tags to one or two granules, signed offset836// Store allocation tag to two granules, zeroing, signed offset837// Store allocation tag and reg pair to memory, signed offset838// Store multiple allocation tags839def : InstRW<[N2Write_1c_1L01_1D], (instrs STGi, ST2Gi, STZGi,840 STZ2Gi, STGPi, STGM, STZGM)>;841 842// FP data processing instructions843// -----------------------------------------------------------------------------844 845// FP absolute value846// FP arithmetic847// FP min/max848// FP negate849// FP select850def : SchedAlias<WriteF, N2Write_2c_1V>;851 852// FP compare853def : SchedAlias<WriteFCmp, N2Write_2c_1V0>;854 855// FP divide and square root operations are performed using an iterative856// algorithm and block subsequent similar operations to the same pipeline857// until complete (Arm Neoverse N2 Software Optimization Guide, 3.14).858 859// FP divide, square root860def : SchedAlias<WriteFDiv, N2Write_7c_7V0>;861 862// FP divide, H-form863def : InstRW<[N2Write_7c_7V0], (instrs FDIVHrr)>;864// FP divide, S-form865def : InstRW<[N2Write_10c_10V0], (instrs FDIVSrr)>;866// FP divide, D-form867def : InstRW<[N2Write_15c_15V0], (instrs FDIVDrr)>;868 869// FP square root, H-form870def : InstRW<[N2Write_7c_7V0], (instrs FSQRTHr)>;871// FP square root, S-form872def : InstRW<[N2Write_9c_9V0], (instrs FSQRTSr)>;873// FP square root, D-form874def : InstRW<[N2Write_16c_16V0], (instrs FSQRTDr)>;875 876// FP multiply877def : WriteRes<WriteFMul, [N2UnitV]> { let Latency = 3; }878 879// FP multiply accumulate880def : InstRW<[N2Write_4c_1V], (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;881 882// FP round to integral883def : InstRW<[N2Write_3c_1V0], (instregex "^FRINT[AIMNPXZ][HSD]r$",884 "^FRINT(32|64)[XZ][SD]r$")>;885 886// FP miscellaneous instructions887// -----------------------------------------------------------------------------888 889// FP convert, from gen to vec reg890def : InstRW<[N2Write_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;891 892// FP convert, from vec to gen reg893def : InstRW<[N2Write_3c_1V], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>;894 895// FP convert, Javascript from vec to gen reg896// FP convert, from vec to vec reg897def : SchedAlias<WriteFCvt, N2Write_3c_1V0>;898 899// FP move, immed900def : SchedAlias<WriteFImm, N2Write_2c_1V>;901 902// FP move, register903def : InstRW<[N2Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>;904 905// FP transfer, from gen to low half of vec reg906def : InstRW<[N2Write_0or3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;907 908// FP transfer, from gen to high half of vec reg909def : InstRW<[N2Write_5c_1M0_1V], (instrs FMOVXDHighr)>;910 911// FP transfer, from vec to gen reg912def : SchedAlias<WriteFCopy, N2Write_2c_1V>;913 914// FP load instructions915// -----------------------------------------------------------------------------916 917// Load vector reg, literal, S/D/Q forms918// Load vector reg, unscaled immed919def : InstRW<[N2Write_6c_1L], (instregex "^LDR[SDQ]l$",920 "^LDUR[BHSDQ]i$")>;921 922// Load vector reg, immed post-index923// Load vector reg, immed pre-index924def : InstRW<[WriteAdr, N2Write_6c_1I_1L], (instregex "^LDR[BHSDQ](post|pre)$")>;925 926// Load vector reg, unsigned immed927def : InstRW<[N2Write_6c_1L], (instregex "^LDR[BHSDQ]ui$")>;928 929// Load vector reg, register offset, basic930// Load vector reg, register offset, scale, S/D-form931// Load vector reg, register offset, extend932// Load vector reg, register offset, extend, scale, S/D-form933def : InstRW<[N2Write_6c_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>;934 935// Load vector reg, register offset, scale, H/Q-form936// Load vector reg, register offset, extend, scale, H/Q-form937def : InstRW<[N2Write_7c_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>;938 939// Load vector pair, immed offset, S/D-form940def : InstRW<[N2Write_6c_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>;941 942// Load vector pair, immed offset, Q-form943def : InstRW<[N2Write_6c_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;944 945// Load vector pair, immed post-index, S/D-form946// Load vector pair, immed pre-index, S/D-form947def : InstRW<[WriteAdr, N2Write_6c_1I_1L, WriteLDHi],948 (instregex "^LDP[SD](pre|post)$")>;949 950// Load vector pair, immed post-index, Q-form951// Load vector pair, immed pre-index, Q-form952def : InstRW<[WriteAdr, N2Write_6c_2I_2L, WriteLDHi], (instrs LDPQpost,953 LDPQpre)>;954 955// FP store instructions956// -----------------------------------------------------------------------------957 958// Store vector reg, unscaled immed, B/H/S/D-form959// Store vector reg, unscaled immed, Q-form960def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STUR[BHSDQ]i$")>;961 962// Store vector reg, immed post-index, B/H/S/D-form963// Store vector reg, immed post-index, Q-form964// Store vector reg, immed pre-index, B/H/S/D-form965// Store vector reg, immed pre-index, Q-form966def : InstRW<[WriteAdr, N2Write_2c_1L01_1V_1I, ReadAdrBase],967 (instregex "^STR[BHSDQ](pre|post)$")>;968 969// Store vector reg, unsigned immed, B/H/S/D-form970// Store vector reg, unsigned immed, Q-form971def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STR[BHSDQ]ui$")>;972 973// Store vector reg, register offset, basic, B/H/S/D-form974// Store vector reg, register offset, basic, Q-form975// Store vector reg, register offset, scale, S/D-form976// Store vector reg, register offset, extend, B/H/S/D-form977// Store vector reg, register offset, extend, Q-form978// Store vector reg, register offset, extend, scale, S/D-form979def : InstRW<[N2Write_2c_1L01_1V, ReadAdrBase],980 (instregex "^STR[BSD]ro[WX]$")>;981 982// Store vector reg, register offset, scale, H-form983// Store vector reg, register offset, scale, Q-form984// Store vector reg, register offset, extend, scale, H-form985// Store vector reg, register offset, extend, scale, Q-form986def : InstRW<[N2Write_2c_1L01_1V, ReadAdrBase],987 (instregex "^STR[HQ]ro[WX]$")>;988 989// Store vector pair, immed offset, S-form990// Store vector pair, immed offset, D-form991def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STN?P[SD]i$")>;992 993// Store vector pair, immed offset, Q-form994def : InstRW<[N2Write_2c_1L01_2V], (instrs STPQi, STNPQi)>;995 996// Store vector pair, immed post-index, S-form997// Store vector pair, immed post-index, D-form998// Store vector pair, immed pre-index, S-form999// Store vector pair, immed pre-index, D-form1000def : InstRW<[WriteAdr, N2Write_2c_1L01_1V_1I],1001 (instregex "^STP[SD](pre|post)$")>;1002 1003// Store vector pair, immed post-index, Q-form1004def : InstRW<[N2Write_2c_1L01_2V_1I], (instrs STPQpost)>;1005 1006// Store vector pair, immed pre-index, Q-form1007def : InstRW<[N2Write_2c_1L01_2V_2I], (instrs STPQpre)>;1008 1009// ASIMD integer instructions1010// -----------------------------------------------------------------------------1011 1012// ASIMD absolute diff1013// ASIMD absolute diff long1014// ASIMD arith, basic1015// ASIMD arith, complex1016// ASIMD arith, pair-wise1017// ASIMD compare1018// ASIMD logical1019// ASIMD max/min, basic and pair-wise1020def : SchedAlias<WriteVd, N2Write_2c_1V>;1021def : SchedAlias<WriteVq, N2Write_2c_1V>;1022 1023// ASIMD absolute diff accum1024// ASIMD absolute diff accum long1025def : InstRW<[N2Write_4c_1V1],1026 (instregex "^SABAv", "^UABAv", "^SABALv", "^UABALv")>;1027 1028// ASIMD arith, reduce, 4H/4S1029def : InstRW<[N2Write_2c_1V1], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>;1030 1031// ASIMD arith, reduce, 8B/8H1032def : InstRW<[N2Write_4c_1V1_1V],1033 (instregex "^(ADDV|[SU]ADDLV)v8(i8|i16)v$")>;1034 1035// ASIMD arith, reduce, 16B1036def : InstRW<[N2Write_4c_1V1], (instrs ADDVv16i8v, SADDLVv16i8v,1037 UADDLVv16i8v)>;1038 1039// ASIMD dot product1040// ASIMD dot product using signed and unsigned integers1041def : InstRW<[N2Write_3c_1V],1042 (instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>;1043 1044// ASIMD matrix multiply-accumulate1045def : InstRW<[N2Write_3c_1V], (instrs SMMLA, UMMLA, USMMLA)>;1046 1047// ASIMD max/min, reduce, 4H/4S1048def : InstRW<[N2Write_2c_1V1], (instregex "^[SU](MAX|MIN)Vv4i16v$",1049 "^[SU](MAX|MIN)Vv4i32v$")>;1050 1051// ASIMD max/min, reduce, 8B/8H1052def : InstRW<[N2Write_4c_1V1_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$",1053 "^[SU](MAX|MIN)Vv8i16v$")>;1054 1055// ASIMD max/min, reduce, 16B1056def : InstRW<[N2Write_4c_2V1], (instregex "[SU](MAX|MIN)Vv16i8v$")>;1057 1058// ASIMD multiply1059def : InstRW<[N2Write_4c_1V0], (instregex "^MULv", "^SQ(R)?DMULHv")>;1060 1061// ASIMD multiply accumulate1062def : InstRW<[N2Write_4c_1V0], (instregex "^MLAv", "^MLSv")>;1063 1064// ASIMD multiply accumulate high1065def : InstRW<[N2Write_4c_1V0], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;1066 1067// ASIMD multiply accumulate long1068def : InstRW<[N2Write_4c_1V0], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;1069 1070// ASIMD multiply accumulate saturating long1071def : InstRW<[N2Write_4c_1V0], (instregex "^SQDMLALv", "^SQDMLSLv")>;1072 1073// ASIMD multiply/multiply long (8x8) polynomial, D-form1074// ASIMD multiply/multiply long (8x8) polynomial, Q-form1075def : InstRW<[N2Write_3c_1V0], (instregex "^PMULL?(v8i8|v16i8)$")>;1076 1077// ASIMD multiply long1078def : InstRW<[N2Write_3c_1V], (instregex "^[SU]MULLv", "^SQDMULLv")>;1079 1080// ASIMD pairwise add and accumulate long1081def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]ADALPv")>;1082 1083// ASIMD shift accumulate1084def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]SRAv", "^[SU]RSRAv")>;1085 1086// ASIMD shift by immed, basic1087def : InstRW<[N2Write_2c_1V1], (instregex "^SHLv", "^SHLLv", "^SHRNv",1088 "^SSHLLv", "^SSHRv", "^USHLLv",1089 "^USHRv")>;1090 1091// ASIMD shift by immed and insert, basic1092def : InstRW<[N2Write_2c_1V1], (instregex "^SLIv", "^SRIv")>;1093 1094// ASIMD shift by immed, complex1095def : InstRW<[N2Write_4c_1V1],1096 (instregex "^RSHRNv", "^SQRSHRNv", "^SQRSHRUNv",1097 "^(SQSHLU?|UQSHL)[bhsd]$",1098 "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",1099 "^SQSHRNv", "^SQSHRUNv", "^SRSHRv", "^UQRSHRNv",1100 "^UQSHRNv", "^URSHRv")>;1101 1102// ASIMD shift by register, basic1103def : InstRW<[N2Write_2c_1V1], (instregex "^[SU]SHLv")>;1104 1105// ASIMD shift by register, complex1106def : InstRW<[N2Write_4c_1V1],1107 (instregex "^[SU]RSHLv", "^[SU]QRSHLv",1108 "^[SU]QSHL(v1i8|v1i16|v1i32|v1i64|v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)$")>;1109 1110// ASIMD floating-point instructions1111// -----------------------------------------------------------------------------1112 1113// ASIMD FP absolute value/difference1114// ASIMD FP arith, normal1115// ASIMD FP compare1116// ASIMD FP complex add1117// ASIMD FP max/min, normal1118// ASIMD FP max/min, pairwise1119// ASIMD FP negate1120// Handled by SchedAlias<WriteV[dq], ...>1121 1122// ASIMD FP complex multiply add1123def : InstRW<[N2Write_4c_1V], (instregex "^FCMLAv")>;1124 1125// ASIMD FP convert, long (F16 to F32)1126def : InstRW<[N2Write_4c_2V0], (instregex "^FCVTL(v4|v8)i16")>;1127 1128// ASIMD FP convert, long (F32 to F64)1129def : InstRW<[N2Write_3c_1V0], (instregex "^FCVTL(v2|v4)i32")>;1130 1131// ASIMD FP convert, narrow (F32 to F16)1132def : InstRW<[N2Write_4c_2V0], (instregex "^FCVTN(v4|v8)i16")>;1133 1134// ASIMD FP convert, narrow (F64 to F32)1135def : InstRW<[N2Write_3c_1V0], (instregex "^FCVTN(v2|v4)i32",1136 "^FCVTXN(v2|v4)f32")>;1137 1138// ASIMD FP convert, other, D-form F32 and Q-form F641139def : InstRW<[N2Write_3c_1V0], (instregex "^[FSU]CVT[AMNPZ][SU]v2f(32|64)$",1140 "^[SU]CVTFv2f(32|64)$")>;1141 1142// ASIMD FP convert, other, D-form F16 and Q-form F321143def : InstRW<[N2Write_4c_2V0], (instregex "^[FSU]CVT[AMNPZ][SU]v4f(16|32)$",1144 "^[SU]CVTFv4f(16|32)$")>;1145 1146// ASIMD FP convert, other, Q-form F161147def : InstRW<[N2Write_6c_4V0], (instregex "^[FSU]CVT[AMNPZ][SU]v8f16$",1148 "^[SU]CVTFv8f16$")>;1149 1150// ASIMD FP divide, D-form, F161151def : InstRW<[N2Write_7c_1V0], (instrs FDIVv4f16)>;1152 1153// ASIMD FP divide, D-form, F321154def : InstRW<[N2Write_10c_2V0], (instrs FDIVv2f32)>;1155 1156// ASIMD FP divide, Q-form, F161157def : InstRW<[N2Write_13c_2V0], (instrs FDIVv8f16)>;1158 1159// ASIMD FP divide, Q-form, F321160def : InstRW<[N2Write_10c_2V0], (instrs FDIVv4f32)>;1161 1162// ASIMD FP divide, Q-form, F641163def : InstRW<[N2Write_15c_2V0], (instrs FDIVv2f64)>;1164 1165// ASIMD FP max/min, reduce, F32 and D-form F161166def : InstRW<[N2Write_4c_1V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;1167 1168// ASIMD FP max/min, reduce, Q-form F161169def : InstRW<[N2Write_6c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;1170 1171// ASIMD FP multiply1172def : InstRW<[N2Write_3c_1V], (instregex "^FMULv", "^FMULXv")>;1173 1174// ASIMD FP multiply accumulate1175def : InstRW<[N2Write_4c_1V], (instregex "^FMLAv", "^FMLSv")>;1176 1177// ASIMD FP multiply accumulate long1178def : InstRW<[N2Write_5c_1V], (instregex "^FMLALv", "^FMLSLv")>;1179 1180// ASIMD FP round, D-form F32 and Q-form F641181def : InstRW<[N2Write_3c_1V0],1182 (instregex "^FRINT[AIMNPXZ]v2f(32|64)$",1183 "^FRINT(32|64)[XZ]v2f(32|64)$")>;1184 1185// ASIMD FP round, D-form F16 and Q-form F321186def : InstRW<[N2Write_4c_2V0],1187 (instregex "^FRINT[AIMNPXZ]v4f(16|32)$",1188 "^FRINT(32|64)[XZ]v4f32$")>;1189 1190 1191// ASIMD FP round, Q-form F161192def : InstRW<[N2Write_6c_4V0], (instregex "^FRINT[AIMNPXZ]v8f16$")>;1193 1194// ASIMD FP square root, D-form, F161195def : InstRW<[N2Write_7c_1V0], (instrs FSQRTv4f16)>;1196 1197// ASIMD FP square root, D-form, F321198def : InstRW<[N2Write_10c_2V0], (instrs FSQRTv2f32)>;1199 1200// ASIMD FP square root, Q-form, F161201def : InstRW<[N2Write_13c_2V0], (instrs FSQRTv8f16)>;1202 1203// ASIMD FP square root, Q-form, F321204def : InstRW<[N2Write_10c_2V0], (instrs FSQRTv4f32)>;1205 1206// ASIMD FP square root, Q-form, F641207def : InstRW<[N2Write_16c_2V0], (instrs FSQRTv2f64)>;1208 1209// ASIMD BFloat16 (BF16) instructions1210// -----------------------------------------------------------------------------1211 1212// ASIMD convert, F32 to BF161213def : InstRW<[N2Write_4c_1V0], (instrs BFCVTN, BFCVTN2)>;1214 1215// ASIMD dot product1216def : InstRW<[N2Write_4c_1V], (instrs BFDOTv4bf16, BFDOTv8bf16)>;1217 1218// ASIMD matrix multiply accumulate1219def : InstRW<[N2Write_5c_1V], (instrs BFMMLA)>;1220 1221// ASIMD multiply accumulate long1222def : InstRW<[N2Write_4c_1V], (instrs BFMLALB, BFMLALBIdx, BFMLALT,1223 BFMLALTIdx)>;1224 1225// Scalar convert, F32 to BF161226def : InstRW<[N2Write_3c_1V0], (instrs BFCVT)>;1227 1228// ASIMD miscellaneous instructions1229// -----------------------------------------------------------------------------1230 1231// ASIMD bit reverse1232// ASIMD bitwise insert1233// ASIMD count1234// ASIMD duplicate, element1235// ASIMD extract1236// ASIMD extract narrow1237// ASIMD insert, element to element1238// ASIMD move, FP immed1239// ASIMD move, integer immed1240// ASIMD reverse1241// ASIMD table lookup, 1 or 2 table regs1242// ASIMD table lookup extension, 1 table reg1243// ASIMD transfer, element to gen reg1244// ASIMD transpose1245// ASIMD unzip/zip1246// Handled by SchedAlias<WriteV[dq], ...>1247 1248def : InstRW<[N2Write_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>;1249 1250// ASIMD duplicate, gen reg1251def : InstRW<[N2Write_3c_1M0], (instregex "^DUPv.+gpr")>;1252 1253// ASIMD extract narrow, saturating1254def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]QXTNv", "^SQXTUNv")>;1255 1256// ASIMD reciprocal and square root estimate, D-form U321257def : InstRW<[N2Write_3c_1V0], (instrs URECPEv2i32, URSQRTEv2i32)>;1258 1259// ASIMD reciprocal and square root estimate, Q-form U321260def : InstRW<[N2Write_4c_2V0], (instrs URECPEv4i32, URSQRTEv4i32)>;1261 1262// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms1263def : InstRW<[N2Write_3c_1V0], (instrs FRECPEv1f16, FRECPEv1i32,1264 FRECPEv1i64, FRECPEv2f32,1265 FRSQRTEv1f16, FRSQRTEv1i32,1266 FRSQRTEv1i64, FRSQRTEv2f32)>;1267 1268// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F321269def : InstRW<[N2Write_4c_2V0], (instrs FRECPEv4f16, FRECPEv4f32,1270 FRSQRTEv4f16, FRSQRTEv4f32)>;1271 1272// ASIMD reciprocal and square root estimate, Q-form F161273def : InstRW<[N2Write_6c_4V0], (instrs FRECPEv8f16, FRSQRTEv8f16)>;1274 1275// ASIMD reciprocal exponent1276def : InstRW<[N2Write_3c_1V0], (instregex "^FRECPXv")>;1277 1278// ASIMD reciprocal step1279def : InstRW<[N2Write_4c_1V], (instregex "^FRECPSv", "^FRSQRTSv")>;1280 1281// ASIMD table lookup, 3 table regs1282def : InstRW<[N2Write_4c_2V], (instrs TBLv8i8Three, TBLv16i8Three)>;1283 1284// ASIMD table lookup, 4 table regs1285def : InstRW<[N2Write_4c_4V], (instrs TBLv8i8Four, TBLv16i8Four)>;1286 1287// ASIMD table lookup extension, 2 table reg1288def : InstRW<[N2Write_4c_2V], (instrs TBXv8i8Two, TBXv16i8Two)>;1289 1290// ASIMD table lookup extension, 3 table reg1291def : InstRW<[N2Write_6c_4V], (instrs TBXv8i8Three, TBXv16i8Three)>;1292 1293// ASIMD table lookup extension, 4 table reg1294def : InstRW<[N2Write_6c_8V], (instrs TBXv8i8Four, TBXv16i8Four)>;1295 1296// ASIMD transfer, gen reg to element1297def : InstRW<[N2Write_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;1298 1299// ASIMD load instructions1300// -----------------------------------------------------------------------------1301 1302// ASIMD load, 1 element, multiple, 1 reg, D-form1303def : InstRW<[N2Write_6c_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;1304def : InstRW<[WriteAdr, N2Write_6c_1L],1305 (instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>;1306 1307// ASIMD load, 1 element, multiple, 1 reg, Q-form1308def : InstRW<[N2Write_6c_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;1309def : InstRW<[WriteAdr, N2Write_6c_1L],1310 (instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>;1311 1312// ASIMD load, 1 element, multiple, 2 reg, D-form1313def : InstRW<[N2Write_6c_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;1314def : InstRW<[WriteAdr, N2Write_6c_2L],1315 (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;1316 1317// ASIMD load, 1 element, multiple, 2 reg, Q-form1318def : InstRW<[N2Write_6c_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;1319def : InstRW<[WriteAdr, N2Write_6c_2L],1320 (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;1321 1322// ASIMD load, 1 element, multiple, 3 reg, D-form1323def : InstRW<[N2Write_6c_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;1324def : InstRW<[WriteAdr, N2Write_6c_3L],1325 (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;1326 1327// ASIMD load, 1 element, multiple, 3 reg, Q-form1328def : InstRW<[N2Write_6c_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;1329def : InstRW<[WriteAdr, N2Write_6c_3L],1330 (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;1331 1332// ASIMD load, 1 element, multiple, 4 reg, D-form1333def : InstRW<[N2Write_7c_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;1334def : InstRW<[WriteAdr, N2Write_7c_4L],1335 (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;1336 1337// ASIMD load, 1 element, multiple, 4 reg, Q-form1338def : InstRW<[N2Write_7c_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;1339def : InstRW<[WriteAdr, N2Write_7c_4L],1340 (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;1341 1342// ASIMD load, 1 element, one lane, B/H/S1343// ASIMD load, 1 element, one lane, D1344def : InstRW<[N2Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)$")>;1345def : InstRW<[WriteAdr, N2Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;1346 1347// ASIMD load, 1 element, all lanes, D-form, B/H/S1348// ASIMD load, 1 element, all lanes, D-form, D1349def : InstRW<[N2Write_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;1350def : InstRW<[WriteAdr, N2Write_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;1351 1352// ASIMD load, 1 element, all lanes, Q-form1353def : InstRW<[N2Write_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;1354def : InstRW<[WriteAdr, N2Write_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;1355 1356// ASIMD load, 2 element, multiple, D-form, B/H/S1357def : InstRW<[N2Write_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;1358def : InstRW<[WriteAdr, N2Write_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;1359 1360// ASIMD load, 2 element, multiple, Q-form, B/H/S1361// ASIMD load, 2 element, multiple, Q-form, D1362def : InstRW<[N2Write_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;1363def : InstRW<[WriteAdr, N2Write_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;1364 1365// ASIMD load, 2 element, one lane, B/H1366// ASIMD load, 2 element, one lane, S1367// ASIMD load, 2 element, one lane, D1368def : InstRW<[N2Write_8c_1L_2V], (instregex "LD2i(8|16|32|64)$")>;1369def : InstRW<[WriteAdr, N2Write_8c_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;1370 1371// ASIMD load, 2 element, all lanes, D-form, B/H/S1372// ASIMD load, 2 element, all lanes, D-form, D1373def : InstRW<[N2Write_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;1374def : InstRW<[WriteAdr, N2Write_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;1375 1376// ASIMD load, 2 element, all lanes, Q-form1377def : InstRW<[N2Write_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;1378def : InstRW<[WriteAdr, N2Write_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;1379 1380// ASIMD load, 3 element, multiple, D-form, B/H/S1381def : InstRW<[N2Write_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;1382def : InstRW<[WriteAdr, N2Write_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;1383 1384// ASIMD load, 3 element, multiple, Q-form, B/H/S1385def : InstRW<[N2Write_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s)$")>;1386def : InstRW<[WriteAdr, N2Write_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s)_POST$")>;1387 1388// ASIMD load, 3 element, multiple, Q-form, D1389def : InstRW<[N2Write_8c_3L_3V], (instregex "LD3Threev(2d)$")>;1390def : InstRW<[WriteAdr, N2Write_8c_3L_3V], (instregex "LD3Threev(2d)_POST$")>;1391 1392// ASIMD load, 3 element, one lane, B/H1393// ASIMD load, 3 element, one lane, S1394// ASIMD load, 3 element, one lane, D1395def : InstRW<[N2Write_8c_2L_3V], (instregex "LD3i(8|16|32|64)$")>;1396def : InstRW<[WriteAdr, N2Write_8c_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;1397 1398// ASIMD load, 3 element, all lanes, D-form, B/H/S1399// ASIMD load, 3 element, all lanes, D-form, D1400def : InstRW<[N2Write_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;1401def : InstRW<[WriteAdr, N2Write_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;1402 1403// ASIMD load, 3 element, all lanes, Q-form, B/H/S1404// ASIMD load, 3 element, all lanes, Q-form, D1405def : InstRW<[N2Write_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;1406def : InstRW<[WriteAdr, N2Write_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;1407 1408// ASIMD load, 4 element, multiple, D-form, B/H/S1409def : InstRW<[N2Write_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;1410def : InstRW<[WriteAdr, N2Write_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;1411 1412// ASIMD load, 4 element, multiple, Q-form, B/H/S1413// ASIMD load, 4 element, multiple, Q-form, D1414def : InstRW<[N2Write_9c_4L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;1415def : InstRW<[WriteAdr, N2Write_9c_4L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;1416 1417// ASIMD load, 4 element, one lane, B/H1418// ASIMD load, 4 element, one lane, S1419// ASIMD load, 4 element, one lane, D1420def : InstRW<[N2Write_8c_3L_4V], (instregex "LD4i(8|16|32|64)$")>;1421def : InstRW<[WriteAdr, N2Write_8c_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;1422 1423// ASIMD load, 4 element, all lanes, D-form, B/H/S1424// ASIMD load, 4 element, all lanes, D-form, D1425def : InstRW<[N2Write_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;1426def : InstRW<[WriteAdr, N2Write_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;1427 1428// ASIMD load, 4 element, all lanes, Q-form, B/H/S1429// ASIMD load, 4 element, all lanes, Q-form, D1430def : InstRW<[N2Write_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;1431def : InstRW<[WriteAdr, N2Write_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;1432 1433// ASIMD store instructions1434// -----------------------------------------------------------------------------1435 1436// ASIMD store, 1 element, multiple, 1 reg, D-form1437def : InstRW<[N2Write_2c_1L01_1V], (instregex "ST1Onev(8b|4h|2s|1d)$")>;1438def : InstRW<[WriteAdr, N2Write_2c_1L01_1V], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;1439 1440// ASIMD store, 1 element, multiple, 1 reg, Q-form1441def : InstRW<[N2Write_2c_1L01_1V], (instregex "ST1Onev(16b|8h|4s|2d)$")>;1442def : InstRW<[WriteAdr, N2Write_2c_1L01_1V], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;1443 1444// ASIMD store, 1 element, multiple, 2 reg, D-form1445def : InstRW<[N2Write_2c_1L01_1V], (instregex "ST1Twov(8b|4h|2s|1d)$")>;1446def : InstRW<[WriteAdr, N2Write_2c_1L01_1V], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;1447 1448// ASIMD store, 1 element, multiple, 2 reg, Q-form1449def : InstRW<[N2Write_2c_2L01_2V], (instregex "ST1Twov(16b|8h|4s|2d)$")>;1450def : InstRW<[WriteAdr, N2Write_2c_2L01_2V], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;1451 1452// ASIMD store, 1 element, multiple, 3 reg, D-form1453def : InstRW<[N2Write_2c_2L01_2V], (instregex "ST1Threev(8b|4h|2s|1d)$")>;1454def : InstRW<[WriteAdr, N2Write_2c_2L01_2V], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;1455 1456// ASIMD store, 1 element, multiple, 3 reg, Q-form1457def : InstRW<[N2Write_2c_3L01_3V], (instregex "ST1Threev(16b|8h|4s|2d)$")>;1458def : InstRW<[WriteAdr, N2Write_2c_3L01_3V], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;1459 1460// ASIMD store, 1 element, multiple, 4 reg, D-form1461def : InstRW<[N2Write_2c_2L01_2V], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;1462def : InstRW<[WriteAdr, N2Write_2c_2L01_2V], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;1463 1464// ASIMD store, 1 element, multiple, 4 reg, Q-form1465def : InstRW<[N2Write_2c_4L01_4V], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;1466def : InstRW<[WriteAdr, N2Write_2c_4L01_4V], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;1467 1468// ASIMD store, 1 element, one lane, B/H/S1469// ASIMD store, 1 element, one lane, D1470def : InstRW<[N2Write_4c_1L01_1V], (instregex "ST1i(8|16|32|64)$")>;1471def : InstRW<[WriteAdr, N2Write_4c_1L01_1V], (instregex "ST1i(8|16|32|64)_POST$")>;1472 1473// ASIMD store, 2 element, multiple, D-form, B/H/S1474def : InstRW<[N2Write_4c_1L01_1V], (instregex "ST2Twov(8b|4h|2s)$")>;1475def : InstRW<[WriteAdr, N2Write_4c_1L01_1V], (instregex "ST2Twov(8b|4h|2s)_POST$")>;1476 1477// ASIMD store, 2 element, multiple, Q-form, B/H/S1478// ASIMD store, 2 element, multiple, Q-form, D1479def : InstRW<[N2Write_4c_2L01_2V], (instregex "ST2Twov(16b|8h|4s|2d)$")>;1480def : InstRW<[WriteAdr, N2Write_4c_2L01_2V], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;1481 1482// ASIMD store, 2 element, one lane, B/H/S1483// ASIMD store, 2 element, one lane, D1484def : InstRW<[N2Write_4c_1L01_1V], (instregex "ST2i(8|16|32|64)$")>;1485def : InstRW<[WriteAdr, N2Write_4c_1L01_1V], (instregex "ST2i(8|16|32|64)_POST$")>;1486 1487// ASIMD store, 3 element, multiple, D-form, B/H/S1488def : InstRW<[N2Write_5c_2L01_2V], (instregex "ST3Threev(8b|4h|2s)$")>;1489def : InstRW<[WriteAdr, N2Write_5c_2L01_2V], (instregex "ST3Threev(8b|4h|2s)_POST$")>;1490 1491// ASIMD store, 3 element, multiple, Q-form, B/H/S1492// ASIMD store, 3 element, multiple, Q-form, D1493def : InstRW<[N2Write_6c_3L01_3V], (instregex "ST3Threev(16b|8h|4s|2d)$")>;1494def : InstRW<[WriteAdr, N2Write_6c_3L01_3V], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;1495 1496// ASIMD store, 3 element, one lane, B/H1497// ASIMD store, 3 element, one lane, S1498// ASIMD store, 3 element, one lane, D1499def : InstRW<[N2Write_6c_3L01_3V], (instregex "ST3i(8|16|32|64)$")>;1500def : InstRW<[WriteAdr, N2Write_6c_3L01_3V], (instregex "ST3i(8|16|32|64)_POST$")>;1501 1502// ASIMD store, 4 element, multiple, D-form, B/H/S1503def : InstRW<[N2Write_6c_3L01_3V], (instregex "ST4Fourv(8b|4h|2s)$")>;1504def : InstRW<[WriteAdr, N2Write_6c_3L01_3V], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;1505 1506// ASIMD store, 4 element, multiple, Q-form, B/H/S1507def : InstRW<[N2Write_7c_6L01_6V], (instregex "ST4Fourv(16b|8h|4s)$")>;1508def : InstRW<[WriteAdr, N2Write_7c_6L01_6V], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;1509 1510// ASIMD store, 4 element, multiple, Q-form, D1511def : InstRW<[N2Write_5c_4L01_4V], (instregex "ST4Fourv(2d)$")>;1512def : InstRW<[WriteAdr, N2Write_5c_4L01_4V], (instregex "ST4Fourv(2d)_POST$")>;1513 1514// ASIMD store, 4 element, one lane, B/H/S1515def : InstRW<[N2Write_6c_3L01_3V], (instregex "ST4i(8|16|32)$")>;1516def : InstRW<[WriteAdr, N2Write_6c_3L01_3V], (instregex "ST4i(8|16|32)_POST$")>;1517 1518// ASIMD store, 4 element, one lane, D1519def : InstRW<[N2Write_4c_3L01_3V], (instregex "ST4i(64)$")>;1520def : InstRW<[WriteAdr, N2Write_4c_3L01_3V], (instregex "ST4i(64)_POST$")>;1521 1522// Cryptography extensions1523// -----------------------------------------------------------------------------1524 1525// Crypto AES ops1526def : InstRW<[N2Write_2c_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;1527 1528// Crypto polynomial (64x64) multiply long1529def : InstRW<[N2Write_2c_1V0], (instrs PMULLv1i64, PMULLv2i64)>;1530 1531// Crypto SHA1 hash acceleration op1532// Crypto SHA1 schedule acceleration ops1533def : InstRW<[N2Write_2c_1V0], (instregex "^SHA1(H|SU0|SU1)")>;1534 1535// Crypto SHA1 hash acceleration ops1536// Crypto SHA256 hash acceleration ops1537def : InstRW<[N2Write_4c_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>;1538 1539// Crypto SHA256 schedule acceleration ops1540def : InstRW<[N2Write_2c_1V0], (instregex "^SHA256SU[01]")>;1541 1542// Crypto SHA512 hash acceleration ops1543def : InstRW<[N2Write_2c_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>;1544 1545// Crypto SHA3 ops1546def : InstRW<[N2Write_2c_1V0], (instrs BCAX, EOR3, RAX1, XAR)>;1547 1548// Crypto SM3 ops1549def : InstRW<[N2Write_2c_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$",1550 "^SM3TT[12][AB]$")>;1551 1552// Crypto SM4 ops1553def : InstRW<[N2Write_4c_1V0], (instrs SM4E, SM4ENCKEY)>;1554 1555// CRC1556// -----------------------------------------------------------------------------1557 1558def : InstRW<[N2Write_2c_1M0], (instregex "^CRC32")>;1559 1560// SVE Predicate instructions1561// -----------------------------------------------------------------------------1562 1563// Loop control, based on predicate1564def : InstRW<[N2Write_2c_1M], (instrs BRKA_PPmP, BRKA_PPzP,1565 BRKB_PPmP, BRKB_PPzP)>;1566 1567// Loop control, based on predicate and flag setting1568def : InstRW<[N2Write_3c_1M], (instrs BRKAS_PPzP, BRKBS_PPzP)>;1569 1570// Loop control, propagating1571def : InstRW<[N2Write_2c_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP, BRKPB_PPzPP)>;1572 1573// Loop control, propagating and flag setting1574def : InstRW<[N2Write_3c_1M0_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP,1575 BRKPBS_PPzPP)>;1576 1577// Loop control, based on GPR1578def : InstRW<[N2Write_3c_1M],1579 (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]$")>;1580 1581def : InstRW<[N2Write_3c_1M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]$")>;1582 1583// Loop terminate1584def : InstRW<[N2Write_1c_1M], (instregex "^CTERM(EQ|NE)_(WW|XX)$")>;1585 1586// Predicate counting scalar1587def : InstRW<[N2Write_2c_1M], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;1588def : InstRW<[N2Write_2c_1M],1589 (instregex "^(CNT|DEC|INC|SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI$",1590 "^SQ(DEC|INC)[BHWD]_XPiWdI$",1591 "^(UQDEC|UQINC)[BHWD]_WPiI$")>;1592 1593// Predicate counting scalar, active predicate1594def : InstRW<[N2Write_2c_1M],1595 (instregex "^CNTP_XPP_[BHSD]$",1596 "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]$",1597 "^(UQDEC|UQINC)P_WP_[BHSD]$",1598 "^(SQDEC|SQINC|UQDEC|UQINC)P_XPWd_[BHSD]$")>;1599 1600// Predicate counting vector, active predicate1601def : InstRW<[N2Write_7c_1M_1M0_1V],1602 (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]$")>;1603 1604// Predicate logical1605def : InstRW<[N2Write_1c_1M0],1606 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP$")>;1607 1608// Predicate logical, flag setting1609def : InstRW<[N2Write_2c_1M0_1M],1610 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP$")>;1611 1612// Predicate reverse1613def : InstRW<[N2Write_2c_1M], (instregex "^REV_PP_[BHSD]$")>;1614 1615// Predicate select1616def : InstRW<[N2Write_1c_1M0], (instrs SEL_PPPP)>;1617 1618// Predicate set1619def : InstRW<[N2Write_2c_1M], (instregex "^PFALSE$", "^PTRUE_[BHSD]$")>;1620 1621// Predicate set/initialize, set flags1622def : InstRW<[N2Write_3c_1M], (instregex "^PTRUES_[BHSD]$")>;1623 1624// Predicate find first/next1625def : InstRW<[N2Write_3c_1M], (instregex "^PFIRST_B$", "^PNEXT_[BHSD]$")>;1626 1627// Predicate test1628def : InstRW<[N2Write_1c_1M], (instrs PTEST_PP)>;1629 1630// Predicate transpose1631def : InstRW<[N2Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSDQ]$")>;1632 1633// Predicate unpack and widen1634def : InstRW<[N2Write_2c_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>;1635 1636// Predicate zip/unzip1637def : InstRW<[N2Write_2c_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSDQ]$")>;1638 1639// SVE integer instructions1640// -----------------------------------------------------------------------------1641 1642// Arithmetic, absolute diff1643def : InstRW<[N2Write_2c_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",1644 "^[SU]ABD_ZPZZ_[BHSD]")>;1645 1646// Arithmetic, absolute diff accum1647def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]ABA_ZZZ_[BHSD]$")>;1648 1649// Arithmetic, absolute diff accum long1650def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]$")>;1651 1652// Arithmetic, absolute diff long1653def : InstRW<[N2Write_2c_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]$")>;1654 1655// Arithmetic, basic1656def : InstRW<[N2Write_2c_1V],1657 (instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]",1658 "^(ADD|SUB)_ZZZ_[BHSD]",1659 "^(ADD|SUB|SUBR)_ZPZZ_[BHSD]",1660 "^(ADD|SUB|SUBR)_ZI_[BHSD]",1661 "^ADR_[SU]XTW_ZZZ_D_[0123]",1662 "^ADR_LSL_ZZZ_[SD]_[0123]",1663 "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",1664 "^SADDLBT_ZZZ_[HSD]",1665 "^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",1666 "^SSUBL(BT|TB)_ZZZ_[HSD]")>;1667 1668// Arithmetic, complex1669def : InstRW<[N2Write_2c_1V],1670 (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]",1671 "^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]",1672 "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]",1673 "^[SU]Q(ADD|SUB)_ZI_[BHSD]",1674 "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]",1675 "^(UQSUB|UQSUBR)_ZPmZ_[BHSD]")>;1676 1677// Arithmetic, large integer1678def : InstRW<[N2Write_2c_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]$")>;1679 1680// Arithmetic, pairwise add1681def : InstRW<[N2Write_2c_1V], (instregex "^ADDP_ZPmZ_[BHSD]$")>;1682 1683// Arithmetic, pairwise add and accum long1684def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]ADALP_ZPmZ_[HSD]$")>;1685 1686// Arithmetic, shift1687def : InstRW<[N2Write_2c_1V1],1688 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",1689 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",1690 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",1691 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",1692 "^(ASR|LSL|LSR)_ZZI_[BHSD]",1693 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",1694 "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>;1695 1696// Arithmetic, shift and accumulate1697def : InstRW<[N2Write_4c_1V1],1698 (instregex "^(SRSRA|SSRA|URSRA|USRA)_ZZI_[BHSD]$")>;1699 1700// Arithmetic, shift by immediate1701// Arithmetic, shift by immediate and insert1702def : InstRW<[N2Write_2c_1V1],1703 (instregex "^(SHRNB|SHRNT|SSHLLB|SSHLLT|USHLLB|USHLLT|SLI|SRI)_ZZI_[BHSD]$")>;1704 1705// Arithmetic, shift complex1706def : InstRW<[N2Write_4c_1V1],1707 (instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]",1708 "^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]",1709 "^[SU]QR?SHL_ZPZZ_[BHSD]",1710 "^(SQSHL|SQSHLU|UQSHL)_(ZPmI|ZPZI)_[BHSD]",1711 "^SQSHRU?N[BT]_ZZI_[BHS]",1712 "^UQR?SHRN[BT]_ZZI_[BHS]")>;1713 1714// Arithmetic, shift right for divide1715def : InstRW<[N2Write_4c_1V1], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;1716 1717// Arithmetic, shift rounding1718def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]",1719 "^[SU]RSHL_ZPZZ_[BHSD]",1720 "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>;1721 1722// Bit manipulation1723def : InstRW<[N2Write_6c_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>;1724 1725// Bitwise select1726def : InstRW<[N2Write_2c_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ$")>;1727 1728// Count/reverse bits1729def : InstRW<[N2Write_2c_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;1730 1731// Broadcast logical bitmask immediate to vector1732def : InstRW<[N2Write_2c_1V], (instrs DUPM_ZI)>;1733 1734// Compare and set flags1735def : InstRW<[N2Write_4c_1V0_1M],1736 (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]$",1737 "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]$")>;1738 1739// Complex add1740def : InstRW<[N2Write_2c_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]$")>;1741 1742// Complex dot product 8-bit element1743def : InstRW<[N2Write_3c_1V], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;1744 1745// Complex dot product 16-bit element1746def : InstRW<[N2Write_4c_1V0], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;1747 1748// Complex multiply-add B, H, S element size1749def : InstRW<[N2Write_4c_1V0], (instregex "^CMLA_ZZZ_[BHS]$",1750 "^CMLA_ZZZI_[HS]$")>;1751 1752// Complex multiply-add D element size1753def : InstRW<[N2Write_5c_2V0], (instrs CMLA_ZZZ_D)>;1754 1755// Conditional extract operations, scalar form1756def : InstRW<[N2Write_8c_1M0_1V1_1V], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>;1757 1758// Conditional extract operations, SIMD&FP scalar and vector forms1759def : InstRW<[N2Write_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]$",1760 "^COMPACT_ZPZ_[SD]$",1761 "^SPLICE_ZPZZ?_[BHSD]$")>;1762 1763// Convert to floating point, 64b to float or convert to double1764def : InstRW<[N2Write_3c_1V0], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",1765 "^[SU]CVTF_ZPmZ_StoD")>;1766 1767// Convert to floating point, 32b to single or half1768def : InstRW<[N2Write_4c_2V0], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;1769 1770// Convert to floating point, 16b to half1771def : InstRW<[N2Write_6c_4V0], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;1772 1773// Copy, scalar1774def : InstRW<[N2Write_5c_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]$")>;1775 1776// Copy, scalar SIMD&FP or imm1777def : InstRW<[N2Write_2c_1V], (instregex "^CPY_ZPm[IV]_[BHSD]$",1778 "^CPY_ZPzI_[BHSD]$")>;1779 1780// Divides, 32 bit1781def : InstRW<[N2Write_12c_1V0], (instregex "^[SU]DIVR?_ZPmZ_S",1782 "^[SU]DIV_ZPZZ_S")>;1783 1784// Divides, 64 bit1785def : InstRW<[N2Write_20c_1V0], (instregex "^[SU]DIVR?_ZPmZ_D",1786 "^[SU]DIV_ZPZZ_D")>;1787 1788// Dot product, 8 bit1789def : InstRW<[N2Write_3c_1V], (instregex "^[SU]DOT_ZZZI?_BtoS$")>;1790 1791// Dot product, 8 bit, using signed and unsigned integers1792def : InstRW<[N2Write_3c_1V], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;1793 1794// Dot product, 16 bit1795def : InstRW<[N2Write_4c_1V0], (instregex "^[SU]DOT_ZZZI?_HtoD$")>;1796 1797// Duplicate, immediate and indexed form1798def : InstRW<[N2Write_2c_1V], (instregex "^DUP_ZI_[BHSD]$",1799 "^DUP_ZZI_[BHSDQ]$")>;1800 1801// Duplicate, scalar form1802def : InstRW<[N2Write_3c_1M0], (instregex "^DUP_ZR_[BHSD]$")>;1803 1804// Extend, sign or zero1805def : InstRW<[N2Write_2c_1V1], (instregex "^[SU]XTB_ZPmZ_[HSD]",1806 "^[SU]XTH_ZPmZ_[SD]",1807 "^[SU]XTW_ZPmZ_[D]")>;1808 1809// Extract1810def : InstRW<[N2Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;1811 1812// Extract narrow saturating1813def : InstRW<[N2Write_4c_1V1], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]$",1814 "^SQXTUN[BT]_ZZ_[BHS]$")>;1815 1816// Extract/insert operation, SIMD and FP scalar form1817def : InstRW<[N2Write_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]$",1818 "^INSR_ZV_[BHSD]$")>;1819 1820// Extract/insert operation, scalar1821def : InstRW<[N2Write_5c_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]$",1822 "^INSR_ZR_[BHSD]$")>;1823 1824// Histogram operations1825def : InstRW<[N2Write_2c_1V], (instregex "^HISTCNT_ZPzZZ_[SD]$",1826 "^HISTSEG_ZZZ$")>;1827 1828// Horizontal operations, B, H, S form, immediate operands only1829def : InstRW<[N2Write_4c_1V0], (instregex "^INDEX_II_[BHS]$")>;1830 1831// Horizontal operations, B, H, S form, scalar, immediate operands/ scalar1832// operands only / immediate, scalar operands1833def : InstRW<[N2Write_7c_1M0_1V0], (instregex "^INDEX_(IR|RI|RR)_[BHS]$")>;1834 1835// Horizontal operations, D form, immediate operands only1836def : InstRW<[N2Write_5c_2V0], (instrs INDEX_II_D)>;1837 1838// Horizontal operations, D form, scalar, immediate operands)/ scalar operands1839// only / immediate, scalar operands1840def : InstRW<[N2Write_8c_2M0_2V0], (instregex "^INDEX_(IR|RI|RR)_D$")>;1841 1842// Logical1843def : InstRW<[N2Write_2c_1V],1844 (instregex "^(AND|EOR|ORR)_ZI",1845 "^(AND|BIC|EOR|ORR)_ZZZ",1846 "^EOR(BT|TB)_ZZZ_[BHSD]",1847 "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]",1848 "^NOT_ZPmZ_[BHSD]")>;1849 1850// Max/min, basic and pairwise1851def : InstRW<[N2Write_2c_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",1852 "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]",1853 "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>;1854 1855// Matching operations1856def : InstRW<[N2Write_2c_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]$")>;1857 1858// Matrix multiply-accumulate1859def : InstRW<[N2Write_3c_1V], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;1860 1861// Move prefix1862def : InstRW<[N2Write_2c_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$",1863 "^MOVPRFX_ZZ$")>;1864 1865// Multiply, B, H, S element size1866def : InstRW<[N2Write_4c_1V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]",1867 "^MUL_ZPZZ_[BHS]",1868 "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]",1869 "^[SU]MULH_ZPZZ_[BHS]")>;1870 1871// Multiply, D element size1872def : InstRW<[N2Write_5c_2V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D",1873 "^MUL_ZPZZ_D",1874 "^[SU]MULH_(ZPmZ|ZZZ)_D",1875 "^[SU]MULH_ZPZZ_D")>;1876 1877// Multiply long1878def : InstRW<[N2Write_4c_1V0], (instregex "^[SU]MULL[BT]_ZZZI_[SD]$",1879 "^[SU]MULL[BT]_ZZZ_[HSD]$")>;1880 1881// Multiply accumulate, B, H, S element size1882def : InstRW<[N2Write_4c_1V0], (instregex "^ML[AS]_ZZZI_[BHS]$",1883 "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_[BHS]")>;1884 1885// Multiply accumulate, D element size1886def : InstRW<[N2Write_5c_2V0], (instregex "^ML[AS]_ZZZI_D$",1887 "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_D")>;1888 1889// Multiply accumulate long1890def : InstRW<[N2Write_4c_1V0], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]$",1891 "^[SU]ML[AS]L[BT]_ZZZI_[SD]$")>;1892 1893// Multiply accumulate saturating doubling long regular1894def : InstRW<[N2Write_4c_1V0], (instregex "^SQDML[AS](LB|LT|LBT)_ZZZ_[HSD]$",1895 "^SQDML[AS](LB|LT)_ZZZI_[SD]$")>;1896 1897// Multiply saturating doubling high, B, H, S element size1898def : InstRW<[N2Write_4c_1V0], (instregex "^SQDMULH_ZZZ_[BHS]$",1899 "^SQDMULH_ZZZI_[HS]$")>;1900 1901// Multiply saturating doubling high, D element size1902def : InstRW<[N2Write_5c_2V0], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>;1903 1904// Multiply saturating doubling long1905def : InstRW<[N2Write_4c_1V0], (instregex "^SQDMULL[BT]_ZZZ_[HSD]$",1906 "^SQDMULL[BT]_ZZZI_[SD]$")>;1907 1908// Multiply saturating rounding doubling regular/complex accumulate, B, H, S1909// element size1910def : InstRW<[N2Write_4c_1V0], (instregex "^SQRDML[AS]H_ZZZ_[BHS]$",1911 "^SQRDCMLAH_ZZZ_[BHS]$",1912 "^SQRDML[AS]H_ZZZI_[HS]$",1913 "^SQRDCMLAH_ZZZI_[HS]$")>;1914 1915// Multiply saturating rounding doubling regular/complex accumulate, D element1916// size1917def : InstRW<[N2Write_5c_2V0], (instregex "^SQRDML[AS]H_ZZZI?_D$",1918 "^SQRDCMLAH_ZZZ_D$")>;1919 1920// Multiply saturating rounding doubling regular/complex, B, H, S element size1921def : InstRW<[N2Write_4c_1V0], (instregex "^SQRDMULH_ZZZ_[BHS]$",1922 "^SQRDMULH_ZZZI_[HS]$")>;1923 1924// Multiply saturating rounding doubling regular/complex, D element size1925def : InstRW<[N2Write_5c_2V0], (instregex "^SQRDMULH_ZZZI?_D$")>;1926 1927// Multiply/multiply long, (8x8) polynomial1928def : InstRW<[N2Write_2c_1V0], (instregex "^PMUL_ZZZ_B$",1929 "^PMULL[BT]_ZZZ_[HDQ]$")>;1930 1931// Predicate counting vector1932def : InstRW<[N2Write_2c_1V0],1933 (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)[HWD]_ZPiI$")>;1934 1935// Reciprocal estimate1936def : InstRW<[N2Write_4c_2V0], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;1937 1938// Reduction, arithmetic, B form1939def : InstRW<[N2Write_11c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;1940 1941// Reduction, arithmetic, H form1942def : InstRW<[N2Write_9c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;1943 1944// Reduction, arithmetic, S form1945def : InstRW<[N2Write_8c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;1946 1947// Reduction, arithmetic, D form1948def : InstRW<[N2Write_8c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;1949 1950// Reduction, logical1951def : InstRW<[N2Write_6c_1V_1V1], (instregex "^(ANDV|EORV|ORV)_VPZ_[BHSD]$")>;1952 1953// Reverse, vector1954def : InstRW<[N2Write_2c_1V], (instregex "^REV_ZZ_[BHSD]$",1955 "^REVB_ZPmZ_[HSD]$",1956 "^REVH_ZPmZ_[SD]$",1957 "^REVW_ZPmZ_D$")>;1958 1959// Select, vector form1960def : InstRW<[N2Write_2c_1V], (instregex "^SEL_ZPZZ_[BHSD]$")>;1961 1962// Table lookup1963def : InstRW<[N2Write_2c_1V], (instregex "^TBL_ZZZZ?_[BHSD]$")>;1964 1965// Table lookup extension1966def : InstRW<[N2Write_2c_1V], (instregex "^TBX_ZZZ_[BHSD]$")>;1967 1968// Transpose, vector form1969def : InstRW<[N2Write_2c_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]$")>;1970 1971// Unpack and extend1972def : InstRW<[N2Write_2c_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]$")>;1973 1974// Zip/unzip1975def : InstRW<[N2Write_2c_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>;1976 1977// SVE floating-point instructions1978// -----------------------------------------------------------------------------1979 1980// Floating point absolute value/difference1981def : InstRW<[N2Write_2c_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]",1982 "^FABD_ZPZZ_[HSD]",1983 "^FABS_ZPmZ_[HSD]")>;1984 1985// Floating point arithmetic1986def : InstRW<[N2Write_2c_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",1987 "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",1988 "^FADDP_ZPmZZ_[HSD]",1989 "^FNEG_ZPmZ_[HSD]",1990 "^FSUBR_ZPm[IZ]_[HSD]",1991 "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;1992 1993// Floating point associative add, F161994def : InstRW<[N2Write_10c_1V1], (instrs FADDA_VPZ_H)>;1995 1996// Floating point associative add, F321997def : InstRW<[N2Write_6c_1V1], (instrs FADDA_VPZ_S)>;1998 1999// Floating point associative add, F642000def : InstRW<[N2Write_4c_1V], (instrs FADDA_VPZ_D)>;2001 2002// Floating point compare2003def : InstRW<[N2Write_2c_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]$",2004 "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]$",2005 "^FCM(LE|LT)_PPzZ0_[HSD]$",2006 "^FCMUO_PPzZZ_[HSD]$")>;2007 2008// Floating point complex add2009def : InstRW<[N2Write_3c_1V], (instregex "^FCADD_ZPmZ_[HSD]$")>;2010 2011// Floating point complex multiply add2012def : InstRW<[N2Write_5c_1V], (instregex "^FCMLA_ZPmZZ_[HSD]$",2013 "^FCMLA_ZZZI_[HS]$")>;2014 2015// Floating point convert, long or narrow (F16 to F32 or F32 to F16)2016def : InstRW<[N2Write_4c_2V0], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",2017 "^FCVTLT_ZPmZ_HtoS",2018 "^FCVTNT_ZPmZ_StoH")>;2019 2020// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F322021// or F64 to F16)2022def : InstRW<[N2Write_3c_1V0], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",2023 "^FCVTLT_ZPmZ_StoD",2024 "^FCVTNT_ZPmZ_DtoS")>;2025 2026// Floating point convert, round to odd2027def : InstRW<[N2Write_3c_1V0], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>;2028 2029// Floating point base2 log, F162030def : InstRW<[N2Write_6c_4V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;2031 2032// Floating point base2 log, F322033def : InstRW<[N2Write_4c_2V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;2034 2035// Floating point base2 log, F642036def : InstRW<[N2Write_3c_1V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;2037 2038// Floating point convert to integer, F162039def : InstRW<[N2Write_6c_4V0], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;2040 2041// Floating point convert to integer, F322042def : InstRW<[N2Write_4c_2V0], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;2043 2044// Floating point convert to integer, F642045def : InstRW<[N2Write_3c_1V0],2046 (instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>;2047 2048// Floating point copy2049def : InstRW<[N2Write_2c_1V], (instregex "^FCPY_ZPmI_[HSD]$",2050 "^FDUP_ZI_[HSD]$")>;2051 2052// Floating point divide, F162053def : InstRW<[N2Write_13c_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;2054 2055// Floating point divide, F322056def : InstRW<[N2Write_10c_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;2057 2058// Floating point divide, F642059def : InstRW<[N2Write_15c_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;2060 2061// Floating point min/max pairwise2062def : InstRW<[N2Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;2063 2064// Floating point min/max2065def : InstRW<[N2Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",2066 "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;2067 2068// Floating point multiply2069def : InstRW<[N2Write_3c_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",2070 "^FMULX_ZPZZ_[HSD]",2071 "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",2072 "^FMUL_ZPZ[IZ]_[HSD]")>;2073 2074// Floating point multiply accumulate2075def : InstRW<[N2Write_4c_1V], (instregex "^F(N?M(AD|SB)|N?ML[AS])_ZPmZZ_[HSD]$",2076 "^FN?ML[AS]_ZPZZZ_[HSD]",2077 "^FML[AS]_ZZZI_[HSD]$")>;2078 2079// Floating point multiply add/sub accumulate long2080def : InstRW<[N2Write_4c_1V], (instregex "^FML[AS]L[BT]_ZZZI?_SHH$")>;2081 2082// Floating point reciprocal estimate, F162083def : InstRW<[N2Write_6c_4V0], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;2084 2085// Floating point reciprocal estimate, F322086def : InstRW<[N2Write_4c_2V0], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>;2087 2088// Floating point reciprocal estimate, F642089def : InstRW<[N2Write_3c_1V0], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>;2090 2091// Floating point reciprocal step2092def : InstRW<[N2Write_4c_1V0], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]$")>;2093 2094// Floating point reduction, F162095def : InstRW<[N2Write_6c_2V],2096 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H$")>;2097 2098// Floating point reduction, F322099def : InstRW<[N2Write_4c_1V],2100 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S$")>;2101 2102// Floating point reduction, F642103def : InstRW<[N2Write_2c_1V],2104 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D$")>;2105 2106// Floating point round to integral, F162107def : InstRW<[N2Write_6c_4V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;2108 2109// Floating point round to integral, F322110def : InstRW<[N2Write_4c_2V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;2111 2112// Floating point round to integral, F642113def : InstRW<[N2Write_3c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;2114 2115// Floating point square root, F162116def : InstRW<[N2Write_13c_1V0], (instregex "^FSQRT_ZPmZ_H")>;2117 2118// Floating point square root, F322119def : InstRW<[N2Write_10c_1V0], (instregex "^FSQRT_ZPmZ_S")>;2120 2121// Floating point square root, F642122def : InstRW<[N2Write_16c_1V0], (instregex "^FSQRT_ZPmZ_D")>;2123 2124// Floating point trigonometric exponentiation2125def : InstRW<[N2Write_3c_1V1], (instregex "^FEXPA_ZZ_[HSD]$")>;2126 2127// Floating point trigonometric multiply add2128def : InstRW<[N2Write_4c_1V], (instregex "^FTMAD_ZZI_[HSD]$")>;2129 2130// Floating point trigonometric, miscellaneous2131def : InstRW<[N2Write_3c_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]$")>;2132 2133// SVE BFloat16 (BF16) instructions2134// -----------------------------------------------------------------------------2135 2136// Convert, F32 to BF162137def : InstRW<[N2Write_3c_1V0], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;2138 2139// Dot product2140def : InstRW<[N2Write_4c_1V], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;2141 2142// Matrix multiply accumulate2143def : InstRW<[N2Write_5c_1V], (instrs BFMMLA_ZZZ_HtoS)>;2144 2145// Multiply accumulate long2146def : InstRW<[N2Write_4c_1V], (instregex "^BFMLAL[BT]_ZZZ(I)?$")>;2147 2148// SVE Load instructions2149// -----------------------------------------------------------------------------2150 2151// Load vector2152def : InstRW<[N2Write_6c_1L], (instrs LDR_ZXI)>;2153 2154// Load predicate2155def : InstRW<[N2Write_6c_1L_1M], (instrs LDR_PXI)>;2156 2157// Contiguous load, scalar + imm2158def : InstRW<[N2Write_6c_1L], (instregex "^LD1[BHWD]_IMM$",2159 "^LD1S?B_[HSD]_IMM$",2160 "^LD1S?H_[SD]_IMM$",2161 "^LD1S?W_D_IMM$" )>;2162// Contiguous load, scalar + scalar2163def : InstRW<[N2Write_6c_1L01], (instregex "^LD1[BHWD]$",2164 "^LD1S?B_[HSD]$",2165 "^LD1S?H_[SD]$",2166 "^LD1S?W_D$" )>;2167 2168// Contiguous load broadcast, scalar + imm2169def : InstRW<[N2Write_6c_1L], (instregex "^LD1R[BHWD]_IMM$",2170 "^LD1RSW_IMM$",2171 "^LD1RS?B_[HSD]_IMM$",2172 "^LD1RS?H_[SD]_IMM$",2173 "^LD1RS?W_D_IMM$",2174 "^LD1RQ_[BHWD]_IMM$")>;2175 2176// Contiguous load broadcast, scalar + scalar2177def : InstRW<[N2Write_6c_1L], (instregex "^LD1RQ_[BHWD]$")>;2178 2179// Non temporal load, scalar + imm2180def : InstRW<[N2Write_6c_1L], (instregex "^LDNT1[BHWD]_ZRI$")>;2181 2182// Non temporal load, scalar + scalar2183def : InstRW<[N2Write_6c_1L_1S], (instregex "^LDNT1[BHWD]_ZRR$")>;2184 2185// Non temporal gather load, vector + scalar 32-bit element size2186def : InstRW<[N2Write_9c_1L_1V], (instregex "^LDNT1[BHW]_ZZR_S$",2187 "^LDNT1S[BH]_ZZR_S$")>;2188 2189// Non temporal gather load, vector + scalar 64-bit element size2190def : InstRW<[N2Write_10c_2L_2V1], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;2191def : InstRW<[N2Write_10c_2L_2V1], (instrs LDNT1D_ZZR_D)>;2192 2193// Contiguous first faulting load, scalar + scalar2194def : InstRW<[N2Write_6c_1L_1S], (instregex "^LDFF1[BHWD]$",2195 "^LDFF1S?B_[HSD]$",2196 "^LDFF1S?H_[SD]$",2197 "^LDFF1S?W_D$")>;2198 2199// Contiguous non faulting load, scalar + imm2200def : InstRW<[N2Write_6c_1L], (instregex "^LDNF1[BHWD]_IMM$",2201 "^LDNF1S?B_[HSD]_IMM$",2202 "^LDNF1S?H_[SD]_IMM$",2203 "^LDNF1S?W_D_IMM$")>;2204 2205// Contiguous Load two structures to two vectors, scalar + imm2206def : InstRW<[N2Write_8c_1L_1V], (instregex "^LD2[BHWD]_IMM$")>;2207 2208// Contiguous Load two structures to two vectors, scalar + scalar2209def : InstRW<[N2Write_9c_1L_1V], (instregex "^LD2[BHWD]$")>;2210 2211// Contiguous Load three structures to three vectors, scalar + imm2212def : InstRW<[N2Write_9c_1L_1V], (instregex "^LD3[BHWD]_IMM$")>;2213 2214// Contiguous Load three structures to three vectors, scalar + scalar2215def : InstRW<[N2Write_10c_1V_1L_1S], (instregex "^LD3[BHWD]$")>;2216 2217// Contiguous Load four structures to four vectors, scalar + imm2218def : InstRW<[N2Write_9c_2L_2V], (instregex "^LD4[BHWD]_IMM$")>;2219 2220// Contiguous Load four structures to four vectors, scalar + scalar2221def : InstRW<[N2Write_10c_2L_2V_2S], (instregex "^LD4[BHWD]$")>;2222 2223// Gather load, vector + imm, 32-bit element size2224def : InstRW<[N2Write_9c_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",2225 "^GLD(FF)?1W_IMM$")>;2226 2227// Gather load, vector + imm, 64-bit element size2228def : InstRW<[N2Write_9c_2L_2V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",2229 "^GLD(FF)?1D_IMM$")>;2230 2231// Gather load, 64-bit element size2232def : InstRW<[N2Write_9c_2L_2V],2233 (instregex "^GLD(FF)?1S?[BHW]_D_[SU]XTW(_SCALED)?$",2234 "^GLD(FF)?1S?[BHW]_D(_SCALED)?$",2235 "^GLD(FF)?1D_[SU]XTW(_SCALED)?$",2236 "^GLD(FF)?1D(_SCALED)?$")>;2237 2238// Gather load, 32-bit scaled offset2239def : InstRW<[N2Write_10c_2L_2V],2240 (instregex "^GLD(FF)?1S?[HW]_S_[SU]XTW_SCALED$",2241 "^GLD(FF)?1W_[SU]XTW_SCALED")>;2242 2243// Gather load, 32-bit unpacked unscaled offset2244def : InstRW<[N2Write_9c_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",2245 "^GLD(FF)?1W_[SU]XTW$")>;2246 2247// SVE Store instructions2248// -----------------------------------------------------------------------------2249 2250// Store from predicate reg2251def : InstRW<[N2Write_1c_1L01], (instrs STR_PXI)>;2252 2253// Store from vector reg2254def : InstRW<[N2Write_2c_1L01_1V], (instrs STR_ZXI)>;2255 2256// Contiguous store, scalar + imm2257def : InstRW<[N2Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$",2258 "^ST1B_[HSD]_IMM$",2259 "^ST1H_[SD]_IMM$",2260 "^ST1W_D_IMM$")>;2261 2262// Contiguous store, scalar + scalar2263def : InstRW<[N2Write_2c_1L01_1S_1V], (instregex "^ST1H(_[SD])?$")>;2264def : InstRW<[N2Write_2c_1L01_1V], (instregex "^ST1[BWD]$",2265 "^ST1B_[HSD]$",2266 "^ST1W_D$")>;2267 2268// Contiguous store two structures from two vectors, scalar + imm2269def : InstRW<[N2Write_4c_1L01_1V], (instregex "^ST2[BHWD]_IMM$")>;2270 2271// Contiguous store two structures from two vectors, scalar + scalar2272def : InstRW<[N2Write_4c_1L01_1S_1V], (instrs ST2H)>;2273 2274// Contiguous store two structures from two vectors, scalar + scalar2275def : InstRW<[N2Write_4c_1L01_1V], (instregex "^ST2[BWD]$")>;2276 2277// Contiguous store three structures from three vectors, scalar + imm2278def : InstRW<[N2Write_7c_5L01_5V], (instregex "^ST3[BHWD]_IMM$")>;2279 2280// Contiguous store three structures from three vectors, scalar + scalar2281def : InstRW<[N2Write_7c_5L01_5S_5V], (instrs ST3H)>;2282 2283// Contiguous store three structures from three vectors, scalar + scalar2284def : InstRW<[N2Write_7c_5L01_5S_5V], (instregex "^ST3[BWD]$")>;2285 2286// Contiguous store four structures from four vectors, scalar + imm2287def : InstRW<[N2Write_11c_9L01_9V], (instregex "^ST4[BHWD]_IMM$")>;2288 2289// Contiguous store four structures from four vectors, scalar + scalar2290def : InstRW<[N2Write_11c_9L01_9S_9V], (instrs ST4H)>;2291 2292// Contiguous store four structures from four vectors, scalar + scalar2293def : InstRW<[N2Write_11c_9L01_9S_9V], (instregex "^ST4[BWD]$")>;2294 2295// Non temporal store, scalar + imm2296def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$")>;2297 2298// Non temporal store, scalar + scalar2299def : InstRW<[N2Write_2c_1L01_1S_1V], (instrs STNT1H_ZRR)>;2300def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STNT1[BWD]_ZRR$")>;2301 2302// Scatter non temporal store, vector + scalar 32-bit element size2303def : InstRW<[N2Write_4c_2L01_2V], (instregex "^STNT1[BHW]_ZZR_S")>;2304 2305// Scatter non temporal store, vector + scalar 64-bit element size2306def : InstRW<[N2Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZZR_D")>;2307 2308// Scatter store vector + imm 32-bit element size2309def : InstRW<[N2Write_4c_2L01_2V], (instregex "^SST1[BH]_S_IMM$",2310 "^SST1W_IMM$")>;2311 2312// Scatter store vector + imm 64-bit element size2313def : InstRW<[N2Write_2c_1L01_1V], (instregex "^SST1[BHW]_D_IMM$",2314 "^SST1D_IMM$")>;2315 2316// Scatter store, 32-bit scaled offset2317def : InstRW<[N2Write_4c_2L01_2V],2318 (instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>;2319 2320// Scatter store, 32-bit unpacked unscaled offset2321def : InstRW<[N2Write_2c_1L01_1V], (instregex "^SST1[BHW]_D_[SU]XTW$",2322 "^SST1D_[SU]XTW$")>;2323 2324// Scatter store, 32-bit unpacked scaled offset2325def : InstRW<[N2Write_2c_1L01_1V], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",2326 "^SST1D_[SU]XTW_SCALED$")>;2327 2328// Scatter store, 32-bit unscaled offset2329def : InstRW<[N2Write_4c_2L01_2V], (instregex "^SST1[BH]_S_[SU]XTW$",2330 "^SST1W_[SU]XTW$")>;2331 2332// Scatter store, 64-bit scaled offset2333def : InstRW<[N2Write_2c_1L01_1V], (instregex "^SST1[HW]_D_SCALED$",2334 "^SST1D_SCALED$")>;2335 2336// Scatter store, 64-bit unscaled offset2337def : InstRW<[N2Write_2c_1L01_1V], (instregex "^SST1[BHW]_D$",2338 "^SST1D$")>;2339 2340// SVE Miscellaneous instructions2341// -----------------------------------------------------------------------------2342 2343// Read first fault register, unpredicated2344def : InstRW<[N2Write_2c_1M0], (instrs RDFFR_P)>;2345 2346// Read first fault register, predicated2347def : InstRW<[N2Write_3c_1M0_1M], (instrs RDFFR_PPz)>;2348 2349// Read first fault register and set flags2350def : InstRW<[N2Write_4c_2M0_2M], (instrs RDFFRS_PPz)>;2351 2352// Set first fault register2353// Write to first fault register2354def : InstRW<[N2Write_2c_1M0], (instrs SETFFR, WRFFR)>;2355 2356// Prefetch2357def : InstRW<[N2Write_4c_1L], (instregex "^PRF[BHWD]")>;2358 2359// SVE Cryptographic instructions2360// -----------------------------------------------------------------------------2361 2362// Crypto AES ops2363def : InstRW<[N2Write_2c_1V], (instregex "^AES[DE]_ZZZ_B$",2364 "^AESI?MC_ZZ_B$")>;2365 2366// Crypto SHA3 ops2367def : InstRW<[N2Write_2c_1V0], (instregex "^(BCAX|EOR3)_ZZZZ$",2368 "^RAX1_ZZZ_D$",2369 "^XAR_ZZZI_[BHSD]$")>;2370 2371// Crypto SM4 ops2372def : InstRW<[N2Write_4c_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;2373 2374}2375