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1//=- AArch64SchedNeoverseN3.td - NeoverseN3 Scheduling Defs --*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the scheduling model for the Arm Neoverse N3 processors.10//11//===----------------------------------------------------------------------===//12 13def NeoverseN3Model : SchedMachineModel {14 let IssueWidth = 5; // Micro-ops dispatched at a time.15 let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer. NOTE: Copied from N2.16 let LoadLatency = 4; // Optimistic load latency.17 let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.18 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.19 let CompleteModel = 1;20 21 list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,22 [HasSVE2p1, HasSVEB16B16, HasPAuthLR, HasCPA, HasCSSC]);23}24 25//===----------------------------------------------------------------------===//26// Define each kind of processor resource and number available on Neoverse N3.27// Instructions are first fetched and then decoded into internal Macro-OPerations28// (MOPs). From there, the MOPs proceed through register renaming and dispatch stages.29// A MOP can be split into two Micro-OPerations (µOPs) further down the pipeline30// after the decode stage. Once dispatched, µOPs wait for their operands and issue31// out-of-order to one of thirteen issue pipelines. Each issue pipeline can accept32// one µOP per cycle.33 34let SchedModel = NeoverseN3Model in {35 36// Define the (13) issue ports.37def N3UnitB : ProcResource<2>; // Branch 0/138def N3UnitS : ProcResource<2>; // Integer Single-Cycle 0/139def N3UnitM0 : ProcResource<1>; // Integer Single/Multi-Cycle 040def N3UnitM1 : ProcResource<1>; // Integer Single/Multi-Cycle 141def N3UnitL01 : ProcResource<2>; // Load/Store 0/142def N3UnitL2 : ProcResource<1>; // Load 243def N3UnitD : ProcResource<2>; // Integer Store data 0/144def N3UnitV0 : ProcResource<1>; // FP/ASIMD 045def N3UnitV1 : ProcResource<1>; // FP/ASIMD 146 47def N3UnitV : ProcResGroup<[N3UnitV0, N3UnitV1]>;48def N3UnitM : ProcResGroup<[N3UnitM0, N3UnitM1]>;49def N3UnitL : ProcResGroup<[N3UnitL01, N3UnitL2]>;50def N3UnitI : ProcResGroup<[N3UnitS, N3UnitM0, N3UnitM1]>;51 52// Group required for modelling SVE gather loads throughput53def N3UnitVL : ProcResGroup<[N3UnitL01, N3UnitV0, N3UnitV1]>;54// Unused group to fix: "error: proc resource group overlaps with N3UnitVL but55// no supergroup contains both."56def : ProcResGroup<[N3UnitL01, N3UnitL2, N3UnitV0, N3UnitV1]>;57 58//===----------------------------------------------------------------------===//59 60def : ReadAdvance<ReadI, 0>;61def : ReadAdvance<ReadISReg, 0>;62def : ReadAdvance<ReadIEReg, 0>;63def : ReadAdvance<ReadIM, 0>;64def : ReadAdvance<ReadIMA, 0>;65def : ReadAdvance<ReadID, 0>;66def : ReadAdvance<ReadExtrHi, 0>;67def : ReadAdvance<ReadAdrBase, 0>;68def : ReadAdvance<ReadST, 0>;69def : ReadAdvance<ReadVLD, 0>;70 71// NOTE: Copied from N2.72def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }73def : WriteRes<WriteBarrier, []> { let Latency = 1; }74def : WriteRes<WriteHint, []> { let Latency = 1; }75 76//===----------------------------------------------------------------------===//77// Define customized scheduler read/write types specific to the Neoverse N3.78 79//===----------------------------------------------------------------------===//80// Define generic 0 micro-op types81 82def N3Write_0c : SchedWriteRes<[]> {83 let Latency = 0;84 let NumMicroOps = 1;85}86 87def N3Write_4c : SchedWriteRes<[]> {88 let Latency = 4;89 let NumMicroOps = 0;90}91 92//===----------------------------------------------------------------------===//93// Define generic 1 micro-op types94 95def N3Write_1c_1B : SchedWriteRes<[N3UnitB]> { let Latency = 1; }96def N3Write_1c_1I : SchedWriteRes<[N3UnitI]> { let Latency = 1; }97def N3Write_2c_1M : SchedWriteRes<[N3UnitM]> { let Latency = 2; }98def N3Write_2c_1M0 : SchedWriteRes<[N3UnitM0]> { let Latency = 2; }99def N3Write_3c_1M : SchedWriteRes<[N3UnitM]> { let Latency = 3; }100def N3Write_1c_1M : SchedWriteRes<[N3UnitM]> { let Latency = 1; }101def N3Write_4c_1M : SchedWriteRes<[N3UnitM]> { let Latency = 4; }102def N3Write_1c_1S : SchedWriteRes<[N3UnitS]> { let Latency = 1; }103def N3Write_4c_1L : SchedWriteRes<[N3UnitL]> { let Latency = 4; }104def N3Write_2c_1V : SchedWriteRes<[N3UnitV]> { let Latency = 2; }105def N3Write_5c_1V0 : SchedWriteRes<[N3UnitV0]> { let Latency = 5; }106def N3Write_7c_1V0 : SchedWriteRes<[N3UnitV0]> { let Latency = 7; }107def N3Write_12c_1V0 : SchedWriteRes<[N3UnitV0]> { let Latency = 12; }108def N3Write_3c_1V : SchedWriteRes<[N3UnitV]> { let Latency = 3; }109def N3Write_4c_1V : SchedWriteRes<[N3UnitV]> { let Latency = 4; }110def N3Write_3c_1V0 : SchedWriteRes<[N3UnitV0]> { let Latency = 3; }111def N3Write_3c_1M0 : SchedWriteRes<[N3UnitM0]> { let Latency = 3; }112def N3Write_6c_1L : SchedWriteRes<[N3UnitL]> { let Latency = 6; }113def N3Write_4c_1V1 : SchedWriteRes<[N3UnitV1]> { let Latency = 4; }114def N3Write_3c_1V1 : SchedWriteRes<[N3UnitV1]> { let Latency = 3; }115def N3Write_4c_1V0 : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }116def N3Write_2c_1V0 : SchedWriteRes<[N3UnitV0]> { let Latency = 2; }117def N3Write_2c_1V1 : SchedWriteRes<[N3UnitV1]> { let Latency = 2; }118def N3Write_5c_1V : SchedWriteRes<[N3UnitV]> { let Latency = 5; }119def N3Write_1c_1L01 : SchedWriteRes<[N3UnitL01]> { let Latency = 1; }120 121def N3Write_12c_1M0_12 : SchedWriteRes<[N3UnitM0]> {122 let Latency = 12;123 let ReleaseAtCycles = [12];124}125 126def N3Write_20c_1M0_20 : SchedWriteRes<[N3UnitM0]> {127 let Latency = 20;128 let ReleaseAtCycles = [20];129}130 131//===----------------------------------------------------------------------===//132// Define generic 2 micro-op types133 134def N3Write_1c_1B_1S : SchedWriteRes<[N3UnitB, N3UnitS]> {135 let Latency = 1;136 let NumMicroOps = 2;137}138 139def N3Write_2c_1M_1B : SchedWriteRes<[N3UnitM, N3UnitB]> {140 let Latency = 2;141 let NumMicroOps = 2;142}143 144def N3Write_5c_1L_1S : SchedWriteRes<[N3UnitL, N3UnitS]> {145 let Latency = 5;146 let NumMicroOps = 2;147}148 149def N3Write_4c_2L : SchedWriteRes<[N3UnitL, N3UnitL]> {150 let Latency = 4;151 let NumMicroOps = 2;152}153 154def N3Write_1c_1L01_1D : SchedWriteRes<[N3UnitL01, N3UnitD]> {155 let Latency = 1;156 let NumMicroOps = 2;157}158 159def N3Write_5c_1L_1I : SchedWriteRes<[N3UnitL, N3UnitI]> {160 let Latency = 5;161 let NumMicroOps = 2;162}163 164def N3Write_6c_2L : SchedWriteRes<[N3UnitL, N3UnitL]> {165 let Latency = 6;166 let NumMicroOps = 2;167}168 169def N3Write_2c_1L01_1V : SchedWriteRes<[N3UnitL01, N3UnitV]> {170 let Latency = 2;171 let NumMicroOps = 2;172}173 174def N3Write_6c_2V1 : SchedWriteRes<[N3UnitV1, N3UnitV1]> {175 let Latency = 6;176 let NumMicroOps = 2;177}178 179def N3Write_4c_2V0 : SchedWriteRes<[N3UnitV0, N3UnitV0]> {180 let Latency = 4;181 let NumMicroOps = 2;182}183 184def N3Write_8c_2V0 : SchedWriteRes<[N3UnitV0, N3UnitV0]> {185 let Latency = 8;186 let NumMicroOps = 2;187}188 189def N3Write_13c_2V0 : SchedWriteRes<[N3UnitV0, N3UnitV0]> {190 let Latency = 13;191 let NumMicroOps = 2;192}193 194def N3Write_4c_2V : SchedWriteRes<[N3UnitV, N3UnitV]> {195 let Latency = 4;196 let NumMicroOps = 2;197}198 199def N3Write_2c_2V : SchedWriteRes<[N3UnitV, N3UnitV]> {200 let Latency = 2;201 let NumMicroOps = 2;202}203 204def N3Write_8c_1L_1V : SchedWriteRes<[N3UnitL, N3UnitV]> {205 let Latency = 8;206 let NumMicroOps = 2;207}208 209def N3Write_2c_1V_1L01 : SchedWriteRes<[N3UnitV, N3UnitL01]> {210 let Latency = 2;211 let NumMicroOps = 2;212}213 214def N3Write_5c_2V0 : SchedWriteRes<[N3UnitV0, N3UnitV0]> {215 let Latency = 5;216 let NumMicroOps = 2;217}218 219def N3Write_7c_1L_1M : SchedWriteRes<[N3UnitL, N3UnitM]> {220 let Latency = 7;221 let NumMicroOps = 2;222}223 224def N3Write_8c_1V_1L : SchedWriteRes<[N3UnitV, N3UnitL]> {225 let Latency = 8;226 let NumMicroOps = 2;227}228 229def N3Write_5c_1M0_1V : SchedWriteRes<[N3UnitM0, N3UnitV]> {230 let Latency = 5;231 let NumMicroOps = 2;232}233 234def N3Write_5c_1V1_1V : SchedWriteRes<[N3UnitV1, N3UnitV]> {235 let Latency = 5;236 let NumMicroOps = 2;237}238 239def N3Write_8c_1M0_1V : SchedWriteRes<[N3UnitM0, N3UnitV]> {240 let Latency = 8;241 let NumMicroOps = 2;242}243 244def N3Write_5c_1M_1L : SchedWriteRes<[N3UnitM, N3UnitL]> {245 let Latency = 5;246 let NumMicroOps = 2;247}248 249def N3Write_7c_1V_1V1 : SchedWriteRes<[N3UnitV, N3UnitV1]> {250 let Latency = 7;251 let NumMicroOps = 2;252}253 254def N3Write_5c_1V_1V1 : SchedWriteRes<[N3UnitV, N3UnitV1]> {255 let Latency = 5;256 let NumMicroOps = 2;257}258 259//===----------------------------------------------------------------------===//260// Define generic 3 micro-op types261 262def N3Write_3c_1L01_1V_1I : SchedWriteRes<[N3UnitL01, N3UnitV, N3UnitI]> {263 let Latency = 3;264 let NumMicroOps = 3;265}266 267def N3Write_2c_1L01_1V_1I : SchedWriteRes<[N3UnitL01, N3UnitV, N3UnitI]> {268 let Latency = 2;269 let NumMicroOps = 3;270}271 272def N3Write_6c_3V : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV]> {273 let Latency = 6;274 let NumMicroOps = 3;275}276 277def N3Write_4c_3V : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV]> {278 let Latency = 4;279 let NumMicroOps = 3;280}281 282def N3Write_6c_3L : SchedWriteRes<[N3UnitL, N3UnitL, N3UnitL]> {283 let Latency = 6;284 let NumMicroOps = 3;285}286 287def N3Write_8c_2L_1V : SchedWriteRes<[N3UnitL, N3UnitL, N3UnitV]> {288 let Latency = 8;289 let NumMicroOps = 3;290}291 292def N3Write_7c_1M_1M0_1V : SchedWriteRes<[N3UnitM, N3UnitM0, N3UnitV]> {293 let Latency = 7;294 let NumMicroOps = 3;295}296 297def N3Write_5c_1M_1L_1I : SchedWriteRes<[N3UnitM, N3UnitL, N3UnitI]> {298 let Latency = 5;299 let NumMicroOps = 3;300}301 302def N3Write_4c_1I_2L : SchedWriteRes<[N3UnitI, N3UnitL, N3UnitL]> {303 let Latency = 4;304 let NumMicroOps = 3;305}306 307def N3Write_1c_1L01_1D_1I : SchedWriteRes<[N3UnitL01, N3UnitD, N3UnitI]> {308 let Latency = 1;309 let NumMicroOps = 3;310}311 312def N3Write_2c_1L01_1I_1V : SchedWriteRes<[N3UnitL01, N3UnitI, N3UnitV]> {313 let Latency = 2;314 let NumMicroOps = 3;315}316 317//===----------------------------------------------------------------------===//318// Define generic 4 micro-op types319 320def N3Write_8c_2V_2V1 : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV1, N3UnitV1]> {321 let Latency = 8;322 let NumMicroOps = 4;323}324 325def N3Write_6c_2I_2L : SchedWriteRes<[N3UnitI, N3UnitI, N3UnitL, N3UnitL]> {326 let Latency = 6;327 let NumMicroOps = 4;328}329 330def N3Write_6c_2L01_2V : SchedWriteRes<[N3UnitVL]> {331 let Latency = 6;332 let NumMicroOps = 4;333 let ReleaseAtCycles = [5];334}335 336def N3Write_6c_4V0 : SchedWriteRes<[N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0]> {337 let Latency = 6;338 let NumMicroOps = 4;339}340 341def N3Write_8c_4V0 : SchedWriteRes<[N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0]> {342 let Latency = 8;343 let NumMicroOps = 4;344}345 346def N3Write_10c_4V0 : SchedWriteRes<[N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0]> {347 let Latency = 10;348 let NumMicroOps = 4;349}350 351def N3Write_6c_4V : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV, N3UnitV]> {352 let Latency = 6;353 let NumMicroOps = 4;354}355 356def N3Write_7c_4L : SchedWriteRes<[N3UnitL, N3UnitL, N3UnitL, N3UnitL]> {357 let Latency = 7;358 let NumMicroOps = 4;359}360 361def N3Write_2c_2L01_2V : SchedWriteRes<[N3UnitL01, N3UnitL01, N3UnitV, N3UnitV]> {362 let Latency = 2;363 let NumMicroOps = 4;364}365 366def N3Write_4c_2V_2L01 : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitL01, N3UnitL01]> {367 let Latency = 4;368 let NumMicroOps = 4;369}370 371def N3Write_2c_2V_2L01 : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitL01, N3UnitL01]> {372 let Latency = 2;373 let NumMicroOps = 4;374}375 376def N3Write_8c_4V : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV, N3UnitV]> {377 let Latency = 8;378 let NumMicroOps = 4;379}380 381//===----------------------------------------------------------------------===//382// Define generic 6 micro-op types383 384def N3Write_4c_3V_3L01 : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV,385 N3UnitL01, N3UnitL01, N3UnitL01]> {386 let Latency = 4;387 let NumMicroOps = 6;388}389 390def N3Write_2c_3V_3L01 : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV,391 N3UnitL01, N3UnitL01, N3UnitL01]> {392 let Latency = 2;393 let NumMicroOps = 6;394}395 396def N3Write_4c_3L01_3V : SchedWriteRes<[N3UnitL01, N3UnitL01, N3UnitL01,397 N3UnitV, N3UnitV, N3UnitV]> {398 let Latency = 4;399 let NumMicroOps = 6;400}401 402def N3Write_3c_3L01_3V : SchedWriteRes<[N3UnitL01, N3UnitL01, N3UnitL01,403 N3UnitV, N3UnitV, N3UnitV]> {404 let Latency = 3;405 let NumMicroOps = 6;406}407 408def N3Write_6c_3L01_3V : SchedWriteRes<[N3UnitL01, N3UnitL01, N3UnitL01,409 N3UnitV, N3UnitV, N3UnitV]> {410 let Latency = 6;411 let NumMicroOps = 6;412}413 414def N3Write_8c_3L_3V : SchedWriteRes<[N3UnitL, N3UnitL, N3UnitL,415 N3UnitV, N3UnitV, N3UnitV]> {416 let Latency = 8;417 let NumMicroOps = 6;418}419 420def N3Write_10c_3L_3V : SchedWriteRes<[N3UnitL, N3UnitL, N3UnitL,421 N3UnitV, N3UnitV, N3UnitV]> {422 let Latency = 10;423 let NumMicroOps = 6;424}425 426//===----------------------------------------------------------------------===//427// Define generic 7 micro-op types428 429def N3Write_8c_4L_3V : SchedWriteRes<[N3UnitL, N3UnitL, N3UnitL, N3UnitL,430 N3UnitV, N3UnitV, N3UnitV]> {431 let Latency = 8;432 let NumMicroOps = 7;433}434 435//===----------------------------------------------------------------------===//436// Define generic 8 micro-op types437 438def N3Write_12c_8V0 : SchedWriteRes<[N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0,439 N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0]> {440 let Latency = 12;441 let NumMicroOps = 8;442}443 444def N3Write_4c_4V_4L01 : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV, N3UnitV,445 N3UnitL01, N3UnitL01, N3UnitL01, N3UnitL01]> {446 let Latency = 4;447 let NumMicroOps = 8;448}449 450def N3Write_8c_8V0 : SchedWriteRes<[N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0,451 N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0]> {452 let Latency = 8;453 let NumMicroOps = 8;454}455 456def N3Write_16c_8V : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV, N3UnitV,457 N3UnitV, N3UnitV, N3UnitV, N3UnitV]> {458 let Latency = 16;459 let NumMicroOps = 8;460}461 462def N3Write_3c_4L01_4V : SchedWriteRes<[N3UnitL01, N3UnitL01, N3UnitL01, N3UnitL01,463 N3UnitV, N3UnitV, N3UnitV, N3UnitV]> {464 let Latency = 3;465 let NumMicroOps = 8;466}467 468def N3Write_8c_4L_4V : SchedWriteRes<[N3UnitL, N3UnitL, N3UnitL, N3UnitL,469 N3UnitV, N3UnitV, N3UnitV, N3UnitV]> {470 let Latency = 8;471 let NumMicroOps = 8;472}473 474//===----------------------------------------------------------------------===//475// Define generic 9 micro-op types476 477def N3Write_10c_6V_3L : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV,478 N3UnitV, N3UnitV, N3UnitV,479 N3UnitL, N3UnitL, N3UnitL]> {480 let Latency = 10;481 let NumMicroOps = 9;482}483 484def N3Write_4c_3L01_3I_3V : SchedWriteRes<[N3UnitL01, N3UnitL01, N3UnitL01,485 N3UnitI, N3UnitI, N3UnitI,486 N3UnitV, N3UnitV, N3UnitV]> {487 let Latency = 4;488 let NumMicroOps = 9;489}490 491def N3Write_3c_3L01_3I_3V : SchedWriteRes<[N3UnitL01, N3UnitL01, N3UnitL01,492 N3UnitI, N3UnitI, N3UnitI,493 N3UnitV, N3UnitV, N3UnitV]> {494 let Latency = 3;495 let NumMicroOps = 9;496}497 498def N3Write_6c_3L01_3I_3V : SchedWriteRes<[N3UnitL01, N3UnitL01, N3UnitL01,499 N3UnitI, N3UnitI, N3UnitI,500 N3UnitV, N3UnitV, N3UnitV]> {501 let Latency = 6;502 let NumMicroOps = 9;503}504 505def N3Write_12c_5V_4L : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV, N3UnitV, N3UnitV,506 N3UnitL, N3UnitL, N3UnitL, N3UnitL]> {507 let Latency = 12;508 let NumMicroOps = 9;509}510 511def N3Write_9c_3V_3L_3I : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV,512 N3UnitL, N3UnitL, N3UnitL,513 N3UnitI, N3UnitI, N3UnitI]> {514 let Latency = 9;515 let NumMicroOps = 9;516}517 518//===----------------------------------------------------------------------===//519// Define generic 12 micro-op types520 521def N3Write_3c_4L01_4I_4V : SchedWriteRes<[N3UnitL01, N3UnitL01, N3UnitL01, N3UnitL01,522 N3UnitI, N3UnitI, N3UnitI, N3UnitI,523 N3UnitV, N3UnitV, N3UnitV, N3UnitV]> {524 let Latency = 3;525 let NumMicroOps = 12;526}527 528def N3Write_9c_4L_4V_4I : SchedWriteRes<[N3UnitL, N3UnitL, N3UnitL, N3UnitL,529 N3UnitV, N3UnitV, N3UnitV, N3UnitV,530 N3UnitI, N3UnitI, N3UnitI, N3UnitI]> {531 let Latency = 9;532 let NumMicroOps = 12;533}534 535//===----------------------------------------------------------------------===//536// Define generic 14 micro-op types537 538def N3Write_13c_4L_5V_5I : SchedWriteRes<[N3UnitL, N3UnitL, N3UnitL, N3UnitL,539 N3UnitV, N3UnitV, N3UnitV, N3UnitV, N3UnitV,540 N3UnitI, N3UnitI, N3UnitI, N3UnitI, N3UnitI]> {541 let Latency = 13;542 let NumMicroOps = 14;543}544 545//===----------------------------------------------------------------------===//546// Define generic 15 micro-op types547 548def N3Write_11c_6V_3L_6I : SchedWriteRes<[N3UnitV, N3UnitV, N3UnitV,549 N3UnitV, N3UnitV, N3UnitV,550 N3UnitL, N3UnitL, N3UnitL,551 N3UnitI, N3UnitI, N3UnitI,552 N3UnitI, N3UnitI, N3UnitI]> {553 let Latency = 11;554 let NumMicroOps = 15;555}556 557//===----------------------------------------------------------------------===//558// Define generic 16 micro-op types559 560def N3Write_16c_16V0 : SchedWriteRes<[N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0,561 N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0,562 N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0,563 N3UnitV0, N3UnitV0, N3UnitV0, N3UnitV0]> {564 let Latency = 16;565 let NumMicroOps = 16;566}567 568 569//===----------------------------------------------------------------------===//570// Define predicate-controlled types571 572def N3Write_0or1c_1I : SchedWriteVariant<[573 SchedVar<NeoverseZeroMove, [N3Write_0c]>,574 SchedVar<NoSchedPred, [N3Write_1c_1I]>]>;575 576def N3Write_0or2c_1V : SchedWriteVariant<[577 SchedVar<NeoverseZeroMove, [N3Write_0c]>,578 SchedVar<NoSchedPred, [N3Write_2c_1V]>]>;579 580def N3Write_0or2c_1M : SchedWriteVariant<[581 SchedVar<NeoverseAllActivePredicate, [N3Write_0c]>,582 SchedVar<NoSchedPred, [N3Write_2c_1M]>]>;583 584def N3Write_0or3c_1M0 : SchedWriteVariant<[585 SchedVar<NeoverseZeroMove, [N3Write_0c]>,586 SchedVar<NoSchedPred, [N3Write_3c_1M0]>]>;587//===----------------------------------------------------------------------===//588// Define forwarded types589// NOTE: SOG, p. 19, n. 2: Accumulator forwarding is not supported for590// consumers of 64 bit multiply high operations?591 592def N3Wr_FMA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }593def N3Rd_FMA : SchedReadAdvance<2, [WriteFMul, N3Wr_FMA]>;594 595def N3Wr_VMA : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }596def N3Rd_VMA : SchedReadAdvance<3, [N3Wr_VMA]>;597 598def N3Wr_VMAL : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }599def N3Rd_VMAL : SchedReadAdvance<3, [N3Wr_VMAL]>;600 601def N3Wr_VMAH : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }602def N3Rd_VMAH : SchedReadAdvance<2, [N3Wr_VMAH]>;603 604def N3Wr_VMASL : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }605def N3Rd_VMASL : SchedReadAdvance<2, [N3Wr_VMASL]>;606 607def N3Wr_ADA : SchedWriteRes<[N3UnitV1]> { let Latency = 4; }608def N3Rd_ADA : SchedReadAdvance<3, [N3Wr_ADA]>;609 610def N3Wr_VDOT : SchedWriteRes<[N3UnitV]> { let Latency = 3; }611def N3Rd_VDOT : SchedReadAdvance<2, [N3Wr_VDOT]>;612 613def N3Wr_VMMA : SchedWriteRes<[N3UnitV]> { let Latency = 3; }614def N3Rd_VMMA : SchedReadAdvance<2, [N3Wr_VMMA]>;615 616def N3Wr_FCMA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }617def N3Rd_FCMA : SchedReadAdvance<2, [N3Wr_FCMA]>;618 619def N3Wr_FPM : SchedWriteRes<[N3UnitV]> { let Latency = 3; }620def N3Wr_FPMA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }621def N3Rd_FPMA : SchedReadAdvance<2, [N3Wr_FPM, N3Wr_FPMA]>;622 623def N3Wr_FPMAL : SchedWriteRes<[N3UnitV]> { let Latency = 4; }624def N3Rd_FPMAL : SchedReadAdvance<2, [N3Wr_FPMAL]>;625 626def N3Wr_BFD : SchedWriteRes<[N3UnitV]> { let Latency = 4; }627def N3Rd_BFD : SchedReadAdvance<2, [N3Wr_BFD]>;628 629def N3Wr_BFMMA : SchedWriteRes<[N3UnitV]> { let Latency = 5; }630def N3Rd_BFMMA : SchedReadAdvance<2, [N3Wr_BFMMA]>;631 632def N3Wr_BFMLA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }633def N3Rd_BFMLA : SchedReadAdvance<2, [N3Wr_BFMLA]>;634 635def N3Wr_CRC : SchedWriteRes<[N3UnitM0]> { let Latency = 2; }636def N3Rd_CRC : SchedReadAdvance<1, [N3Wr_CRC]>;637 638def N3Wr_ZA : SchedWriteRes<[N3UnitV1]> { let Latency = 4; }639def N3Rd_ZA : SchedReadAdvance<3, [N3Wr_ZA]>;640def N3Wr_ZPA : SchedWriteRes<[N3UnitV1]> { let Latency = 4; }641def N3Rd_ZPA : SchedReadAdvance<3, [N3Wr_ZPA]>;642def N3Wr_ZSA : SchedWriteRes<[N3UnitV1]> { let Latency = 4; }643def N3Rd_ZSA : SchedReadAdvance<3, [N3Wr_ZSA]>;644 645def N3Wr_ZDOTB : SchedWriteRes<[N3UnitV]> { let Latency = 3; }646def N3Rd_ZDOTB : SchedReadAdvance<2, [N3Wr_ZDOTB]>;647def N3Wr_ZDOTH : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }648def N3Rd_ZDOTH : SchedReadAdvance<3, [N3Wr_ZDOTH]>;649 650def N3Wr_ZCMABHS : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }651def N3Rd_ZCMABHS : SchedReadAdvance<3, [N3Wr_ZCMABHS]>;652def N3Wr_ZCMAD : SchedWriteRes<[N3UnitV0, N3UnitV0]> { let Latency = 5; }653def N3Rd_ZCMAD : SchedReadAdvance<2, [N3Wr_ZCMAD]>;654 655def N3Wr_ZMMA : SchedWriteRes<[N3UnitV]> { let Latency = 3; }656def N3Rd_ZMMA : SchedReadAdvance<2, [N3Wr_ZMMA]>;657 658def N3Wr_ZMABHS : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }659def N3Rd_ZMABHS : SchedReadAdvance<3, [N3Wr_ZMABHS]>;660def N3Wr_ZMAD : SchedWriteRes<[N3UnitV0, N3UnitV0]> { let Latency = 5; }661def N3Rd_ZMAD : SchedReadAdvance<2, [N3Wr_ZMAD]>;662 663def N3Wr_ZMAL : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }664def N3Rd_ZMAL : SchedReadAdvance<3, [N3Wr_ZMAL]>;665 666def N3Wr_ZMASQL : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }667def N3Wr_ZMASQBHS : SchedWriteRes<[N3UnitV0]> { let Latency = 4; }668def N3Wr_ZMASQD : SchedWriteRes<[N3UnitV0, N3UnitV0]> { let Latency = 5; }669def N3Rd_ZMASQ : SchedReadAdvance<2, [N3Wr_ZMASQL, N3Wr_ZMASQBHS,670 N3Wr_ZMASQD]>;671 672def N3Wr_ZFCMA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }673def N3Rd_ZFCMA : SchedReadAdvance<2, [N3Wr_ZFCMA]>;674 675def N3Wr_ZFMA : SchedWriteRes<[N3UnitV]> { let Latency = 4; }676def N3Rd_ZFMA : SchedReadAdvance<2, [N3Wr_ZFMA]>;677 678def N3Wr_ZFMAL : SchedWriteRes<[N3UnitV]> { let Latency = 4; }679def N3Rd_ZFMAL : SchedReadAdvance<2, [N3Wr_ZFMAL]>;680 681def N3Wr_ZBFDOT : SchedWriteRes<[N3UnitV]> { let Latency = 4; }682def N3Rd_ZBFDOT : SchedReadAdvance<2, [N3Wr_ZBFDOT]>;683def N3Wr_ZBFMMA : SchedWriteRes<[N3UnitV]> { let Latency = 5; }684def N3Rd_ZBFMMA : SchedReadAdvance<2, [N3Wr_ZBFMMA]>;685def N3Wr_ZBFMAL : SchedWriteRes<[N3UnitV]> { let Latency = 4; }686def N3Rd_ZBFMAL : SchedReadAdvance<2, [N3Wr_ZBFMAL]>;687 688// Miscellaneous689// -----------------------------------------------------------------------------690 691def : InstRW<[WriteI], (instrs COPY)>;692 693// Branch Instructions694// -----------------------------------------------------------------------------695 696// Branch, immed697// Compare and branch698def : SchedAlias<WriteBr, N3Write_1c_1B>;699 700// Branch, register701def : SchedAlias<WriteBrReg, N3Write_1c_1B>;702 703// Branch and link, immed704// Branch and link, register705def : InstRW<[N3Write_1c_1B_1S], (instrs BL, BLR)>;706 707// Arithmetic and Logical Instructions708// -----------------------------------------------------------------------------709 710// ALU, basic711// ALU, basic, flagset712// Arithmetic, immediate to logical address tag713// Conditional compare714// Conditional select715def : SchedAlias<WriteI, N3Write_1c_1I>;716def : InstRW<[N3Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>;717 718// ALU, extend and shift719def : SchedAlias<WriteIEReg, N3Write_2c_1M>;720 721def N3WriteISReg : SchedWriteVariant<[722 SchedVar<IsCheapLSL, [N3Write_1c_1I]>,723 SchedVar<NoSchedPred, [N3Write_2c_1M]>]>;724 725// Arithmetic, LSL shift, shift <= 4726// Arithmetic, flagset, LSL shift, shift <= 4727// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4728def : SchedAlias<WriteISReg, N3WriteISReg>;729 730// Convert floating-point condition flags731def : SchedAlias<WriteSys, N3Write_1c_1I>;732 733// Flag manipulation instructions734def : InstRW<[N3Write_1c_1I], (instrs SETF8, SETF16, RMIF, CFINV)>;735 736// Insert Random Tags737def : InstRW<[N3Write_2c_1M0], (instrs IRG, IRGstack)>;738 739// Insert Tag Mask740// Subtract Pointer741// Subtract Pointer, flagset742def : InstRW<[N3Write_1c_1I], (instrs GMI, SUBP, SUBPS)>;743 744// Logical, shift, no flagset745def : InstRW<[N3Write_1c_1I],746 (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;747def : InstRW<[N3Write_0or1c_1I], (instregex "^ORR[WX]rs$")>;748 749// Logical, shift, flagset750def : InstRW<[N3Write_2c_1M], (instregex "^(AND|BIC)S[WX]rs$")>;751 752// Divide and Multiply Instructions753// -----------------------------------------------------------------------------754 755// Integer divides are performed using an iterative algorithm and block any756// subsequent divide operations until complete.757 758// Divide, W-form759def : SchedAlias<WriteID32, N3Write_12c_1M0_12>;760 761// Divide, X-form762def : SchedAlias<WriteID64, N3Write_20c_1M0_20>;763 764def N3Wr_IM : SchedWriteRes<[N3UnitM]> { let Latency = 2; }765def N3Wr_IMA : SchedWriteRes<[N3UnitM0]> { let Latency = 2; }766def N3Wr_IMUL : SchedWriteVariant<[767 SchedVar<IsReg3ZeroPred, [N3Wr_IM]>,768 SchedVar<NoSchedPred, [N3Wr_IMA]>]>;769def N3Rd_IMA : SchedReadAdvance<1, [N3Wr_IMA]>;770 771def : SchedAlias<WriteIM32, N3Write_2c_1M0>;772def : SchedAlias<WriteIM64, N3Write_2c_1M0>;773 774// NOTE: Modified from V2775 776// Multiply777// Multiply accumulate, W-form778// Multiply accumulate, X-form779// Multiply accumulate long780// Multiply long781def : InstRW<[N3Wr_IMUL, ReadIM, ReadIM, N3Rd_IMA],782 (instregex "^M(ADD|SUB)[WX]rrr$",783 "^(S|U)M(ADD|SUB)Lrrr$")>;784 785// Multiply high786def : InstRW<[N3Write_3c_1M], (instrs SMULHrr, UMULHrr)>;787 788// Pointer Authentication Instructions789// -----------------------------------------------------------------------------790 791// Authenticate data address792// Authenticate instruction address793def : InstRW<[N3Write_1c_1M], (instrs AUTDA, AUTDB, AUTDZA, AUTDZB,794 AUTIA, AUTIB, AUTIA1716, AUTIB1716,795 AUTIASP, AUTIBSP, AUTIAZ, AUTIBZ, AUTIZA,796 AUTIZB)>;797 798// Branch and link, register, with pointer authentication799// Branch, register, with pointer authentication800// Branch, return, with pointer authentication801def : InstRW<[N3Write_2c_1M_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA,802 BRAAZ, BRAB, BRABZ, RETAA, RETAB,803 ERETAA, ERETAB)>;804 805// Compute pointer authentication code for data address806def : InstRW<[N3Write_4c_1M], (instrs PACDA, PACDB, PACDZA, PACDZB)>;807 808// Compute pointer authentication code, using generic key809def : InstRW<[N3Write_4c_1M], (instrs PACGA)>;810 811// Compute pointer authentication code for instruction address812def : InstRW<[N3Write_4c_1M], (instrs PACIA, PACIB, PACIA1716, PACIB1716,813 PACIASP, PACIBSP, PACIAZ, PACIBZ, PACIZA,814 PACIZB)>;815 816// Load register, with pointer authentication817def : InstRW<[N3Write_5c_1M_1L], (instregex "^LDRA[AB]indexed")>;818def : InstRW<[N3Write_5c_1M_1L_1I], (instregex "^LDRA[AB]writeback")>;819 820// Strip pointer authentication code821def : InstRW<[N3Write_1c_1M], (instrs XPACD, XPACI, XPACLRI)>;822 823// Miscellaneous data-processing instructions824// -----------------------------------------------------------------------------825 826// Address generation827def : InstRW<[N3Write_1c_1S], (instrs ADR, ADRP)>;828 829// Bitfield extract, one, two regs830def : SchedAlias<WriteExtr, N3Write_1c_1I>;831 832// Bitfield move, basic833// Bitfield move, insert834// Variable shift835def : SchedAlias<WriteIS, N3Write_1c_1I>;836 837// Count leading838// Reverse bits/bytes839// Covered by WriteI840 841// Move immed842def : SchedAlias<WriteImm, N3Write_1c_1I>;843 844// Load instructions845// -----------------------------------------------------------------------------846 847// Load register, literal848def : InstRW<[N3Write_5c_1L_1S], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>;849 850// Load register, unscaled immed851// Load register, immed post-index852// Load register, immed pre-index853// Load register, unsigned immed854// Load register, immed unprivileged855def : SchedAlias<WriteAdr, N3Write_1c_1I>;856def : SchedAlias<WriteLD, N3Write_4c_1L>;857 858// Load register, register offset, basic859// Load register, register offset, scale by 4/8860// Load register, register offset, scale by 2861// Load register, register offset, extend862// Load register, register offset, extend, scale by 4/8863// Load register, register offset, extend, scale by 2864def : SchedAlias<WriteLDIdx, N3Write_4c_1L>;865 866def : SchedAlias<WriteLDHi, N3Write_4c>;867 868// Load pair, signed immed offset, normal, W-form869def : InstRW<[WriteLD, WriteLDHi], (instrs LDPWi, LDNPWi)>;870 871// Load pair, signed immed offset, normal, X-form872def : InstRW<[N3Write_4c_2L, WriteLDHi], (instrs LDPXi, LDNPXi)>;873 874// Load pair, signed immed offset, signed words875def : InstRW<[N3Write_4c_1I_2L, WriteLDHi], (instrs LDPSWi)>;876 877// Load pair, immed post-index or immed pre-index, normal, W-form878def : InstRW<[WriteAdr, WriteLD, WriteLDHi], (instrs LDPWpost, LDPWpre)>;879 880// Load pair, immed post-index or immed pre-index, normal, X-form881def : InstRW<[WriteAdr, N3Write_4c_2L, WriteLDHi], (instrs LDPXpost, LDPXpre)>;882 883// Load pair, immed post-index or immed pre-index, signed words884def : InstRW<[WriteAdr, N3Write_4c_1I_2L, WriteLDHi], (instrs LDPSWpost, LDPSWpre)>;885 886// Store instructions887// -----------------------------------------------------------------------------888 889// Store register, unscaled immed890// Store register, immed unprivileged891// Store register, unsigned immed892// Store register, immed post-index893// Store register, immed pre-index894def : SchedAlias<WriteST, N3Write_1c_1L01_1D>;895 896// Store register, register offset, basic897// Store register, register offset, scaled by 4/8898// Store register, register offset, scaled by 2899// Store register, register offset, extend900// Store register, register offset, extend, scale by 4/8901// Store register, register offset, extend, scale by 2902def : SchedAlias<WriteSTIdx, N3Write_1c_1L01_1D>;903 904// Store pair, immed offset905// Store pair, immed post-index906// Store pair, immed pre-index907def : SchedAlias<WriteSTP, N3Write_1c_1L01_1D>;908 909// Tag Load instructions910// -----------------------------------------------------------------------------911 912// Load allocation tag913def : InstRW<[N3Write_5c_1L_1I], (instrs LDG)>;914 915// Load multiple allocation tags916def : InstRW<[N3Write_4c_1L], (instrs LDGM)>;917 918// Tag store instructions919// -----------------------------------------------------------------------------920 921// Store allocation tags to one or two granules, post-index922// Store allocation tags to one or two granules, pre-index923// Store allocation tag to one or two granules, zeroing, post-index924// Store allocation Tag to one or two granules, zeroing, pre-index925def : InstRW<[N3Write_1c_1L01_1D_1I], (instregex "^STZ?2?G(Post|Pre)Index$")>;926 927// Store allocation tags to one or two granules, signed offset928// Store allocation tag to two granules, zeroing, signed offset929def : InstRW<[N3Write_1c_1L01_1D], (instregex "^STZ?2?Gi$")>;930 931// Store allocation tag and reg pair to memory, post-Index932// Store allocation tag and reg pair to memory, pre-Index933def : InstRW<[N3Write_1c_1L01_1D_1I], (instrs STGPpost, STGPpre)>;934 935// Store allocation tag and reg pair to memory, signed offset936// Store multiple allocation tags937// Store multiple allocation tags, zeroing938def : InstRW<[N3Write_1c_1L01_1D], (instrs STGPi, STGM, STZGM)>;939 940// FP data processing instructions941// -----------------------------------------------------------------------------942 943// FP absolute value944// FP arithmetic945// FP min/max946// FP negate947// FP select948def : SchedAlias<WriteF, N3Write_2c_1V>;949 950// FP compare951def : SchedAlias<WriteFCmp, N3Write_2c_1V>;952 953// FP divide and square root operations are now performed using954// a fully pipelined data path.955 956// FP divide, H-form957// FP square root, H-form958def : InstRW<[N3Write_5c_1V0], (instrs FDIVHrr, FSQRTHr)>;959 960// FP divide, S-form961// FP square root, S-form962def : SchedAlias<WriteFDiv , N3Write_7c_1V0>;963 964// FP divide, D-form965// FP square root, D-form966def : InstRW<[N3Write_12c_1V0], (instrs FDIVDrr, FSQRTDr)>;967 968// FP multiply969def : WriteRes<WriteFMul, [N3UnitV]> { let Latency = 3; }970 971// FP multiply accumulate972def : InstRW<[N3Wr_FMA, ReadDefault, ReadDefault, N3Rd_FMA],973 (instregex "^(FMADD|FMSUB|FNMADD|FNMSUB)[DHS]rrr$")>;974 975// FP round to integral976def : InstRW<[N3Write_3c_1V0], (instregex "^FRINT([AIMNPXZ]|32X|64X|32Z|64Z)[DHS]r$")>;977 978// FP miscellaneous instructions979// -----------------------------------------------------------------------------980 981// FP convert, from gen to vec reg982def : InstRW<[N3Write_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;983 984// FP convert, from vec to gen reg985// FP convert, Javascript from vec to gen reg986// FP convert, from vec to vec reg987def : SchedAlias<WriteFCvt, N3Write_3c_1V0>;988 989// FP move, immed990def : SchedAlias<WriteFImm, N3Write_2c_1V>;991 992// FP move, register993def : InstRW<[N3Write_2c_1V], (instrs FMOVHr)>;994def : InstRW<[N3Write_0c], (instrs FMOVSr, FMOVDr)>;995 996// FP transfer, from gen to low half of vec reg997def : InstRW<[N3Write_0or3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;998 999// FP transfer, from gen to high half of vec reg1000def : InstRW<[N3Write_5c_1M0_1V], (instrs FMOVXDHighr)>;1001 1002// FP transfer, from vec to gen reg1003def : SchedAlias<WriteFCopy, N3Write_3c_1V>;1004 1005// FP load instructions1006// -----------------------------------------------------------------------------1007 1008// Load vector reg, literal, S/D/Q forms1009// Load vector reg, unscaled immed1010// Load vector reg, unsigned immed1011def : InstRW<[N3Write_6c_1L], (instregex "^LDR[SDQ]l$",1012 "^LDUR[BHSDQ]i$",1013 "^LDR[BHSDQ]ui$")>;1014// Load vector reg, immed post-index1015// Load vector reg, immed pre-index1016def : InstRW<[WriteAdr, N3Write_6c_1L], (instregex "^LDR[BHSDQ](post|pre)$")>;1017 1018// Load vector reg, register offset, basic1019// Load vector reg, register offset, scale, S/D-form1020// Load vector reg, register offset, scale, H/Q-form1021// Load vector reg, register offset, extend1022// Load vector reg, register offset, extend, scale, S/D-form1023// Load vector reg, register offset, extend, scale, H/Q-form1024def : InstRW<[N3Write_6c_1L], (instregex "^LDR[BHSDQ]ro[WX]$")>;1025 1026// Load vector pair, immed offset, S/D-form1027def : InstRW<[N3Write_6c_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>;1028 1029// Load vector pair, immed offset, Q-form1030def : InstRW<[N3Write_6c_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;1031 1032// Load vector pair, immed post-index, S/D-form1033// Load vector pair, immed pre-index, S/D-form1034// Load vector pair, immed post-index, Q-form1035// Load vector pair, immed pre-index, Q-form1036def : InstRW<[WriteAdr, N3Write_6c_2I_2L, WriteLDHi], (instregex "^LDP[SDQ](post|pre)$")>;1037 1038// FP store instructions1039// -----------------------------------------------------------------------------1040 1041// Store vector reg, unscaled immed, B/H/S/D-form1042// Store vector reg, unscaled immed, Q-form1043def : InstRW<[N3Write_2c_1L01_1V], (instregex "^STUR[BHSDQ]i$")>;1044 1045// Store vector reg, immed post-index, B/H/S/D-form1046// Store vector reg, immed post-index, Q-form1047def : InstRW<[WriteAdr, N3Write_2c_1L01_1V_1I], (instregex "^STR[BHSDQ]post$")>;1048 1049// Store vector reg, immed pre-index, B/H/S/D-form1050def : InstRW<[WriteAdr, N3Write_3c_1L01_1V_1I], (instregex "^STR[BHSD]pre$")>;1051 1052// Store vector reg, immed pre-index, Q-form1053def : InstRW<[WriteAdr, N3Write_2c_1L01_1V_1I], (instrs STRQpre)>;1054 1055// Store vector reg, unsigned immed, B/H/S/D-form1056// Store vector reg, unsigned immed, Q-form1057def : InstRW<[N3Write_2c_1L01_1V], (instregex "^STR[BHSDQ]ui$")>;1058 1059// Store vector reg, register offset, basic, B/H/S/D-form1060// Store vector reg, register offset, scale, H-form1061// Store vector reg, register offset, scale, S/D-form1062// Store vector reg, register offset, extend, B/H/S/D-form1063// Store vector reg, register offset, extend, scale, H-form1064// Store vector reg, register offset, extend, scale, S/D-form1065def : InstRW<[N3Write_2c_1L01_1V], (instregex "^STR[BHSD]ro[WX]$")>;1066 1067def N3WriteSTRQro : SchedWriteVariant<[1068 SchedVar<ScaledIdxPred, [N3Write_2c_1L01_1V_1I]>,1069 SchedVar<NoSchedPred, [N3Write_2c_1L01_1V]>]>;1070 1071// Store vector reg, register offset, basic, Q-form1072// Store vector reg, register offset, scale, Q-form1073// Store vector reg, register offset, extend, Q-form1074// Store vector reg, register offset, extend, scale, Q-form1075def : InstRW<[N3WriteSTRQro], (instregex "^STRQro[WX]$")>;1076 1077// Store vector pair, immed offset, S-form1078// Store vector pair, immed offset, D-form1079// Store vector pair, immed offset, Q-form1080def : InstRW<[N3Write_2c_1L01_1V], (instregex "^STN?P[SDQ]i$")>;1081 1082// Store vector pair, immed post-index, S-form1083// Store vector pair, immed post-index, D-form1084// Store vector pair, immed post-index, Q-form1085// Store vector pair, immed pre-index, S-form1086// Store vector pair, immed pre-index, D-form1087// Store vector pair, immed pre-index, Q-form1088def : InstRW<[WriteAdr, N3Write_2c_1L01_1V_1I], (instregex "^STP[SDQ](post|pre)$")>;1089 1090// ASIMD integer instructions1091// -----------------------------------------------------------------------------1092 1093// ASIMD absolute diff1094// ASIMD absolute diff long1095// ASIMD arith, basic1096// ASIMD arith, complex1097// ASIMD arith, pair-wise1098// ASIMD compare1099// ASIMD logical1100// ASIMD max/min, basic and pair-wise1101def : InstRW<[N3Write_0or2c_1V], (instrs ORRv16i8, ORRv8i8)>;1102 1103def : SchedAlias<WriteVd, N3Write_2c_1V>;1104def : SchedAlias<WriteVq, N3Write_2c_1V>;1105 1106// ASIMD absolute diff accum1107// ASIMD absolute diff accum long1108// ASIMD pairwise add and accumulate long1109// ASIMD shift accumulate1110def : InstRW<[N3Wr_ADA, N3Rd_ADA], (instregex "^[SU]ABAL?v",1111 "^[SU]ADALPv",1112 "^[SU]R?SRA(v|d)")>;1113 1114// ASIMD arith, reduce, 4H/4S1115def : InstRW<[N3Write_3c_1V1], (instregex "^[SU]?ADDL?Vv4i(16|32)v$")>;1116 1117// ASIMD arith, reduce, 8B/8H1118def : InstRW<[N3Write_5c_1V1_1V], (instregex "^[SU]?ADDL?Vv8i(8|16)v$")>;1119 1120// ASIMD arith, reduce, 16B1121def : InstRW<[N3Write_6c_2V1], (instregex "^[SU]?ADDL?Vv16i8v$")>;1122 1123// ASIMD dot product1124// ASIMD dot product using signed and unsigned integers1125def : InstRW<[N3Wr_VDOT, N3Rd_VDOT],1126 (instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>;1127 1128// ASIMD matrix multiply-accumulate1129def : InstRW<[N3Wr_VMMA, N3Rd_VMMA], (instrs SMMLA, UMMLA, USMMLA)>;1130 1131// ASIMD max/min, reduce, 4H/4S1132def : InstRW<[N3Write_3c_1V1], (instregex "^[SU](MAX|MIN)Vv4i(16|32)v$")>;1133 1134// ASIMD max/min, reduce, 8B/8H1135def : InstRW<[N3Write_5c_1V1_1V], (instregex "^[SU](MAX|MIN)Vv8i(8|16)v$")>;1136 1137// ASIMD max/min, reduce, 16B1138def : InstRW<[N3Write_6c_2V1], (instregex "[SU](MAX|MIN)Vv16i8v$")>;1139 1140// ASIMD multiply1141def : InstRW<[N3Write_4c_1V0], (instregex "^MULv", "^SQ(R)?DMULHv")>;1142 1143// ASIMD multiply accumulate1144def : InstRW<[N3Wr_VMA, N3Rd_VMA], (instregex "^MLAv", "^MLSv")>;1145 1146// ASIMD multiply accumulate high1147def : InstRW<[N3Wr_VMAH, N3Rd_VMAH], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;1148 1149// ASIMD multiply accumulate long1150def : InstRW<[N3Wr_VMAL, N3Rd_VMAL], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;1151 1152// ASIMD multiply accumulate saturating long1153def : InstRW<[N3Wr_VMASL, N3Rd_VMASL], (instregex "^SQDMLAL(v|i16|i32)", "^SQDMLSL(v|i16|i32)")>;1154 1155// ASIMD multiply/multiply long (8x8) polynomial, D-form1156// ASIMD multiply/multiply long (8x8) polynomial, Q-form1157def : InstRW<[N3Write_2c_1V0], (instregex "^PMULL?(v8i8|v16i8)$")>;1158 1159// ASIMD multiply long1160def : InstRW<[N3Write_4c_1V0], (instregex "^[SU]MULLv", "^SQDMULL(v|i16|i32)")>;1161 1162// ASIMD shift by immed, basic1163def : InstRW<[N3Write_2c_1V1], (instregex "^SHL(v|d)", "^SHLLv", "^SHRNv",1164 "^SSHLLv", "^SSHR(v|d)", "^USHLLv",1165 "^USHR(v|d)")>;1166 1167// ASIMD shift by immed and insert, basic1168def : InstRW<[N3Write_2c_1V1], (instregex "^SLI(v|d)", "^SRI(v|d)")>;1169 1170// ASIMD shift by immed, complex1171def : InstRW<[N3Write_4c_1V1],1172 (instregex "^RSHRNv", "^SQRSHRN[vbhs]", "^SQRSHRUN[vbhs]",1173 "^(SQSHLU?|UQSHL)[bhsd]$",1174 "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",1175 "^SQSHRN[vbhs]", "^SQSHRUN[vbhs]", "^SRSHR(v|d)",1176 "^UQRSHRN[vbhs]", "^UQSHRN[vbhs]","^URSHR(v|d)")>;1177 1178// ASIMD shift by register, basic1179def : InstRW<[N3Write_2c_1V1], (instregex "^[SU]SHLv")>;1180 1181// ASIMD shift by register, complex1182def : InstRW<[N3Write_4c_1V1],1183 (instregex "^[SU]RSHLv", "^[SU]QRSHLv",1184 "^[SU]QSHL(v1i8|v1i16|v1i32|v1i64|v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)$")>;1185 1186// ASIMD floating-point instructions1187// -----------------------------------------------------------------------------1188 1189// ASIMD FP absolute value/difference1190// ASIMD FP arith, normal1191// ASIMD FP compare1192// ASIMD FP max/min, normal1193// ASIMD FP negate1194// Covered by WriteV[dq]1195 1196// ASIMD FP complex add1197def : InstRW<[N3Write_3c_1V], (instregex "^FCADDv")>;1198 1199// ASIMD FP complex multiply add1200def : InstRW<[N3Wr_FCMA, N3Rd_FCMA], (instregex "^FCMLAv")>;1201 1202// ASIMD FP convert, long (F16 to F32)1203def : InstRW<[N3Write_4c_2V0], (instregex "^FCVTL(v4|v8)i16")>;1204 1205// ASIMD FP convert, long (F32 to F64)1206def : InstRW<[N3Write_3c_1V0], (instregex "^FCVTL(v2|v4)i32")>;1207 1208// ASIMD FP convert, narrow (F32 to F16)1209def : InstRW<[N3Write_4c_2V0], (instregex "^FCVTN(v4|v8)i16")>;1210 1211// ASIMD FP convert, narrow (F64 to F32)1212def : InstRW<[N3Write_3c_1V0], (instregex "^FCVTN(v2|v4)i32", "^FCVTXNv1i64",1213 "^FCVTXN(v2|v4)f32")>;1214 1215// ASIMD FP convert, other, D-form F32 and Q-form F641216def : InstRW<[N3Write_3c_1V0], (instregex "^[FSU]CVT[AMNPZ][SU](v2f(32|64)|s|d|v1i32|v1i64|v2i32_shift|v2i64_shift)$",1217 "^[SU]CVTF(v2f(32|64)|s|d|v1i32|v1i64|v2i32_shift|v2i64_shift)$")>;1218 1219// ASIMD FP convert, other, D-form F16 and Q-form F321220def : InstRW<[N3Write_4c_2V0], (instregex "^[FSU]CVT[AMNPZ][SU](v4f(16|32)|v4i(16|32)_shift)$",1221 "^[SU]CVTF(v4f(16|32)|v4i(16|32)_shift)$")>;1222 1223// ASIMD FP convert, other, Q-form F161224def : InstRW<[N3Write_6c_4V0], (instregex "^[FSU]CVT[AMNPZ][SU]v8f16$",1225 "^[SU]CVTFv8f16$")>;1226 1227// ASIMD FP divide and square root operations are now performed using1228// a fully pipelined data path.1229 1230// ASIMD FP divide, D-form, F161231def : InstRW<[N3Write_8c_4V0], (instrs FDIVv4f16)>;1232 1233// ASIMD FP divide, D-form, F321234def : InstRW<[N3Write_8c_2V0], (instrs FDIVv2f32)>;1235 1236// ASIMD FP divide, Q-form, F161237def : InstRW<[N3Write_12c_8V0], (instrs FDIVv8f16)>;1238 1239// ASIMD FP divide, Q-form, F321240def : InstRW<[N3Write_10c_4V0], (instrs FDIVv4f32)>;1241 1242// ASIMD FP divide, Q-form, F641243def : InstRW<[N3Write_13c_2V0], (instrs FDIVv2f64)>;1244 1245// ASIMD FP arith, max/min, pairwise1246def : InstRW<[N3Write_3c_1V], (instregex "^FADDPv", "^FMAXPv", "^FMAXNMPv",1247 "^FMINPv", "^FMINNMPv")>;1248 1249// ASIMD FP max/min, reduce, F32 and D-form F161250def : InstRW<[N3Write_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;1251 1252// ASIMD FP max/min, reduce, Q-form F161253def : InstRW<[N3Write_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;1254 1255// ASIMD FP multiply1256def : InstRW<[N3Wr_FPM], (instregex "^FMULv", "^FMULX(v|32|64)")>;1257 1258// ASIMD FP multiply accumulate1259def : InstRW<[N3Wr_FPMA, N3Rd_FPMA], (instregex "^FMLAv", "^FMLSv")>;1260 1261// ASIMD FP multiply accumulate long1262def : InstRW<[N3Wr_FPMAL, N3Rd_FPMAL], (instregex "^FMLALv", "^FMLSLv")>;1263 1264// ASIMD FP round, D-form F32 and Q-form F641265def : InstRW<[N3Write_3c_1V0],1266 (instregex "^FRINT[AIMNPXZ]v2f(32|64)$",1267 "^FRINT(32|64)[XZ]v2f(32|64)$")>;1268 1269// ASIMD FP round, D-form F16 and Q-form F321270def : InstRW<[N3Write_4c_2V0],1271 (instregex "^FRINT[AIMNPXZ]v4f(16|32)$",1272 "^FRINT(32|64)[XZ]v4f32$")>;1273 1274// ASIMD FP round, Q-form F161275def : InstRW<[N3Write_6c_4V0], (instregex "^FRINT[AIMNPXZ]v8f16$")>;1276 1277// ASIMD FP square root, D-form, F161278def : InstRW<[N3Write_8c_4V0], (instrs FSQRTv4f16)>;1279 1280// ASIMD FP square root, D-form, F321281def : InstRW<[N3Write_8c_2V0], (instrs FSQRTv2f32)>;1282 1283// ASIMD FP square root, Q-form, F161284def : InstRW<[N3Write_12c_8V0], (instrs FSQRTv8f16)>;1285 1286// ASIMD FP square root, Q-form, F321287def : InstRW<[N3Write_10c_4V0], (instrs FSQRTv4f32)>;1288 1289// ASIMD FP square root, Q-form, F641290def : InstRW<[N3Write_13c_2V0], (instrs FSQRTv2f64)>;1291 1292// ASIMD BFloat16 (BF16) instructions1293// -----------------------------------------------------------------------------1294 1295// ASIMD convert, F32 to BF161296def : InstRW<[N3Write_4c_2V0], (instrs BFCVTN, BFCVTN2)>;1297 1298// ASIMD dot product1299def : InstRW<[N3Wr_BFD, N3Rd_BFD], (instrs BFDOTv4bf16, BFDOTv8bf16)>;1300 1301// ASIMD matrix multiply accumulate1302def : InstRW<[N3Wr_BFMMA, N3Rd_BFMMA], (instrs BFMMLA)>;1303 1304// ASIMD multiply accumulate long1305def : InstRW<[N3Wr_BFMLA, N3Rd_BFMLA],1306 (instrs BFMLALB, BFMLALBIdx, BFMLALT, BFMLALTIdx)>;1307 1308// Scalar convert, F32 to BF161309def : InstRW<[N3Write_3c_1V0], (instrs BFCVT)>;1310 1311// ASIMD miscellaneous instructions1312// -----------------------------------------------------------------------------1313 1314// ASIMD bit reverse1315// ASIMD bitwise insert1316// ASIMD count1317// ASIMD duplicate, element1318// ASIMD extract1319// ASIMD extract narrow1320// ASIMD insert, element to element1321// ASIMD move, FP immed1322// ASIMD move, integer immed1323// ASIMD reverse1324// ASIMD table lookup, 1 or 2 table regs1325// ASIMD table lookup extension, 1 table reg1326// ASIMD transpose1327// ASIMD unzip/zip1328// Covered by WriteV[dq]1329def : InstRW<[N3Write_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>;1330 1331// ASIMD duplicate, gen reg1332def : InstRW<[N3Write_3c_1M0], (instregex "^DUPv.+gpr")>;1333 1334// ASIMD extract narrow, saturating1335def : InstRW<[N3Write_4c_1V1], (instregex "^[SU]QXTNv", "^SQXTUNv")>;1336 1337// ASIMD reciprocal and square root estimate, D-form U321338def : InstRW<[N3Write_3c_1V0], (instrs URECPEv2i32, URSQRTEv2i32)>;1339 1340// ASIMD reciprocal and square root estimate, Q-form U321341def : InstRW<[N3Write_4c_2V0], (instrs URECPEv4i32, URSQRTEv4i32)>;1342 1343// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms1344def : InstRW<[N3Write_3c_1V0], (instrs FRECPEv1f16, FRECPEv1i32,1345 FRECPEv1i64, FRECPEv2f32, FRECPEv2f64,1346 FRSQRTEv1f16, FRSQRTEv1i32,1347 FRSQRTEv1i64, FRSQRTEv2f32, FRSQRTEv2f64)>;1348 1349// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F321350def : InstRW<[N3Write_4c_2V0], (instrs FRECPEv4f16, FRECPEv4f32,1351 FRSQRTEv4f16, FRSQRTEv4f32)>;1352 1353// ASIMD reciprocal and square root estimate, Q-form F161354def : InstRW<[N3Write_6c_4V0], (instrs FRECPEv8f16, FRSQRTEv8f16)>;1355 1356// ASIMD reciprocal exponent1357def : InstRW<[N3Write_3c_1V0], (instregex "^FRECPXv")>;1358 1359// ASIMD reciprocal step1360def : InstRW<[N3Write_4c_1V], (instregex "^FRECPS(v|32|64)", "^FRSQRTS(v|32|64)")>;1361 1362// ASIMD table lookup, 3 table regs1363def : InstRW<[N3Write_4c_2V], (instrs TBLv8i8Three, TBLv16i8Three)>;1364 1365// ASIMD table lookup, 4 table regs1366def : InstRW<[N3Write_4c_3V], (instrs TBLv8i8Four, TBLv16i8Four)>;1367 1368// ASIMD table lookup extension, 2 table reg1369def : InstRW<[N3Write_4c_2V], (instrs TBXv8i8Two, TBXv16i8Two)>;1370 1371// ASIMD table lookup extension, 3 table reg1372def : InstRW<[N3Write_6c_3V], (instrs TBXv8i8Three, TBXv16i8Three)>;1373 1374// ASIMD table lookup extension, 4 table reg1375def : InstRW<[N3Write_6c_4V], (instrs TBXv8i8Four, TBXv16i8Four)>;1376 1377// ASIMD transfer, element to gen reg1378def : InstRW<[N3Write_2c_2V], (instregex "^SMOVvi(((8|16)to(32|64))|32to64)$",1379 "^UMOVvi(8|16|32|64)$")>;1380 1381// ASIMD transfer, gen reg to element1382def : InstRW<[N3Write_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;1383 1384// ASIMD load instructions1385// -----------------------------------------------------------------------------1386 1387// ASIMD load, 1 element, multiple, 1 reg, D-form1388def : InstRW<[N3Write_6c_1L],1389 (instregex "^LD1Onev(8b|4h|2s|1d)$")>;1390def : InstRW<[WriteAdr, N3Write_6c_1L],1391 (instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>;1392 1393// ASIMD load, 1 element, multiple, 1 reg, Q-form1394def : InstRW<[N3Write_6c_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;1395def : InstRW<[WriteAdr, N3Write_6c_1L],1396 (instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>;1397 1398// ASIMD load, 1 element, multiple, 2 reg, D-form1399def : InstRW<[N3Write_6c_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;1400def : InstRW<[WriteAdr, N3Write_6c_2L],1401 (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;1402 1403// ASIMD load, 1 element, multiple, 2 reg, Q-form1404def : InstRW<[N3Write_6c_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;1405def : InstRW<[WriteAdr, N3Write_6c_2L],1406 (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;1407 1408// ASIMD load, 1 element, multiple, 3 reg, D-form1409def : InstRW<[N3Write_6c_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;1410def : InstRW<[WriteAdr, N3Write_6c_3L],1411 (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;1412 1413// ASIMD load, 1 element, multiple, 3 reg, Q-form1414def : InstRW<[N3Write_6c_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;1415def : InstRW<[WriteAdr, N3Write_6c_3L],1416 (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;1417 1418// ASIMD load, 1 element, multiple, 4 reg, D-form1419def : InstRW<[N3Write_7c_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;1420def : InstRW<[WriteAdr, N3Write_7c_4L],1421 (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;1422 1423// ASIMD load, 1 element, multiple, 4 reg, Q-form1424def : InstRW<[N3Write_7c_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;1425def : InstRW<[WriteAdr, N3Write_7c_4L],1426 (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;1427 1428// ASIMD load, 1 element, one lane, B/H/S1429// ASIMD load, 1 element, one lane, D1430def : InstRW<[N3Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)$")>;1431def : InstRW<[WriteAdr, N3Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;1432 1433// ASIMD load, 1 element, all lanes, D-form, B/H/S1434// ASIMD load, 1 element, all lanes, D-form, D1435def : InstRW<[N3Write_6c_1L], (instregex "LD1Rv(8b|4h|2s|1d)$")>;1436def : InstRW<[WriteAdr, N3Write_6c_1L], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;1437 1438// ASIMD load, 1 element, all lanes, Q-form1439def : InstRW<[N3Write_6c_1L], (instregex "LD1Rv(16b|8h|4s|2d)$")>;1440def : InstRW<[WriteAdr, N3Write_6c_1L], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;1441 1442// ASIMD load, 2 element, multiple, D-form, B/H/S1443def : InstRW<[N3Write_8c_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>;1444def : InstRW<[WriteAdr, N3Write_8c_1L_1V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;1445 1446// ASIMD load, 2 element, multiple, Q-form, B/H/S1447// ASIMD load, 2 element, multiple, Q-form, D1448def : InstRW<[N3Write_8c_2L_1V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;1449def : InstRW<[WriteAdr, N3Write_8c_2L_1V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;1450 1451// ASIMD load, 2 element, one lane, B/H1452// ASIMD load, 2 element, one lane, S1453// ASIMD load, 2 element, one lane, D1454def : InstRW<[N3Write_8c_1L_1V], (instregex "LD2i(8|16|32|64)$")>;1455def : InstRW<[WriteAdr, N3Write_8c_1L_1V], (instregex "LD2i(8|16|32|64)_POST$")>;1456 1457// ASIMD load, 2 element, all lanes, D-form, B/H/S1458// ASIMD load, 2 element, all lanes, D-form, D1459def : InstRW<[N3Write_6c_2L], (instregex "LD2Rv(8b|4h|2s|1d)$")>;1460def : InstRW<[WriteAdr, N3Write_6c_2L], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;1461 1462// ASIMD load, 2 element, all lanes, Q-form1463def : InstRW<[N3Write_6c_2L], (instregex "LD2Rv(16b|8h|4s|2d)$")>;1464def : InstRW<[WriteAdr, N3Write_6c_2L], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;1465 1466// ASIMD load, 3 element, multiple, D-form, B/H/S1467def : InstRW<[N3Write_8c_3L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;1468def : InstRW<[WriteAdr, N3Write_8c_3L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;1469 1470// ASIMD load, 3 element, multiple, Q-form, B/H/S1471def : InstRW<[N3Write_10c_3L_3V], (instregex "LD3Threev(16b|8h|4s)$")>;1472def : InstRW<[WriteAdr, N3Write_10c_3L_3V], (instregex "LD3Threev(16b|8h|4s)_POST$")>;1473 1474// ASIMD load, 3 element, multiple, Q-form, D1475def : InstRW<[N3Write_10c_3L_3V], (instregex "LD3Threev(2d)$")>;1476def : InstRW<[WriteAdr, N3Write_10c_3L_3V], (instregex "LD3Threev(2d)_POST$")>;1477 1478// ASIMD load, 3 element, one lane, B/H1479// ASIMD load, 3 element, one lane, S1480// ASIMD load, 3 element, one lane, D1481def : InstRW<[N3Write_8c_3L_3V], (instregex "LD3i(8|16|32|64)$")>;1482def : InstRW<[WriteAdr, N3Write_8c_3L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;1483 1484// ASIMD load, 3 element, all lanes, D-form, B/H/S1485// ASIMD load, 3 element, all lanes, D-form, D1486def : InstRW<[N3Write_6c_3L], (instregex "LD3Rv(8b|4h|2s|1d)$")>;1487def : InstRW<[WriteAdr, N3Write_6c_3L], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;1488 1489// ASIMD load, 3 element, all lanes, Q-form, B/H/S1490// ASIMD load, 3 element, all lanes, Q-form, D1491def : InstRW<[N3Write_6c_3L], (instregex "LD3Rv(16b|8h|4s|2d)$")>;1492def : InstRW<[WriteAdr, N3Write_6c_3L], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;1493 1494// ASIMD load, 4 element, multiple, D-form, B/H/S1495def : InstRW<[N3Write_8c_4L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;1496def : InstRW<[WriteAdr, N3Write_8c_4L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;1497 1498// ASIMD load, 4 element, multiple, Q-form, B/H/S1499// ASIMD load, 4 element, multiple, Q-form, D1500def : InstRW<[N3Write_8c_4L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;1501def : InstRW<[WriteAdr, N3Write_8c_4L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;1502 1503// ASIMD load, 4 element, one lane, B/H1504// ASIMD load, 4 element, one lane, S1505// ASIMD load, 4 element, one lane, D1506def : InstRW<[N3Write_8c_4L_4V], (instregex "LD4i(8|16|32|64)$")>;1507def : InstRW<[WriteAdr, N3Write_8c_4L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;1508 1509// ASIMD load, 4 element, all lanes, D-form, B/H/S1510// ASIMD load, 4 element, all lanes, Q-form, B/H/S1511def : InstRW<[N3Write_8c_4L_3V], (instregex "LD4Rv(8b|4h|2s)$",1512 "LD4Rv(16b|8h|4s)$")>;1513def : InstRW<[WriteAdr, N3Write_8c_4L_3V], (instregex "LD4Rv(8b|4h|2s)_POST$",1514 "LD4Rv(16b|8h|4s)_POST$")>;1515 1516// ASIMD load, 4 element, all lanes, D-form, D1517// ASIMD load, 4 element, all lanes, Q-form, D1518def : InstRW<[N3Write_8c_4L_4V], (instregex "LD4Rv1d$", "LD4Rv2d$")>;1519def : InstRW<[WriteAdr, N3Write_8c_4L_4V], (instregex "LD4Rv1d_POST$", "LD4Rv2d_POST$")>;1520 1521// ASIMD store instructions1522// -----------------------------------------------------------------------------1523 1524// ASIMD store, 1 element, multiple, 1 reg, D-form1525def : InstRW<[N3Write_2c_1L01_1V], (instregex "ST1Onev(8b|4h|2s|1d)$")>;1526def : InstRW<[WriteAdr, N3Write_2c_1L01_1V], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;1527 1528// ASIMD store, 1 element, multiple, 1 reg, Q-form1529def : InstRW<[N3Write_2c_1L01_1V], (instregex "ST1Onev(16b|8h|4s|2d)$")>;1530def : InstRW<[WriteAdr, N3Write_2c_1L01_1V], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;1531 1532// ASIMD store, 1 element, multiple, 2 reg, D-form1533def : InstRW<[N3Write_2c_1L01_1V], (instregex "ST1Twov(8b|4h|2s|1d)$")>;1534def : InstRW<[WriteAdr, N3Write_2c_1L01_1V], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;1535 1536// ASIMD store, 1 element, multiple, 2 reg, Q-form1537def : InstRW<[N3Write_2c_1L01_1V], (instregex "ST1Twov(16b|8h|4s|2d)$")>;1538def : InstRW<[WriteAdr, N3Write_2c_1L01_1V], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;1539 1540// ASIMD store, 1 element, multiple, 3 reg, D-form1541def : InstRW<[N3Write_2c_2L01_2V], (instregex "ST1Threev(8b|4h|2s|1d)$")>;1542def : InstRW<[WriteAdr, N3Write_2c_2L01_2V], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;1543 1544// ASIMD store, 1 element, multiple, 3 reg, Q-form1545def : InstRW<[N3Write_2c_2L01_2V], (instregex "ST1Threev(16b|8h|4s|2d)$")>;1546def : InstRW<[WriteAdr, N3Write_2c_2L01_2V], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;1547 1548// ASIMD store, 1 element, multiple, 4 reg, D-form1549def : InstRW<[N3Write_2c_2L01_2V], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;1550def : InstRW<[WriteAdr, N3Write_2c_2L01_2V], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;1551 1552// ASIMD store, 1 element, multiple, 4 reg, Q-form1553def : InstRW<[N3Write_2c_2L01_2V], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;1554def : InstRW<[WriteAdr, N3Write_2c_2L01_2V], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;1555 1556// ASIMD store, 1 element, one lane, B/H/S1557// ASIMD store, 1 element, one lane, D1558def : InstRW<[N3Write_2c_1L01_1V], (instregex "ST1i(8|16|32|64)$")>;1559def : InstRW<[WriteAdr, N3Write_2c_1L01_1V], (instregex "ST1i(8|16|32|64)_POST$")>;1560 1561// ASIMD store, 2 element, multiple, D-form, B/H/S1562// ASIMD store, 2 element, multiple, Q-form, B/H/S1563// ASIMD store, 2 element, multiple, Q-form, D1564def : InstRW<[N3Write_2c_1V_1L01], (instregex "ST2Twov(8b|4h|2s)$",1565 "ST2Twov(16b|8h|4s|2d)$")>;1566def : InstRW<[WriteAdr, N3Write_2c_1V_1L01], (instregex "ST2Twov(8b|4h|2s)_POST$",1567 "ST2Twov(16b|8h|4s|2d)_POST$")>;1568 1569// ASIMD store, 2 element, one lane, B/H/S1570// ASIMD store, 2 element, one lane, D1571def : InstRW<[N3Write_2c_1V_1L01], (instregex "ST2i(8|16|32|64)$")>;1572def : InstRW<[WriteAdr, N3Write_2c_1V_1L01], (instregex "ST2i(8|16|32|64)_POST$")>;1573 1574// ASIMD store, 3 element, multiple, D-form, B/H/S1575def : InstRW<[N3Write_4c_2V_2L01], (instregex "ST3Threev(8b|4h|2s)$")>;1576def : InstRW<[WriteAdr, N3Write_4c_2V_2L01], (instregex "ST3Threev(8b|4h|2s)_POST$")>;1577 1578// ASIMD store, 3 element, multiple, Q-form, B/H/S1579def : InstRW<[N3Write_4c_3V_3L01], (instregex "ST3Threev(16b|8h|4s)$")>;1580def : InstRW<[WriteAdr, N3Write_4c_3V_3L01], (instregex "ST3Threev(16b|8h|4s)_POST$")>;1581 1582// ASIMD store, 3 element, multiple, Q-form, D1583def : InstRW<[N3Write_2c_3V_3L01], (instregex "ST3Threev2d$")>;1584def : InstRW<[WriteAdr, N3Write_2c_3V_3L01], (instregex "ST3Threev2d_POST$")>;1585 1586// ASIMD store, 3 element, one lane, B/H1587// ASIMD store, 3 element, one lane, S1588// ASIMD store, 3 element, one lane, D1589def : InstRW<[N3Write_2c_2V_2L01], (instregex "ST3i(8|16|32|64)$")>;1590def : InstRW<[WriteAdr, N3Write_2c_2V_2L01], (instregex "ST3i(8|16|32|64)_POST$")>;1591 1592// ASIMD store, 4 element, multiple, D-form, B/H/S1593def : InstRW<[N3Write_4c_2V_2L01], (instregex "ST4Fourv(8b|4h|2s)$")>;1594def : InstRW<[WriteAdr, N3Write_4c_2V_2L01], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;1595 1596// ASIMD store, 4 element, multiple, Q-form, B/H/S1597def : InstRW<[N3Write_4c_4V_4L01], (instregex "ST4Fourv(16b|8h|4s)$")>;1598def : InstRW<[WriteAdr, N3Write_4c_4V_4L01], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;1599 1600// ASIMD store, 4 element, multiple, Q-form, D1601def : InstRW<[N3Write_2c_2V_2L01], (instregex "ST4Fourv(2d)$")>;1602def : InstRW<[WriteAdr, N3Write_2c_2V_2L01], (instregex "ST4Fourv(2d)_POST$")>;1603 1604// ASIMD store, 4 element, one lane, B/H/S1605// ASIMD store, 4 element, one lane, D1606def : InstRW<[N3Write_2c_2V_2L01], (instregex "ST4i(8|16|32|64)$")>;1607def : InstRW<[WriteAdr, N3Write_2c_2V_2L01], (instregex "ST4i(8|16|32|64)_POST$")>;1608 1609// Cryptography extensions1610// -----------------------------------------------------------------------------1611 1612// Crypto AES ops1613def : InstRW<[N3Write_2c_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;1614 1615// Crypto polynomial (64x64) multiply long1616def : InstRW<[N3Write_2c_1V0], (instrs PMULLv1i64, PMULLv2i64)>;1617 1618// Crypto SHA1 hash acceleration op1619// Crypto SHA1 schedule acceleration ops1620def : InstRW<[N3Write_2c_1V0], (instregex "^SHA1(H|SU0|SU1)")>;1621 1622// Crypto SHA1 hash acceleration ops1623// Crypto SHA256 hash acceleration ops1624def : InstRW<[N3Write_4c_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>;1625 1626// Crypto SHA256 schedule acceleration ops1627def : InstRW<[N3Write_2c_1V0], (instregex "^SHA256SU[01]")>;1628 1629// Crypto SHA512 hash acceleration ops1630def : InstRW<[N3Write_2c_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>;1631 1632// Crypto SHA3 ops1633def : InstRW<[N3Write_2c_1V], (instrs BCAX, EOR3, RAX1, XAR)>;1634 1635// Crypto SM3 ops1636def : InstRW<[N3Write_2c_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$",1637 "^SM3TT[12][AB]$")>;1638 1639// Crypto SM4 ops1640def : InstRW<[N3Write_4c_1V0], (instrs SM4E, SM4ENCKEY)>;1641 1642// CRC1643// -----------------------------------------------------------------------------1644 1645// CRC checksum ops1646def : InstRW<[N3Wr_CRC, N3Rd_CRC], (instregex "^CRC32")>;1647 1648// SVE Predicate instructions1649// -----------------------------------------------------------------------------1650 1651// Loop control, based on predicate1652def : InstRW<[N3Write_2c_1M], (instrs BRKA_PPmP, BRKA_PPzP,1653 BRKB_PPmP, BRKB_PPzP)>;1654 1655// Loop control, based on predicate and flag setting1656def : InstRW<[N3Write_2c_1M], (instrs BRKAS_PPzP, BRKBS_PPzP)>;1657 1658// Loop control, propagating1659def : InstRW<[N3Write_2c_1M], (instrs BRKN_PPzP, BRKPA_PPzPP, BRKPB_PPzPP)>;1660 1661// Loop control, propagating and flag setting1662def : InstRW<[N3Write_2c_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP, BRKPBS_PPzPP)>;1663 1664// Loop control, based on GPR1665def : InstRW<[N3Write_2c_1M],1666 (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]$")>;1667def : InstRW<[N3Write_2c_1M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]$")>;1668 1669// Loop terminate1670def : InstRW<[N3Write_1c_1M], (instregex "^CTERM(EQ|NE)_(WW|XX)")>;1671 1672// Predicate counting scalar1673def : InstRW<[N3Write_1c_1I], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;1674def : InstRW<[N3Write_1c_1I],1675 (instregex "^(CNT|SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI",1676 "^SQ(DEC|INC)[BHWD]_XPiWdI",1677 "^UQ(DEC|INC)[BHWD]_WPiI")>;1678 1679// Predicate counting scalar, ALL, {1,2,4}1680def : InstRW<[N3Write_1c_1I], (instregex "^(DEC|INC)[BHWD]_XPiI")>;1681 1682// Predicate counting scalar, active predicate1683def : InstRW<[N3Write_2c_1M],1684 (instregex "^CNTP_XPP_[BHSD]",1685 "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]",1686 "^(UQDEC|UQINC)P_WP_[BHSD]",1687 "^(SQDEC|SQINC)P_XPWd_[BHSD]")>;1688 1689// Predicate counting vector, active predicate1690def : InstRW<[N3Write_7c_1M_1M0_1V],1691 (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]")>;1692 1693// Predicate logical1694def : InstRW<[N3Write_1c_1M],1695 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP")>;1696 1697// Predicate logical, flag setting1698def : InstRW<[N3Write_1c_1M],1699 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;1700 1701// Predicate reverse1702def : InstRW<[N3Write_2c_1M], (instregex "^REV_PP_[BHSD]")>;1703 1704// Predicate select1705def : InstRW<[N3Write_1c_1M], (instrs SEL_PPPP)>;1706 1707// Predicate set1708def : InstRW<[N3Write_0c], (instrs PFALSE)>;1709def : InstRW<[N3Write_0or2c_1M], (instregex "^PTRUE_[BHSD]")>;1710 1711// Predicate set/initialize, set flags1712def : InstRW<[N3Write_0or2c_1M], (instregex "^PTRUES_[BHSD]")>;1713 1714// Predicate find first/next1715def : InstRW<[N3Write_2c_1M], (instregex "^PFIRST_B$", "^PNEXT_[BHSD]$")>;1716 1717// Predicate test1718def : InstRW<[N3Write_1c_1M], (instrs PTEST_PP)>;1719 1720// Predicate transpose1721def : InstRW<[N3Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSDQ]$")>;1722 1723// Predicate unpack and widen1724def : InstRW<[N3Write_2c_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>;1725 1726// Predicate zip/unzip1727def : InstRW<[N3Write_2c_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSDQ]$")>;1728 1729// SVE integer instructions1730// -----------------------------------------------------------------------------1731 1732// Arithmetic, absolute diff1733def : InstRW<[N3Write_2c_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",1734 "^[SU]ABD_ZPZZ_[BHSD]")>;1735 1736// Arithmetic, absolute diff accum1737def : InstRW<[N3Wr_ZA, N3Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]$")>;1738 1739// Arithmetic, absolute diff accum long1740def : InstRW<[N3Wr_ZA, N3Rd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]$")>;1741 1742// Arithmetic, absolute diff long1743def : InstRW<[N3Write_2c_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]$")>;1744 1745// Arithmetic, basic1746def : InstRW<[N3Write_2c_1V],1747 (instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]",1748 "^(ADD|SUB)_ZZZ_[BHSD]",1749 "^(ADD|SUB|SUBR)_ZPZZ_[BHSD]",1750 "^(ADD|SUB|SUBR)_ZI_[BHSD]",1751 "^ADR_[SU]XTW_ZZZ_D_[0123]",1752 "^ADR_LSL_ZZZ_[SD]_[0123]",1753 "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",1754 "^SADDLBT_ZZZ_[HSD]",1755 "^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",1756 "^SSUBL(BT|TB)_ZZZ_[HSD]")>;1757 1758// Arithmetic, complex1759def : InstRW<[N3Write_2c_1V],1760 (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]",1761 "^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]",1762 "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]",1763 "^[SU]Q(ADD|SUB)_ZI_[BHSD]",1764 "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]",1765 "^(UQSUB|UQSUBR)_ZPmZ_[BHSD]")>;1766 1767// Arithmetic, large integer1768def : InstRW<[N3Write_2c_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]$")>;1769 1770// Arithmetic, pairwise add1771def : InstRW<[N3Write_2c_1V], (instregex "^ADDP_ZPmZ_[BHSD]$")>;1772 1773// Arithmetic, pairwise add and accum long1774def : InstRW<[N3Wr_ZPA, ReadDefault, N3Rd_ZPA],1775 (instregex "^[SU]ADALP_ZPmZ_[HSD]$")>;1776 1777// Arithmetic, shift1778def : InstRW<[N3Write_2c_1V1],1779 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",1780 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",1781 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",1782 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",1783 "^(ASR|LSL|LSR)_ZZI_[BHSD]",1784 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",1785 "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>;1786 1787// Arithmetic, shift and accumulate1788def : InstRW<[N3Wr_ZSA, N3Rd_ZSA],1789 (instregex "^(SRSRA|SSRA|URSRA|USRA)_ZZI_[BHSD]$")>;1790 1791// Arithmetic, shift by immediate1792// Arithmetic, shift by immediate and insert1793def : InstRW<[N3Write_2c_1V1],1794 (instregex "^(SHRNB|SHRNT|SSHLLB|SSHLLT|USHLLB|USHLLT|SLI|SRI)_ZZI_[BHSD]$")>;1795 1796// Arithmetic, shift complex1797def : InstRW<[N3Write_4c_1V1],1798 (instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]",1799 "^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]",1800 "^[SU]QR?SHL_ZPZZ_[BHSD]",1801 "^(SQSHL|SQSHLU|UQSHL)_(ZPmI|ZPZI)_[BHSD]",1802 "^SQSHRU?N[BT]_ZZI_[BHS]",1803 "^UQR?SHRN[BT]_ZZI_[BHS]")>;1804 1805// Arithmetic, shift right for divide1806def : InstRW<[N3Write_4c_1V1], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;1807 1808// Arithmetic, shift rounding1809def : InstRW<[N3Write_4c_1V1], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]",1810 "^[SU]RSHL_ZPZZ_[BHSD]",1811 "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>;1812 1813// Bit manipulation1814def : InstRW<[N3Write_4c_2V0], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>;1815 1816// Bitwise select1817def : InstRW<[N3Write_2c_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ$")>;1818 1819// Count/reverse bits1820def : InstRW<[N3Write_2c_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;1821 1822// Broadcast logical bitmask immediate to vector1823def : InstRW<[N3Write_2c_1V], (instrs DUPM_ZI)>;1824 1825// Compare and set flags1826def : InstRW<[N3Write_2c_1V],1827 (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]$",1828 "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]$")>;1829 1830// Complex add1831def : InstRW<[N3Write_2c_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]$")>;1832 1833// Complex dot product 8-bit element1834def : InstRW<[N3Wr_ZDOTB, N3Rd_ZDOTB], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;1835 1836// Complex dot product 16-bit element1837def : InstRW<[N3Wr_ZDOTH, N3Rd_ZDOTH], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;1838 1839// Complex multiply-add B, H, S element size1840def : InstRW<[N3Wr_ZCMABHS, N3Rd_ZCMABHS],1841 (instregex "^CMLA_ZZZ_[BHS]$", "^CMLA_ZZZI_[HS]$")>;1842 1843// Complex multiply-add D element size1844def : InstRW<[N3Wr_ZCMAD, N3Rd_ZCMAD], (instrs CMLA_ZZZ_D)>;1845 1846// Conditional extract operations, scalar form1847def : InstRW<[N3Write_8c_1M0_1V], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>;1848 1849// Conditional extract operations, SIMD&FP scalar and vector forms1850def : InstRW<[N3Write_2c_1V], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]$",1851 "^COMPACT_ZPZ_[SD]$",1852 "^SPLICE_ZPZZ?_[BHSD]$")>;1853 1854// Convert to floating point, 64b to float or convert to double1855def : InstRW<[N3Write_3c_1V0], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",1856 "^[SU]CVTF_ZPmZ_StoD")>;1857 1858// Convert to floating point, 32b to single or half1859def : InstRW<[N3Write_4c_2V0], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;1860 1861// Convert to floating point, 16b to half1862def : InstRW<[N3Write_6c_4V0], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;1863 1864// Copy, scalar1865def : InstRW<[N3Write_5c_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]$")>;1866 1867// Copy, scalar SIMD&FP or imm1868def : InstRW<[N3Write_2c_1V], (instregex "^CPY_ZPm[IV]_[BHSD]$",1869 "^CPY_ZPzI_[BHSD]$")>;1870 1871// SVE integer divide operations are now performed using1872// a fully pipelined data path.1873 1874// Divides, 32 bit1875def : InstRW<[N3Write_8c_8V0], (instregex "^[SU]DIVR?_ZPmZ_S",1876 "^[SU]DIV_ZPZZ_S")>;1877 1878// Divides, 64 bit1879def : InstRW<[N3Write_16c_16V0], (instregex "^[SU]DIVR?_ZPmZ_D",1880 "^[SU]DIV_ZPZZ_D")>;1881 1882// Dot product, 8 bit1883def : InstRW<[N3Wr_ZDOTB, N3Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_BtoS$")>;1884 1885// Dot product, 8 bit, using signed and unsigned integers1886def : InstRW<[N3Wr_ZDOTB, N3Rd_ZDOTB],1887 (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;1888 1889// Dot product, 16 bit1890def : InstRW<[N3Wr_ZDOTH, N3Rd_ZDOTH], (instregex "^[SU]DOT_ZZZI?_HtoD$")>;1891 1892// Duplicate, immediate and indexed form1893def : InstRW<[N3Write_2c_1V], (instregex "^DUP_ZI_[BHSD]$",1894 "^DUP_ZZI_[BHSDQ]$")>;1895 1896// Duplicate, scalar form1897def : InstRW<[N3Write_3c_1M0], (instregex "^DUP_ZR_[BHSD]$")>;1898 1899// Extend, sign or zero1900def : InstRW<[N3Write_2c_1V], (instregex "^[SU]XTB_ZPmZ_[HSD]",1901 "^[SU]XTH_ZPmZ_[SD]",1902 "^[SU]XTW_ZPmZ_[D]")>;1903 1904// Extract1905def : InstRW<[N3Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;1906 1907// Extract narrow saturating1908def : InstRW<[N3Write_4c_1V1], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]$",1909 "^SQXTUN[BT]_ZZ_[BHS]$")>;1910 1911// Extract/insert operation, SIMD and FP scalar form1912def : InstRW<[N3Write_2c_1V], (instregex "^LAST[AB]_VPZ_[BHSD]$",1913 "^INSR_ZV_[BHSD]$")>;1914 1915// Extract/insert operation, scalar1916def : InstRW<[N3Write_5c_1V], (instregex "^LAST[AB]_RPZ_[BHSD]$",1917 "^INSR_ZR_[BHSD]$")>;1918 1919// Histogram operations1920def : InstRW<[N3Write_2c_1V], (instregex "^HISTCNT_ZPzZZ_[SD]$",1921 "^HISTSEG_ZZZ$")>;1922 1923// Horizontal operations, B, H, S form, immediate operands only1924def : InstRW<[N3Write_2c_1V], (instregex "^INDEX_II_[BHS]$")>;1925 1926// Horizontal operations, B, H, S form, scalar, immediate operands / scalar operands only / immediate, scalar operands1927def : InstRW<[N3Write_5c_1M0_1V], (instregex "^INDEX_(IR|RI|RR)_[BHS]$")>;1928 1929// Horizontal operations, D form, immediate operands only1930def : InstRW<[N3Write_2c_1V], (instrs INDEX_II_D)>;1931 1932// Horizontal operations, D form, scalar, immediate operands / scalar operands only / immediate, scalar operands1933def : InstRW<[N3Write_5c_1M0_1V], (instregex "^INDEX_(IR|RI|RR)_D$")>;1934 1935// Logical1936def : InstRW<[N3Write_2c_1V],1937 (instregex "^(AND|EOR|ORR)_ZI",1938 "^(AND|BIC|EOR)_ZZZ",1939 "^EOR(BT|TB)_ZZZ_[BHSD]",1940 "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]",1941 "^NOT_ZPmZ_[BHSD]")>;1942def : InstRW<[N3Write_0or2c_1V], (instrs ORR_ZZZ)>;1943 1944// Max/min, basic and pairwise1945def : InstRW<[N3Write_2c_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",1946 "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]",1947 "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>;1948 1949// Matching operations1950def : InstRW<[N3Write_2c_1V], (instregex "^N?MATCH_PPzZZ_[BH]$")>;1951 1952// Matrix multiply-accumulate1953def : InstRW<[N3Wr_ZMMA, N3Rd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;1954 1955// Move prefix1956def : InstRW<[N3Write_2c_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$",1957 "^MOVPRFX_ZZ$")>;1958 1959// Multiply, B, H, S element size1960def : InstRW<[N3Write_4c_1V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]",1961 "^MUL_ZPZZ_[BHS]",1962 "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]",1963 "^[SU]MULH_ZPZZ_[BHS]")>;1964 1965// Multiply, D element size1966def : InstRW<[N3Write_5c_2V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D",1967 "^MUL_ZPZZ_D",1968 "^[SU]MULH_(ZPmZ|ZZZ)_D",1969 "^[SU]MULH_ZPZZ_D")>;1970 1971// Multiply long1972def : InstRW<[N3Write_4c_1V0], (instregex "^[SU]MULL[BT]_ZZZI_[SD]$",1973 "^[SU]MULL[BT]_ZZZ_[HSD]$")>;1974 1975// Multiply accumulate, B, H, S element size1976def : InstRW<[N3Wr_ZMABHS, ReadDefault, N3Rd_ZMABHS],1977 (instregex "^ML[AS]_ZZZI_[BHS]$",1978 "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_[BHS]")>;1979 1980// Multiply accumulate, D element size1981def : InstRW<[N3Wr_ZMAD, ReadDefault, N3Rd_ZMAD], (instregex "^ML[AS]_ZZZI_D$",1982 "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_D")>;1983 1984// Multiply accumulate long1985def : InstRW<[N3Wr_ZMAL, N3Rd_ZMAL], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]$",1986 "^[SU]ML[AS]L[BT]_ZZZI_[SD]$")>;1987 1988// Multiply accumulate saturating doubling long regular1989def : InstRW<[N3Wr_ZMASQL, N3Rd_ZMASQ],1990 (instregex "^SQDML[AS](LB|LT|LBT)_ZZZ_[HSD]$",1991 "^SQDML[AS](LB|LT)_ZZZI_[SD]$")>;1992 1993// Multiply saturating doubling high, B, H, S element size1994def : InstRW<[N3Write_4c_1V0], (instregex "^SQDMULH_ZZZ_[BHS]$",1995 "^SQDMULH_ZZZI_[HS]$")>;1996 1997// Multiply saturating doubling high, D element size1998def : InstRW<[N3Write_5c_2V0], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>;1999 2000// Multiply saturating doubling long2001def : InstRW<[N3Write_4c_1V0], (instregex "^SQDMULL[BT]_ZZZ_[HSD]$",2002 "^SQDMULL[BT]_ZZZI_[SD]$")>;2003 2004// Multiply saturating rounding doubling regular/complex accumulate, B, H, S element size2005def : InstRW<[N3Wr_ZMASQBHS, N3Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZ_[BHS]$",2006 "^SQRDCMLAH_ZZZ_[BHS]$",2007 "^SQRDML[AS]H_ZZZI_[HS]$",2008 "^SQRDCMLAH_ZZZI_[HS]$")>;2009 2010// Multiply saturating rounding doubling regular/complex accumulate, D element size2011def : InstRW<[N3Wr_ZMASQD, N3Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZI?_D$",2012 "^SQRDCMLAH_ZZZ_D$")>;2013 2014// Multiply saturating rounding doubling regular/complex, B, H, S element size2015def : InstRW<[N3Write_4c_1V0], (instregex "^SQRDMULH_ZZZ_[BHS]$",2016 "^SQRDMULH_ZZZI_[HS]$")>;2017 2018// Multiply saturating rounding doubling regular/complex, D element size2019def : InstRW<[N3Write_5c_2V0], (instregex "^SQRDMULH_ZZZI?_D$")>;2020 2021// Multiply/multiply long, (8x8) polynomial2022def : InstRW<[N3Write_2c_1V0], (instregex "^PMUL_ZZZ_B$",2023 "^PMULL[BT]_ZZZ_[HDQ]$")>;2024 2025// Predicate counting vector2026def : InstRW<[N3Write_2c_1V],2027 (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)[HWD]_ZPiI$")>;2028 2029// Reciprocal estimate2030def : InstRW<[N3Write_4c_1V0], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;2031 2032// Reduction, arithmetic, B form2033def : InstRW<[N3Write_8c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;2034 2035// Reduction, arithmetic, H form2036def : InstRW<[N3Write_7c_1V_1V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;2037 2038// Reduction, arithmetic, S form2039def : InstRW<[N3Write_4c_1V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;2040 2041// Reduction, arithmetic, D form2042def : InstRW<[N3Write_4c_1V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;2043 2044// Reduction, logical2045def : InstRW<[N3Write_5c_1V_1V1], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]$")>;2046 2047// Reverse, vector2048def : InstRW<[N3Write_2c_1V], (instregex "^REV_ZZ_[BHSD]$",2049 "^REVB_ZPmZ_[HSD]$",2050 "^REVH_ZPmZ_[SD]$",2051 "^REVW_ZPmZ_D$")>;2052 2053// Select, vector form2054// Table lookup2055// Table lookup extension2056// Transpose, vector form2057// Unpack and extend2058// Zip/unzip2059def : InstRW<[N3Write_2c_1V], (instregex "^SEL_ZPZZ_[BHSD]$",2060 "^TBL_ZZZZ?_[BHSD]$",2061 "^TBX_ZZZ_[BHSD]$",2062 "^TRN[12]_ZZZ_[BHSDQ]$",2063 "^[SU]UNPK(HI|LO)_ZZ_[HSD]$",2064 "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>;2065 2066// SVE floating-point instructions2067// -----------------------------------------------------------------------------2068 2069// Floating point absolute value/difference2070def : InstRW<[N3Write_2c_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]",2071 "^FABD_ZPZZ_[HSD]",2072 "^FABS_ZPmZ_[HSD]")>;2073 2074// Floating point arithmetic2075def : InstRW<[N3Write_2c_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",2076 "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",2077 "^FNEG_ZPmZ_[HSD]",2078 "^FSUBR_ZPm[IZ]_[HSD]",2079 "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;2080 2081// Floating point associative add, F162082def : InstRW<[N3Write_16c_8V], (instrs FADDA_VPZ_H)>;2083 2084// Floating point associative add, F322085def : InstRW<[N3Write_8c_4V], (instrs FADDA_VPZ_S)>;2086 2087// Floating point associative add, F642088def : InstRW<[N3Write_4c_2V], (instrs FADDA_VPZ_D)>;2089 2090// Floating point compare2091def : InstRW<[N3Write_2c_1V], (instregex "^FAC(GE|GT)_PPzZZ_[HSD]$",2092 "^FCM(EQ|GE|GT|NE|UO)_PPzZZ_[HSD]$",2093 "^FCM(EQ|GE|GT|LE|LT|NE)_PPzZ0_[HSD]$")>;2094 2095// Floating point complex add2096def : InstRW<[N3Write_3c_1V], (instregex "^FCADD_ZPmZ_[HSD]$")>;2097 2098// Floating point complex multiply add2099def : InstRW<[N3Wr_ZFCMA, ReadDefault, N3Rd_ZFCMA],2100 (instregex "^FCMLA_ZPmZZ_[HSD]")>;2101def : InstRW<[N3Wr_ZFCMA, N3Rd_ZFCMA], (instregex "^FCMLA_ZZZI_[HS]")>;2102 2103// Floating point convert, long or narrow (F16 to F32 or F32 to F16)2104def : InstRW<[N3Write_4c_2V0], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",2105 "^FCVTLT_ZPmZ_HtoS",2106 "^FCVTNT_ZPmZ_StoH")>;2107 2108// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F32 or F64 to F16)2109def : InstRW<[N3Write_3c_1V0], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",2110 "^FCVTLT_ZPmZ_StoD",2111 "^FCVTNT_ZPmZ_DtoS")>;2112 2113// Floating point convert, round to odd2114def : InstRW<[N3Write_3c_1V0], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>;2115 2116// Floating point base2 log, F162117def : InstRW<[N3Write_6c_4V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;2118 2119// Floating point base2 log, F322120def : InstRW<[N3Write_4c_2V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;2121 2122// Floating point base2 log, F642123def : InstRW<[N3Write_3c_1V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;2124 2125// Floating point convert to integer, F162126def : InstRW<[N3Write_6c_4V0], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;2127 2128// Floating point convert to integer, F322129def : InstRW<[N3Write_4c_2V0], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;2130 2131// Floating point convert to integer, F642132def : InstRW<[N3Write_3c_1V0],2133 (instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>;2134 2135// Floating point copy2136def : InstRW<[N3Write_2c_1V], (instregex "^FCPY_ZPmI_[HSD]$",2137 "^FDUP_ZI_[HSD]$")>;2138 2139// SVE FP divide and square root operations are now performed using2140// a fully pipelined data path.2141 2142// Floating point divide, F162143def : InstRW<[N3Write_12c_8V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;2144 2145// Floating point divide, F322146def : InstRW<[N3Write_10c_4V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;2147 2148// Floating point divide, F642149def : InstRW<[N3Write_13c_2V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;2150 2151// Floating point arith, min/max pairwise2152def : InstRW<[N3Write_3c_1V], (instregex "^FADDP_ZPmZZ_[HSD]",2153 "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;2154 2155// Floating point min/max2156def : InstRW<[N3Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",2157 "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;2158 2159// Floating point multiply2160def : InstRW<[N3Write_3c_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",2161 "^FMULX_ZPZZ_[HSD]",2162 "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",2163 "^FMUL_ZPZ[IZ]_[HSD]")>;2164 2165// Floating point multiply accumulate2166def : InstRW<[N3Wr_ZFMA, ReadDefault, N3Rd_ZFMA],2167 (instregex "^FN?ML[AS]_ZPmZZ_[HSD]",2168 "^FN?(MAD|MSB)_ZPmZZ_[HSD]")>;2169def : InstRW<[N3Wr_ZFMA, N3Rd_ZFMA],2170 (instregex "^FML[AS]_ZZZI_[HSD]",2171 "^FN?ML[AS]_ZPZZZ_[HSD]")>;2172 2173// Floating point multiply add/sub accumulate long2174def : InstRW<[N3Wr_ZFMAL, N3Rd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH$")>;2175 2176// Floating point reciprocal estimate, F162177def : InstRW<[N3Write_6c_4V0], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;2178 2179// Floating point reciprocal estimate, F322180def : InstRW<[N3Write_4c_2V0], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>;2181 2182// Floating point reciprocal estimate, F642183def : InstRW<[N3Write_3c_1V0], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>;2184 2185// Floating point reciprocal step2186def : InstRW<[N3Write_4c_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]$")>;2187 2188// Floating point reduction, F162189def : InstRW<[N3Write_6c_3V],2190 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H$")>;2191 2192// Floating point reduction, F322193def : InstRW<[N3Write_4c_2V],2194 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S$")>;2195 2196// Floating point reduction, F642197def : InstRW<[N3Write_2c_1V],2198 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D$")>;2199 2200// Floating point round to integral, F162201def : InstRW<[N3Write_6c_4V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;2202 2203// Floating point round to integral, F322204def : InstRW<[N3Write_4c_2V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;2205 2206// Floating point round to integral, F642207def : InstRW<[N3Write_3c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;2208 2209// Floating point square root, F162210def : InstRW<[N3Write_12c_8V0], (instregex "^FSQRT_ZPmZ_H")>;2211 2212// Floating point square root, F322213def : InstRW<[N3Write_10c_4V0], (instregex "^FSQRT_ZPmZ_S")>;2214 2215// Floating point square root F642216def : InstRW<[N3Write_13c_2V0], (instregex "^FSQRT_ZPmZ_D")>;2217 2218// Floating point trigonometric exponentiation2219def : InstRW<[N3Write_2c_1V], (instregex "^FEXPA_ZZ_[HSD]$")>;2220 2221// Floating point trigonometric multiply add2222def : InstRW<[N3Write_4c_1V], (instregex "^FTMAD_ZZI_[HSD]$")>;2223 2224// Floating point trigonometric, miscellaneous2225def : InstRW<[N3Write_3c_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]$")>;2226 2227// SVE BFloat16 (BF16) instructions2228// -----------------------------------------------------------------------------2229 2230// Convert, F32 to BF162231def : InstRW<[N3Write_4c_2V0], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;2232 2233// Dot product2234def : InstRW<[N3Wr_ZBFDOT, N3Rd_ZBFDOT], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;2235 2236// Matrix multiply accumulate2237def : InstRW<[N3Wr_ZBFMMA, N3Rd_ZBFMMA], (instrs BFMMLA_ZZZ_HtoS)>;2238 2239// Multiply accumulate long2240def : InstRW<[N3Wr_ZBFMAL, N3Rd_ZBFMAL], (instregex "^BFMLAL[BT]_ZZZ(I)?$")>;2241 2242// SVE Load instructions2243// -----------------------------------------------------------------------------2244 2245// Load vector2246def : InstRW<[N3Write_6c_1L], (instrs LDR_ZXI)>;2247 2248// Load predicate2249def : InstRW<[N3Write_7c_1L_1M], (instrs LDR_PXI)>;2250 2251// Contiguous load, scalar + imm2252def : InstRW<[N3Write_6c_1L], (instregex "^LD1[BHWD]_IMM$",2253 "^LD1S?B_[HSD]_IMM$",2254 "^LD1S?H_[SD]_IMM$",2255 "^LD1S?W_D_IMM$" )>;2256 2257// Contiguous load, scalar + scalar2258def : InstRW<[N3Write_6c_1L], (instregex "^LD1[BHWD]$",2259 "^LD1S?B_[HSD]$",2260 "^LD1S?H_[SD]$",2261 "^LD1S?W_D$" )>;2262 2263// Contiguous load broadcast, scalar + imm2264def : InstRW<[N3Write_6c_1L], (instregex "^LD1R[BHWD]_IMM$",2265 "^LD1RSW_IMM$",2266 "^LD1RS?B_[HSD]_IMM$",2267 "^LD1RS?H_[SD]_IMM$",2268 "^LD1RS?W_D_IMM$",2269 "^LD1RQ_[BHWD]_IMM$")>;2270 2271// Contiguous load broadcast, scalar + scalar2272def : InstRW<[N3Write_6c_1L], (instregex "^LD1RQ_[BHWD]$")>;2273 2274// Non temporal load, scalar + imm2275def : InstRW<[N3Write_6c_1L], (instregex "^LDNT1[BHWD]_ZRI$")>;2276 2277// Non temporal load, scalar + scalar2278def : InstRW<[N3Write_6c_1L], (instregex "^LDNT1[BHWD]_ZRR$")>;2279 2280// Non temporal gather load, vector + scalar 32-bit element size2281def : InstRW<[N3Write_7c_4L], (instregex "^LDNT1[BHW]_ZZR_S$",2282 "^LDNT1S[BH]_ZZR_S$")>;2283 2284// Non temporal gather load, vector + scalar 64-bit element size2285def : InstRW<[N3Write_6c_2L01_2V], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;2286def : InstRW<[N3Write_6c_2L01_2V], (instrs LDNT1D_ZZR_D)>;2287 2288// Contiguous first faulting load, scalar + scalar2289def : InstRW<[N3Write_6c_1L], (instregex "^LDFF1[BHWD]$",2290 "^LDFF1S?B_[HSD]$",2291 "^LDFF1S?H_[SD]$",2292 "^LDFF1S?W_D$")>;2293 2294// Contiguous non faulting load, scalar + imm2295def : InstRW<[N3Write_6c_1L], (instregex "^LDNF1[BHWD]_IMM$",2296 "^LDNF1S?B_[HSD]_IMM$",2297 "^LDNF1S?H_[SD]_IMM$",2298 "^LDNF1S?W_D_IMM$")>;2299 2300// Contiguous Load two structures to two vectors, scalar + imm2301def : InstRW<[N3Write_8c_1V_1L], (instregex "^LD2[BHWD]_IMM$")>;2302 2303// Contiguous Load two structures to two vectors, scalar + scalar2304def : InstRW<[N3Write_8c_1V_1L], (instregex "^LD2[BHWD]$")>;2305 2306// Contiguous Load three structures to three vectors, scalar + imm2307def : InstRW<[N3Write_8c_3L_3V], (instregex "^LD3D_IMM$")>;2308 2309// Contiguous Load three structures to three vectors, scalar + imm2310def : InstRW<[N3Write_10c_6V_3L], (instregex "^LD3[BHW]_IMM$")>;2311 2312// Contiguous Load three structures to three vectors, scalar + scalar2313def : InstRW<[N3Write_9c_3V_3L_3I], (instregex "^LD3D$")>;2314 2315// Contiguous Load three structures to three vectors, scalar + scalar2316def : InstRW<[N3Write_11c_6V_3L_6I], (instregex "^LD3[BHW]$")>;2317 2318// Contiguous Load four structures to four vectors, scalar + imm2319def : InstRW<[N3Write_8c_4L_4V], (instregex "^LD4D_IMM$")>;2320 2321// Contiguous Load four structures to four vectors, scalar + imm2322def : InstRW<[N3Write_12c_5V_4L], (instregex "^LD4[BHW]_IMM$")>;2323 2324// Contiguous Load four structures to four vectors, scalar + scalar2325def : InstRW<[N3Write_9c_4L_4V_4I], (instregex "^LD4D$")>;2326 2327// Contiguous Load four structures to four vectors, scalar + scalar2328def : InstRW<[N3Write_13c_4L_5V_5I], (instregex "^LD4[BHW]$")>;2329 2330// Gather load, vector + imm, 32-bit element size2331def : InstRW<[N3Write_7c_4L], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",2332 "^GLD(FF)?1W_IMM$")>;2333 2334// Gather load, vector + imm, 64-bit element size2335def : InstRW<[N3Write_6c_2L01_2V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",2336 "^GLD(FF)?1D_IMM$")>;2337 2338// Gather load, 64-bit element size2339def : InstRW<[N3Write_6c_2L01_2V],2340 (instregex "^GLD(FF)?1S?[BHW]_D_[SU]XTW(_SCALED)?$",2341 "^GLD(FF)?1S?[BHW]_D(_SCALED)?$",2342 "^GLD(FF)?1D_[SU]XTW(_SCALED)?$",2343 "^GLD(FF)?1D(_SCALED)?$")>;2344 2345// Gather load, 32-bit element size2346def : InstRW<[N3Write_7c_4L],2347 (instregex "^GLD(FF)?1S?[HW]_S_[SU]XTW_SCALED$",2348 "^GLD(FF)?1W_[SU]XTW_SCALED",2349 "^GLD(FF)?1S?[BH]_S_[SU]XTW$",2350 "^GLD(FF)?1W_[SU]XTW$")>;2351 2352// SVE Store instructions2353// -----------------------------------------------------------------------------2354 2355// Store from predicate reg2356def : InstRW<[N3Write_1c_1L01], (instrs STR_PXI)>;2357 2358// Store from vector reg2359def : InstRW<[N3Write_2c_1L01_1V], (instrs STR_ZXI)>;2360 2361// Contiguous store, scalar + imm2362def : InstRW<[N3Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$",2363 "^ST1B_[HSD]_IMM$",2364 "^ST1H_[SD]_IMM$",2365 "^ST1W_D_IMM$")>;2366 2367// Contiguous store, scalar + scalar2368def : InstRW<[N3Write_2c_1L01_1I_1V], (instregex "^ST1H(_[SD])?$")>;2369 2370// Contiguous store, scalar + scalar2371def : InstRW<[N3Write_2c_1L01_1V], (instregex "^ST1[BWD]$",2372 "^ST1B_[HSD]$",2373 "^ST1W_D$")>;2374 2375// Contiguous store two structures from two vectors, scalar + imm2376def : InstRW<[N3Write_2c_1L01_1V], (instregex "^ST2[BHWD]_IMM$")>;2377 2378// Contiguous store two structures from two vectors, scalar + scalar2379def : InstRW<[N3Write_2c_1L01_1V], (instregex "^ST2[BHWD]$")>;2380 2381// Contiguous store three structures from three vectors, scalar + imm2382def : InstRW<[N3Write_4c_3L01_3V], (instregex "^ST3[BHW]_IMM$")>;2383 2384// Contiguous store three structures from three vectors, scalar + imm2385def : InstRW<[N3Write_3c_3L01_3V], (instregex "^ST3D_IMM$")>;2386 2387// Contiguous store three structures from three vectors, scalar + scalar2388def : InstRW<[N3Write_4c_3L01_3I_3V], (instregex "^ST3[BHW]$")>;2389 2390// Contiguous store three structures from three vectors, scalar + scalar2391def : InstRW<[N3Write_3c_3L01_3I_3V], (instregex "^ST3D$")>;2392 2393// Contiguous store four structures from four vectors, scalar + imm2394def : InstRW<[N3Write_6c_3L01_3V], (instregex "^ST4[BHW]_IMM$")>;2395 2396// Contiguous store four structures from four vectors, scalar + imm2397def : InstRW<[N3Write_3c_4L01_4V], (instregex "^ST4D_IMM$")>;2398 2399// Contiguous store four structures from four vectors, scalar + scalar2400def : InstRW<[N3Write_3c_4L01_4I_4V], (instregex "^ST4D$")>;2401 2402// Contiguous store four structures from four vectors, scalar + scalar2403def : InstRW<[N3Write_6c_3L01_3I_3V], (instregex "^ST4[BHW]$")>;2404 2405// Non temporal store, scalar + imm2406def : InstRW<[N3Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$")>;2407 2408// Non temporal store, scalar + scalar2409def : InstRW<[N3Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZRR$")>;2410 2411// Scatter non temporal store, vector + scalar 32-bit element size2412def : InstRW<[N3Write_2c_2L01_2V], (instregex "^STNT1[BHW]_ZZR_S")>;2413 2414// Scatter non temporal store, vector + scalar 64-bit element size2415def : InstRW<[N3Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZZR_D")>;2416 2417// Scatter store vector + imm 32-bit element size2418def : InstRW<[N3Write_2c_2L01_2V], (instregex "^SST1[BH]_S_IMM$",2419 "^SST1W_IMM$")>;2420 2421// Scatter store vector + imm 64-bit element size2422def : InstRW<[N3Write_2c_1L01_1V], (instregex "^SST1[BHW]_D_IMM$",2423 "^SST1D_IMM$")>;2424 2425// Scatter store, 32-bit scaled offset2426def : InstRW<[N3Write_2c_2L01_2V],2427 (instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>;2428 2429// Scatter store, 32-bit unpacked unscaled offset2430def : InstRW<[N3Write_2c_1L01_1V], (instregex "^SST1[BHW]_D_[SU]XTW$",2431 "^SST1D_[SU]XTW$")>;2432 2433// Scatter store, 32-bit unpacked scaled offset2434def : InstRW<[N3Write_2c_1L01_1V], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",2435 "^SST1D_[SU]XTW_SCALED$")>;2436 2437// Scatter store, 32-bit unscaled offset2438def : InstRW<[N3Write_2c_2L01_2V], (instregex "^SST1[BH]_S_[SU]XTW$",2439 "^SST1W_[SU]XTW$")>;2440 2441// Scatter store, 64-bit scaled offset2442def : InstRW<[N3Write_2c_1L01_1V], (instregex "^SST1[HW]_D_SCALED$",2443 "^SST1D_SCALED$")>;2444 2445// Scatter store, 64-bit unscaled offset2446def : InstRW<[N3Write_2c_1L01_1V], (instregex "^SST1[BHW]_D$",2447 "^SST1D$")>;2448 2449// SVE Miscellaneous instructions2450// -----------------------------------------------------------------------------2451 2452// Read first fault register, unpredicated2453def : InstRW<[N3Write_2c_1M], (instrs RDFFR_P)>;2454 2455// Read first fault register, predicated2456def : InstRW<[N3Write_2c_1M], (instrs RDFFR_PPz)>;2457 2458// Read first fault register and set flags2459def : InstRW<[N3Write_2c_1M], (instrs RDFFRS_PPz)>;2460 2461// Set first fault register2462def : InstRW<[N3Write_0c], (instrs SETFFR)>;2463 2464// Write to first fault register2465def : InstRW<[N3Write_2c_1M0], (instrs WRFFR)>;2466 2467// Prefetch2468def : InstRW<[N3Write_4c_1L], (instregex "^PRF[BHWD]")>;2469 2470// SVE Cryptographic instructions2471// -----------------------------------------------------------------------------2472 2473// Crypto AES ops2474def : InstRW<[N3Write_2c_1V], (instregex "^AES[DE]_ZZZ_B$",2475 "^AESI?MC_ZZ_B$")>;2476 2477// Crypto SHA3 ops2478def : InstRW<[N3Write_2c_1V], (instregex "^(BCAX|EOR3)_ZZZZ$",2479 "^RAX1_ZZZ_D$",2480 "^XAR_ZZZI_[BHSD]$")>;2481 2482// Crypto SM4 ops2483def : InstRW<[N3Write_4c_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;2484 2485}2486