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1//=- AArch64SchedNeoverseV1.td - NeoverseV1 Scheduling Model -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the scheduling model for the Arm Neoverse V1 processors.10//11// References:12// - "Arm Neoverse V1 Software Optimization Guide"13// - "Arm Neoverse V1 Platform: Unleashing a new performance tier for Arm-based computing"14// https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/neoverse-v1-platform-a-new-performance-tier-for-arm15// - "Neoverse V1"16// https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v117 18//19//===----------------------------------------------------------------------===//20 21def NeoverseV1Model : SchedMachineModel {22 let IssueWidth = 8; // This value comes from the decode bandwidth23 // and empirical measurements showed that this24 // value is better.25 let MicroOpBufferSize = 256; // Micro-op re-order buffer.26 let LoadLatency = 4; // Optimistic load latency.27 let MispredictPenalty = 11; // Cycles cost of branch mispredicted.28 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.29 let CompleteModel = 1;30 31 list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,32 SMEUnsupported.F,33 [HasMTE, HasCPA,34 HasCSSC]);35}36 37//===----------------------------------------------------------------------===//38// Define each kind of processor resource and number available on Neoverse V1.39// Instructions are first fetched and then decoded into internal macro-ops40// (MOPs). From there, the MOPs proceed through register renaming and dispatch41// stages. A MOP can be split into one or more micro-ops further down the42// pipeline, after the decode stage. Once dispatched, micro-ops wait for their43// operands and issue out-of-order to one of the issue pipelines. Each issue44// pipeline can accept one micro-op per cycle.45 46let SchedModel = NeoverseV1Model in {47 48// Define the issue ports.49def V1UnitB : ProcResource<2>; // Branch 0/150def V1UnitS : ProcResource<2>; // Integer single cycle 0/151def V1UnitM0 : ProcResource<1>; // Integer multicycle 052def V1UnitM1 : ProcResource<1>; // Integer multicycle 153def V1UnitL01 : ProcResource<2>; // Load/Store 0/154def V1UnitL2 : ProcResource<1>; // Load 255def V1UnitD : ProcResource<2>; // Store data 0/156def V1UnitV0 : ProcResource<1>; // FP/ASIMD 057def V1UnitV1 : ProcResource<1>; // FP/ASIMD 158def V1UnitV2 : ProcResource<1>; // FP/ASIMD 259def V1UnitV3 : ProcResource<1>; // FP/ASIMD 360def V1UnitFlg : ProcResource<3>; // Flags61 62def V1UnitI : ProcResGroup<[V1UnitS,63 V1UnitM0, V1UnitM1]>; // Integer units64def V1UnitM : ProcResGroup<[V1UnitM0, V1UnitM1]>; // Integer multicycle units65def V1UnitL : ProcResGroup<[V1UnitL01, V1UnitL2]>; // Load units66def V1UnitV : ProcResGroup<[V1UnitV0, V1UnitV1,67 V1UnitV2, V1UnitV3]>; // FP/ASIMD units68def V1UnitV01 : ProcResGroup<[V1UnitV0, V1UnitV1]>; // FP/ASIMD 0/1 units69def V1UnitV02 : ProcResGroup<[V1UnitV0, V1UnitV2]>; // FP/ASIMD 0/2 units70def V1UnitV13 : ProcResGroup<[V1UnitV1, V1UnitV3]>; // FP/ASIMD 1/3 units71 72// Define commonly used read types.73 74// No generic forwarding is provided for these types.75def : ReadAdvance<ReadI, 0>;76def : ReadAdvance<ReadISReg, 0>;77def : ReadAdvance<ReadIEReg, 0>;78def : ReadAdvance<ReadIM, 0>;79def : ReadAdvance<ReadIMA, 0>;80def : ReadAdvance<ReadID, 0>;81def : ReadAdvance<ReadExtrHi, 0>;82def : ReadAdvance<ReadAdrBase, 0>;83def : ReadAdvance<ReadST, 0>;84def : ReadAdvance<ReadVLD, 0>;85 86def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }87def : WriteRes<WriteBarrier, []> { let Latency = 1; }88def : WriteRes<WriteHint, []> { let Latency = 1; }89 90 91//===----------------------------------------------------------------------===//92// Define generic 0 micro-op types93 94let Latency = 0, NumMicroOps = 0 in95def V1Write_0c_0Z : SchedWriteRes<[]>;96 97def V1Write_0c : SchedWriteRes<[]> { let Latency = 0; }98 99//===----------------------------------------------------------------------===//100// Define generic 1 micro-op types101 102def V1Write_1c_1B : SchedWriteRes<[V1UnitB]> { let Latency = 1; }103def V1Write_1c_1I : SchedWriteRes<[V1UnitI]> { let Latency = 1; }104def V1Write_1c_1I_1Flg : SchedWriteRes<[V1UnitI, V1UnitFlg]> { let Latency = 1; }105def V1Write_4c_1L : SchedWriteRes<[V1UnitL]> { let Latency = 4; }106def V1Write_6c_1L : SchedWriteRes<[V1UnitL]> { let Latency = 6; }107def V1Write_1c_1L01 : SchedWriteRes<[V1UnitL01]> { let Latency = 1; }108def V1Write_4c_1L01 : SchedWriteRes<[V1UnitL01]> { let Latency = 4; }109def V1Write_6c_1L01 : SchedWriteRes<[V1UnitL01]> { let Latency = 6; }110def V1Write_2c_1M : SchedWriteRes<[V1UnitM]> { let Latency = 2; }111def V1Write_2c_1M_1Flg : SchedWriteRes<[V1UnitM, V1UnitFlg]> { let Latency = 2; }112def V1Write_3c_1M : SchedWriteRes<[V1UnitM]> { let Latency = 3; }113def V1Write_4c_1M : SchedWriteRes<[V1UnitM]> { let Latency = 4; }114def V1Write_1c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 1; }115def V1Write_2c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 2; }116def V1Write_3c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 3; }117def V1Write_5c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 5; }118def V1Write_12c5_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 12;119 let ReleaseAtCycles = [5]; }120def V1Write_20c5_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 20;121 let ReleaseAtCycles = [5]; }122def V1Write_2c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 2; }123def V1Write_3c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 3; }124def V1Write_4c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 4; }125def V1Write_5c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 5; }126def V1Write_2c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 2; }127def V1Write_3c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 3; }128def V1Write_4c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 4; }129def V1Write_6c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 6; }130def V1Write_10c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 10;131 let ReleaseAtCycles = [7]; }132def V1Write_12c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 12;133 let ReleaseAtCycles = [7]; }134def V1Write_13c10_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 13;135 let ReleaseAtCycles = [10]; }136def V1Write_15c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 15;137 let ReleaseAtCycles = [7]; }138def V1Write_16c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 16;139 let ReleaseAtCycles = [7]; }140def V1Write_20c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 20;141 let ReleaseAtCycles = [7]; }142def V1Write_2c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 2; }143def V1Write_3c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 3; }144def V1Write_4c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 4; }145def V1Write_5c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 5; }146def V1Write_3c_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 3; }147def V1Write_4c_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 4; }148def V1Write_7c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 7;149 let ReleaseAtCycles = [7]; }150def V1Write_10c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 10;151 let ReleaseAtCycles = [7]; }152def V1Write_13c5_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13;153 let ReleaseAtCycles = [5]; }154def V1Write_13c11_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13;155 let ReleaseAtCycles = [11]; }156def V1Write_15c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 15;157 let ReleaseAtCycles = [7]; }158def V1Write_16c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 16;159 let ReleaseAtCycles = [7]; }160def V1Write_2c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 2; }161def V1Write_3c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 3; }162def V1Write_4c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 4; }163def V1Write_2c_1V13 : SchedWriteRes<[V1UnitV13]> { let Latency = 2; }164def V1Write_4c_1V13 : SchedWriteRes<[V1UnitV13]> { let Latency = 4; }165 166//===----------------------------------------------------------------------===//167// Define generic 2 micro-op types168 169let Latency = 1, NumMicroOps = 2 in170def V1Write_1c_1B_1S : SchedWriteRes<[V1UnitB, V1UnitS]>;171let Latency = 6, NumMicroOps = 2 in172def V1Write_6c_1B_1M0 : SchedWriteRes<[V1UnitB, V1UnitM0]>;173let Latency = 3, NumMicroOps = 2 in174def V1Write_3c_1I_1M : SchedWriteRes<[V1UnitI, V1UnitM]>;175let Latency = 5, NumMicroOps = 2 in176def V1Write_5c_1I_1L : SchedWriteRes<[V1UnitI, V1UnitL]>;177let Latency = 7, NumMicroOps = 2 in178def V1Write_7c_1I_1L : SchedWriteRes<[V1UnitI, V1UnitL]>;179let Latency = 6, NumMicroOps = 2 in180def V1Write_6c_2L : SchedWriteRes<[V1UnitL, V1UnitL]>;181let Latency = 6, NumMicroOps = 2 in182def V1Write_6c_1L_1M : SchedWriteRes<[V1UnitL, V1UnitM]>;183let Latency = 8, NumMicroOps = 2 in184def V1Write_8c_1L_1V : SchedWriteRes<[V1UnitL, V1UnitV]>;185let Latency = 9, NumMicroOps = 2 in186def V1Write_9c_1L_1V : SchedWriteRes<[V1UnitL, V1UnitV]>;187let Latency = 11, NumMicroOps = 2 in188def V1Write_11c_1L_1V : SchedWriteRes<[V1UnitL, V1UnitV]>;189let Latency = 1, NumMicroOps = 2 in190def V1Write_1c_1L01_1D : SchedWriteRes<[V1UnitL01, V1UnitD]>;191let Latency = 6, NumMicroOps = 2 in192def V1Write_6c_1L01_1S : SchedWriteRes<[V1UnitL01, V1UnitS]>;193let Latency = 7, NumMicroOps = 2 in194def V1Write_7c_1L01_1S : SchedWriteRes<[V1UnitL01, V1UnitS]>;195let Latency = 2, NumMicroOps = 2 in196def V1Write_2c_1L01_1V : SchedWriteRes<[V1UnitL01, V1UnitV]>;197let Latency = 4, NumMicroOps = 2 in198def V1Write_4c_1L01_1V : SchedWriteRes<[V1UnitL01, V1UnitV]>;199let Latency = 6, NumMicroOps = 2 in200def V1Write_6c_1L01_1V : SchedWriteRes<[V1UnitL01, V1UnitV]>;201let Latency = 2, NumMicroOps = 2 in202def V1Write_2c_1L01_1V01 : SchedWriteRes<[V1UnitL01, V1UnitV01]>;203let Latency = 4, NumMicroOps = 2 in204def V1Write_4c_1L01_1V01 : SchedWriteRes<[V1UnitL01, V1UnitV01]>;205let Latency = 2, NumMicroOps = 2 in206def V1Write_2c_2M0 : SchedWriteRes<[V1UnitM0, V1UnitM0]>;207let Latency = 3, NumMicroOps = 2 in208def V1Write_3c_2M0 : SchedWriteRes<[V1UnitM0, V1UnitM0]>;209let Latency = 9, NumMicroOps = 2 in210def V1Write_9c_1M0_1L : SchedWriteRes<[V1UnitM0, V1UnitL]>;211let Latency = 5, NumMicroOps = 2 in212def V1Write_5c_1M0_1V : SchedWriteRes<[V1UnitM0, V1UnitV]>;213let Latency = 4, NumMicroOps = 2 in214def V1Write_4c_1M0_1V0 : SchedWriteRes<[V1UnitM0, V1UnitV0]>;215let Latency = 7, NumMicroOps = 2 in216def V1Write_7c_1M0_1V0 : SchedWriteRes<[V1UnitM0, V1UnitV1]>;217let Latency = 5, NumMicroOps = 2 in218def V1Write_5c_1M0_1V01 : SchedWriteRes<[V1UnitM0, V1UnitV01]>;219let Latency = 6, NumMicroOps = 2 in220def V1Write_6c_1M0_1V1 : SchedWriteRes<[V1UnitM0, V1UnitV1]>;221let Latency = 9, NumMicroOps = 2 in222def V1Write_9c_1M0_1V1 : SchedWriteRes<[V1UnitM0, V1UnitV1]>;223let Latency = 4, NumMicroOps = 2 in224def V1Write_4c_2V : SchedWriteRes<[V1UnitV, V1UnitV]>;225let Latency = 8, NumMicroOps = 2 in226def V1Write_8c_1V_1V01 : SchedWriteRes<[V1UnitV, V1UnitV01]>;227let Latency = 4, NumMicroOps = 2 in228def V1Write_4c_2V0 : SchedWriteRes<[V1UnitV0, V1UnitV0]>;229let Latency = 5, NumMicroOps = 2 in230def V1Write_5c_2V0 : SchedWriteRes<[V1UnitV0, V1UnitV0]>;231let Latency = 2, NumMicroOps = 2 in232def V1Write_2c_2V01 : SchedWriteRes<[V1UnitV01, V1UnitV01]>;233let Latency = 4, NumMicroOps = 2 in234def V1Write_4c_2V01 : SchedWriteRes<[V1UnitV01, V1UnitV01]>;235let Latency = 4, NumMicroOps = 2 in236def V1Write_4c_2V02 : SchedWriteRes<[V1UnitV02, V1UnitV02]>;237let Latency = 6, NumMicroOps = 2 in238def V1Write_6c_2V02 : SchedWriteRes<[V1UnitV02, V1UnitV02]>;239let Latency = 4, NumMicroOps = 2 in240def V1Write_4c_1V13_1V : SchedWriteRes<[V1UnitV13, V1UnitV]>;241let Latency = 4, NumMicroOps = 2 in242def V1Write_4c_2V13 : SchedWriteRes<[V1UnitV13, V1UnitV13]>;243 244//===----------------------------------------------------------------------===//245// Define generic 3 micro-op types246 247let Latency = 2, NumMicroOps = 3 in248def V1Write_2c_1I_1L01_1V01 : SchedWriteRes<[V1UnitI, V1UnitL01, V1UnitV01]>;249let Latency = 7, NumMicroOps = 3 in250def V1Write_7c_2M0_1V01 : SchedWriteRes<[V1UnitM0, V1UnitM0, V1UnitV01]>;251let Latency = 8, NumMicroOps = 3 in252def V1Write_8c_1L_2V : SchedWriteRes<[V1UnitL, V1UnitV, V1UnitV]>;253let Latency = 6, NumMicroOps = 3 in254def V1Write_6c_3L : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL]>;255let Latency = 2, NumMicroOps = 3 in256def V1Write_2c_1L01_1S_1V : SchedWriteRes<[V1UnitL01, V1UnitS, V1UnitV]>;257let Latency = 4, NumMicroOps = 3 in258def V1Write_4c_1L01_1S_1V : SchedWriteRes<[V1UnitL01, V1UnitS, V1UnitV]>;259let Latency = 2, NumMicroOps = 3 in260def V1Write_2c_2L01_1V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitV01]>;261let Latency = 6, NumMicroOps = 3 in262def V1Write_6c_3V : SchedWriteRes<[V1UnitV, V1UnitV, V1UnitV]>;263let Latency = 4, NumMicroOps = 3 in264def V1Write_4c_3V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01]>;265let Latency = 6, NumMicroOps = 3 in266def V1Write_6c_3V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01]>;267let Latency = 8, NumMicroOps = 3 in268def V1Write_8c_3V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01]>;269 270//===----------------------------------------------------------------------===//271// Define generic 4 micro-op types272 273let Latency = 8, NumMicroOps = 4 in274def V1Write_8c_2M0_2V0 : SchedWriteRes<[V1UnitM0, V1UnitM0,275 V1UnitV0, V1UnitV0]>;276let Latency = 7, NumMicroOps = 4 in277def V1Write_7c_4L : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL, V1UnitL]>;278let Latency = 8, NumMicroOps = 4 in279def V1Write_8c_2L_2V : SchedWriteRes<[V1UnitL, V1UnitL,280 V1UnitV, V1UnitV]>;281let Latency = 9, NumMicroOps = 4 in282def V1Write_9c_2L_2V : SchedWriteRes<[V1UnitL, V1UnitL,283 V1UnitV, V1UnitV]>;284let Latency = 11, NumMicroOps = 4 in285def V1Write_11c_2L_2V : SchedWriteRes<[V1UnitL, V1UnitL,286 V1UnitV, V1UnitV]>;287let Latency = 10, NumMicroOps = 4 in288def V1Write_10c_2L01_2V : SchedWriteRes<[V1UnitL01, V1UnitL01,289 V1UnitV, V1UnitV]>;290let Latency = 2, NumMicroOps = 4 in291def V1Write_2c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01,292 V1UnitV01, V1UnitV01]>;293let Latency = 4, NumMicroOps = 4 in294def V1Write_4c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01,295 V1UnitV01, V1UnitV01]>;296let Latency = 8, NumMicroOps = 4 in297def V1Write_8c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01,298 V1UnitV01, V1UnitV01]>;299let Latency = 9, NumMicroOps = 4 in300def V1Write_9c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01,301 V1UnitV01, V1UnitV01]>;302let Latency = 10, NumMicroOps = 4 in303def V1Write_10c_2L01_2V01 : SchedWriteRes<[V1UnitL01, V1UnitL01,304 V1UnitV01, V1UnitV01]>;305let Latency = 10, NumMicroOps = 4 in306def V1Write_10c_1V_1V01_2V1 : SchedWriteRes<[V1UnitV, V1UnitV01,307 V1UnitV1, V1UnitV1]>;308let Latency = 12, NumMicroOps = 4 in309def V1Write_12c_1V_1V01_2V1 : SchedWriteRes<[V1UnitV, V1UnitV01,310 V1UnitV1, V1UnitV1]>;311let Latency = 6, NumMicroOps = 4 in312def V1Write_6c_4V0 : SchedWriteRes<[V1UnitV0, V1UnitV0,313 V1UnitV0, V1UnitV0]>;314let Latency = 12, NumMicroOps = 4 in315def V1Write_12c_4V01 : SchedWriteRes<[V1UnitV01, V1UnitV01,316 V1UnitV01, V1UnitV01]>;317let Latency = 6, NumMicroOps = 4 in318def V1Write_6c_4V02 : SchedWriteRes<[V1UnitV02, V1UnitV02]>;319 320//===----------------------------------------------------------------------===//321// Define generic 5 micro-op types322 323let Latency = 8, NumMicroOps = 5 in324def V1Write_8c_2L_3V : SchedWriteRes<[V1UnitL, V1UnitL,325 V1UnitV, V1UnitV, V1UnitV]>;326let Latency = 14, NumMicroOps = 5 in327def V1Write_14c_1V_1V0_2V1_1V13 : SchedWriteRes<[V1UnitV,328 V1UnitV0,329 V1UnitV1, V1UnitV1,330 V1UnitV13]>;331let Latency = 9, NumMicroOps = 5 in332def V1Write_9c_1V_4V01 : SchedWriteRes<[V1UnitV,333 V1UnitV01, V1UnitV01,334 V1UnitV01, V1UnitV01]>;335let Latency = 6, NumMicroOps = 5 in336def V1Write_6c_5V01 : SchedWriteRes<[V1UnitV01, V1UnitV01,337 V1UnitV01, V1UnitV01, V1UnitV01]>;338 339//===----------------------------------------------------------------------===//340// Define generic 6 micro-op types341 342let Latency = 6, NumMicroOps = 6 in343def V1Write_6c_3L_3V : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL,344 V1UnitV, V1UnitV, V1UnitV]>;345let Latency = 8, NumMicroOps = 6 in346def V1Write_8c_3L_3V : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL,347 V1UnitV, V1UnitV, V1UnitV]>;348let Latency = 2, NumMicroOps = 6 in349def V1Write_2c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01,350 V1UnitV01, V1UnitV01, V1UnitV01]>;351let Latency = 5, NumMicroOps = 6 in352def V1Write_5c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01,353 V1UnitV01, V1UnitV01, V1UnitV01]>;354let Latency = 6, NumMicroOps = 6 in355def V1Write_6c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01,356 V1UnitV01, V1UnitV01, V1UnitV01]>;357let Latency = 11, NumMicroOps = 6 in358def V1Write_11c_3L01_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01,359 V1UnitV01, V1UnitV01, V1UnitV01]>;360let Latency = 11, NumMicroOps = 6 in361def V1Write_11c_1V_5V01 : SchedWriteRes<[V1UnitV,362 V1UnitV01, V1UnitV01,363 V1UnitV01, V1UnitV01, V1UnitV01]>;364let Latency = 13, NumMicroOps = 6 in365def V1Write_13c_6V01 : SchedWriteRes<[V1UnitV01, V1UnitV01, V1UnitV01,366 V1UnitV01, V1UnitV01, V1UnitV01]>;367 368//===----------------------------------------------------------------------===//369// Define generic 7 micro-op types370 371let Latency = 8, NumMicroOps = 7 in372def V1Write_8c_3L_4V : SchedWriteRes<[V1UnitL, V1UnitL, V1UnitL,373 V1UnitV, V1UnitV, V1UnitV, V1UnitV]>;374let Latency = 8, NumMicroOps = 7 in375def V1Write_13c_3L01_1S_3V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01,376 V1UnitS,377 V1UnitV01, V1UnitV01, V1UnitV01]>;378 379//===----------------------------------------------------------------------===//380// Define generic 8 micro-op types381 382let Latency = 9, NumMicroOps = 8 in383def V1Write_9c_4L_4V : SchedWriteRes<[V1UnitL, V1UnitL,384 V1UnitL, V1UnitL,385 V1UnitV, V1UnitV,386 V1UnitV, V1UnitV]>;387let Latency = 2, NumMicroOps = 8 in388def V1Write_2c_4L01_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01,389 V1UnitL01, V1UnitL01,390 V1UnitV01, V1UnitV01,391 V1UnitV01, V1UnitV01]>;392let Latency = 4, NumMicroOps = 8 in393def V1Write_4c_4L01_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01,394 V1UnitL01, V1UnitL01,395 V1UnitV01, V1UnitV01,396 V1UnitV01, V1UnitV01]>;397let Latency = 12, NumMicroOps = 8 in398def V1Write_12c_4L01_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01,399 V1UnitL01, V1UnitL01,400 V1UnitV01, V1UnitV01,401 V1UnitV01, V1UnitV01]>;402 403//===----------------------------------------------------------------------===//404// Define generic 10 micro-op types405 406let Latency = 13, NumMicroOps = 10 in407def V1Write_13c_4L01_2S_4V01 : SchedWriteRes<[V1UnitL01, V1UnitL01,408 V1UnitL01, V1UnitL01,409 V1UnitS, V1UnitS,410 V1UnitV01, V1UnitV01,411 V1UnitV01, V1UnitV01]>;412let Latency = 7, NumMicroOps = 10 in413def V1Write_7c_5L01_5V : SchedWriteRes<[V1UnitL01, V1UnitL01,414 V1UnitL01, V1UnitL01, V1UnitL01,415 V1UnitV, V1UnitV,416 V1UnitV, V1UnitV, V1UnitV]>;417let Latency = 11, NumMicroOps = 10 in418def V1Write_11c_10V0 : SchedWriteRes<[V1UnitV0,419 V1UnitV0, V1UnitV0, V1UnitV0,420 V1UnitV0, V1UnitV0, V1UnitV0,421 V1UnitV0, V1UnitV0, V1UnitV0]>;422 423//===----------------------------------------------------------------------===//424// Define generic 12 micro-op types425 426let Latency = 7, NumMicroOps = 12 in427def V1Write_7c_6L01_6V01 : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01,428 V1UnitL01, V1UnitL01, V1UnitL01,429 V1UnitV01, V1UnitV01, V1UnitV01,430 V1UnitV01, V1UnitV01, V1UnitV01]>;431 432//===----------------------------------------------------------------------===//433// Define generic 15 micro-op types434 435let Latency = 7, NumMicroOps = 15 in436def V1Write_7c_5L01_5S_5V : SchedWriteRes<[V1UnitL01, V1UnitL01,437 V1UnitL01, V1UnitL01, V1UnitL01,438 V1UnitS, V1UnitS,439 V1UnitS, V1UnitS, V1UnitS,440 V1UnitV, V1UnitV,441 V1UnitV, V1UnitV, V1UnitV]>;442 443 444//===----------------------------------------------------------------------===//445// Define generic 18 micro-op types446 447let Latency = 19, NumMicroOps = 18 in448def V1Write_11c_9L01_9V : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01,449 V1UnitL01, V1UnitL01, V1UnitL01, 450 V1UnitL01, V1UnitL01, V1UnitL01,451 V1UnitV, V1UnitV, V1UnitV, 452 V1UnitV, V1UnitV, V1UnitV,453 V1UnitV, V1UnitV, V1UnitV]>;454let Latency = 19, NumMicroOps = 18 in455def V1Write_19c_18V0 : SchedWriteRes<[V1UnitV0, V1UnitV0, V1UnitV0,456 V1UnitV0, V1UnitV0, V1UnitV0, 457 V1UnitV0, V1UnitV0, V1UnitV0,458 V1UnitV0, V1UnitV0, V1UnitV0, 459 V1UnitV0, V1UnitV0, V1UnitV0,460 V1UnitV0, V1UnitV0, V1UnitV0]>;461 462//===----------------------------------------------------------------------===//463// Define generic 27 micro-op types464 465let Latency = 11, NumMicroOps = 27 in466def V1Write_11c_9L01_9S_9V : SchedWriteRes<[V1UnitL01, V1UnitL01, V1UnitL01,467 V1UnitL01, V1UnitL01, V1UnitL01, 468 V1UnitL01, V1UnitL01, V1UnitL01,469 V1UnitS, V1UnitS, V1UnitS, 470 V1UnitS, V1UnitS, V1UnitS,471 V1UnitS, V1UnitS, V1UnitS,472 V1UnitV, V1UnitV, V1UnitV, 473 V1UnitV, V1UnitV, V1UnitV,474 V1UnitV, V1UnitV, V1UnitV]>;475 476//===----------------------------------------------------------------------===//477// Define predicate-controlled types478 479def V1Write_0or1c_1I : SchedWriteVariant<[480 SchedVar<NeoverseZeroMove, [V1Write_0c]>,481 SchedVar<NoSchedPred, [V1Write_1c_1I]>]>;482 483def V1Write_0or3c_1M0 : SchedWriteVariant<[484 SchedVar<NeoverseZeroMove, [V1Write_0c]>,485 SchedVar<NoSchedPred, [V1Write_3c_1M0]>]>;486 487//===----------------------------------------------------------------------===//488// Define forwarded types489 490// NOTE: SOG, p. 20, n. 2: Accumulator forwarding is not supported for491// consumers of 64 bit multiply high operations?492def V1Wr_IM : SchedWriteRes<[V1UnitM]> { let Latency = 2; }493def V1Wr_IMA : SchedWriteRes<[V1UnitM0]> { let Latency = 2; }494def V1WriteIM : SchedWriteVariant<495 [SchedVar<NeoverseMULIdiomPred, [V1Wr_IM]>,496 SchedVar<NoSchedPred, [V1Wr_IMA]>]>;497def V1Rd_IMA : SchedReadAdvance<1, [V1Wr_IMA]>;498 499def V1Wr_FMA : SchedWriteRes<[V1UnitV]> { let Latency = 4; }500def V1Rd_FMA : SchedReadAdvance<2, [WriteFMul, V1Wr_FMA]>;501 502def V1Wr_ADA : SchedWriteRes<[V1UnitV13]> { let Latency = 4; }503def V1Rd_ADA : SchedReadAdvance<3, [V1Wr_ADA]>;504 505def V1Wr_VDOT : SchedWriteRes<[V1UnitV]> { let Latency = 3; }506def V1Rd_VDOT : SchedReadAdvance<2, [V1Wr_VDOT]>;507 508def V1Wr_VMMA : SchedWriteRes<[V1UnitV]> { let Latency = 3; }509def V1Rd_VMMA : SchedReadAdvance<2, [V1Wr_VMMA]>;510 511def V1Wr_VMA : SchedWriteRes<[V1UnitV02]> { let Latency = 4; }512def V1Rd_VMA : SchedReadAdvance<3, [V1Wr_VMA]>;513 514def V1Wr_VMAL : SchedWriteRes<[V1UnitV02]> { let Latency = 4; }515def V1Rd_VMAL : SchedReadAdvance<3, [V1Wr_VMAL]>;516 517def V1Wr_VSA : SchedWriteRes<[V1UnitV13]> { let Latency = 4; }518def V1Rd_VSA : SchedReadAdvance<3, [V1Wr_VSA]>;519 520def V1Wr_FCMA : SchedWriteRes<[V1UnitV]> { let Latency = 4; }521def V1Rd_FCMA : SchedReadAdvance<2, [V1Wr_FCMA]>;522 523def V1Wr_FPM : SchedWriteRes<[V1UnitV]> { let Latency = 3; }524def V1Wr_FPMA : SchedWriteRes<[V1UnitV]> { let Latency = 4; }525def V1Rd_FPMA : SchedReadAdvance<2, [V1Wr_FPM, V1Wr_FPMA]>;526 527def V1Wr_FPMAL : SchedWriteRes<[V1UnitV]> { let Latency = 5; }528def V1Rd_FPMAL : SchedReadAdvance<3, [V1Wr_FPMAL]>;529 530def V1Wr_BFD : SchedWriteRes<[V1UnitV]> { let Latency = 4; }531def V1Rd_BFD : SchedReadAdvance<2, [V1Wr_BFD]>;532 533def V1Wr_BFMMA : SchedWriteRes<[V1UnitV]> { let Latency = 5; }534def V1Rd_BFMMA : SchedReadAdvance<2, [V1Wr_BFMMA]>;535 536def V1Wr_BFMLA : SchedWriteRes<[V1UnitV]> { let Latency = 4; }537def V1Rd_BFMLA : SchedReadAdvance<2, [V1Wr_BFMLA]>;538 539def V1Wr_CRC : SchedWriteRes<[V1UnitM0]> { let Latency = 2; }540def V1Rd_CRC : SchedReadAdvance<1, [V1Wr_CRC]>;541 542def V1Wr_ZDOTB : SchedWriteRes<[V1UnitV01]> { let Latency = 3; }543def V1Rd_ZDOTB : SchedReadAdvance<2, [V1Wr_ZDOTB]>;544 545def V1Wr_ZUDOTB : SchedWriteRes<[V1UnitV]> { let Latency = 3; }546def V1Rd_ZUDOTB : SchedReadAdvance<2, [V1Wr_ZUDOTB]>;547 548def V1Wr_ZDOTH : SchedWriteRes<[V1UnitV0]> { let Latency = 4; }549def V1Rd_ZDOTH : SchedReadAdvance<3, [V1Wr_ZDOTH]>;550 551def V1Wr_ZMMA : SchedWriteRes<[V1UnitV01]> { let Latency = 3; }552def V1Rd_ZMMA : SchedReadAdvance<2, [V1Wr_ZMMA]>;553 554let Latency = 5, NumMicroOps = 2 in555def V1Wr_ZMAD : SchedWriteRes<[V1UnitV0, V1UnitV0]>;556def V1Rd_ZMAD : SchedReadAdvance<3, [V1Wr_ZMAD]>;557 558def V1Wr_ZFCMA : SchedWriteRes<[V1UnitV01]> { let Latency = 5; }559def V1Rd_ZFCMA : SchedReadAdvance<3, [V1Wr_ZFCMA]>;560 561def V1Wr_ZFMA : SchedWriteRes<[V1UnitV01]> { let Latency = 4; }562def V1Rd_ZFMA : SchedReadAdvance<2, [V1Wr_ZFMA]>;563 564def V1Wr_ZBFDOT : SchedWriteRes<[V1UnitV01]> { let Latency = 4; }565def V1Rd_ZBFDOT : SchedReadAdvance<2, [V1Wr_ZBFDOT]>;566def V1Wr_ZBFMMA : SchedWriteRes<[V1UnitV01]> { let Latency = 5; }567def V1Rd_ZBFMMA : SchedReadAdvance<2, [V1Wr_ZBFMMA]>;568def V1Wr_ZBFMAL : SchedWriteRes<[V1UnitV01]> { let Latency = 5; }569def V1Rd_ZBFMAL : SchedReadAdvance<3, [V1Wr_ZBFMAL]>;570 571// Miscellaneous Instructions572// -----------------------------------------------------------------------------573 574// COPY575def : InstRW<[V1Write_1c_1I], (instrs COPY)>;576 577// MSR578def : WriteRes<WriteSys, []> { let Latency = 1; }579 580 581// Branch Instructions582// -----------------------------------------------------------------------------583 584// Branch, immed585// Compare and branch586def : SchedAlias<WriteBr, V1Write_1c_1B>;587 588// Branch, register589def : SchedAlias<WriteBrReg, V1Write_1c_1B>;590 591// Branch and link, immed592// Branch and link, register593def : InstRW<[V1Write_1c_1B_1S], (instrs BL, BLR)>;594 595// Compare and branch596def : InstRW<[V1Write_1c_1B], (instregex "^[CT]BN?Z[XW]$")>;597 598 599// Arithmetic and Logical Instructions600// -----------------------------------------------------------------------------601 602// ALU, basic603// Conditional compare604// Conditional select605// Logical, basic606// Address generation607// Count leading608// Reverse bits/bytes609// Move immediate610def : SchedAlias<WriteI, V1Write_1c_1I>;611 612// ALU, basic, flagset613def : InstRW<[V1Write_1c_1I_1Flg],614 (instregex "^(ADD|SUB)S[WX]r[ir]$",615 "^(ADC|SBC)S[WX]r$",616 "^ANDS[WX]ri$",617 "^(AND|BIC)S[WX]rr$")>;618def : InstRW<[V1Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>;619 620// ALU, extend and shift621def : SchedAlias<WriteIEReg, V1Write_2c_1M>;622 623// Arithmetic, LSL shift, shift <= 4624// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4625def V1WriteISReg : SchedWriteVariant<626 [SchedVar<IsCheapLSL, [V1Write_1c_1I]>,627 SchedVar<NoSchedPred, [V1Write_2c_1M]>]>;628def : SchedAlias<WriteISReg, V1WriteISReg>;629 630// Arithmetic, flagset, LSL shift, shift <= 4631// Arithmetic, flagset, LSR/ASR/ROR shift or LSL shift > 4632def V1WriteISRegS : SchedWriteVariant<633 [SchedVar<IsCheapLSL, [V1Write_1c_1I_1Flg]>,634 SchedVar<NoSchedPred, [V1Write_2c_1M_1Flg]>]>;635def : InstRW<[V1WriteISRegS],636 (instregex "^(ADD|SUB)S(([WX]r[sx])|Xrx64)$")>;637 638// Logical, shift, no flagset639def : InstRW<[V1Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;640def : InstRW<[V1Write_0or1c_1I], (instregex "^ORR[WX]rs$")>;641 642// Logical, shift, flagset643def : InstRW<[V1Write_2c_1M_1Flg], (instregex "^(AND|BIC)S[WX]rs$")>;644 645// Flag manipulation instructions646def : InstRW<[V1Write_1c_1I_1Flg], (instrs SETF8, SETF16, RMIF, CFINV)>;647 648 649// Divide and multiply instructions650// -----------------------------------------------------------------------------651 652// Divide653def : SchedAlias<WriteID32, V1Write_12c5_1M0>;654def : SchedAlias<WriteID64, V1Write_20c5_1M0>;655 656def : SchedAlias<WriteIM32, V1Write_2c_1M>;657def : SchedAlias<WriteIM64, V1Write_2c_1M>;658 659// Multiply660// Multiply accumulate, W-form661// Multiply accumulate, X-form662def : InstRW<[V1WriteIM, ReadIM, ReadIM, V1Rd_IMA],663 (instregex "^M(ADD|SUB)[WX]rrr$")>;664 665// Multiply accumulate long666// Multiply long667def : InstRW<[V1WriteIM, ReadIM, ReadIM, V1Rd_IMA],668 (instregex "^(S|U)M(ADD|SUB)Lrrr$")>;669// Multiply high670def : InstRW<[V1Write_3c_1M, ReadIM, ReadIM], (instrs SMULHrr, UMULHrr)>;671 672 673// Pointer Authentication Instructions (v8.3 PAC)674// -----------------------------------------------------------------------------675 676// Authenticate data address677// Authenticate instruction address678// Compute pointer authentication code for data address679// Compute pointer authentication code, using generic key680// Compute pointer authentication code for instruction address681def : InstRW<[V1Write_5c_1M0], (instregex "^AUT",682 "^PAC")>;683 684// Branch and link, register, with pointer authentication685// Branch, register, with pointer authentication686// Branch, return, with pointer authentication687def : InstRW<[V1Write_6c_1B_1M0], (instregex "^BL?RA[AB]Z?$",688 "^E?RETA[AB]$")>;689 690// Load register, with pointer authentication691def : InstRW<[V1Write_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;692 693// Strip pointer authentication code694def : InstRW<[V1Write_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;695 696 697// Miscellaneous data-processing instructions698// -----------------------------------------------------------------------------699 700// Bitfield extract, one reg701// Bitfield extract, two regs702def V1WriteExtr : SchedWriteVariant<703 [SchedVar<IsRORImmIdiomPred, [V1Write_1c_1I]>,704 SchedVar<NoSchedPred, [V1Write_3c_1I_1M]>]>;705def : SchedAlias<WriteExtr, V1WriteExtr>;706 707// Bitfield move, basic708// Variable shift709def : SchedAlias<WriteIS, V1Write_1c_1I>;710 711// Bitfield move, insert712def : InstRW<[V1Write_2c_1M], (instregex "^BFM[WX]ri$")>;713 714// Move immediate715def : SchedAlias<WriteImm, V1Write_1c_1I>;716 717 718// Load instructions719// -----------------------------------------------------------------------------720 721// Load register, immed offset722def : SchedAlias<WriteLD, V1Write_4c_1L>;723 724// Load register, immed offset, index725def : SchedAlias<WriteLDIdx, V1Write_4c_1L>;726def : SchedAlias<WriteAdr, V1Write_1c_1I>;727 728// Load pair, immed offset729def : SchedAlias<WriteLDHi, V1Write_4c_1L>;730def : InstRW<[V1Write_4c_1L, V1Write_0c_0Z], (instrs LDPWi, LDNPWi)>;731def : InstRW<[WriteAdr, V1Write_4c_1L, V1Write_0c_0Z],732 (instrs LDPWpost, LDPWpre)>;733 734// Load pair, signed immed offset, signed words735def : InstRW<[V1Write_5c_1I_1L, V1Write_0c_0Z], (instrs LDPSWi)>;736 737// Load pair, immed post or pre-index, signed words738def : InstRW<[WriteAdr, V1Write_5c_1I_1L, V1Write_0c_0Z],739 (instrs LDPSWpost, LDPSWpre)>;740 741 742// Store instructions743// -----------------------------------------------------------------------------744 745// Store register, immed offset746def : SchedAlias<WriteST, V1Write_1c_1L01_1D>;747 748// Store register, immed offset, index749def : SchedAlias<WriteSTIdx, V1Write_1c_1L01_1D>;750 751// Store pair, immed offset752def : SchedAlias<WriteSTP, V1Write_1c_1L01_1D>;753 754 755// FP data processing instructions756// -----------------------------------------------------------------------------757 758// FP absolute value759// FP arithmetic760// FP min/max761// FP negate762def : SchedAlias<WriteF, V1Write_2c_1V>;763 764// FP compare765def : SchedAlias<WriteFCmp, V1Write_2c_1V0>;766 767// FP divide768// FP square root769def : SchedAlias<WriteFDiv, V1Write_10c7_1V02>;770 771// FP divide, H-form772// FP square root, H-form773def : InstRW<[V1Write_7c7_1V02], (instrs FDIVHrr, FSQRTHr)>;774 775// FP divide, S-form776// FP square root, S-form777def : InstRW<[V1Write_10c7_1V02], (instrs FDIVSrr, FSQRTSr)>;778 779// FP divide, D-form780def : InstRW<[V1Write_15c7_1V02], (instrs FDIVDrr)>;781 782// FP square root, D-form783def : InstRW<[V1Write_16c7_1V02], (instrs FSQRTDr)>;784 785// FP multiply786def : WriteRes<WriteFMul, [V1UnitV]> { let Latency = 3; }787 788// FP multiply accumulate789def : InstRW<[V1Wr_FMA, ReadDefault, ReadDefault, V1Rd_FMA],790 (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;791 792// FP round to integral793def : InstRW<[V1Write_3c_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$",794 "^FRINT(32|64)[XZ][SD]r$")>;795 796// FP select797def : InstRW<[V1Write_2c_1V01], (instregex "^FCSEL[HSD]rrr$")>;798 799 800// FP miscellaneous instructions801// -----------------------------------------------------------------------------802 803// FP convert, from gen to vec reg804def : InstRW<[V1Write_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;805 806// FP convert, from vec to gen reg807def : InstRW<[V1Write_3c_1V0], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>;808 809// FP convert, Javascript from vec to gen reg810def : InstRW<[V1Write_3c_1V0], (instrs FJCVTZS)>;811 812// FP convert, from vec to vec reg813def : SchedAlias<WriteFCvt, V1Write_3c_1V02>;814 815// FP move, immed816def : SchedAlias<WriteFImm, V1Write_2c_1V>;817 818// FP move, register819def : InstRW<[V1Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>;820 821// FP transfer, from gen to low half of vec reg822def : InstRW<[V1Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;823 824// FP transfer, from gen to high half of vec reg825def : InstRW<[V1Write_5c_1M0_1V], (instrs FMOVXDHighr)>;826 827// FP transfer, from vec to gen reg828def : SchedAlias<WriteFCopy, V1Write_2c_1V1>;829 830 831// FP load instructions832// -----------------------------------------------------------------------------833 834// Load vector reg, literal, S/D/Q forms835// Load vector reg, unscaled immed836// Load vector reg, unsigned immed837def : InstRW<[V1Write_6c_1L, ReadAdrBase], (instregex "^LDR[SDQ]l$",838 "^LDUR[BHSDQ]i$",839 "^LDR[BHSDQ]ui$")>;840 841// Load vector reg, immed post-index842// Load vector reg, immed pre-index843def : InstRW<[WriteAdr, V1Write_6c_1L],844 (instregex "^LDR[BHSDQ](post|pre)$")>;845 846// Load vector reg, register offset, basic847// Load vector reg, register offset, scale, S/D-form848// Load vector reg, register offset, extend849// Load vector reg, register offset, extend, scale, S/D-form850def : InstRW<[V1Write_6c_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>;851 852// Load vector reg, register offset, scale, H/Q-form853// Load vector reg, register offset, extend, scale, H/Q-form854def : InstRW<[V1Write_7c_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>;855 856// Load vector pair, immed offset, S/D-form857def : InstRW<[V1Write_6c_1L, V1Write_0c_0Z], (instregex "^LDN?P[SD]i$")>;858 859// Load vector pair, immed offset, Q-form860def : InstRW<[V1Write_6c_1L, WriteLDHi], (instrs LDPQi, LDNPQi)>;861 862// Load vector pair, immed post-index, S/D-form863// Load vector pair, immed pre-index, S/D-form864def : InstRW<[WriteAdr, V1Write_6c_1L, V1Write_0c_0Z],865 (instregex "^LDP[SD](pre|post)$")>;866 867// Load vector pair, immed post-index, Q-form868// Load vector pair, immed pre-index, Q-form869def : InstRW<[WriteAdr, V1Write_6c_1L, WriteLDHi],870 (instrs LDPQpost, LDPQpre)>;871 872 873// FP store instructions874// -----------------------------------------------------------------------------875 876// Store vector reg, unscaled immed, B/H/S/D/Q-form877def : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STUR[BHSDQ]i$")>;878 879// Store vector reg, immed post-index, B/H/S/D/Q-form880// Store vector reg, immed pre-index, B/H/S/D/Q-form881def : InstRW<[WriteAdr, V1Write_2c_1L01_1V01],882 (instregex "^STR[BHSDQ](pre|post)$")>;883 884// Store vector reg, unsigned immed, B/H/S/D/Q-form885def : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STR[BHSDQ]ui$")>;886 887// Store vector reg, register offset, basic, B/S/D-form888// Store vector reg, register offset, scale, B/S/D-form889// Store vector reg, register offset, extend, B/S/D-form890// Store vector reg, register offset, extend, scale, B/S/D-form891def : InstRW<[V1Write_2c_1L01_1V01, ReadAdrBase],892 (instregex "^STR[BSD]ro[WX]$")>;893 894// Store vector reg, register offset, basic, H/Q-form895// Store vector reg, register offset, scale, H/Q-form896// Store vector reg, register offset, extend, H/Q-form897// Store vector reg, register offset, extend, scale, H/Q-form898def : InstRW<[V1Write_2c_1I_1L01_1V01, ReadAdrBase],899 (instregex "^STR[HQ]ro[WX]$")>;900 901// Store vector pair, immed offset, S/D/Q-form902def : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STN?P[SDQ]i$")>;903 904// Store vector pair, immed post-index, S/D-form905// Store vector pair, immed pre-index, S/D-form906def : InstRW<[WriteAdr, V1Write_2c_1L01_1V01],907 (instregex "^STP[SD](pre|post)$")>;908 909// Store vector pair, immed post-index, Q-form910// Store vector pair, immed pre-index, Q-form911def : InstRW<[WriteAdr, V1Write_2c_2L01_1V01], (instrs STPQpre, STPQpost)>;912 913 914// ASIMD integer instructions915// -----------------------------------------------------------------------------916 917// ASIMD absolute diff918// ASIMD absolute diff long919// ASIMD arith, basic920// ASIMD arith, complex921// ASIMD arith, pair-wise922// ASIMD compare923// ASIMD logical924// ASIMD max/min, basic and pair-wise925def : SchedAlias<WriteVd, V1Write_2c_1V>;926def : SchedAlias<WriteVq, V1Write_2c_1V>;927 928// ASIMD absolute diff accum929// ASIMD absolute diff accum long930// ASIMD pairwise add and accumulate long931def : InstRW<[V1Wr_ADA, V1Rd_ADA], (instregex "^[SU]ABAL?v", "^[SU]ADALPv")>;932 933// ASIMD arith, reduce, 4H/4S934// ASIMD max/min, reduce, 4H/4S935def : InstRW<[V1Write_2c_1V13], (instregex "^(ADD|[SU]ADDL)Vv4(i16|i32)v$",936 "^[SU](MAX|MIN)Vv4(i16|i32)v$")>;937 938// ASIMD arith, reduce, 8B/8H939// ASIMD max/min, reduce, 8B/8H940def : InstRW<[V1Write_4c_1V13_1V], (instregex "^(ADD|[SU]ADDL)Vv8(i8|i16)v$",941 "^[SU](MAX|MIN)Vv8(i8|i16)v$")>;942 943// ASIMD arith, reduce, 16B944// ASIMD max/min, reduce, 16B945def : InstRW<[V1Write_4c_2V13], (instregex "^(ADD|[SU]ADDL)Vv16i8v$",946 "[SU](MAX|MIN)Vv16i8v$")>;947 948// ASIMD dot product949// ASIMD dot product using signed and unsigned integers950def : InstRW<[V1Wr_VDOT, V1Rd_VDOT],951 (instregex "^([SU]|SU|US)DOT(lane)?v(8|16)i8$")>;952 953// ASIMD matrix multiply-accumulate954def : InstRW<[V1Wr_VMMA, V1Rd_VMMA], (instrs SMMLA, UMMLA, USMMLA)>;955 956// ASIMD multiply957def : InstRW<[V1Write_4c_1V02], (instregex "^MULv", "^SQ(R)?DMULHv")>;958 959// ASIMD multiply accumulate960def : InstRW<[V1Wr_VMA, V1Rd_VMA], (instregex "^MLAv", "^MLSv")>;961 962// ASIMD multiply accumulate long963def : InstRW<[V1Wr_VMAL, V1Rd_VMAL], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;964 965// ASIMD multiply accumulate high966def : InstRW<[V1Write_4c_1V02], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;967 968// ASIMD multiply accumulate saturating long969def : InstRW<[V1Write_4c_1V02], (instregex "^SQDML[AS]L[iv]")>;970 971// ASIMD multiply/multiply long (8x8) polynomial972def : InstRW<[V1Write_3c_1V01], (instregex "^PMULL?v(8|16)i8$")>;973 974// ASIMD multiply long975def : InstRW<[V1Write_3c_1V02], (instregex "^([SU]|SQD)MULLv")>;976 977// ASIMD shift accumulate978def : InstRW<[V1Wr_VSA, V1Rd_VSA], (instregex "^[SU]SRAv", "^[SU]RSRAv")>;979 980// ASIMD shift by immed, complex981// ASIMD shift by register, complex982def : InstRW<[V1Write_4c_1V13],983 (instregex "^RSHRNv", "^SQRSHRU?Nv", "^(SQSHLU?|UQSHL)[bhsd]$",984 "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",985 "^SQSHU?RNv", "^[SU]RSHRv", "^UQR?SHRNv", 986 "^[SU]Q?RSHLv", "^[SU]QSHLv")>;987 988// ASIMD shift by immed, basic989// ASIMD shift by immed and insert, basic990// ASIMD shift by register, basic991def : InstRW<[V1Write_2c_1V13], (instregex "^SHLL?v", "^SHRNv", "^[SU]SHLLv",992 "^[SU]SHRv", "^S[LR]Iv", "^[SU]SHLv")>;993 994 995// ASIMD FP instructions996// -----------------------------------------------------------------------------997 998// ASIMD FP absolute value/difference999// ASIMD FP arith, normal1000// ASIMD FP compare1001// ASIMD FP max/min, normal1002// ASIMD FP max/min, pairwise1003// ASIMD FP negate1004// Covered by "SchedAlias (WriteV[dq]...)" above1005 1006// ASIMD FP complex add1007def : InstRW<[V1Write_4c_1V], (instregex "^FCADD(v[48]f16|v[24]f32|v2f64)$")>;1008 1009// ASIMD FP complex multiply add1010def : InstRW<[V1Wr_FCMA, V1Rd_FCMA], (instregex "^FCMLAv")>;1011 1012// ASIMD FP multiply1013def : InstRW<[V1Wr_FPM], (instregex "^FMULX?v")>;1014 1015// ASIMD FP multiply accumulate1016def : InstRW<[V1Wr_FPMA, V1Rd_FPMA], (instregex "^FML[AS]v")>;1017 1018// ASIMD FP multiply accumulate long1019def : InstRW<[V1Wr_FPMAL, V1Rd_FPMAL], (instregex "^FML[AS]L2?v")>;1020 1021// ASIMD FP convert, long (F16 to F32)1022def : InstRW<[V1Write_4c_2V02], (instregex "^FCVTLv[48]i16$")>;1023 1024// ASIMD FP convert, long (F32 to F64)1025def : InstRW<[V1Write_3c_1V02], (instregex "^FCVTLv[24]i32$")>;1026 1027// ASIMD FP convert, narrow (F32 to F16)1028def : InstRW<[V1Write_4c_2V02], (instregex "^FCVTNv[48]i16$")>;1029 1030// ASIMD FP convert, narrow (F64 to F32)1031def : InstRW<[V1Write_3c_1V02], (instregex "^FCVTNv[24]i32$",1032 "^FCVTXN(v[24]f32|v1i64)$")>;1033 1034// ASIMD FP convert, other, D-form F32 and Q-form F641035def : InstRW<[V1Write_3c_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$",1036 "^FCVT[AMNPZ][SU]v2i(32|64)_shift$",1037 "^FCVT[AMNPZ][SU]v1i64$",1038 "^FCVTZ[SU]d$",1039 "^[SU]CVTFv2f(32|64)$",1040 "^[SU]CVTFv2i(32|64)_shift$",1041 "^[SU]CVTFv1i64$",1042 "^[SU]CVTFd$")>;1043 1044// ASIMD FP convert, other, D-form F16 and Q-form F321045def : InstRW<[V1Write_4c_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$",1046 "^FCVT[AMNPZ][SU]v4i(16|32)_shift$",1047 "^FCVT[AMNPZ][SU]v1i32$",1048 "^FCVTZ[SU]s$",1049 "^[SU]CVTFv4f(16|32)$",1050 "^[SU]CVTFv4i(16|32)_shift$",1051 "^[SU]CVTFv1i32$",1052 "^[SU]CVTFs$")>;1053 1054// ASIMD FP convert, other, Q-form F161055def : InstRW<[V1Write_6c_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$",1056 "^FCVT[AMNPZ][SU]v8i16_shift$",1057 "^FCVT[AMNPZ][SU]v1f16$",1058 "^FCVTZ[SU]h$",1059 "^[SU]CVTFv8f16$",1060 "^[SU]CVTFv8i16_shift$",1061 "^[SU]CVTFv1i16$",1062 "^[SU]CVTFh$")>;1063 1064// ASIMD FP divide, D-form, F161065// ASIMD FP square root, D-form, F161066def : InstRW<[V1Write_7c7_1V02], (instrs FDIVv4f16, FSQRTv4f16)>;1067 1068// ASIMD FP divide, F321069// ASIMD FP square root, F321070def : InstRW<[V1Write_10c7_1V02], (instrs FDIVv2f32, FDIVv4f32,1071 FSQRTv2f32, FSQRTv4f32)>;1072 1073// ASIMD FP divide, Q-form, F161074def : InstRW<[V1Write_13c5_1V02], (instrs FDIVv8f16)>;1075 1076// ASIMD FP divide, Q-form, F641077def : InstRW<[V1Write_15c7_1V02], (instrs FDIVv2f64)>;1078 1079// ASIMD FP square root, Q-form, F161080def : InstRW<[V1Write_13c11_1V02], (instrs FSQRTv8f16)>;1081 1082// ASIMD FP square root, Q-form, F641083def : InstRW<[V1Write_16c7_1V02], (instrs FSQRTv2f64)>;1084 1085// ASIMD FP max/min, reduce, F32 and D-form F161086def : InstRW<[V1Write_4c_2V], (instregex "^F(MAX|MIN)(NM)?Vv4(i16|i32)v$")>;1087 1088// ASIMD FP max/min, reduce, Q-form F161089def : InstRW<[V1Write_6c_3V], (instregex "^F(MAX|MIN)(NM)?Vv8i16v$")>;1090 1091// ASIMD FP round, D-form F32 and Q-form F641092def : InstRW<[V1Write_3c_1V02], (instregex "^FRINT[AIMNPXZ]v2f(32|64)$")>;1093 1094// ASIMD FP round, D-form F16 and Q-form F321095def : InstRW<[V1Write_4c_2V02], (instregex "^FRINT[AIMNPXZ]v4f(16|32)$")>;1096 1097// ASIMD FP round, Q-form F161098def : InstRW<[V1Write_6c_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>;1099 1100 1101// ASIMD BF instructions1102// -----------------------------------------------------------------------------1103 1104// ASIMD convert, F32 to BF161105def : InstRW<[V1Write_4c_1V02], (instrs BFCVTN, BFCVTN2)>;1106 1107// ASIMD dot product1108def : InstRW<[V1Wr_BFD, V1Rd_BFD], (instregex "^BF(DOT|16DOTlane)v[48]bf16$")>;1109 1110// ASIMD matrix multiply accumulate1111def : InstRW<[V1Wr_BFMMA, V1Rd_BFMMA], (instrs BFMMLA)>;1112 1113// ASIMD multiply accumulate long1114def : InstRW<[V1Wr_BFMLA, V1Rd_BFMLA], (instregex "^BFMLAL[BT](Idx)?$")>;1115 1116// Scalar convert, F32 to BF161117def : InstRW<[V1Write_3c_1V02], (instrs BFCVT)>;1118 1119 1120// ASIMD miscellaneous instructions1121// -----------------------------------------------------------------------------1122 1123// ASIMD bit reverse1124// ASIMD bitwise insert1125// ASIMD count1126// ASIMD duplicate, element1127// ASIMD extract1128// ASIMD extract narrow1129// ASIMD insert, element to element1130// ASIMD move, FP immed1131// ASIMD move, integer immed1132// ASIMD reverse1133// ASIMD table lookup, 1 or 2 table regs1134// ASIMD table lookup extension, 1 table reg1135// ASIMD transfer, element to gen reg1136// ASIMD transpose1137// ASIMD unzip/zip1138// Covered by "SchedAlias (WriteV[dq]...)" above1139 1140// ASIMD duplicate, gen reg1141def : InstRW<[V1Write_3c_1M0],1142 (instregex "^DUP((v16|v8)i8|(v8|v4)i16|(v4|v2)i32|v2i64)gpr$")>;1143 1144// ASIMD extract narrow, saturating1145def : InstRW<[V1Write_4c_1V13], (instregex "^[SU]QXTNv", "^SQXTUNv")>;1146 1147// ASIMD reciprocal and square root estimate, D-form U321148// ASIMD reciprocal and square root estimate, D-form F32 and F641149def : InstRW<[V1Write_3c_1V02], (instrs URECPEv2i32,1150 URSQRTEv2i32,1151 FRECPEv1i32, FRECPEv2f32, FRECPEv1i64,1152 FRSQRTEv1i32, FRSQRTEv2f32, FRSQRTEv1i64)>;1153 1154// ASIMD reciprocal and square root estimate, Q-form U321155// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F32 and F641156def : InstRW<[V1Write_4c_1V02], (instrs URECPEv4i32,1157 URSQRTEv4i32,1158 FRECPEv1f16, FRECPEv4f16,1159 FRECPEv4f32, FRECPEv2f64,1160 FRSQRTEv1f16, FRSQRTEv4f16,1161 FRSQRTEv4f32, FRSQRTEv2f64)>;1162 1163// ASIMD reciprocal and square root estimate, Q-form F161164def : InstRW<[V1Write_6c_2V02], (instrs FRECPEv8f16,1165 FRSQRTEv8f16)>;1166 1167// ASIMD reciprocal exponent1168def : InstRW<[V1Write_3c_1V02], (instrs FRECPXv1f16, FRECPXv1i32, FRECPXv1i64)>;1169 1170// ASIMD reciprocal step1171def : InstRW<[V1Write_4c_1V], (instregex "^FRECPS(16|32|64)$", "^FRECPSv",1172 "^FRSQRTS(16|32|64)$", "^FRSQRTSv")>;1173 1174// ASIMD table lookup, 1 or 2 table regs1175// ASIMD table lookup extension, 1 table reg1176def : InstRW<[V1Write_2c_2V01], (instregex "^TBLv(8|16)i8(One|Two)$",1177 "^TBXv(8|16)i8One$")>;1178 1179// ASIMD table lookup, 3 table regs1180// ASIMD table lookup extension, 2 table reg1181def : InstRW<[V1Write_4c_2V01], (instrs TBLv8i8Three, TBLv16i8Three,1182 TBXv8i8Two, TBXv16i8Two)>;1183 1184// ASIMD table lookup, 4 table regs1185def : InstRW<[V1Write_4c_3V01], (instrs TBLv8i8Four, TBLv16i8Four)>;1186 1187// ASIMD table lookup extension, 3 table reg1188def : InstRW<[V1Write_6c_3V01], (instrs TBXv8i8Three, TBXv16i8Three)>;1189 1190// ASIMD table lookup extension, 4 table reg1191def : InstRW<[V1Write_6c_5V01], (instrs TBXv8i8Four, TBXv16i8Four)>;1192 1193// ASIMD transfer, element to gen reg1194def : InstRW<[V1Write_2c_1V], (instregex "^SMOVvi(((8|16)to(32|64))|32to64)$",1195 "^UMOVvi(8|16|32|64)$")>;1196 1197// ASIMD transfer, gen reg to element1198def : InstRW<[V1Write_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;1199 1200 1201// ASIMD load instructions1202// -----------------------------------------------------------------------------1203 1204// ASIMD load, 1 element, multiple, 1 reg1205def : InstRW<[V1Write_6c_1L],1206 (instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;1207def : InstRW<[WriteAdr, V1Write_6c_1L],1208 (instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;1209 1210// ASIMD load, 1 element, multiple, 2 reg1211def : InstRW<[V1Write_6c_2L],1212 (instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;1213def : InstRW<[WriteAdr, V1Write_6c_2L],1214 (instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;1215 1216// ASIMD load, 1 element, multiple, 3 reg1217def : InstRW<[V1Write_6c_3L],1218 (instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;1219def : InstRW<[WriteAdr, V1Write_6c_3L],1220 (instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;1221 1222// ASIMD load, 1 element, multiple, 4 reg, D-form1223def : InstRW<[V1Write_6c_2L],1224 (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;1225def : InstRW<[WriteAdr, V1Write_6c_2L],1226 (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;1227 1228// ASIMD load, 1 element, multiple, 4 reg, Q-form1229def : InstRW<[V1Write_7c_4L],1230 (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;1231def : InstRW<[WriteAdr, V1Write_7c_4L],1232 (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;1233 1234// ASIMD load, 1 element, one lane1235// ASIMD load, 1 element, all lanes1236def : InstRW<[V1Write_8c_1L_1V],1237 (instregex "^LD1(i|Rv)(8|16|32|64)$",1238 "^LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;1239def : InstRW<[WriteAdr, V1Write_8c_1L_1V],1240 (instregex "^LD1i(8|16|32|64)_POST$",1241 "^LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;1242 1243// ASIMD load, 2 element, multiple, D-form1244def : InstRW<[V1Write_8c_1L_2V],1245 (instregex "^LD2Twov(8b|4h|2s)$")>;1246def : InstRW<[WriteAdr, V1Write_8c_1L_2V],1247 (instregex "^LD2Twov(8b|4h|2s)_POST$")>;1248 1249// ASIMD load, 2 element, multiple, Q-form1250def : InstRW<[V1Write_8c_2L_2V],1251 (instregex "^LD2Twov(16b|8h|4s|2d)$")>;1252def : InstRW<[WriteAdr, V1Write_8c_2L_2V],1253 (instregex "^LD2Twov(16b|8h|4s|2d)_POST$")>;1254 1255// ASIMD load, 2 element, one lane1256// ASIMD load, 2 element, all lanes1257def : InstRW<[V1Write_8c_1L_2V],1258 (instregex "^LD2i(8|16|32|64)$",1259 "^LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;1260def : InstRW<[WriteAdr, V1Write_8c_1L_2V],1261 (instregex "^LD2i(8|16|32|64)_POST$",1262 "^LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;1263 1264// ASIMD load, 3 element, multiple, D-form1265// ASIMD load, 3 element, one lane1266// ASIMD load, 3 element, all lanes1267def : InstRW<[V1Write_8c_2L_3V],1268 (instregex "^LD3Threev(8b|4h|2s)$",1269 "^LD3i(8|16|32|64)$",1270 "^LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;1271def : InstRW<[WriteAdr, V1Write_8c_2L_3V],1272 (instregex "^LD3Threev(8b|4h|2s)_POST$",1273 "^LD3i(8|16|32|64)_POST$",1274 "^LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;1275 1276// ASIMD load, 3 element, multiple, Q-form1277def : InstRW<[V1Write_8c_3L_3V],1278 (instregex "^LD3Threev(16b|8h|4s|2d)$")>;1279def : InstRW<[WriteAdr, V1Write_8c_3L_3V],1280 (instregex "^LD3Threev(16b|8h|4s|2d)_POST$")>;1281 1282// ASIMD load, 4 element, multiple, D-form1283// ASIMD load, 4 element, one lane1284// ASIMD load, 4 element, all lanes1285def : InstRW<[V1Write_8c_3L_4V],1286 (instregex "^LD4Fourv(8b|4h|2s)$",1287 "^LD4i(8|16|32|64)$",1288 "^LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;1289def : InstRW<[WriteAdr, V1Write_8c_3L_4V],1290 (instregex "^LD4Fourv(8b|4h|2s)_POST$",1291 "^LD4i(8|16|32|64)_POST$",1292 "^LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;1293 1294// ASIMD load, 4 element, multiple, Q-form1295def : InstRW<[V1Write_9c_4L_4V],1296 (instregex "^LD4Fourv(16b|8h|4s|2d)$")>;1297def : InstRW<[WriteAdr, V1Write_9c_4L_4V],1298 (instregex "^LD4Fourv(16b|8h|4s|2d)_POST$")>;1299 1300 1301// ASIMD store instructions1302// -----------------------------------------------------------------------------1303 1304// ASIMD store, 1 element, multiple, 1 reg1305// ASIMD store, 1 element, multiple, 2 reg, D-form1306def : InstRW<[V1Write_2c_1L01_1V01],1307 (instregex "^ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$",1308 "^ST1Twov(8b|4h|2s|1d)$")>;1309def : InstRW<[WriteAdr, V1Write_2c_1L01_1V01],1310 (instregex "^ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$",1311 "^ST1Twov(8b|4h|2s|1d)_POST$")>;1312 1313// ASIMD store, 1 element, multiple, 2 reg, Q-form1314// ASIMD store, 1 element, multiple, 3 reg, D-form1315// ASIMD store, 1 element, multiple, 4 reg, D-form1316def : InstRW<[V1Write_2c_2L01_2V01],1317 (instregex "^ST1Twov(16b|8h|4s|2d)$",1318 "^ST1Threev(8b|4h|2s|1d)$",1319 "^ST1Fourv(8b|4h|2s|1d)$")>;1320def : InstRW<[WriteAdr, V1Write_2c_2L01_2V01],1321 (instregex "^ST1Twov(16b|8h|4s|2d)_POST$",1322 "^ST1Threev(8b|4h|2s|1d)_POST$",1323 "^ST1Fourv(8b|4h|2s|1d)_POST$")>;1324 1325// ASIMD store, 1 element, multiple, 3 reg, Q-form1326def : InstRW<[V1Write_2c_3L01_3V01],1327 (instregex "^ST1Threev(16b|8h|4s|2d)$")>;1328def : InstRW<[WriteAdr, V1Write_2c_3L01_3V01],1329 (instregex "^ST1Threev(16b|8h|4s|2d)_POST$")>;1330 1331// ASIMD store, 1 element, multiple, 4 reg, Q-form1332def : InstRW<[V1Write_2c_4L01_4V01],1333 (instregex "^ST1Fourv(16b|8h|4s|2d)$")>;1334def : InstRW<[WriteAdr, V1Write_2c_4L01_4V01],1335 (instregex "^ST1Fourv(16b|8h|4s|2d)_POST$")>;1336 1337// ASIMD store, 1 element, one lane1338// ASIMD store, 2 element, multiple, D-form1339// ASIMD store, 2 element, one lane1340def : InstRW<[V1Write_4c_1L01_1V01],1341 (instregex "^ST1i(8|16|32|64)$",1342 "^ST2Twov(8b|4h|2s)$",1343 "^ST2i(8|16|32|64)$")>;1344def : InstRW<[WriteAdr, V1Write_4c_1L01_1V01],1345 (instregex "^ST1i(8|16|32|64)_POST$",1346 "^ST2Twov(8b|4h|2s)_POST$",1347 "^ST2i(8|16|32|64)_POST$")>;1348 1349// ASIMD store, 2 element, multiple, Q-form1350// ASIMD store, 3 element, multiple, D-form1351// ASIMD store, 3 element, one lane1352// ASIMD store, 4 element, one lane, D1353def : InstRW<[V1Write_4c_2L01_2V01],1354 (instregex "^ST2Twov(16b|8h|4s|2d)$",1355 "^ST3Threev(8b|4h|2s)$",1356 "^ST3i(8|16|32|64)$",1357 "^ST4i64$")>;1358def : InstRW<[WriteAdr, V1Write_4c_2L01_2V01],1359 (instregex "^ST2Twov(16b|8h|4s|2d)_POST$",1360 "^ST3Threev(8b|4h|2s)_POST$",1361 "^ST3i(8|16|32|64)_POST$",1362 "^ST4i64_POST$")>;1363 1364// ASIMD store, 3 element, multiple, Q-form1365def : InstRW<[V1Write_5c_3L01_3V01],1366 (instregex "^ST3Threev(16b|8h|4s|2d)$")>;1367def : InstRW<[WriteAdr, V1Write_5c_3L01_3V01],1368 (instregex "^ST3Threev(16b|8h|4s|2d)_POST$")>;1369 1370// ASIMD store, 4 element, multiple, D-form1371def : InstRW<[V1Write_6c_3L01_3V01],1372 (instregex "^ST4Fourv(8b|4h|2s)$")>;1373def : InstRW<[WriteAdr, V1Write_6c_3L01_3V01],1374 (instregex "^ST4Fourv(8b|4h|2s)_POST$")>;1375 1376// ASIMD store, 4 element, multiple, Q-form, B/H/S1377def : InstRW<[V1Write_7c_6L01_6V01],1378 (instregex "^ST4Fourv(16b|8h|4s)$")>;1379def : InstRW<[WriteAdr, V1Write_7c_6L01_6V01],1380 (instregex "^ST4Fourv(16b|8h|4s)_POST$")>;1381 1382// ASIMD store, 4 element, multiple, Q-form, D1383def : InstRW<[V1Write_4c_4L01_4V01],1384 (instrs ST4Fourv2d)>;1385def : InstRW<[WriteAdr, V1Write_4c_4L01_4V01],1386 (instrs ST4Fourv2d_POST)>;1387 1388// ASIMD store, 4 element, one lane, B/H/S1389def : InstRW<[V1Write_6c_3L_3V],1390 (instregex "^ST4i(8|16|32)$")>;1391def : InstRW<[WriteAdr, V1Write_6c_3L_3V],1392 (instregex "^ST4i(8|16|32)_POST$")>;1393 1394 1395// Cryptography extensions1396// -----------------------------------------------------------------------------1397 1398// Crypto polynomial (64x64) multiply long1399// Covered by "SchedAlias (WriteV[dq]...)" above1400 1401// Crypto AES ops1402def V1WriteVC : WriteSequence<[V1Write_2c_1V]>;1403def V1ReadVC : SchedReadAdvance<2, [V1WriteVC]>;1404def : InstRW<[V1WriteVC], (instrs AESDrr, AESErr)>;1405def : InstRW<[V1Write_2c_1V, V1ReadVC], (instrs AESMCrr, AESIMCrr)>;1406 1407// Crypto SHA1 hash acceleration op1408// Crypto SHA1 schedule acceleration ops1409// Crypto SHA256 schedule acceleration ops1410// Crypto SHA512 hash acceleration ops1411// Crypto SM3 ops1412def : InstRW<[V1Write_2c_1V0], (instregex "^SHA1(H|SU[01])rr$",1413 "^SHA256SU[01]rr$",1414 "^SHA512(H2?|SU[01])$",1415 "^SM3(PARTW(1|2SM3SS1)|TT[12][AB])$")>;1416 1417// Crypto SHA1 hash acceleration ops1418// Crypto SHA256 hash acceleration ops1419// Crypto SM4 ops1420def : InstRW<[V1Write_4c_1V0], (instregex "^SHA1[CMP]rrr$",1421 "^SHA256H2?rrr$",1422 "^SM4E(KEY)?$")>;1423 1424// Crypto SHA3 ops1425def : InstRW<[V1Write_2c_1V0], (instrs BCAX, EOR3, RAX1, XAR)>;1426 1427 1428// CRC instruction1429// -----------------------------------------------------------------------------1430 1431// CRC checksum ops1432def : InstRW<[V1Wr_CRC, V1Rd_CRC], (instregex "^CRC32C?[BHWX]rr$")>;1433 1434 1435// SVE Predicate instructions1436// -----------------------------------------------------------------------------1437 1438// Loop control, based on predicate1439def : InstRW<[V1Write_2c_1M0], (instregex "^BRK[AB]_PP[mz]P$")>;1440def : InstRW<[V1Write_2c_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP, BRKPB_PPzPP)>;1441 1442// Loop control, based on predicate and flag setting1443def : InstRW<[V1Write_3c_2M0], (instrs BRKAS_PPzP, BRKBS_PPzP, BRKNS_PPzP,1444 BRKPAS_PPzPP, BRKPBS_PPzPP)>;1445 1446// Loop control, based on GPR1447def : InstRW<[V1Write_3c_2M0], (instregex "^WHILE(LE|LO|LS|LT)_P(WW|XX)_[BHSD]$")>;1448 1449// Loop terminate1450def : InstRW<[V1Write_1c_1M0], (instregex "^CTERM(EQ|NE)_(WW|XX)$")>;1451 1452// Predicate counting scalar1453// Predicate counting scalar, active predicate1454def : InstRW<[V1Write_2c_1M0], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;1455def : InstRW<[V1Write_2c_1M0], (instregex "^(CNT|([SU]Q)?(DEC|INC))[BHWD]_XPiI$",1456 "^SQ(DEC|INC)[BHWD]_XPiWdI$",1457 "^UQ(DEC|INC)[BHWD]_WPiI$",1458 "^CNTP_XPP_[BHSD]$",1459 "^([SU]Q)?(DEC|INC)P_XP_[BHSD]$",1460 "^UQ(DEC|INC)P_WP_[BHSD]$",1461 "^[SU]Q(DEC|INC)P_XPWd_[BHSD]$")>;1462 1463// Predicate counting vector, active predicate1464def : InstRW<[V1Write_7c_2M0_1V01], (instregex "^([SU]Q)?(DEC|INC)P_ZP_[HSD]$")>;1465 1466// Predicate logical1467def : InstRW<[V1Write_1c_1M0],1468 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP$")>;1469 1470// Predicate logical, flag setting1471def : InstRW<[V1Write_2c_2M0],1472 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)S_PPzPP$")>;1473 1474// Predicate reverse1475// Predicate set/initialize/find next1476// Predicate transpose1477// Predicate unpack and widen1478// Predicate zip/unzip1479def : InstRW<[V1Write_2c_1M0], (instregex "^REV_PP_[BHSD]$",1480 "^PFALSE$", "^PFIRST_B$",1481 "^PNEXT_[BHSD]$", "^PTRUE_[BHSD]$",1482 "^TRN[12]_PPP_[BHSDQ]$",1483 "^(ZIP|UZP)[12]_PPP_[BHSDQ]$")>;1484 1485// Predicate set/initialize/find next1486// Predicate unpack and widen1487def : InstRW<[V1Write_2c_1M0], (instrs PTEST_PP,1488 PUNPKHI_PP, PUNPKLO_PP)>;1489 1490// Predicate select1491def : InstRW<[V1Write_1c_1M0], (instrs SEL_PPPP)>;1492 1493// Predicate set/initialize, set flags1494def : InstRW<[V1Write_3c_2M0], (instregex "^PTRUES_[BHSD]$")>;1495 1496 1497 1498// SVE integer instructions1499// -----------------------------------------------------------------------------1500 1501// Arithmetic, basic1502// Logical1503def : InstRW<[V1Write_2c_1V01],1504 (instregex "^(ABS|CNOT|NEG)_ZPmZ_[BHSD]",1505 "^(ADD|SUB)_Z(I|P[mZ]Z|ZZ)_[BHSD]",1506 "^ADR_[SU]XTW_ZZZ_D_[0123]$",1507 "^ADR_LSL_ZZZ_[SD]_[0123]$",1508 "^[SU]ABD_ZP[mZ]Z_[BHSD]",1509 "^[SU](MAX|MIN)_Z(I|P[mZ]Z)_[BHSD]",1510 "^[SU]Q(ADD|SUB)_Z(I|ZZ)_[BHSD]$",1511 "^SUBR_Z(I|P[mZ]Z)_[BHSD]",1512 "^(AND|EOR|ORR)_ZI$",1513 "^(AND|BIC|EOR|EOR(BT|TB)?|ORR)_ZP?ZZ",1514 "^EOR(BT|TB)_ZZZ_[BHSD]$",1515 "^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]")>;1516 1517// Arithmetic, shift1518def : InstRW<[V1Write_2c_1V1],1519 (instregex "^(ASR|LSL|LSR)_WIDE_Z(Pm|Z)Z_[BHS]",1520 "^(ASR|LSL|LSR)_ZPm[IZ]_[BHSD]",1521 "^(ASR|LSL|LSR)_ZZI_[BHSD]",1522 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",1523 "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>;1524 1525// Arithmetic, shift right for divide1526def : InstRW<[V1Write_4c_1V1], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;1527 1528// Count/reverse bits1529def : InstRW<[V1Write_2c_1V01], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;1530 1531// Broadcast logical bitmask immediate to vector1532def : InstRW<[V1Write_2c_1V01], (instrs DUPM_ZI)>;1533 1534// Compare and set flags1535def : InstRW<[V1Write_4c_1M0_1V0],1536 (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]$",1537 "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]$")>;1538 1539// Conditional extract operations, scalar form1540def : InstRW<[V1Write_9c_1M0_1V1], (instregex "^CLAST[AB]_RPZ_[BHSD]$")>;1541 1542// Conditional extract operations, SIMD&FP scalar and vector forms1543def : InstRW<[V1Write_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]$",1544 "^COMPACT_ZPZ_[SD]$",1545 "^SPLICE_ZPZZ?_[BHSD]$")>;1546 1547// Convert to floating point, 64b to float or convert to double1548def : InstRW<[V1Write_3c_1V0], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",1549 "^[SU]CVTF_ZPmZ_StoD")>;1550 1551// Convert to floating point, 32b to single or half1552def : InstRW<[V1Write_4c_2V0], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;1553 1554// Convert to floating point, 16b to half1555def : InstRW<[V1Write_6c_4V0], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;1556 1557// Copy, scalar1558def : InstRW<[V1Write_5c_1M0_1V01], (instregex "^CPY_ZPmR_[BHSD]$")>;1559 1560// Copy, scalar SIMD&FP or imm1561def : InstRW<[V1Write_2c_1V01], (instregex "^CPY_ZP([mz]I|mV)_[BHSD]$")>;1562 1563// Divides, 32 bit1564def : InstRW<[V1Write_12c7_1V0], (instregex "^[SU]DIVR?_ZPmZ_S",1565 "^[SU]DIV_ZPZZ_S")>;1566 1567// Divides, 64 bit1568def : InstRW<[V1Write_20c7_1V0], (instregex "^[SU]DIVR?_ZPmZ_D",1569 "^[SU]DIV_ZPZZ_D")>;1570 1571// Dot product, 8 bit1572def : InstRW<[V1Wr_ZDOTB, V1Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_BtoS$")>;1573 1574// Dot product, 8 bit, using signed and unsigned integers1575def : InstRW<[V1Wr_ZUDOTB, V1Rd_ZUDOTB],1576 (instrs SUDOT_ZZZI, USDOT_ZZZ, USDOT_ZZZI)>;1577 1578// Dot product, 16 bit1579def : InstRW<[V1Wr_ZDOTH, V1Rd_ZDOTH], (instregex "^[SU]DOT_ZZZI?_HtoD$")>;1580 1581// Duplicate, immediate and indexed form1582def : InstRW<[V1Write_2c_1V01], (instregex "^DUP_ZI_[BHSD]$",1583 "^DUP_ZZI_[BHSDQ]$")>;1584 1585// Duplicate, scalar form1586def : InstRW<[V1Write_3c_1M0], (instregex "^DUP_ZR_[BHSD]$")>;1587 1588// Extend, sign or zero1589def : InstRW<[V1Write_2c_1V1], (instregex "^[SU]XTB_ZPmZ_[HSD]",1590 "^[SU]XTH_ZPmZ_[SD]",1591 "^[SU]XTW_ZPmZ_[D]")>;1592 1593// Extract1594def : InstRW<[V1Write_2c_1V01], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE)>;1595 1596// Extract/insert operation, SIMD and FP scalar form1597def : InstRW<[V1Write_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]$",1598 "^INSR_ZV_[BHSD]$")>;1599 1600// Extract/insert operation, scalar1601def : InstRW<[V1Write_6c_1M0_1V1], (instregex "^LAST[AB]_RPZ_[BHSD]$",1602 "^INSR_ZR_[BHSD]$")>;1603 1604// Horizontal operations, B, H, S form, imm, imm1605def : InstRW<[V1Write_4c_1V0], (instregex "^INDEX_II_[BHS]$")>;1606 1607// Horizontal operations, B, H, S form, scalar, imm / scalar / imm, scalar1608def : InstRW<[V1Write_7c_1M0_1V0], (instregex "^INDEX_(IR|RI|RR)_[BHS]$")>;1609 1610// Horizontal operations, D form, imm, imm1611def : InstRW<[V1Write_5c_2V0], (instrs INDEX_II_D)>;1612 1613// Horizontal operations, D form, scalar, imm / scalar / imm, scalar1614def : InstRW<[V1Write_8c_2M0_2V0], (instregex "^INDEX_(IR|RI|RR)_D$")>;1615 1616// Move prefix1617def : InstRW<[V1Write_2c_1V01], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$",1618 "^MOVPRFX_ZZ$")>;1619 1620// Matrix multiply-accumulate1621def : InstRW<[V1Wr_ZMMA, V1Rd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;1622 1623// Multiply, B, H, S element size1624def : InstRW<[V1Write_4c_1V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]",1625 "^MUL_ZPZZ_[BHS]",1626 "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]",1627 "^[SU]MULH_ZPZZ_[BHS]")>;1628 1629// Multiply, D element size1630def : InstRW<[V1Write_5c_2V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D",1631 "^MUL_ZPZZ_D",1632 "^[SU]MULH_(ZPmZ|ZZZ)_D",1633 "^[SU]MULH_ZPZZ_D")>;1634 1635// Multiply accumulate, D element size1636def : InstRW<[V1Wr_ZMAD, V1Rd_ZMAD],1637 (instregex "^ML[AS]_ZPZZZ_D")>;1638def : InstRW<[V1Wr_ZMAD, ReadDefault, V1Rd_ZMAD],1639 (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;1640 1641// Multiply accumulate, B, H, S element size1642// NOTE: This is not specified in the SOG.1643def : InstRW<[V1Write_4c_1V0], (instregex "^(ML[AS]|MAD|MSB)_(ZPmZZ|ZPZZZ)_[BHS]")>;1644 1645// Predicate counting vector1646def : InstRW<[V1Write_2c_1V0], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI$")>;1647 1648// Reduction, arithmetic, B form1649def : InstRW<[V1Write_14c_1V_1V0_2V1_1V13],1650 (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;1651 1652// Reduction, arithmetic, H form1653def : InstRW<[V1Write_12c_1V_1V01_2V1],1654 (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;1655 1656// Reduction, arithmetic, S form1657def : InstRW<[V1Write_10c_1V_1V01_2V1],1658 (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;1659 1660// Reduction, arithmetic, D form1661def : InstRW<[V1Write_8c_1V_1V01],1662 (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;1663 1664// Reduction, logical1665def : InstRW<[V1Write_12c_4V01], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]$")>;1666 1667// Reverse, vector1668def : InstRW<[V1Write_2c_1V01], (instregex "^REV_ZZ_[BHSD]$",1669 "^REVB_ZPmZ_[HSD]$",1670 "^REVH_ZPmZ_[SD]$",1671 "^REVW_ZPmZ_D$")>;1672 1673// Select, vector form1674// Table lookup1675// Table lookup extension1676// Transpose, vector form1677// Unpack and extend1678// Zip/unzip1679def : InstRW<[V1Write_2c_1V01], (instregex "^SEL_ZPZZ_[BHSD]$",1680 "^TB[LX]_ZZZ_[BHSD]$",1681 "^TRN[12]_ZZZ_[BHSDQ]$",1682 "^[SU]UNPK(HI|LO)_ZZ_[HSD]$",1683 "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>;1684 1685 1686// SVE floating-point instructions1687// -----------------------------------------------------------------------------1688 1689// Floating point absolute value/difference1690def : InstRW<[V1Write_2c_1V01], (instregex "^FAB[SD]_ZPmZ_[HSD]",1691 "^FABD_ZPZZ_[HSD]",1692 "^FABS_ZPmZ_[HSD]")>;1693 1694// Floating point arithmetic1695def : InstRW<[V1Write_2c_1V01], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",1696 "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",1697 "^FADDP_ZPmZZ_[HSD]",1698 "^FNEG_ZPmZ_[HSD]",1699 "^FSUBR_ZPm[IZ]_[HSD]",1700 "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;1701 1702// Floating point associative add, F161703def : InstRW<[V1Write_19c_18V0], (instrs FADDA_VPZ_H)>;1704 1705// Floating point associative add, F321706def : InstRW<[V1Write_11c_10V0], (instrs FADDA_VPZ_S)>;1707 1708// Floating point associative add, F641709def : InstRW<[V1Write_8c_3V01], (instrs FADDA_VPZ_D)>;1710 1711// Floating point compare1712def : InstRW<[V1Write_2c_1V0], (instregex "^FAC(GE|GT)_PPzZZ_[HSD]$",1713 "^FCM(EQ|GE|GT|NE|UO)_PPzZZ_[HSD]$",1714 "^FCM(EQ|GE|GT|LE|LT|NE)_PPzZ0_[HSD]$")>;1715 1716// Floating point complex add1717def : InstRW<[V1Write_3c_1V01], (instregex "^FCADD_ZPmZ_[HSD]$")>;1718 1719// Floating point complex multiply add1720def : InstRW<[V1Wr_ZFCMA, ReadDefault, V1Rd_ZFCMA], (instregex "^FCMLA_ZPmZZ_[HSD]")>;1721def : InstRW<[V1Wr_ZFCMA, V1Rd_ZFCMA], (instregex "^FCMLA_ZZZI_[HS]")>;1722 1723// Floating point convert, long or narrow (F16 to F32 or F32 to F16)1724// Floating point convert to integer, F321725def : InstRW<[V1Write_4c_2V0], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",1726 "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;1727 1728// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F32 or F64 to F16)1729// Floating point convert to integer, F641730def : InstRW<[V1Write_3c_1V0], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",1731 "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>;1732 1733// Floating point convert to integer, F161734def : InstRW<[V1Write_6c_4V0], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;1735 1736// Floating point copy1737def : InstRW<[V1Write_2c_1V01], (instregex "^FCPY_ZPmI_[HSD]$",1738 "^FDUP_ZI_[HSD]$")>;1739 1740// Floating point divide, F161741def : InstRW<[V1Write_13c10_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;1742 1743// Floating point divide, F321744def : InstRW<[V1Write_10c7_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;1745 1746// Floating point divide, F641747def : InstRW<[V1Write_15c7_1V0], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;1748 1749// Floating point min/max1750def : InstRW<[V1Write_2c_1V01], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",1751 "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;1752 1753// Floating point multiply1754def : InstRW<[V1Write_3c_1V01], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",1755 "^FMULX_ZPZZ_[HSD]",1756 "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",1757 "^FMUL_ZPZ[IZ]_[HSD]")>;1758 1759// Floating point multiply accumulate1760def : InstRW<[V1Wr_ZFMA, ReadDefault, V1Rd_ZFMA],1761 (instregex "^FN?ML[AS]_ZPmZZ_[HSD]",1762 "^FN?(MAD|MSB)_ZPmZZ_[HSD]")>;1763def : InstRW<[V1Wr_ZFMA, V1Rd_ZFMA],1764 (instregex "^FML[AS]_ZZZI_[HSD]",1765 "^FN?ML[AS]_ZPZZZ_[HSD]")>;1766 1767// Floating point reciprocal step1768def : InstRW<[V1Write_4c_1V01], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]")>;1769 1770// Floating point reciprocal estimate, F161771def : InstRW<[V1Write_6c_4V0], (instrs FRECPE_ZZ_H, FRSQRTE_ZZ_H)>;1772 1773// Floating point reciprocal estimate, F321774def : InstRW<[V1Write_4c_2V0], (instrs FRECPE_ZZ_S, FRSQRTE_ZZ_S)>;1775 1776// Floating point reciprocal estimate, F641777def : InstRW<[V1Write_3c_1V0], (instrs FRECPE_ZZ_D, FRSQRTE_ZZ_D)>;1778 1779// Floating point reciprocal exponent1780def : InstRW<[V1Write_3c_1V0], (instregex "^FRECPX_ZPmZ_[HSD]")>;1781 1782// Floating point reduction, F161783def : InstRW<[V1Write_13c_6V01], (instregex "^F(ADD|((MAX|MIN)(NM)?))V_VPZ_H$")>;1784 1785// Floating point reduction, F321786def : InstRW<[V1Write_11c_1V_5V01], (instregex "^F(ADD|((MAX|MIN)(NM)?))V_VPZ_S$")>;1787 1788// Floating point reduction, F641789def : InstRW<[V1Write_9c_1V_4V01], (instregex "^F(ADD|((MAX|MIN)(NM)?))V_VPZ_D$")>;1790 1791// Floating point round to integral, F161792def : InstRW<[V1Write_6c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;1793 1794// Floating point round to integral, F321795def : InstRW<[V1Write_4c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;1796 1797// Floating point round to integral, F641798def : InstRW<[V1Write_3c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;1799 1800// Floating point square root, F161801def : InstRW<[V1Write_13c10_1V0], (instregex "^FSQRT_ZPmZ_H")>;1802 1803// Floating point square root, F321804def : InstRW<[V1Write_10c7_1V0], (instregex "^FSQRT_ZPmZ_S")>;1805 1806// Floating point square root, F641807def : InstRW<[V1Write_16c7_1V0], (instregex "^FSQRT_ZPmZ_D")>;1808 1809// Floating point trigonometric1810def : InstRW<[V1Write_3c_1V01], (instregex "^FEXPA_ZZ_[HSD]$",1811 "^FTMAD_ZZI_[HSD]$",1812 "^FTS(MUL|SEL)_ZZZ_[HSD]$")>;1813 1814 1815// SVE BFloat16 (BF16) instructions1816// -----------------------------------------------------------------------------1817 1818// Convert, F32 to BF161819def : InstRW<[V1Write_4c_1V0], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;1820 1821// Dot product1822def : InstRW<[V1Wr_ZBFDOT, V1Rd_ZBFDOT], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;1823 1824// Matrix multiply accumulate1825def : InstRW<[V1Wr_ZBFMMA, V1Rd_ZBFMMA], (instrs BFMMLA_ZZZ_HtoS)>;1826 1827// Multiply accumulate long1828def : InstRW<[V1Wr_ZBFMAL, V1Rd_ZBFMAL], (instregex "^BFMLAL[BT]_ZZZ(I)?$")>;1829 1830 1831// SVE Load instructions1832// -----------------------------------------------------------------------------1833 1834// Load vector1835def : InstRW<[V1Write_6c_1L01], (instrs LDR_ZXI)>;1836 1837// Load predicate1838def : InstRW<[V1Write_6c_1L_1M], (instrs LDR_PXI)>;1839 1840// Contiguous load, scalar + imm1841// Contiguous load, scalar + scalar1842// Contiguous load broadcast, scalar + imm1843// Contiguous load broadcast, scalar + scalar1844def : InstRW<[V1Write_6c_1L01], (instregex "^LD1[BHWD]_IMM$",1845 "^LD1S?B_[HSD]_IMM$",1846 "^LD1S?H_[SD]_IMM$",1847 "^LD1S?W_D_IMM$",1848 "^LD1[BWD]$",1849 "^LD1S?B_[HSD]$",1850 "^LD1S?W_D$",1851 "^LD1R[BHWD]_IMM$",1852 "^LD1RSW_IMM$",1853 "^LD1RS?B_[HSD]_IMM$",1854 "^LD1RS?H_[SD]_IMM$",1855 "^LD1RS?W_D_IMM$",1856 "^LD1RQ_[BHWD]_IMM$",1857 "^LD1RQ_[BWD]$")>;1858def : InstRW<[V1Write_7c_1L01_1S], (instregex "^LD1H$",1859 "^LD1S?H_[SD]$",1860 "^LD1RQ_H$")>;1861 1862// Non temporal load, scalar + imm1863def : InstRW<[V1Write_6c_1L01], (instregex "^LDNT1[BHWD]_ZRI$")>;1864 1865// Non temporal load, scalar + scalar1866def : InstRW<[V1Write_7c_1L01_1S], (instrs LDNT1H_ZRR)>;1867def : InstRW<[V1Write_6c_1L01_1S], (instregex "^LDNT1[BWD]_ZRR$")>;1868 1869// Contiguous first faulting load, scalar + scalar1870def : InstRW<[V1Write_7c_1L01_1S], (instregex "^LDFF1H$",1871 "^LDFF1S?H_[SD]$")>;1872def : InstRW<[V1Write_6c_1L01_1S], (instregex "^LDFF1[BWD]$",1873 "^LDFF1S?B_[HSD]$",1874 "^LDFF1S?W_D$")>;1875 1876// Contiguous non faulting load, scalar + imm1877def : InstRW<[V1Write_6c_1L01], (instregex "^LDNF1[BHWD]_IMM$",1878 "^LDNF1S?B_[HSD]_IMM$",1879 "^LDNF1S?H_[SD]_IMM$",1880 "^LDNF1S?W_D_IMM$")>;1881 1882// Contiguous Load two structures to two vectors, scalar + imm1883def : InstRW<[V1Write_8c_2L01_2V01], (instregex "^LD2[BHWD]_IMM$")>;1884 1885// Contiguous Load two structures to two vectors, scalar + scalar1886def : InstRW<[V1Write_10c_2L01_2V01], (instrs LD2H)>;1887def : InstRW<[V1Write_9c_2L01_2V01], (instregex "^LD2[BWD]$")>;1888 1889// Contiguous Load three structures to three vectors, scalar + imm1890def : InstRW<[V1Write_11c_3L01_3V01], (instregex "^LD3[BHWD]_IMM$")>;1891 1892// Contiguous Load three structures to three vectors, scalar + scalar1893def : InstRW<[V1Write_13c_3L01_1S_3V01], (instregex "^LD3[BHWD]$")>;1894 1895// Contiguous Load four structures to four vectors, scalar + imm1896def : InstRW<[V1Write_12c_4L01_4V01], (instregex "^LD4[BHWD]_IMM$")>;1897 1898// Contiguous Load four structures to four vectors, scalar + scalar1899def : InstRW<[V1Write_13c_4L01_2S_4V01], (instregex "^LD4[BHWD]$")>;1900 1901// Gather load, vector + imm, 32-bit element size1902def : InstRW<[V1Write_11c_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",1903 "^GLD(FF)?1W_IMM$")>;1904 1905// Gather load, vector + imm, 64-bit element size1906def : InstRW<[V1Write_9c_2L_2V],1907 (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",1908 "^GLD(FF)?1S?[BHW]_D(_[SU]XTW)?(_SCALED)?$",1909 "^GLD(FF)?1D_IMM$",1910 "^GLD(FF)?1D(_[SU]XTW)?(_SCALED)?$")>;1911 1912// Gather load, 32-bit scaled offset1913def : InstRW<[V1Write_11c_2L_2V],1914 (instregex "^GLD(FF)?1S?[HW]_S_[SU]XTW_SCALED$",1915 "^GLD(FF)?1W_[SU]XTW_SCALED")>;1916 1917// Gather load, 32-bit unpacked unscaled offset1918def : InstRW<[V1Write_9c_1L_1V],1919 (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",1920 "^GLD(FF)?1W_[SU]XTW$")>;1921 1922// Prefetch1923// NOTE: This is not specified in the SOG.1924def : InstRW<[V1Write_4c_1L01], (instregex "^PRF[BHWD]")>;1925 1926 1927// SVE Store instructions1928// -----------------------------------------------------------------------------1929 1930// Store from predicate reg1931def : InstRW<[V1Write_1c_1L01], (instrs STR_PXI)>;1932 1933// Store from vector reg1934def : InstRW<[V1Write_2c_1L01_1V], (instrs STR_ZXI)>;1935 1936// Contiguous store, scalar + imm1937// Contiguous store, scalar + scalar1938def : InstRW<[V1Write_2c_1L01_1V], (instregex "^ST1[BHWD]_IMM$",1939 "^ST1B_[HSD]_IMM$",1940 "^ST1H_[SD]_IMM$",1941 "^ST1W_D_IMM$",1942 "^ST1[BWD]$",1943 "^ST1B_[HSD]$",1944 "^ST1W_D$")>;1945def : InstRW<[V1Write_2c_1L01_1S_1V], (instregex "^ST1H(_[SD])?$")>;1946 1947// Contiguous store two structures from two vectors, scalar + imm1948// Contiguous store two structures from two vectors, scalar + scalar1949def : InstRW<[V1Write_4c_1L01_1V], (instregex "^ST2[BHWD]_IMM$",1950 "^ST2[BWD]$")>;1951def : InstRW<[V1Write_4c_1L01_1S_1V], (instrs ST2H)>;1952 1953// Contiguous store three structures from three vectors, scalar + imm1954def : InstRW<[V1Write_7c_5L01_5V], (instregex "^ST3[BHWD]_IMM$")>;1955 1956// Contiguous store three structures from three vectors, scalar + scalar1957def : InstRW<[V1Write_7c_5L01_5S_5V], (instregex "^ST3[BHWD]$")>;1958 1959// Contiguous store four structures from four vectors, scalar + imm1960def : InstRW<[V1Write_11c_9L01_9V], (instregex "^ST4[BHWD]_IMM$")>;1961 1962// Contiguous store four structures from four vectors, scalar + scalar1963def : InstRW<[V1Write_11c_9L01_9S_9V], (instregex "^ST4[BHWD]$")>;1964 1965// Non temporal store, scalar + imm1966// Non temporal store, scalar + scalar1967def : InstRW<[V1Write_2c_1L01_1V], (instregex "^STNT1[BHWD]_ZRI$",1968 "^STNT1[BWD]_ZRR$")>;1969def : InstRW<[V1Write_2c_1L01_1S_1V], (instrs STNT1H_ZRR)>;1970 1971// Scatter store vector + imm 32-bit element size1972// Scatter store, 32-bit scaled offset1973// Scatter store, 32-bit unscaled offset1974def : InstRW<[V1Write_10c_2L01_2V], (instregex "^SST1[BH]_S_IMM$",1975 "^SST1W_IMM$",1976 "^SST1(H_S|W)_[SU]XTW_SCALED$",1977 "^SST1[BH]_S_[SU]XTW$",1978 "^SST1W_[SU]XTW$")>;1979 1980// Scatter store, 32-bit unpacked unscaled offset1981// Scatter store, 32-bit unpacked scaled offset1982def : InstRW<[V1Write_6c_1L01_1V], (instregex "^SST1[BHW]_D_[SU]XTW$",1983 "^SST1D_[SU]XTW$",1984 "^SST1[HW]_D_[SU]XTW_SCALED$",1985 "^SST1D_[SU]XTW_SCALED$")>;1986 1987// Scatter store vector + imm 64-bit element size1988// Scatter store, 64-bit scaled offset1989// Scatter store, 64-bit unscaled offset1990def : InstRW<[V1Write_6c_1L01_1V], (instregex "^SST1[BHW]_D_IMM$",1991 "^SST1D_IMM$",1992 "^SST1[HW]_D_SCALED$",1993 "^SST1D_SCALED$",1994 "^SST1[BHW]_D$",1995 "^SST1D$")>;1996 1997 1998// SVE Miscellaneous instructions1999// -----------------------------------------------------------------------------2000 2001// Read first fault register, unpredicated2002// Set first fault register2003// Write to first fault register2004def : InstRW<[V1Write_2c_1M0], (instrs RDFFR_P,2005 SETFFR,2006 WRFFR)>;2007 2008// Read first fault register, predicated2009def : InstRW<[V1Write_3c_2M0], (instrs RDFFR_PPz)>;2010 2011// Read first fault register and set flags2012def : InstRW<[V1Write_4c_1M], (instrs RDFFRS_PPz)>;2013 2014 2015}2016