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1//=- AArch64SchedNeoverseV2.td - NeoverseV2 Scheduling Defs --*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the scheduling model for the Arm Neoverse V2 processors.10// All information is taken from the V2 Software Optimisation guide:11//12// https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p213//14//===----------------------------------------------------------------------===//15 16def NeoverseV2Model : SchedMachineModel {17 let IssueWidth = 6; // This value comes from the decode bandwidth18 // and empirical measurements showed that a19 // lower value is better.20 let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.21 let LoadLatency = 4; // Optimistic load latency.22 let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.23 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.24 let CompleteModel = 1;25 26 list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,27 [HasSVE2p1, HasSVEB16B16,28 HasCPA, HasCSSC]);29}30 31//===----------------------------------------------------------------------===//32// Define each kind of processor resource and number available on Neoverse V2.33// Instructions are first fetched and then decoded into internal macro-ops34// (MOPs). From there, the MOPs proceed through register renaming and dispatch35// stages. A MOP can be split into two micro-ops further down the pipeline36// after the decode stage. Once dispatched, micro-ops wait for their operands37// and issue out-of-order to one of seventeen issue pipelines. Each issue38// pipeline can accept one micro-op per cycle.39 40let SchedModel = NeoverseV2Model in {41 42// Define the (17) issue ports.43def V2UnitB : ProcResource<2>; // Branch 0/144def V2UnitS0 : ProcResource<1>; // Integer single-cycle 045def V2UnitS1 : ProcResource<1>; // Integer single-cycle 146def V2UnitS2 : ProcResource<1>; // Integer single-cycle 247def V2UnitS3 : ProcResource<1>; // Integer single-cycle 348def V2UnitM0 : ProcResource<1>; // Integer single/multicycle 049def V2UnitM1 : ProcResource<1>; // Integer single/multicycle 150def V2UnitV0 : ProcResource<1>; // FP/ASIMD 051def V2UnitV1 : ProcResource<1>; // FP/ASIMD 152def V2UnitV2 : ProcResource<1>; // FP/ASIMD 253def V2UnitV3 : ProcResource<1>; // FP/ASIMD 354def V2UnitL01 : ProcResource<2>; // Load/Store 0/155def V2UnitL2 : ProcResource<1>; // Load 256def V2UnitD : ProcResource<2>; // Store data 0/157def V2UnitFlg : ProcResource<3>; // Flags58 59def V2UnitR : ProcResGroup<[V2UnitS0, V2UnitS1]>; // Integer single-cycle 0/160def V2UnitS : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitS2, V2UnitS3]>; // Integer single-cycle 0/1/2/361def V2UnitF : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitM0, V2UnitM1]>; // Integer single-cycle 0/1 and single/multicycle 0/162def V2UnitI : ProcResGroup<[V2UnitS0, V2UnitS1, V2UnitS2, V2UnitS3, V2UnitM0, V2UnitM1]>; // Integer single-cycle 0/1/2/3 and single/multicycle 0/163def V2UnitM : ProcResGroup<[V2UnitM0, V2UnitM1]>; // Integer single/multicycle 0/164def V2UnitL : ProcResGroup<[V2UnitL01, V2UnitL2]>; // Load/Store 0/1 and Load 265def V2UnitV : ProcResGroup<[V2UnitV0, V2UnitV1, V2UnitV2, V2UnitV3]>; // FP/ASIMD 0/1/2/366def V2UnitV01 : ProcResGroup<[V2UnitV0, V2UnitV1]>; // FP/ASIMD 0/167def V2UnitV02 : ProcResGroup<[V2UnitV0, V2UnitV2]>; // FP/ASIMD 0/268def V2UnitV13 : ProcResGroup<[V2UnitV1, V2UnitV3]>; // FP/ASIMD 1/369def V2UnitV23 : ProcResGroup<[V2UnitV2, V2UnitV3]>; // FP/ASIMD 2/370 71// Define commonly used read types.72 73// No forwarding is provided for these types.74def : ReadAdvance<ReadI, 0>;75def : ReadAdvance<ReadISReg, 0>;76def : ReadAdvance<ReadIEReg, 0>;77def : ReadAdvance<ReadIM, 0>;78def : ReadAdvance<ReadIMA, 0>;79def : ReadAdvance<ReadID, 0>;80def : ReadAdvance<ReadExtrHi, 0>;81def : ReadAdvance<ReadAdrBase, 0>;82def : ReadAdvance<ReadST, 0>;83def : ReadAdvance<ReadVLD, 0>;84 85// NOTE: Copied from N2.86def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }87def : WriteRes<WriteBarrier, []> { let Latency = 1; }88def : WriteRes<WriteHint, []> { let Latency = 1; }89def : WriteRes<WriteLDHi, []> { let Latency = 4; }90 91//===----------------------------------------------------------------------===//92// Define customized scheduler read/write types specific to the Neoverse V2.93 94//===----------------------------------------------------------------------===//95 96// Define generic 0 micro-op types97def V2Write_0c : SchedWriteRes<[]> { let Latency = 0; }98 99// Define generic 1 micro-op types100 101def V2Write_1c_1B : SchedWriteRes<[V2UnitB]> { let Latency = 1; }102def V2Write_1c_1F : SchedWriteRes<[V2UnitF]> { let Latency = 1; }103def V2Write_1c_1F_1Flg : SchedWriteRes<[V2UnitF, V2UnitFlg]> { let Latency = 1; }104def V2Write_1c_1I : SchedWriteRes<[V2UnitI]> { let Latency = 1; }105def V2Write_1c_1M : SchedWriteRes<[V2UnitM]> { let Latency = 1; }106def V2Write_1c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 1; }107def V2Write_1c_1L01 : SchedWriteRes<[V2UnitL01]> { let Latency = 1; }108def V2Write_2c_1M : SchedWriteRes<[V2UnitM]> { let Latency = 2; }109def V2Write_2c_1M_1Flg : SchedWriteRes<[V2UnitM, V2UnitFlg]> { let Latency = 2; }110def V2Write_3c_1M : SchedWriteRes<[V2UnitM]> { let Latency = 3; }111def V2Write_2c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }112def V2Write_3c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 3; }113def V2Write_5c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 5; }114def V2Write_12c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 12;115 let ReleaseAtCycles = [12]; }116def V2Write_20c_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 20;117 let ReleaseAtCycles = [20]; }118def V2Write_4c_1L : SchedWriteRes<[V2UnitL]> { let Latency = 4; }119def V2Write_6c_1L : SchedWriteRes<[V2UnitL]> { let Latency = 6; }120def V2Write_2c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 2; }121def V2Write_2c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 2; }122def V2Write_2c_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 2; }123def V2Write_2c_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 2; }124def V2Write_3c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 3; }125def V2Write_3c_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 3;126 let ReleaseAtCycles = [2]; }127def V2Write_3c_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 3; }128def V2Write_4c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 4; }129def V2Write_5c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 5; }130def V2Write_6c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 6; }131def V2Write_12c_1V : SchedWriteRes<[V2UnitV]> { let Latency = 12; }132def V2Write_3c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 3; }133def V2Write_3c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 3; }134def V2Write_4c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 4; }135def V2Write_4c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }136def V2Write_7c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 7;137 let ReleaseAtCycles = [7]; }138def V2Write_7c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 7;139 let ReleaseAtCycles = [2]; }140def V2Write_9c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 9; }141def V2Write_9c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 9;142 let ReleaseAtCycles = [2]; }143def V2Write_10c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 10; }144def V2Write_10c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 10;145 let ReleaseAtCycles = [2]; }146def V2Write_12c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 12;147 let ReleaseAtCycles = [11]; }148def V2Write_13c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 13; }149def V2Write_15c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 15; }150def V2Write_15c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 15;151 let ReleaseAtCycles = [8]; }152def V2Write_16c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 16; }153def V2Write_16c_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 16;154 let ReleaseAtCycles = [8]; }155def V2Write_20c_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 20;156 let ReleaseAtCycles = [20]; }157def V2Write_2c_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 2; }158def V2Write_2c_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 2; }159def V2Write_3c_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 3; }160def V2Write_3c_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 3; }161def V2Write_4c_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 4; }162def V2Write_4c_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 4; }163def V2Write_6c_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 6; }164def V2Write_10c_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 10; }165def V2Write_6c_1L01 : SchedWriteRes<[V2UnitL01]> { let Latency = 6; }166 167//===----------------------------------------------------------------------===//168// Define generic 2 micro-op types169 170def V2Write_1c_1B_1R : SchedWriteRes<[V2UnitB, V2UnitR]> {171 let Latency = 1;172 let NumMicroOps = 2;173}174 175def V2Write_6c_1M0_1B : SchedWriteRes<[V2UnitM0, V2UnitB]> {176 let Latency = 6;177 let NumMicroOps = 2;178}179 180def V2Write_9c_1M0_1L : SchedWriteRes<[V2UnitM0, V2UnitL]> {181 let Latency = 9;182 let NumMicroOps = 2;183}184 185def V2Write_3c_1I_1M : SchedWriteRes<[V2UnitI, V2UnitM]> {186 let Latency = 3;187 let NumMicroOps = 2;188}189 190def V2Write_1c_2M : SchedWriteRes<[V2UnitM, V2UnitM]> {191 let Latency = 1;192 let NumMicroOps = 2;193}194 195def V2Write_3c_2M : SchedWriteRes<[V2UnitM, V2UnitM]> {196 let Latency = 3;197 let NumMicroOps = 2;198}199 200def V2Write_4c_2M : SchedWriteRes<[V2UnitM, V2UnitM]> {201 let Latency = 4;202 let NumMicroOps = 2;203}204 205def V2Write_5c_1L_1F : SchedWriteRes<[V2UnitL, V2UnitF]> {206 let Latency = 5;207 let NumMicroOps = 2;208}209 210def V2Write_6c_1I_1L : SchedWriteRes<[V2UnitI, V2UnitL]> {211 let Latency = 6;212 let NumMicroOps = 2;213}214 215def V2Write_7c_1F_1L : SchedWriteRes<[V2UnitF, V2UnitL]> {216 let Latency = 7;217 let NumMicroOps = 2;218}219 220def V2Write_7c_1I_1L : SchedWriteRes<[V2UnitI, V2UnitL]> {221 let Latency = 7;222 let NumMicroOps = 2;223}224 225def V2Write_1c_1L01_1D : SchedWriteRes<[V2UnitL01, V2UnitD]> {226 let Latency = 1;227 let NumMicroOps = 2;228}229 230def V2Write_5c_1M0_1V : SchedWriteRes<[V2UnitM0, V2UnitV]> {231 let Latency = 5;232 let NumMicroOps = 2;233}234 235def V2Write_2c_1L01_1V01 : SchedWriteRes<[V2UnitL01, V2UnitV01]> {236 let Latency = 2;237 let NumMicroOps = 2;238}239 240def V2Write_2c_1L01_1V : SchedWriteRes<[V2UnitL01, V2UnitV]> {241 let Latency = 2;242 let NumMicroOps = 2;243}244 245def V2Write_2c_2V01 : SchedWriteRes<[V2UnitV01, V2UnitV01]> {246 let Latency = 2;247 let NumMicroOps = 2;248}249 250def V2Write_4c_2V01 : SchedWriteRes<[V2UnitV01, V2UnitV01]> {251 let Latency = 4;252 let NumMicroOps = 2;253}254 255def V2Write_4c_1L01_1V01 : SchedWriteRes<[V2UnitL01, V2UnitV01]> {256 let Latency = 4;257 let NumMicroOps = 2;258}259 260def V2Write_5c_1V13_1V : SchedWriteRes<[V2UnitV13, V2UnitV]> {261 let Latency = 5;262 let NumMicroOps = 2;263}264 265def V2Write_4c_2V0 : SchedWriteRes<[V2UnitV0, V2UnitV0]> {266 let Latency = 4;267 let NumMicroOps = 2;268}269 270def V2Write_4c_2V02 : SchedWriteRes<[V2UnitV02, V2UnitV02]> {271 let Latency = 4;272 let NumMicroOps = 2;273}274 275def V2Write_4c_2V : SchedWriteRes<[V2UnitV, V2UnitV]> {276 let Latency = 4;277 let NumMicroOps = 2;278}279 280def V2Write_6c_2V : SchedWriteRes<[V2UnitV, V2UnitV]> {281 let Latency = 6;282 let NumMicroOps = 2;283}284 285def V2Write_6c_2L : SchedWriteRes<[V2UnitL, V2UnitL]> {286 let Latency = 6;287 let NumMicroOps = 2;288}289 290def V2Write_8c_1L_1V : SchedWriteRes<[V2UnitL, V2UnitV]> {291 let Latency = 8;292 let NumMicroOps = 2;293}294 295def V2Write_4c_1L01_1V : SchedWriteRes<[V2UnitL01, V2UnitV]> {296 let Latency = 4;297 let NumMicroOps = 2;298}299 300def V2Write_3c_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {301 let Latency = 3;302 let NumMicroOps = 2;303}304 305def V2Write_4c_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {306 let Latency = 4;307 let NumMicroOps = 2;308}309 310def V2Write_1c_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {311 let Latency = 1;312 let NumMicroOps = 2;313}314 315def V2Write_2c_1M0_1M : SchedWriteRes<[V2UnitM0, V2UnitM]> {316 let Latency = 2;317 let NumMicroOps = 2;318}319 320def V2Write_6c_2V1 : SchedWriteRes<[V2UnitV1, V2UnitV1]> {321 let Latency = 6;322 let NumMicroOps = 2;323}324 325def V2Write_4c_1V0_1M0 : SchedWriteRes<[V2UnitV0, V2UnitM0]> {326 let Latency = 4;327 let NumMicroOps = 2;328}329 330def V2Write_5c_1V0_1M0 : SchedWriteRes<[V2UnitV0, V2UnitM0]> {331 let Latency = 5;332 let NumMicroOps = 2;333}334 335def V2Write_5c_2V0 : SchedWriteRes<[V2UnitV0, V2UnitV0]> {336 let Latency = 5;337 let NumMicroOps = 2;338}339 340def V2Write_5c_2V02 : SchedWriteRes<[V2UnitV02, V2UnitV02]> {341 let Latency = 5;342 let NumMicroOps = 2;343}344 345def V2Write_6c_1V1_1M0 : SchedWriteRes<[V2UnitV1, V2UnitM0]> {346 let Latency = 6;347 let NumMicroOps = 2;348}349 350def V2Write_7c_1M0_1V02 : SchedWriteRes<[V2UnitM0, V2UnitV02]> {351 let Latency = 7;352 let NumMicroOps = 2;353}354 355def V2Write_2c_1V0_1M : SchedWriteRes<[V2UnitV0, V2UnitM]> {356 let Latency = 2;357 let NumMicroOps = 2;358}359 360def V2Write_3c_1V0_1M : SchedWriteRes<[V2UnitV0, V2UnitM]> {361 let Latency = 3;362 let NumMicroOps = 2;363}364 365def V2Write_6c_1V_1V13 : SchedWriteRes<[V2UnitV, V2UnitV13]> {366 let Latency = 6;367 let NumMicroOps = 2;368}369 370def V2Write_6c_1L_1M : SchedWriteRes<[V2UnitL, V2UnitM]> {371 let Latency = 6;372 let NumMicroOps = 2;373}374 375def V2Write_6c_1L_1S : SchedWriteRes<[V2UnitL, V2UnitS]> {376 let Latency = 6;377 let NumMicroOps = 2;378}379 380def V2Write_6c_2V13 : SchedWriteRes<[V2UnitV13, V2UnitV13]> {381 let Latency = 6;382 let NumMicroOps = 2;383}384 385def V2Write_8c_1M0_1V01 : SchedWriteRes<[V2UnitM0, V2UnitV01]> {386 let Latency = 8;387 let NumMicroOps = 2;388}389 390//===----------------------------------------------------------------------===//391// Define generic 3 micro-op types392 393def V2Write_1c_1L01_1D_1I : SchedWriteRes<[V2UnitL01, V2UnitD, V2UnitI]> {394 let Latency = 1;395 let NumMicroOps = 3;396}397 398def V2Write_2c_1L01_1V01_1I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitI]> {399 let Latency = 2;400 let NumMicroOps = 3;401}402 403def V2Write_2c_1L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01]> {404 let Latency = 2;405 let NumMicroOps = 3;406}407 408def V2Write_4c_1L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01]> {409 let Latency = 4;410 let NumMicroOps = 3;411}412 413def V2Write_9c_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> {414 let Latency = 9;415 let NumMicroOps = 3;416}417 418def V2Write_4c_3V01 : SchedWriteRes<[V2UnitV01, V2UnitV01, V2UnitV01]> {419 let Latency = 4;420 let NumMicroOps = 3;421}422 423def V2Write_7c_1M_1M0_1V : SchedWriteRes<[V2UnitM, V2UnitM0, V2UnitV]> {424 let Latency = 7;425 let NumMicroOps = 3;426}427 428def V2Write_2c_1L01_1S_1V : SchedWriteRes<[V2UnitL01, V2UnitS, V2UnitV]> {429 let Latency = 2;430 let NumMicroOps = 3;431}432 433def V2Write_2c_1L01_1S_1V01 : SchedWriteRes<[V2UnitL01, V2UnitS, V2UnitV01]> {434 let Latency = 2;435 let NumMicroOps = 3;436}437 438def V2Write_6c_3L : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL]> {439 let Latency = 6;440 let NumMicroOps = 3;441}442 443def V2Write_6c_3V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV]> {444 let Latency = 6;445 let NumMicroOps = 3;446}447 448def V2Write_8c_1L_2V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV]> {449 let Latency = 8;450 let NumMicroOps = 3;451}452 453//===----------------------------------------------------------------------===//454// Define generic 4 micro-op types455 456def V2Write_2c_1L01_2V01_1I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01,457 V2UnitI]> {458 let Latency = 2;459 let NumMicroOps = 4;460}461 462def V2Write_2c_2L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,463 V2UnitV01, V2UnitV01]> {464 let Latency = 2;465 let NumMicroOps = 4;466}467 468def V2Write_4c_2L01_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,469 V2UnitV01, V2UnitV01]> {470 let Latency = 4;471 let NumMicroOps = 4;472}473 474def V2Write_5c_1I_3L : SchedWriteRes<[V2UnitI, V2UnitL, V2UnitL, V2UnitL]> {475 let Latency = 5;476 let NumMicroOps = 4;477}478 479def V2Write_9c_2L_2V1 : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV1,480 V2UnitV1]> {481 let Latency = 9;482 let NumMicroOps = 4;483}484 485def V2Write_6c_4V0 : SchedWriteRes<[V2UnitV0, V2UnitV0, V2UnitV0, V2UnitV0]> {486 let Latency = 6;487 let NumMicroOps = 4;488}489 490def V2Write_8c_4V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {491 let Latency = 8;492 let NumMicroOps = 4;493}494 495def V2Write_6c_2V_2V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13,496 V2UnitV13]> {497 let Latency = 6;498 let NumMicroOps = 4;499}500 501def V2Write_8c_2V_2V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13,502 V2UnitV13]> {503 let Latency = 8;504 let NumMicroOps = 4;505}506 507def V2Write_6c_4V02 : SchedWriteRes<[V2UnitV02, V2UnitV02, V2UnitV02,508 V2UnitV02]> {509 let Latency = 6;510 let NumMicroOps = 4;511}512 513def V2Write_6c_4V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {514 let Latency = 6;515 let NumMicroOps = 4;516}517 518def V2Write_8c_2L_2V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV]> {519 let Latency = 8;520 let NumMicroOps = 4;521}522 523def V2Write_9c_2L_2V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV]> {524 let Latency = 9;525 let NumMicroOps = 4;526}527 528def V2Write_2c_2L01_2V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV,529 V2UnitV]> {530 let Latency = 2;531 let NumMicroOps = 4;532}533 534def V2Write_4c_2L01_2V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV,535 V2UnitV]> {536 let Latency = 4;537 let NumMicroOps = 4;538}539 540def V2Write_8c_2M0_2V02 : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitV02,541 V2UnitV02]> {542 let Latency = 8;543 let NumMicroOps = 4;544}545 546def V2Write_8c_2V_2V1 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV1,547 V2UnitV1]> {548 let Latency = 8;549 let NumMicroOps = 4;550}551 552def V2Write_4c_2M0_2M : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitM,553 V2UnitM]> {554 let Latency = 4;555 let NumMicroOps = 4;556}557 558def V2Write_5c_2M0_2M : SchedWriteRes<[V2UnitM0, V2UnitM0, V2UnitM,559 V2UnitM]> {560 let Latency = 5;561 let NumMicroOps = 4;562}563 564def V2Write_6c_2I_2L : SchedWriteRes<[V2UnitI, V2UnitI, V2UnitL, V2UnitL]> {565 let Latency = 6;566 let NumMicroOps = 4;567}568 569def V2Write_7c_4L : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL]> {570 let Latency = 7;571 let NumMicroOps = 4;572}573 574def V2Write_6c_1L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01,575 V2UnitV01]> {576 let Latency = 6;577 let NumMicroOps = 4;578}579 580//===----------------------------------------------------------------------===//581// Define generic 5 micro-op types582 583def V2Write_2c_1L01_2V01_2I : SchedWriteRes<[V2UnitL01, V2UnitV01, V2UnitV01,584 V2UnitI, V2UnitI]> {585 let Latency = 2;586 let NumMicroOps = 5;587}588 589def V2Write_8c_2L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV, V2UnitV,590 V2UnitV]> {591 let Latency = 8;592 let NumMicroOps = 5;593}594 595def V2Write_9c_1L_4V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV,596 V2UnitV]> {597 let Latency = 9;598 let NumMicroOps = 5;599}600 601def V2Write_10c_1L_4V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV,602 V2UnitV]> {603 let Latency = 10;604 let NumMicroOps = 5;605}606 607def V2Write_6c_5V : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV, V2UnitV,608 V2UnitV]> {609 let Latency = 6;610 let NumMicroOps = 5;611}612 613//===----------------------------------------------------------------------===//614// Define generic 6 micro-op types615 616def V2Write_8c_3L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,617 V2UnitV, V2UnitV, V2UnitV]> {618 let Latency = 8;619 let NumMicroOps = 6;620}621 622def V2Write_9c_3L_3V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,623 V2UnitV, V2UnitV, V2UnitV]> {624 let Latency = 9;625 let NumMicroOps = 6;626}627 628def V2Write_9c_2L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV,629 V2UnitV, V2UnitV, V2UnitV]> {630 let Latency = 9;631 let NumMicroOps = 6;632}633 634def V2Write_9c_2L_2V_2S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitV,635 V2UnitV, V2UnitS, V2UnitS]> {636 let Latency = 9;637 let NumMicroOps = 6;638}639 640def V2Write_9c_2V_4V13 : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV13,641 V2UnitV13, V2UnitV13, V2UnitV13]> {642 let Latency = 9;643 let NumMicroOps = 6;644}645 646def V2Write_2c_3L01_3V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,647 V2UnitV, V2UnitV, V2UnitV]> {648 let Latency = 2;649 let NumMicroOps = 6;650}651 652def V2Write_4c_2L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01,653 V2UnitV01, V2UnitV01, V2UnitV01]> {654 let Latency = 4;655 let NumMicroOps = 6;656}657 658def V2Write_5c_2L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01,659 V2UnitV01, V2UnitV01, V2UnitV01]> {660 let Latency = 5;661 let NumMicroOps = 6;662}663 664def V2Write_2c_3L01_3V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,665 V2UnitV01, V2UnitV01, V2UnitV01]> {666 let Latency = 2;667 let NumMicroOps = 6;668}669 670def V2Write_4c_2L01_2S_2V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitS,671 V2UnitS, V2UnitV01, V2UnitV01]> {672 let Latency = 4;673 let NumMicroOps = 6;674}675 676//===----------------------------------------------------------------------===//677// Define generic 7 micro-op types678 679def V2Write_8c_3L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,680 V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {681 let Latency = 8;682 let NumMicroOps = 7;683}684 685//===----------------------------------------------------------------------===//686// Define generic 8 micro-op types687 688def V2Write_2c_4L01_4V : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,689 V2UnitL01, V2UnitV, V2UnitV, V2UnitV,690 V2UnitV]> {691 let Latency = 2;692 let NumMicroOps = 8;693}694 695def V2Write_2c_4L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,696 V2UnitL01, V2UnitV01, V2UnitV01,697 V2UnitV01, V2UnitV01]> {698 let Latency = 2;699 let NumMicroOps = 8;700}701 702def V2Write_4c_4L01_4V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,703 V2UnitL01, V2UnitV01, V2UnitV01,704 V2UnitV01, V2UnitV01]> {705 let Latency = 4;706 let NumMicroOps = 8;707}708 709def V2Write_6c_2L01_6V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitV01,710 V2UnitV01, V2UnitV01, V2UnitV01,711 V2UnitV01, V2UnitV01]> {712 let Latency = 6;713 let NumMicroOps = 8;714}715 716def V2Write_8c_4L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL,717 V2UnitV, V2UnitV, V2UnitV, V2UnitV]> {718 let Latency = 8;719 let NumMicroOps = 8;720}721 722//===----------------------------------------------------------------------===//723// Define generic 9 micro-op types724 725def V2Write_6c_3L01_6V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,726 V2UnitV01, V2UnitV01, V2UnitV01,727 V2UnitV01, V2UnitV01, V2UnitV01]> {728 let Latency = 6;729 let NumMicroOps = 9;730}731 732def V2Write_10c_1L_8V : SchedWriteRes<[V2UnitL, V2UnitV, V2UnitV, V2UnitV,733 V2UnitV, V2UnitV, V2UnitV, V2UnitV,734 V2UnitV]> {735 let Latency = 10;736 let NumMicroOps = 9;737}738 739def V2Write_10c_3V_3L_3S : SchedWriteRes<[V2UnitV, V2UnitV, V2UnitV,740 V2UnitL, V2UnitL, V2UnitL,741 V2UnitS, V2UnitS, V2UnitS]> {742 let Latency = 10;743 let NumMicroOps = 9;744}745 746//===----------------------------------------------------------------------===//747// Define generic 10 micro-op types748 749def V2Write_9c_6L_4V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL, V2UnitL,750 V2UnitL, V2UnitL, V2UnitV, V2UnitV,751 V2UnitV, V2UnitV]> {752 let Latency = 9;753 let NumMicroOps = 10;754}755 756//===----------------------------------------------------------------------===//757// Define generic 12 micro-op types758 759def V2Write_5c_4L01_8V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,760 V2UnitL01, V2UnitV01, V2UnitV01,761 V2UnitV01, V2UnitV01, V2UnitV01,762 V2UnitV01, V2UnitV01, V2UnitV01]> {763 let Latency = 5;764 let NumMicroOps = 12;765}766 767def V2Write_9c_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,768 V2UnitL, V2UnitV, V2UnitV,769 V2UnitV, V2UnitV, V2UnitV,770 V2UnitV, V2UnitV, V2UnitV]> {771 let Latency = 9;772 let NumMicroOps = 12;773}774 775def V2Write_10c_4L_8V : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,776 V2UnitL, V2UnitV, V2UnitV,777 V2UnitV, V2UnitV, V2UnitV,778 V2UnitV, V2UnitV, V2UnitV]> {779 let Latency = 10;780 let NumMicroOps = 12;781}782 783//===----------------------------------------------------------------------===//784// Define generic 16 micro-op types785 786def V2Write_7c_4L01_12V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,787 V2UnitL01, V2UnitV01, V2UnitV01,788 V2UnitV01, V2UnitV01, V2UnitV01,789 V2UnitV01, V2UnitV01, V2UnitV01,790 V2UnitV01, V2UnitV01, V2UnitV01,791 V2UnitV01]> {792 let Latency = 7;793 let NumMicroOps = 16;794}795 796def V2Write_10c_4L_8V_4S : SchedWriteRes<[V2UnitL, V2UnitL, V2UnitL,797 V2UnitL, V2UnitV, V2UnitV,798 V2UnitV, V2UnitV, V2UnitV,799 V2UnitV, V2UnitV, V2UnitV,800 V2UnitS, V2UnitS, V2UnitS,801 V2UnitS]> {802 let Latency = 10;803 let NumMicroOps = 16;804}805 806//===----------------------------------------------------------------------===//807// Define generic 18 micro-op types808 809def V2Write_7c_9L01_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,810 V2UnitL01, V2UnitL01, V2UnitL01,811 V2UnitL01, V2UnitL01, V2UnitL01,812 V2UnitV01, V2UnitV01, V2UnitV01,813 V2UnitV01, V2UnitV01, V2UnitV01,814 V2UnitV01, V2UnitV01, V2UnitV01]> {815 let Latency = 7;816 let NumMicroOps = 18;817}818 819//===----------------------------------------------------------------------===//820// Define generic 27 micro-op types821 822def V2Write_7c_9L01_9S_9V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,823 V2UnitL01, V2UnitL01, V2UnitL01,824 V2UnitL01, V2UnitL01, V2UnitL01,825 V2UnitS, V2UnitS, V2UnitS,826 V2UnitS, V2UnitS, V2UnitS,827 V2UnitS, V2UnitS, V2UnitS,828 V2UnitV01, V2UnitV01, V2UnitV01,829 V2UnitV01, V2UnitV01, V2UnitV01,830 V2UnitV01, V2UnitV01,831 V2UnitV01]> {832 let Latency = 7;833 let NumMicroOps = 27;834}835 836//===----------------------------------------------------------------------===//837// Define generic 36 micro-op types838 839def V2Write_11c_18L01_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01, V2UnitL01,840 V2UnitL01, V2UnitL01, V2UnitL01,841 V2UnitL01, V2UnitL01, V2UnitL01,842 V2UnitL01, V2UnitL01, V2UnitL01,843 V2UnitL01, V2UnitL01, V2UnitL01,844 V2UnitL01, V2UnitL01, V2UnitL01,845 V2UnitV01, V2UnitV01, V2UnitV01,846 V2UnitV01, V2UnitV01, V2UnitV01,847 V2UnitV01, V2UnitV01, V2UnitV01,848 V2UnitV01, V2UnitV01, V2UnitV01,849 V2UnitV01, V2UnitV01, V2UnitV01,850 V2UnitV01, V2UnitV01,851 V2UnitV01]> {852 let Latency = 11;853 let NumMicroOps = 36;854}855 856//===----------------------------------------------------------------------===//857// Define generic 54 micro-op types858 859def V2Write_11c_18L01_18S_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,860 V2UnitL01, V2UnitL01,861 V2UnitL01, V2UnitL01,862 V2UnitL01, V2UnitL01,863 V2UnitL01, V2UnitL01,864 V2UnitL01, V2UnitL01,865 V2UnitL01, V2UnitL01,866 V2UnitL01, V2UnitL01,867 V2UnitL01, V2UnitL01,868 V2UnitS, V2UnitS, V2UnitS,869 V2UnitS, V2UnitS, V2UnitS,870 V2UnitS, V2UnitS, V2UnitS,871 V2UnitS, V2UnitS, V2UnitS,872 V2UnitS, V2UnitS, V2UnitS,873 V2UnitS, V2UnitS, V2UnitS,874 V2UnitV01, V2UnitV01,875 V2UnitV01, V2UnitV01,876 V2UnitV01, V2UnitV01,877 V2UnitV01, V2UnitV01,878 V2UnitV01, V2UnitV01,879 V2UnitV01, V2UnitV01,880 V2UnitV01, V2UnitV01,881 V2UnitV01, V2UnitV01,882 V2UnitV01, V2UnitV01]> {883 let Latency = 11;884 let NumMicroOps = 54;885}886 887//===----------------------------------------------------------------------===//888// Define predicate-controlled types889 890def V2Write_ArithI : SchedWriteVariant<[891 SchedVar<IsCheapLSL, [V2Write_1c_1I]>,892 SchedVar<NoSchedPred, [V2Write_2c_1M]>]>;893 894def V2Write_ArithF : SchedWriteVariant<[895 SchedVar<IsCheapLSL, [V2Write_1c_1F_1Flg]>,896 SchedVar<NoSchedPred, [V2Write_2c_1M_1Flg]>]>;897 898def V2Write_Logical : SchedWriteVariant<[899 SchedVar<NeoverseNoLSL, [V2Write_1c_1F_1Flg]>,900 SchedVar<NoSchedPred, [V2Write_2c_1M_1Flg]>]>;901 902def V2Write_Extr : SchedWriteVariant<[903 SchedVar<IsRORImmIdiomPred, [V2Write_1c_1I]>,904 SchedVar<NoSchedPred, [V2Write_3c_1I_1M]>]>;905 906def V2Write_LdrHQ : SchedWriteVariant<[907 SchedVar<NeoverseHQForm, [V2Write_7c_1I_1L]>,908 SchedVar<NoSchedPred, [V2Write_6c_1L]>]>;909 910def V2Write_StrHQ : SchedWriteVariant<[911 SchedVar<NeoverseHQForm, [V2Write_2c_1L01_1V01_1I]>,912 SchedVar<NoSchedPred, [V2Write_2c_1L01_1V01]>]>;913 914def V2Write_0or1c_1I : SchedWriteVariant<[915 SchedVar<NeoverseZeroMove, [V2Write_0c]>,916 SchedVar<NoSchedPred, [V2Write_1c_1I]>]>;917 918def V2Write_0or2c_1V : SchedWriteVariant<[919 SchedVar<NeoverseZeroMove, [V2Write_0c]>,920 SchedVar<NoSchedPred, [V2Write_2c_1V]>]>;921 922def V2Write_0or3c_1M0 : SchedWriteVariant<[923 SchedVar<NeoverseZeroMove, [V2Write_0c]>,924 SchedVar<NoSchedPred, [V2Write_3c_1M0]>]>;925 926def V2Write_2or3c_1M : SchedWriteVariant<[927 SchedVar<NeoversePdIsPg, [V2Write_3c_1M]>,928 SchedVar<NoSchedPred, [V2Write_2c_1M]>]>;929 930def V2Write_3or4c_2M : SchedWriteVariant<[931 SchedVar<NeoversePdIsPg, [V2Write_4c_2M]>,932 SchedVar<NoSchedPred, [V2Write_3c_2M]>]>;933 934def V2Write_1or2c_1M0 : SchedWriteVariant<[935 SchedVar<NeoversePdIsPg, [V2Write_2c_1M0]>,936 SchedVar<NoSchedPred, [V2Write_1c_1M0]>]>;937 938def V2Write_2or3c_1M0 : SchedWriteVariant<[939 SchedVar<NeoversePdIsPg, [V2Write_3c_1M0]>,940 SchedVar<NoSchedPred, [V2Write_2c_1M0]>]>;941 942def V2Write_1or2c_1M0_1M : SchedWriteVariant<[943 SchedVar<NeoversePdIsPg, [V2Write_2c_1M0_1M]>,944 SchedVar<NoSchedPred, [V2Write_1c_1M0_1M]>]>;945 946def V2Write_3or4c_1M0_1M : SchedWriteVariant<[947 SchedVar<NeoversePdIsPg, [V2Write_4c_1M0_1M]>,948 SchedVar<NoSchedPred, [V2Write_3c_1M0_1M]>]>;949 950def V2Write_4or5c_2M0_2M : SchedWriteVariant<[951 SchedVar<NeoversePdIsPg, [V2Write_5c_2M0_2M]>,952 SchedVar<NoSchedPred, [V2Write_4c_2M0_2M]>]>;953 954def V2Write_4or5c_1V0_1M0 : SchedWriteVariant<[955 SchedVar<NeoversePdIsPg, [V2Write_5c_1V0_1M0]>,956 SchedVar<NoSchedPred, [V2Write_4c_1V0_1M0]>]>;957 958def V2Write_2or3c_1V0_1M : SchedWriteVariant<[959 SchedVar<NeoversePdIsPg, [V2Write_3c_1V0_1M]>,960 SchedVar<NoSchedPred, [V2Write_2c_1V0_1M]>]>;961 962def V2Write_IncDec : SchedWriteVariant<[963 SchedVar<NeoverseCheapIncDec, [V2Write_1c_1F]>,964 SchedVar<NoSchedPred, [V2Write_2c_1M]>]>;965 966//===----------------------------------------------------------------------===//967// Define forwarded types968 969// NOTE: SOG, p. 16, n. 2: Accumulator forwarding is not supported for970// consumers of 64 bit multiply high operations?971def V2Wr_IM : SchedWriteRes<[V2UnitM]> { let Latency = 2; }972def V2Wr_IMA : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }973def V2Wr_IMUL : SchedWriteVariant<[974 SchedVar<IsReg3ZeroPred, [V2Wr_IM]>,975 SchedVar<NoSchedPred, [V2Wr_IMA]>]>;976def V2Rd_IMA : SchedReadAdvance<1, [V2Wr_IMA]>;977 978def V2Wr_FMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; }979def V2Rd_FMA : SchedReadAdvance<2, [WriteFMul, V2Wr_FMA]>;980 981def V2Wr_VA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; }982def V2Rd_VA : SchedReadAdvance<3, [V2Wr_VA]>;983 984def V2Wr_VDOT : SchedWriteRes<[V2UnitV]> { let Latency = 3; }985def V2Rd_VDOT : SchedReadAdvance<2, [V2Wr_VDOT]>;986 987def V2Wr_VMMA : SchedWriteRes<[V2UnitV]> { let Latency = 3; }988def V2Rd_VMMA : SchedReadAdvance<2, [V2Wr_VMMA]>;989 990def V2Wr_VMA : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }991def V2Rd_VMA : SchedReadAdvance<3, [V2Wr_VMA]>;992 993def V2Wr_VMAH : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 4; }994def V2Rd_VMAH : SchedReadAdvance<2, [V2Wr_VMAH]>;995 996def V2Wr_VMAL : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }997def V2Rd_VMAL : SchedReadAdvance<3, [V2Wr_VMAL]>;998 999def V2Wr_VPA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; }1000def V2Rd_VPA : SchedReadAdvance<3, [V2Wr_VPA]>;1001 1002def V2Wr_VSA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; }1003def V2Rd_VSA : SchedReadAdvance<3, [V2Wr_VSA]>;1004 1005def V2Wr_VFCMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; }1006def V2Rd_VFCMA : SchedReadAdvance<2, [V2Wr_VFCMA]>;1007 1008def V2Wr_VFM : SchedWriteRes<[V2UnitV]> { let Latency = 3; }1009def V2Wr_VFMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; }1010def V2Rd_VFMA : SchedReadAdvance<2, [V2Wr_VFM, V2Wr_VFMA]>;1011 1012def V2Wr_VFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 4; }1013def V2Rd_VFMAL : SchedReadAdvance<2, [V2Wr_VFMAL]>;1014 1015def V2Wr_VBFDOT : SchedWriteRes<[V2UnitV]> { let Latency = 5; }1016def V2Rd_VBFDOT : SchedReadAdvance<2, [V2Wr_VBFDOT]>;1017def V2Wr_VBFMMA : SchedWriteRes<[V2UnitV]> { let Latency = 6; }1018def V2Rd_VBFMMA : SchedReadAdvance<2, [V2Wr_VBFMMA]>;1019def V2Wr_VBFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 5; }1020def V2Rd_VBFMAL : SchedReadAdvance<3, [V2Wr_VBFMAL]>;1021 1022def V2Wr_CRC : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }1023def V2Rd_CRC : SchedReadAdvance<1, [V2Wr_CRC]>;1024 1025def V2Wr_ZA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; }1026def V2Rd_ZA : SchedReadAdvance<3, [V2Wr_ZA]>;1027def V2Wr_ZPA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; }1028def V2Rd_ZPA : SchedReadAdvance<3, [V2Wr_ZPA]>;1029def V2Wr_ZSA : SchedWriteRes<[V2UnitV13]> { let Latency = 4; }1030def V2Rd_ZSA : SchedReadAdvance<3, [V2Wr_ZSA]>;1031 1032def V2Wr_ZDOTB : SchedWriteRes<[V2UnitV]> { let Latency = 3; }1033def V2Rd_ZDOTB : SchedReadAdvance<2, [V2Wr_ZDOTB]>;1034def V2Wr_ZDOTH : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }1035def V2Rd_ZDOTH : SchedReadAdvance<3, [V2Wr_ZDOTH]>;1036 1037// NOTE: SOG p. 43: Complex multiply-add B, H, S element size: How to reduce1038// throughput to 1 in case of forwarding?1039def V2Wr_ZCMABHS : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }1040def V2Rd_ZCMABHS : SchedReadAdvance<3, [V2Wr_ZCMABHS]>;1041def V2Wr_ZCMAD : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 5; }1042def V2Rd_ZCMAD : SchedReadAdvance<2, [V2Wr_ZCMAD]>;1043 1044def V2Wr_ZMMA : SchedWriteRes<[V2UnitV]> { let Latency = 3; }1045def V2Rd_ZMMA : SchedReadAdvance<2, [V2Wr_ZMMA]>;1046 1047def V2Wr_ZMABHS : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 4; }1048def V2Rd_ZMABHS : SchedReadAdvance<3, [V2Wr_ZMABHS]>;1049def V2Wr_ZMAD : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 5; }1050def V2Rd_ZMAD : SchedReadAdvance<2, [V2Wr_ZMAD]>;1051 1052def V2Wr_ZMAL : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }1053def V2Rd_ZMAL : SchedReadAdvance<3, [V2Wr_ZMAL]>;1054 1055def V2Wr_ZMASQL : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }1056def V2Wr_ZMASQBHS : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }1057def V2Wr_ZMASQD : SchedWriteRes<[V2UnitV02, V2UnitV02]> { let Latency = 5; }1058def V2Rd_ZMASQ : SchedReadAdvance<2, [V2Wr_ZMASQL, V2Wr_ZMASQBHS,1059 V2Wr_ZMASQD]>;1060 1061def V2Wr_ZFCMA : SchedWriteRes<[V2UnitV]> { let Latency = 5; }1062def V2Rd_ZFCMA : SchedReadAdvance<3, [V2Wr_ZFCMA]>;1063 1064def V2Wr_ZFMA : SchedWriteRes<[V2UnitV]> { let Latency = 4; }1065def V2Rd_ZFMA : SchedReadAdvance<2, [V2Wr_ZFMA]>;1066 1067def V2Wr_ZFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 4; }1068def V2Rd_ZFMAL : SchedReadAdvance<2, [V2Wr_ZFMAL]>;1069 1070def V2Wr_ZBFDOT : SchedWriteRes<[V2UnitV]> { let Latency = 5; }1071def V2Rd_ZBFDOT : SchedReadAdvance<2, [V2Wr_ZBFDOT]>;1072def V2Wr_ZBFMMA : SchedWriteRes<[V2UnitV]> { let Latency = 6; }1073def V2Rd_ZBFMMA : SchedReadAdvance<2, [V2Wr_ZBFMMA]>;1074def V2Wr_ZBFMAL : SchedWriteRes<[V2UnitV]> { let Latency = 5; }1075def V2Rd_ZBFMAL : SchedReadAdvance<3, [V2Wr_ZBFMAL]>;1076 1077//===----------------------------------------------------------------------===//1078// Define types with long resource cycles (rc)1079 1080def V2Write_6c_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ReleaseAtCycles = [ 5]; }1081def V2Write_7c_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ReleaseAtCycles = [ 7]; }1082def V2Write_10c_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 5]; }1083def V2Write_10c_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }1084def V2Write_10c_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [10]; }1085def V2Write_10c_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }1086def V2Write_13c_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [12]; }1087def V2Write_13c_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [13]; }1088def V2Write_15c_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ReleaseAtCycles = [14]; }1089def V2Write_16c_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [14]; }1090def V2Write_16c_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [15]; }1091 1092// Miscellaneous1093// -----------------------------------------------------------------------------1094 1095def : InstRW<[WriteI], (instrs COPY)>;1096 1097// §3.3 Branch instructions1098// -----------------------------------------------------------------------------1099 1100// Branch, immed1101// Compare and branch1102def : SchedAlias<WriteBr, V2Write_1c_1B>;1103 1104// Branch, register1105def : SchedAlias<WriteBrReg, V2Write_1c_1B>;1106 1107// Branch and link, immed1108// Branch and link, register1109def : InstRW<[V2Write_1c_1B_1R], (instrs BL, BLR)>;1110 1111// §3.4 Arithmetic and Logical Instructions1112// -----------------------------------------------------------------------------1113 1114// ALU, basic1115def : SchedAlias<WriteI, V2Write_1c_1I>;1116 1117// ALU, basic, flagset1118def : InstRW<[V2Write_1c_1F_1Flg],1119 (instregex "^(ADD|SUB)S[WX]r[ir]$",1120 "^(ADC|SBC)S[WX]r$",1121 "^ANDS[WX]ri$",1122 "^(AND|BIC)S[WX]rr$")>;1123def : InstRW<[V2Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>;1124 1125// ALU, extend and shift1126def : SchedAlias<WriteIEReg, V2Write_2c_1M>;1127 1128// Arithmetic, LSL shift, shift <= 41129// Arithmetic, flagset, LSL shift, shift <= 41130// Arithmetic, LSR/ASR/ROR shift or LSL shift > 41131def : SchedAlias<WriteISReg, V2Write_ArithI>;1132def : InstRW<[V2Write_ArithF],1133 (instregex "^(ADD|SUB)S[WX]rs$")>;1134 1135// Arithmetic, immediate to logical address tag1136def : InstRW<[V2Write_2c_1M], (instrs ADDG, SUBG)>;1137 1138// Conditional compare1139def : InstRW<[V2Write_1c_1F_1Flg], (instregex "^CCM[NP][WX][ir]")>;1140 1141// Convert floating-point condition flags1142// Flag manipulation instructions1143def : WriteRes<WriteSys, []> { let Latency = 1; }1144 1145// Insert Random Tags1146def : InstRW<[V2Write_2c_1M], (instrs IRG, IRGstack)>;1147 1148// Insert Tag Mask1149// Subtract Pointer1150def : InstRW<[V2Write_1c_1I], (instrs GMI, SUBP)>;1151 1152// Subtract Pointer, flagset1153def : InstRW<[V2Write_1c_1F_1Flg], (instrs SUBPS)>;1154 1155// Logical, shift, no flagset1156def : InstRW<[V2Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;1157def : InstRW<[V2Write_0or1c_1I], (instregex "^ORR[WX]rs$")>;1158 1159// Logical, shift, flagset1160def : InstRW<[V2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;1161 1162// Move and shift instructions1163// -----------------------------------------------------------------------------1164 1165def : SchedAlias<WriteImm, V2Write_1c_1I>;1166 1167// §3.5 Divide and multiply instructions1168// -----------------------------------------------------------------------------1169 1170// SDIV, UDIV1171def : SchedAlias<WriteID32, V2Write_12c_1M0>;1172def : SchedAlias<WriteID64, V2Write_20c_1M0>;1173 1174def : SchedAlias<WriteIM32, V2Write_2c_1M>;1175def : SchedAlias<WriteIM64, V2Write_2c_1M>;1176 1177// Multiply1178// Multiply accumulate, W-form1179// Multiply accumulate, X-form1180def : InstRW<[V2Wr_IMUL, ReadIM, ReadIM, V2Rd_IMA],1181 (instregex "^M(ADD|SUB)[WX]rrr$")>;1182 1183// Multiply accumulate long1184// Multiply long1185def : InstRW<[V2Wr_IMUL, ReadIM, ReadIM, V2Rd_IMA],1186 (instregex "^(S|U)M(ADD|SUB)Lrrr$")>;1187 1188// Multiply high1189def : InstRW<[V2Write_3c_1M], (instrs SMULHrr, UMULHrr)>;1190 1191// Pointer Authentication Instructions (v8.3 PAC)1192// -----------------------------------------------------------------------------1193 1194// Authenticate data address1195// Authenticate instruction address1196// Compute pointer authentication code for data address1197// Compute pointer authentication code, using generic key1198// Compute pointer authentication code for instruction address1199def : InstRW<[V2Write_5c_1M0], (instregex "^AUT", "^PAC")>;1200 1201// Branch and link, register, with pointer authentication1202// Branch, register, with pointer authentication1203// Branch, return, with pointer authentication1204def : InstRW<[V2Write_6c_1M0_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA,1205 BRAAZ, BRAB, BRABZ, RETAA, RETAB,1206 ERETAA, ERETAB)>;1207 1208 1209// Load register, with pointer authentication1210def : InstRW<[V2Write_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;1211 1212// Strip pointer authentication code1213def : InstRW<[V2Write_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;1214 1215// Miscellaneous data-processing instructions1216// -----------------------------------------------------------------------------1217 1218// Address generation1219def : InstRW<[V2Write_1c_1F], (instrs ADR, ADRP)>;1220 1221// Bitfield extract, one reg1222// Bitfield extract, two regs1223def : SchedAlias<WriteExtr, V2Write_Extr>;1224def : InstRW<[V2Write_Extr], (instrs EXTRWrri, EXTRXrri)>;1225 1226// Bitfield move, basic1227def : SchedAlias<WriteIS, V2Write_1c_1I>;1228 1229// Bitfield move, insert1230def : InstRW<[V2Write_2c_1M], (instregex "^BFM[WX]ri$")>;1231 1232// Load instructions1233// -----------------------------------------------------------------------------1234 1235// NOTE: SOG p. 19: Throughput of LDN?P X-form should be 2, but reported as 3.1236 1237def : SchedAlias<WriteLD, V2Write_4c_1L>;1238def : SchedAlias<WriteLDIdx, V2Write_4c_1L>;1239 1240// Load register, literal1241def : InstRW<[V2Write_5c_1L_1F], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>;1242 1243// Load pair, signed immed offset, signed words1244def : InstRW<[V2Write_5c_1I_3L, WriteLDHi], (instrs LDPSWi)>;1245 1246// Load pair, immed post-index or immed pre-index, signed words1247def : InstRW<[WriteAdr, V2Write_5c_1I_3L, WriteLDHi],1248 (instregex "^LDPSW(post|pre)$")>;1249 1250// Store instructions1251// -----------------------------------------------------------------------------1252 1253// NOTE: SOG, p. 20: Unsure if STRH uses pipeline I.1254 1255def : SchedAlias<WriteST, V2Write_1c_1L01_1D>;1256def : SchedAlias<WriteSTIdx, V2Write_1c_1L01_1D>;1257def : SchedAlias<WriteSTP, V2Write_1c_1L01_1D>;1258def : SchedAlias<WriteAdr, V2Write_1c_1I>;1259 1260// Tag load instructions1261// -----------------------------------------------------------------------------1262 1263// Load allocation tag1264// Load multiple allocation tags1265def : InstRW<[V2Write_4c_1L], (instrs LDG, LDGM)>;1266 1267// Tag store instructions1268// -----------------------------------------------------------------------------1269 1270// Store allocation tags to one or two granules, post-index1271// Store allocation tags to one or two granules, pre-index1272// Store allocation tag to one or two granules, zeroing, post-index1273// Store Allocation Tag to one or two granules, zeroing, pre-index1274// Store allocation tag and reg pair to memory, post-Index1275// Store allocation tag and reg pair to memory, pre-Index1276def : InstRW<[V2Write_1c_1L01_1D_1I], (instrs STGPreIndex, STGPostIndex,1277 ST2GPreIndex, ST2GPostIndex,1278 STZGPreIndex, STZGPostIndex,1279 STZ2GPreIndex, STZ2GPostIndex,1280 STGPpre, STGPpost)>;1281 1282// Store allocation tags to one or two granules, signed offset1283// Store allocation tag to two granules, zeroing, signed offset1284// Store allocation tag and reg pair to memory, signed offset1285// Store multiple allocation tags1286def : InstRW<[V2Write_1c_1L01_1D], (instrs STGi, ST2Gi, STZGi,1287 STZ2Gi, STGPi, STGM, STZGM)>;1288 1289// FP data processing instructions1290// -----------------------------------------------------------------------------1291 1292// FP absolute value1293// FP arithmetic1294// FP min/max1295// FP negate1296// FP select1297def : SchedAlias<WriteF, V2Write_2c_1V>;1298 1299// FP compare1300def : SchedAlias<WriteFCmp, V2Write_2c_1V0>;1301 1302// FP divide, square root1303def : SchedAlias<WriteFDiv, V2Write_7c_1V02>;1304 1305// FP divide, H-form1306def : InstRW<[V2Write_7c_1V02], (instrs FDIVHrr)>;1307// FP divide, S-form1308def : InstRW<[V2Write_10c_1V02], (instrs FDIVSrr)>;1309// FP divide, D-form1310def : InstRW<[V2Write_15c_1V02], (instrs FDIVDrr)>;1311 1312// FP square root, H-form1313def : InstRW<[V2Write_7c_1V02], (instrs FSQRTHr)>;1314// FP square root, S-form1315def : InstRW<[V2Write_9c_1V02], (instrs FSQRTSr)>;1316// FP square root, D-form1317def : InstRW<[V2Write_16c_1V02], (instrs FSQRTDr)>;1318 1319// FP multiply1320def : WriteRes<WriteFMul, [V2UnitV]> { let Latency = 3; }1321 1322// FP multiply accumulate1323def : InstRW<[V2Wr_FMA, ReadDefault, ReadDefault, V2Rd_FMA],1324 (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;1325 1326// FP round to integral1327def : InstRW<[V2Write_3c_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$",1328 "^FRINT(32|64)[XZ][SD]r$")>;1329 1330// FP miscellaneous instructions1331// -----------------------------------------------------------------------------1332 1333// FP convert, from gen to vec reg1334def : InstRW<[V2Write_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;1335 1336// FP convert, from vec to gen reg1337def : InstRW<[V2Write_3c_1V01],1338 (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]ri?$")>;1339 1340// FP convert, Javascript from vec to gen reg1341def : SchedAlias<WriteFCvt, V2Write_3c_1V0>;1342 1343// FP convert, from vec to vec reg1344def : InstRW<[V2Write_3c_1V02], (instrs FCVTSHr, FCVTDHr, FCVTHSr, FCVTDSr,1345 FCVTHDr, FCVTSDr, FCVTXNv1i64)>;1346 1347// FP move, immed1348// FP move, register1349def : SchedAlias<WriteFImm, V2Write_2c_1V>;1350 1351// FP transfer, from gen to low half of vec reg1352def : InstRW<[V2Write_0or3c_1M0],1353 (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;1354 1355// FP transfer, from gen to high half of vec reg1356def : InstRW<[V2Write_5c_1M0_1V], (instrs FMOVXDHighr)>;1357 1358// FP transfer, from vec to gen reg1359def : SchedAlias<WriteFCopy, V2Write_2c_2V01>;1360 1361// FP load instructions1362// -----------------------------------------------------------------------------1363 1364// Load vector reg, literal, S/D/Q forms1365def : InstRW<[V2Write_7c_1F_1L], (instregex "^LDR[SDQ]l$")>;1366 1367// Load vector reg, unscaled immed1368def : InstRW<[V2Write_6c_1L], (instregex "^LDUR[BHSDQ]i$")>;1369 1370// Load vector reg, immed post-index1371// Load vector reg, immed pre-index1372def : InstRW<[WriteAdr, V2Write_6c_1I_1L],1373 (instregex "^LDR[BHSDQ](pre|post)$")>;1374 1375// Load vector reg, unsigned immed1376def : InstRW<[V2Write_6c_1L], (instregex "^LDR[BHSDQ]ui$")>;1377 1378// Load vector reg, register offset, basic1379// Load vector reg, register offset, scale, S/D-form1380// Load vector reg, register offset, scale, H/Q-form1381// Load vector reg, register offset, extend1382// Load vector reg, register offset, extend, scale, S/D-form1383// Load vector reg, register offset, extend, scale, H/Q-form1384def : InstRW<[V2Write_LdrHQ, ReadAdrBase], (instregex "^LDR[BHSDQ]ro[WX]$")>;1385 1386// Load vector pair, immed offset, S/D-form1387def : InstRW<[V2Write_6c_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>;1388 1389// Load vector pair, immed offset, Q-form1390def : InstRW<[V2Write_6c_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;1391 1392// Load vector pair, immed post-index, S/D-form1393// Load vector pair, immed pre-index, S/D-form1394def : InstRW<[WriteAdr, V2Write_6c_1I_1L, WriteLDHi],1395 (instregex "^LDP[SD](pre|post)$")>;1396 1397// Load vector pair, immed post-index, Q-form1398// Load vector pair, immed pre-index, Q-form1399def : InstRW<[WriteAdr, V2Write_6c_2I_2L, WriteLDHi], (instrs LDPQpost,1400 LDPQpre)>;1401 1402// FP store instructions1403// -----------------------------------------------------------------------------1404 1405// Store vector reg, unscaled immed, B/H/S/D-form1406// Store vector reg, unscaled immed, Q-form1407def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^STUR[BHSDQ]i$")>;1408 1409// Store vector reg, immed post-index, B/H/S/D-form1410// Store vector reg, immed post-index, Q-form1411// Store vector reg, immed pre-index, B/H/S/D-form1412// Store vector reg, immed pre-index, Q-form1413def : InstRW<[WriteAdr, V2Write_2c_1L01_1V01_1I],1414 (instregex "^STR[BHSDQ](pre|post)$")>;1415 1416// Store vector reg, unsigned immed, B/H/S/D-form1417// Store vector reg, unsigned immed, Q-form1418def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^STR[BHSDQ]ui$")>;1419 1420// Store vector reg, register offset, basic, B/H/S/D-form1421// Store vector reg, register offset, basic, Q-form1422// Store vector reg, register offset, scale, H-form1423// Store vector reg, register offset, scale, S/D-form1424// Store vector reg, register offset, scale, Q-form1425// Store vector reg, register offset, extend, B/H/S/D-form1426// Store vector reg, register offset, extend, Q-form1427// Store vector reg, register offset, extend, scale, H-form1428// Store vector reg, register offset, extend, scale, S/D-form1429// Store vector reg, register offset, extend, scale, Q-form1430def : InstRW<[V2Write_StrHQ, ReadAdrBase],1431 (instregex "^STR[BHSDQ]ro[WX]$")>;1432 1433// Store vector pair, immed offset, S-form1434// Store vector pair, immed offset, D-form1435def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^STN?P[SD]i$")>;1436 1437// Store vector pair, immed offset, Q-form1438def : InstRW<[V2Write_2c_1L01_2V01], (instrs STPQi, STNPQi)>;1439 1440// Store vector pair, immed post-index, S-form1441// Store vector pair, immed post-index, D-form1442// Store vector pair, immed pre-index, S-form1443// Store vector pair, immed pre-index, D-form1444def : InstRW<[WriteAdr, V2Write_2c_1L01_1V01_1I],1445 (instregex "^STP[SD](pre|post)$")>;1446 1447// Store vector pair, immed post-index, Q-form1448def : InstRW<[V2Write_2c_1L01_2V01_1I], (instrs STPQpost)>;1449 1450// Store vector pair, immed pre-index, Q-form1451def : InstRW<[V2Write_2c_1L01_2V01_2I], (instrs STPQpre)>;1452 1453// ASIMD integer instructions1454// -----------------------------------------------------------------------------1455 1456// ASIMD absolute diff1457// ASIMD absolute diff long1458// ASIMD arith, basic1459// ASIMD arith, complex1460// ASIMD arith, pair-wise1461// ASIMD compare1462// ASIMD logical1463// ASIMD max/min, basic and pair-wise1464def : SchedAlias<WriteVd, V2Write_2c_1V>;1465def : SchedAlias<WriteVq, V2Write_2c_1V>;1466 1467// ASIMD absolute diff accum1468// ASIMD absolute diff accum long1469def : InstRW<[V2Wr_VA, V2Rd_VA], (instregex "^[SU]ABAL?v")>;1470 1471// ASIMD arith, reduce, 4H/4S1472def : InstRW<[V2Write_3c_1V13], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>;1473 1474// ASIMD arith, reduce, 8B/8H1475def : InstRW<[V2Write_5c_1V13_1V],1476 (instregex "^(ADDV|[SU]ADDLV)v8(i8|i16)v$")>;1477 1478// ASIMD arith, reduce, 16B1479def : InstRW<[V2Write_6c_2V13], (instregex "^(ADDV|[SU]ADDLV)v16i8v$")>;1480 1481// ASIMD dot product1482// ASIMD dot product using signed and unsigned integers1483def : InstRW<[V2Wr_VDOT, V2Rd_VDOT],1484 (instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>;1485 1486// ASIMD matrix multiply-accumulate1487def : InstRW<[V2Wr_VMMA, V2Rd_VMMA], (instrs SMMLA, UMMLA, USMMLA)>;1488 1489// ASIMD max/min, reduce, 4H/4S1490def : InstRW<[V2Write_3c_1V13], (instregex "^[SU](MAX|MIN)Vv4i16v$",1491 "^[SU](MAX|MIN)Vv4i32v$")>;1492 1493// ASIMD max/min, reduce, 8B/8H1494def : InstRW<[V2Write_5c_1V13_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$",1495 "^[SU](MAX|MIN)Vv8i16v$")>;1496 1497// ASIMD max/min, reduce, 16B1498def : InstRW<[V2Write_6c_2V13], (instregex "[SU](MAX|MIN)Vv16i8v$")>;1499 1500// ASIMD multiply1501def : InstRW<[V2Write_4c_1V02], (instregex "^MULv", "^SQ(R)?DMULHv")>;1502 1503// ASIMD multiply accumulate1504def : InstRW<[V2Wr_VMA, V2Rd_VMA], (instregex "^MLAv", "^MLSv")>;1505 1506// ASIMD multiply accumulate high1507def : InstRW<[V2Wr_VMAH, V2Rd_VMAH], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;1508 1509// ASIMD multiply accumulate long1510def : InstRW<[V2Wr_VMAL, V2Rd_VMAL], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;1511 1512// ASIMD multiply accumulate saturating long1513def : InstRW<[V2Write_4c_1V02], (instregex "^SQDML[AS]L[iv]")>;1514 1515// ASIMD multiply/multiply long (8x8) polynomial, D-form1516// ASIMD multiply/multiply long (8x8) polynomial, Q-form1517def : InstRW<[V2Write_3c_1V23], (instregex "^PMULL?(v8i8|v16i8)$")>;1518 1519// ASIMD multiply long1520def : InstRW<[V2Write_3c_1V02], (instregex "^[SU]MULLv", "^SQDMULL[iv]")>;1521 1522// ASIMD pairwise add and accumulate long1523def : InstRW<[V2Wr_VPA, V2Rd_VPA], (instregex "^[SU]ADALPv")>;1524 1525// ASIMD shift accumulate1526def : InstRW<[V2Wr_VSA, V2Rd_VSA], (instregex "^[SU]SRA[dv]", "^[SU]RSRA[dv]")>;1527 1528// ASIMD shift by immed, basic1529def : InstRW<[V2Write_2c_1V13], (instregex "^SHL[dv]", "^SHLLv", "^SHRNv",1530 "^SSHLLv", "^SSHR[dv]", "^USHLLv",1531 "^USHR[dv]")>;1532 1533// ASIMD shift by immed and insert, basic1534def : InstRW<[V2Write_2c_1V13], (instregex "^SLI[dv]", "^SRI[dv]")>;1535 1536// ASIMD shift by immed, complex1537def : InstRW<[V2Write_4c_1V13],1538 (instregex "^RSHRNv", "^SQRSHRU?N[bhsv]", "^(SQSHLU?|UQSHL)[bhsd]$",1539 "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",1540 "^SQSHRU?N[bhsv]", "^SRSHR[dv]", "^UQRSHRN[bhsv]",1541 "^UQSHRN[bhsv]", "^URSHR[dv]")>;1542 1543// ASIMD shift by register, basic1544def : InstRW<[V2Write_2c_1V13], (instregex "^[SU]SHLv")>;1545 1546// ASIMD shift by register, complex1547def : InstRW<[V2Write_4c_1V13],1548 (instregex "^[SU]RSHLv", "^[SU]QRSHLv",1549 "^[SU]QSHL(v1i8|v1i16|v1i32|v1i64|v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)$")>;1550 1551// ASIMD floating-point instructions1552// -----------------------------------------------------------------------------1553 1554// ASIMD FP absolute value/difference1555// ASIMD FP arith, normal1556// ASIMD FP compare1557// ASIMD FP complex add1558// ASIMD FP max/min, normal1559// ASIMD FP max/min, pairwise1560// ASIMD FP negate1561// Handled by SchedAlias<WriteV[dq], ...>1562 1563// ASIMD FP complex multiply add1564def : InstRW<[V2Wr_VFCMA, V2Rd_VFCMA], (instregex "^FCMLAv")>;1565 1566// ASIMD FP convert, long (F16 to F32)1567def : InstRW<[V2Write_4c_2V02], (instregex "^FCVTL(v4|v8)i16")>;1568 1569// ASIMD FP convert, long (F32 to F64)1570def : InstRW<[V2Write_3c_1V02], (instregex "^FCVTL(v2|v4)i32")>;1571 1572// ASIMD FP convert, narrow (F32 to F16)1573def : InstRW<[V2Write_4c_2V02], (instregex "^FCVTN(v4|v8)i16")>;1574 1575// ASIMD FP convert, narrow (F64 to F32)1576def : InstRW<[V2Write_3c_1V02], (instregex "^FCVTN(v2|v4)i32",1577 "^FCVTXN(v2|v4)f32")>;1578 1579// ASIMD FP convert, other, D-form F32 and Q-form F641580def : InstRW<[V2Write_3c_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$",1581 "^FCVT[AMNPZ][SU]v2i(32|64)_shift$",1582 "^FCVT[AMNPZ][SU]v1i64$",1583 "^FCVTZ[SU]d$",1584 "^[SU]CVTFv2f(32|64)$",1585 "^[SU]CVTFv2i(32|64)_shift$",1586 "^[SU]CVTFv1i64$",1587 "^[SU]CVTFd$")>;1588 1589// ASIMD FP convert, other, D-form F16 and Q-form F321590def : InstRW<[V2Write_4c_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$",1591 "^FCVT[AMNPZ][SU]v4i(16|32)_shift$",1592 "^FCVT[AMNPZ][SU]v1i32$",1593 "^FCVTZ[SU]s$",1594 "^[SU]CVTFv4f(16|32)$",1595 "^[SU]CVTFv4i(16|32)_shift$",1596 "^[SU]CVTFv1i32$",1597 "^[SU]CVTFs$")>;1598 1599// ASIMD FP convert, other, Q-form F161600def : InstRW<[V2Write_6c_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$",1601 "^FCVT[AMNPZ][SU]v8i16_shift$",1602 "^FCVT[AMNPZ][SU]v1f16$",1603 "^FCVTZ[SU]h$",1604 "^[SU]CVTFv8f16$",1605 "^[SU]CVTFv8i16_shift$",1606 "^[SU]CVTFv1i16$",1607 "^[SU]CVTFh$")>;1608 1609// ASIMD FP divide, D-form, F161610def : InstRW<[V2Write_7c_1V02_7rc], (instrs FDIVv4f16)>;1611 1612// ASIMD FP divide, D-form, F321613def : InstRW<[V2Write_10c_1V02_5rc], (instrs FDIVv2f32)>;1614 1615// ASIMD FP divide, Q-form, F161616def : InstRW<[V2Write_13c_1V02_13rc], (instrs FDIVv8f16)>;1617 1618// ASIMD FP divide, Q-form, F321619def : InstRW<[V2Write_10c_1V02_10rc], (instrs FDIVv4f32)>;1620 1621// ASIMD FP divide, Q-form, F641622def : InstRW<[V2Write_15c_1V02_14rc], (instrs FDIVv2f64)>;1623 1624// ASIMD FP max/min, reduce, F32 and D-form F161625def : InstRW<[V2Write_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;1626 1627// ASIMD FP max/min, reduce, Q-form F161628def : InstRW<[V2Write_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;1629 1630// ASIMD FP multiply1631def : InstRW<[V2Wr_VFM], (instregex "^FMULv", "^FMULXv")>;1632 1633// ASIMD FP multiply accumulate1634def : InstRW<[V2Wr_VFMA, V2Rd_VFMA], (instregex "^FMLAv", "^FMLSv")>;1635 1636// ASIMD FP multiply accumulate long1637def : InstRW<[V2Wr_VFMAL, V2Rd_VFMAL], (instregex "^FML[AS]L2?(lane)?v")>;1638 1639// ASIMD FP round, D-form F32 and Q-form F641640def : InstRW<[V2Write_3c_1V02],1641 (instregex "^FRINT[AIMNPXZ]v2f(32|64)$",1642 "^FRINT(32|64)[XZ]v2f(32|64)$")>;1643 1644// ASIMD FP round, D-form F16 and Q-form F321645def : InstRW<[V2Write_4c_2V02],1646 (instregex "^FRINT[AIMNPXZ]v4f(16|32)$",1647 "^FRINT(32|64)[XZ]v4f32$")>;1648 1649// ASIMD FP round, Q-form F161650def : InstRW<[V2Write_6c_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>;1651 1652// ASIMD FP square root, D-form, F161653def : InstRW<[V2Write_7c_1V02_7rc], (instrs FSQRTv4f16)>;1654 1655// ASIMD FP square root, D-form, F321656def : InstRW<[V2Write_10c_1V02_5rc], (instrs FSQRTv2f32)>;1657 1658// ASIMD FP square root, Q-form, F161659def : InstRW<[V2Write_13c_1V02_13rc], (instrs FSQRTv8f16)>;1660 1661// ASIMD FP square root, Q-form, F321662def : InstRW<[V2Write_10c_1V02_9rc], (instrs FSQRTv4f32)>;1663 1664// ASIMD FP square root, Q-form, F641665def : InstRW<[V2Write_16c_1V02_15rc], (instrs FSQRTv2f64)>;1666 1667// ASIMD BFloat16 (BF16) instructions1668// -----------------------------------------------------------------------------1669 1670// ASIMD convert, F32 to BF161671def : InstRW<[V2Write_4c_2V02], (instrs BFCVTN, BFCVTN2)>;1672 1673// ASIMD dot product1674def : InstRW<[V2Wr_VBFDOT, V2Rd_VBFDOT], (instrs BFDOTv4bf16, BFDOTv8bf16)>;1675 1676// ASIMD matrix multiply accumulate1677def : InstRW<[V2Wr_VBFMMA, V2Rd_VBFMMA], (instrs BFMMLA)>;1678 1679// ASIMD multiply accumulate long1680def : InstRW<[V2Wr_VBFMAL, V2Rd_VBFMAL], (instrs BFMLALB, BFMLALBIdx, BFMLALT,1681 BFMLALTIdx)>;1682 1683// Scalar convert, F32 to BF161684def : InstRW<[V2Write_3c_1V02], (instrs BFCVT)>;1685 1686// ASIMD miscellaneous instructions1687// -----------------------------------------------------------------------------1688 1689// ASIMD bit reverse1690// ASIMD bitwise insert1691// ASIMD count1692// ASIMD duplicate, element1693// ASIMD extract1694// ASIMD extract narrow1695// ASIMD insert, element to element1696// ASIMD move, FP immed1697// ASIMD move, integer immed1698// ASIMD reverse1699// ASIMD table lookup extension, 1 table reg1700// ASIMD transpose1701// ASIMD unzip/zip1702// Handled by SchedAlias<WriteV[dq], ...>1703def : InstRW<[V2Write_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>;1704 1705// ASIMD duplicate, gen reg1706def : InstRW<[V2Write_3c_1M0], (instregex "^DUPv.+gpr")>;1707 1708// ASIMD extract narrow, saturating1709def : InstRW<[V2Write_4c_1V13], (instregex "^[SU]QXTNv", "^SQXTUNv")>;1710 1711// ASIMD reciprocal and square root estimate, D-form U321712def : InstRW<[V2Write_3c_1V02], (instrs URECPEv2i32, URSQRTEv2i32)>;1713 1714// ASIMD reciprocal and square root estimate, Q-form U321715def : InstRW<[V2Write_4c_2V02], (instrs URECPEv4i32, URSQRTEv4i32)>;1716 1717// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms1718def : InstRW<[V2Write_3c_1V02], (instrs FRECPEv1f16, FRECPEv1i32,1719 FRECPEv1i64, FRECPEv2f32,1720 FRSQRTEv1f16, FRSQRTEv1i32,1721 FRSQRTEv1i64, FRSQRTEv2f32)>;1722 1723// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F321724def : InstRW<[V2Write_4c_2V02], (instrs FRECPEv4f16, FRECPEv4f32,1725 FRSQRTEv4f16, FRSQRTEv4f32)>;1726 1727// ASIMD reciprocal and square root estimate, Q-form F161728def : InstRW<[V2Write_6c_4V02], (instrs FRECPEv8f16, FRSQRTEv8f16)>;1729 1730// ASIMD reciprocal exponent1731def : InstRW<[V2Write_3c_1V02], (instregex "^FRECPXv")>;1732 1733// ASIMD reciprocal step1734def : InstRW<[V2Write_4c_1V], (instregex "^FRECPS(32|64|v)",1735 "^FRSQRTS(32|64|v)")>;1736 1737// ASIMD table lookup, 1 or 2 table regs1738def : InstRW<[V2Write_2c_1V01], (instrs TBLv8i8One, TBLv16i8One,1739 TBLv8i8Two, TBLv16i8Two)>;1740 1741// ASIMD table lookup, 3 table regs1742def : InstRW<[V2Write_4c_2V01], (instrs TBLv8i8Three, TBLv16i8Three)>;1743 1744// ASIMD table lookup, 4 table regs1745def : InstRW<[V2Write_4c_3V01], (instrs TBLv8i8Four, TBLv16i8Four)>;1746 1747// ASIMD table lookup extension, 2 table reg1748def : InstRW<[V2Write_4c_2V], (instrs TBXv8i8Two, TBXv16i8Two)>;1749 1750// ASIMD table lookup extension, 3 table reg1751def : InstRW<[V2Write_6c_3V], (instrs TBXv8i8Three, TBXv16i8Three)>;1752 1753// ASIMD table lookup extension, 4 table reg1754def : InstRW<[V2Write_6c_5V], (instrs TBXv8i8Four, TBXv16i8Four)>;1755 1756// ASIMD transfer, element to gen reg1757def : InstRW<[V2Write_2c_2V01], (instregex "^[SU]MOVv")>;1758 1759// ASIMD transfer, gen reg to element1760def : InstRW<[V2Write_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;1761 1762// ASIMD load instructions1763// -----------------------------------------------------------------------------1764 1765// ASIMD load, 1 element, multiple, 1 reg, D-form1766def : InstRW<[V2Write_6c_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;1767def : InstRW<[WriteAdr, V2Write_6c_1L],1768 (instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>;1769 1770// ASIMD load, 1 element, multiple, 1 reg, Q-form1771def : InstRW<[V2Write_6c_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;1772def : InstRW<[WriteAdr, V2Write_6c_1L],1773 (instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>;1774 1775// ASIMD load, 1 element, multiple, 2 reg, D-form1776def : InstRW<[V2Write_6c_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;1777def : InstRW<[WriteAdr, V2Write_6c_2L],1778 (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;1779 1780// ASIMD load, 1 element, multiple, 2 reg, Q-form1781def : InstRW<[V2Write_6c_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;1782def : InstRW<[WriteAdr, V2Write_6c_2L],1783 (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;1784 1785// ASIMD load, 1 element, multiple, 3 reg, D-form1786def : InstRW<[V2Write_6c_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;1787def : InstRW<[WriteAdr, V2Write_6c_3L],1788 (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;1789 1790// ASIMD load, 1 element, multiple, 3 reg, Q-form1791def : InstRW<[V2Write_6c_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;1792def : InstRW<[WriteAdr, V2Write_6c_3L],1793 (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;1794 1795// ASIMD load, 1 element, multiple, 4 reg, D-form1796def : InstRW<[V2Write_7c_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;1797def : InstRW<[WriteAdr, V2Write_7c_4L],1798 (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;1799 1800// ASIMD load, 1 element, multiple, 4 reg, Q-form1801def : InstRW<[V2Write_7c_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;1802def : InstRW<[WriteAdr, V2Write_7c_4L],1803 (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;1804 1805// ASIMD load, 1 element, one lane, B/H/S1806// ASIMD load, 1 element, one lane, D1807def : InstRW<[V2Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)$")>;1808def : InstRW<[WriteAdr, V2Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;1809 1810// ASIMD load, 1 element, all lanes, D-form, B/H/S1811// ASIMD load, 1 element, all lanes, D-form, D1812def : InstRW<[V2Write_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;1813def : InstRW<[WriteAdr, V2Write_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;1814 1815// ASIMD load, 1 element, all lanes, Q-form1816def : InstRW<[V2Write_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;1817def : InstRW<[WriteAdr, V2Write_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;1818 1819// ASIMD load, 2 element, multiple, D-form, B/H/S1820def : InstRW<[V2Write_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;1821def : InstRW<[WriteAdr, V2Write_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;1822 1823// ASIMD load, 2 element, multiple, Q-form, B/H/S1824// ASIMD load, 2 element, multiple, Q-form, D1825def : InstRW<[V2Write_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;1826def : InstRW<[WriteAdr, V2Write_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;1827 1828// ASIMD load, 2 element, one lane, B/H1829// ASIMD load, 2 element, one lane, S1830// ASIMD load, 2 element, one lane, D1831def : InstRW<[V2Write_8c_1L_2V], (instregex "LD2i(8|16|32|64)$")>;1832def : InstRW<[WriteAdr, V2Write_8c_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;1833 1834// ASIMD load, 2 element, all lanes, D-form, B/H/S1835// ASIMD load, 2 element, all lanes, D-form, D1836def : InstRW<[V2Write_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;1837def : InstRW<[WriteAdr, V2Write_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;1838 1839// ASIMD load, 2 element, all lanes, Q-form1840def : InstRW<[V2Write_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;1841def : InstRW<[WriteAdr, V2Write_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;1842 1843// ASIMD load, 3 element, multiple, D-form, B/H/S1844def : InstRW<[V2Write_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;1845def : InstRW<[WriteAdr, V2Write_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;1846 1847// ASIMD load, 3 element, multiple, Q-form, B/H/S1848// ASIMD load, 3 element, multiple, Q-form, D1849def : InstRW<[V2Write_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)$")>;1850def : InstRW<[WriteAdr, V2Write_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;1851 1852// ASIMD load, 3 element, one lane, B/H1853// ASIMD load, 3 element, one lane, S1854// ASIMD load, 3 element, one lane, D1855def : InstRW<[V2Write_8c_2L_3V], (instregex "LD3i(8|16|32|64)$")>;1856def : InstRW<[WriteAdr, V2Write_8c_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;1857 1858// ASIMD load, 3 element, all lanes, D-form, B/H/S1859// ASIMD load, 3 element, all lanes, D-form, D1860def : InstRW<[V2Write_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;1861def : InstRW<[WriteAdr, V2Write_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;1862 1863// ASIMD load, 3 element, all lanes, Q-form, B/H/S1864// ASIMD load, 3 element, all lanes, Q-form, D1865def : InstRW<[V2Write_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;1866def : InstRW<[WriteAdr, V2Write_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;1867 1868// ASIMD load, 4 element, multiple, D-form, B/H/S1869def : InstRW<[V2Write_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;1870def : InstRW<[WriteAdr, V2Write_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;1871 1872// ASIMD load, 4 element, multiple, Q-form, B/H/S1873// ASIMD load, 4 element, multiple, Q-form, D1874def : InstRW<[V2Write_9c_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;1875def : InstRW<[WriteAdr, V2Write_9c_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;1876 1877// ASIMD load, 4 element, one lane, B/H1878// ASIMD load, 4 element, one lane, S1879// ASIMD load, 4 element, one lane, D1880def : InstRW<[V2Write_8c_3L_4V], (instregex "LD4i(8|16|32|64)$")>;1881def : InstRW<[WriteAdr, V2Write_8c_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;1882 1883// ASIMD load, 4 element, all lanes, D-form, B/H/S1884// ASIMD load, 4 element, all lanes, D-form, D1885def : InstRW<[V2Write_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;1886def : InstRW<[WriteAdr, V2Write_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;1887 1888// ASIMD load, 4 element, all lanes, Q-form, B/H/S1889// ASIMD load, 4 element, all lanes, Q-form, D1890def : InstRW<[V2Write_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;1891def : InstRW<[WriteAdr, V2Write_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;1892 1893// ASIMD store instructions1894// -----------------------------------------------------------------------------1895 1896// ASIMD store, 1 element, multiple, 1 reg, D-form1897def : InstRW<[V2Write_2c_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)$")>;1898def : InstRW<[WriteAdr, V2Write_2c_1L01_1V01], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;1899 1900// ASIMD store, 1 element, multiple, 1 reg, Q-form1901def : InstRW<[V2Write_2c_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)$")>;1902def : InstRW<[WriteAdr, V2Write_2c_1L01_1V01], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;1903 1904// ASIMD store, 1 element, multiple, 2 reg, D-form1905def : InstRW<[V2Write_2c_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)$")>;1906def : InstRW<[WriteAdr, V2Write_2c_1L01_1V01], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;1907 1908// ASIMD store, 1 element, multiple, 2 reg, Q-form1909def : InstRW<[V2Write_2c_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)$")>;1910def : InstRW<[WriteAdr, V2Write_2c_2L01_2V01], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;1911 1912// ASIMD store, 1 element, multiple, 3 reg, D-form1913def : InstRW<[V2Write_2c_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)$")>;1914def : InstRW<[WriteAdr, V2Write_2c_2L01_2V01], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;1915 1916// ASIMD store, 1 element, multiple, 3 reg, Q-form1917def : InstRW<[V2Write_2c_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)$")>;1918def : InstRW<[WriteAdr, V2Write_2c_3L01_3V01], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;1919 1920// ASIMD store, 1 element, multiple, 4 reg, D-form1921def : InstRW<[V2Write_2c_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;1922def : InstRW<[WriteAdr, V2Write_2c_2L01_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;1923 1924// ASIMD store, 1 element, multiple, 4 reg, Q-form1925def : InstRW<[V2Write_2c_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;1926def : InstRW<[WriteAdr, V2Write_2c_4L01_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;1927 1928// ASIMD store, 1 element, one lane, B/H/S1929// ASIMD store, 1 element, one lane, D1930def : InstRW<[V2Write_4c_1L01_2V01], (instregex "ST1i(8|16|32|64)$")>;1931def : InstRW<[WriteAdr, V2Write_4c_1L01_2V01], (instregex "ST1i(8|16|32|64)_POST$")>;1932 1933// ASIMD store, 2 element, multiple, D-form, B/H/S1934def : InstRW<[V2Write_4c_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)$")>;1935def : InstRW<[WriteAdr, V2Write_4c_1L01_2V01], (instregex "ST2Twov(8b|4h|2s)_POST$")>;1936 1937// ASIMD store, 2 element, multiple, Q-form, B/H/S1938// ASIMD store, 2 element, multiple, Q-form, D1939def : InstRW<[V2Write_4c_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)$")>;1940def : InstRW<[WriteAdr, V2Write_4c_2L01_4V01], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;1941 1942// ASIMD store, 2 element, one lane, B/H/S1943// ASIMD store, 2 element, one lane, D1944def : InstRW<[V2Write_4c_1L01_2V01], (instregex "ST2i(8|16|32|64)$")>;1945def : InstRW<[WriteAdr, V2Write_4c_1L01_2V01], (instregex "ST2i(8|16|32|64)_POST$")>;1946 1947// ASIMD store, 3 element, multiple, D-form, B/H/S1948def : InstRW<[V2Write_5c_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)$")>;1949def : InstRW<[WriteAdr, V2Write_5c_2L01_4V01], (instregex "ST3Threev(8b|4h|2s)_POST$")>;1950 1951// ASIMD store, 3 element, multiple, Q-form, B/H/S1952// ASIMD store, 3 element, multiple, Q-form, D1953def : InstRW<[V2Write_6c_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)$")>;1954def : InstRW<[WriteAdr, V2Write_6c_3L01_6V01], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;1955 1956// ASIMD store, 3 element, one lane, B/H1957// ASIMD store, 3 element, one lane, S1958// ASIMD store, 3 element, one lane, D1959def : InstRW<[V2Write_5c_2L01_4V01], (instregex "ST3i(8|16|32|64)$")>;1960def : InstRW<[WriteAdr, V2Write_5c_2L01_4V01], (instregex "ST3i(8|16|32|64)_POST$")>;1961 1962// ASIMD store, 4 element, multiple, D-form, B/H/S1963def : InstRW<[V2Write_6c_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)$")>;1964def : InstRW<[WriteAdr, V2Write_6c_2L01_6V01], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;1965 1966// ASIMD store, 4 element, multiple, Q-form, B/H/S1967def : InstRW<[V2Write_7c_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)$")>;1968def : InstRW<[WriteAdr, V2Write_7c_4L01_12V01], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;1969 1970// ASIMD store, 4 element, multiple, Q-form, D1971def : InstRW<[V2Write_5c_4L01_8V01], (instregex "ST4Fourv(2d)$")>;1972def : InstRW<[WriteAdr, V2Write_5c_4L01_8V01], (instregex "ST4Fourv(2d)_POST$")>;1973 1974// ASIMD store, 4 element, one lane, B/H/S1975def : InstRW<[V2Write_6c_1L01_3V01], (instregex "ST4i(8|16|32)$")>;1976def : InstRW<[WriteAdr, V2Write_6c_1L01_3V01], (instregex "ST4i(8|16|32)_POST$")>;1977 1978// ASIMD store, 4 element, one lane, D1979def : InstRW<[V2Write_4c_2L01_4V01], (instregex "ST4i(64)$")>;1980def : InstRW<[WriteAdr, V2Write_4c_2L01_4V01], (instregex "ST4i(64)_POST$")>;1981 1982// Cryptography extensions1983// -----------------------------------------------------------------------------1984 1985// Crypto AES ops1986def : InstRW<[V2Write_2c_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;1987 1988// Crypto polynomial (64x64) multiply long1989def : InstRW<[V2Write_2c_1V], (instrs PMULLv1i64, PMULLv2i64)>;1990 1991// Crypto SHA1 hash acceleration op1992// Crypto SHA1 schedule acceleration ops1993def : InstRW<[V2Write_2c_1V0], (instregex "^SHA1(H|SU0|SU1)")>;1994 1995// Crypto SHA1 hash acceleration ops1996// Crypto SHA256 hash acceleration ops1997def : InstRW<[V2Write_4c_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>;1998 1999// Crypto SHA256 schedule acceleration ops2000def : InstRW<[V2Write_2c_1V0], (instregex "^SHA256SU[01]")>;2001 2002// Crypto SHA512 hash acceleration ops2003def : InstRW<[V2Write_2c_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>;2004 2005// Crypto SHA3 ops2006def : InstRW<[V2Write_2c_1V0], (instrs BCAX, EOR3, RAX1, XAR)>;2007 2008// Crypto SM3 ops2009def : InstRW<[V2Write_2c_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$",2010 "^SM3TT[12][AB]$")>;2011 2012// Crypto SM4 ops2013def : InstRW<[V2Write_4c_1V0], (instrs SM4E, SM4ENCKEY)>;2014 2015// CRC2016// -----------------------------------------------------------------------------2017 2018def : InstRW<[V2Wr_CRC, V2Rd_CRC], (instregex "^CRC32")>;2019 2020// SVE Predicate instructions2021// -----------------------------------------------------------------------------2022 2023// Loop control, based on predicate2024def : InstRW<[V2Write_2or3c_1M], (instrs BRKA_PPmP, BRKA_PPzP,2025 BRKB_PPmP, BRKB_PPzP)>;2026 2027// Loop control, based on predicate and flag setting2028def : InstRW<[V2Write_3or4c_2M], (instrs BRKAS_PPzP, BRKBS_PPzP)>;2029 2030// Loop control, propagating2031def : InstRW<[V2Write_2or3c_1M0], (instrs BRKN_PPzP, BRKPA_PPzPP,2032 BRKPB_PPzPP)>;2033 2034// Loop control, propagating and flag setting2035def : InstRW<[V2Write_3or4c_1M0_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP,2036 BRKPBS_PPzPP)>;2037 2038// Loop control, based on GPR2039def : InstRW<[V2Write_3c_2M],2040 (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]")>;2041def : InstRW<[V2Write_3c_2M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]")>;2042 2043// Loop terminate2044def : InstRW<[V2Write_1c_2M], (instregex "^CTERM(EQ|NE)_(WW|XX)")>;2045 2046// Predicate counting scalar2047def : InstRW<[V2Write_2c_1M], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;2048def : InstRW<[V2Write_2c_1M],2049 (instregex "^(CNT|SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI",2050 "^SQ(DEC|INC)[BHWD]_XPiWdI",2051 "^UQ(DEC|INC)[BHWD]_WPiI")>;2052 2053// Predicate counting scalar, ALL, {1,2,4}2054def : InstRW<[V2Write_IncDec], (instregex "^(DEC|INC)[BHWD]_XPiI")>;2055 2056// Predicate counting scalar, active predicate2057def : InstRW<[V2Write_2c_1M],2058 (instregex "^CNTP_XPP_[BHSD]",2059 "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]",2060 "^(UQDEC|UQINC)P_WP_[BHSD]",2061 "^(SQDEC|SQINC)P_XPWd_[BHSD]")>;2062 2063// Predicate counting vector, active predicate2064def : InstRW<[V2Write_7c_1M_1M0_1V],2065 (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]")>;2066 2067// Predicate logical2068def : InstRW<[V2Write_1or2c_1M0],2069 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP")>;2070 2071// Predicate logical, flag setting2072def : InstRW<[V2Write_1or2c_1M0_1M],2073 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;2074 2075// Predicate reverse2076def : InstRW<[V2Write_2c_1M], (instregex "^REV_PP_[BHSD]")>;2077 2078// Predicate select2079def : InstRW<[V2Write_1c_1M0], (instrs SEL_PPPP)>;2080 2081// Predicate set2082def : InstRW<[V2Write_2c_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;2083 2084// Predicate set/initialize, set flags2085def : InstRW<[V2Write_3c_2M], (instregex "^PTRUES_[BHSD]")>;2086 2087// Predicate find first/next2088def : InstRW<[V2Write_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;2089 2090// Predicate test2091def : InstRW<[V2Write_1c_1M], (instrs PTEST_PP)>;2092 2093// Predicate transpose2094def : InstRW<[V2Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;2095 2096// Predicate unpack and widen2097def : InstRW<[V2Write_2c_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>;2098 2099// Predicate zip/unzip2100def : InstRW<[V2Write_2c_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]")>;2101 2102// SVE integer instructions2103// -----------------------------------------------------------------------------2104 2105// Arithmetic, absolute diff2106def : InstRW<[V2Write_2c_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",2107 "^[SU]ABD_ZPZZ_[BHSD]")>;2108 2109// Arithmetic, absolute diff accum2110def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]")>;2111 2112// Arithmetic, absolute diff accum long2113def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]")>;2114 2115// Arithmetic, absolute diff long2116def : InstRW<[V2Write_2c_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]")>;2117 2118// Arithmetic, basic2119def : InstRW<[V2Write_2c_1V],2120 (instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]",2121 "^(ADD|SUB)_ZZZ_[BHSD]",2122 "^(ADD|SUB|SUBR)_ZPZZ_[BHSD]",2123 "^(ADD|SUB|SUBR)_ZI_[BHSD]",2124 "^ADR_[SU]XTW_ZZZ_D_[0123]",2125 "^ADR_LSL_ZZZ_[SD]_[0123]",2126 "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",2127 "^SADDLBT_ZZZ_[HSD]",2128 "^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",2129 "^SSUBL(BT|TB)_ZZZ_[HSD]")>;2130 2131// Arithmetic, complex2132def : InstRW<[V2Write_2c_1V],2133 (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]",2134 "^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]",2135 "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]",2136 "^[SU]Q(ADD|SUB)_ZI_[BHSD]",2137 "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]",2138 "^(UQSUB|UQSUBR)_ZPmZ_[BHSD]")>;2139 2140// Arithmetic, large integer2141def : InstRW<[V2Write_2c_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]")>;2142 2143// Arithmetic, pairwise add2144def : InstRW<[V2Write_2c_1V], (instregex "^ADDP_ZPmZ_[BHSD]")>;2145 2146// Arithmetic, pairwise add and accum long2147def : InstRW<[V2Wr_ZPA, ReadDefault, V2Rd_ZPA],2148 (instregex "^[SU]ADALP_ZPmZ_[HSD]")>;2149 2150// Arithmetic, shift2151def : InstRW<[V2Write_2c_1V13],2152 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",2153 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",2154 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",2155 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",2156 "^(ASR|LSL|LSR)_ZZI_[BHSD]",2157 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",2158 "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>;2159 2160// Arithmetic, shift and accumulate2161def : InstRW<[V2Wr_ZSA, V2Rd_ZSA], (instregex "^[SU]R?SRA_ZZI_[BHSD]")>;2162 2163// Arithmetic, shift by immediate2164def : InstRW<[V2Write_2c_1V13], (instregex "^SHRN[BT]_ZZI_[BHS]",2165 "^[SU]SHLL[BT]_ZZI_[HSD]")>;2166 2167// Arithmetic, shift by immediate and insert2168def : InstRW<[V2Write_2c_1V13], (instregex "^(SLI|SRI)_ZZI_[BHSD]")>;2169 2170// Arithmetic, shift complex2171def : InstRW<[V2Write_4c_1V13],2172 (instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]",2173 "^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]",2174 "^[SU]QR?SHL_ZPZZ_[BHSD]",2175 "^(SQSHL|SQSHLU|UQSHL)_(ZPmI|ZPZI)_[BHSD]",2176 "^SQSHRU?N[BT]_ZZI_[BHS]",2177 "^UQR?SHRN[BT]_ZZI_[BHS]")>;2178 2179// Arithmetic, shift right for divide2180def : InstRW<[V2Write_4c_1V13], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;2181 2182// Arithmetic, shift rounding2183def : InstRW<[V2Write_4c_1V13], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]",2184 "^[SU]RSHL_ZPZZ_[BHSD]",2185 "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>;2186 2187// Bit manipulation2188def : InstRW<[V2Write_6c_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>;2189 2190// Bitwise select2191def : InstRW<[V2Write_2c_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ")>;2192 2193// Count/reverse bits2194def : InstRW<[V2Write_2c_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;2195 2196// Broadcast logical bitmask immediate to vector2197def : InstRW<[V2Write_2c_1V], (instrs DUPM_ZI)>;2198 2199// Compare and set flags2200def : InstRW<[V2Write_4or5c_1V0_1M0],2201 (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]",2202 "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]")>;2203 2204// Complex add2205def : InstRW<[V2Write_2c_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]")>;2206 2207// Complex dot product 8-bit element2208def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;2209 2210// Complex dot product 16-bit element2211def : InstRW<[V2Wr_ZDOTH, V2Rd_ZDOTH], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;2212 2213// Complex multiply-add B, H, S element size2214def : InstRW<[V2Wr_ZCMABHS, V2Rd_ZCMABHS], (instregex "^CMLA_ZZZ_[BHS]",2215 "^CMLA_ZZZI_[HS]")>;2216 2217// Complex multiply-add D element size2218def : InstRW<[V2Wr_ZCMAD, V2Rd_ZCMAD], (instrs CMLA_ZZZ_D)>;2219 2220// Conditional extract operations, scalar form2221def : InstRW<[V2Write_8c_1M0_1V01], (instregex "^CLAST[AB]_RPZ_[BHSD]")>;2222 2223// Conditional extract operations, SIMD&FP scalar and vector forms2224def : InstRW<[V2Write_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]",2225 "^COMPACT_ZPZ_[SD]",2226 "^SPLICE_ZPZZ?_[BHSD]")>;2227 2228// Convert to floating point, 64b to float or convert to double2229def : InstRW<[V2Write_3c_1V02], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",2230 "^[SU]CVTF_ZPmZ_StoD")>;2231 2232// Convert to floating point, 32b to single or half2233def : InstRW<[V2Write_4c_2V02], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;2234 2235// Convert to floating point, 16b to half2236def : InstRW<[V2Write_6c_4V02], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;2237 2238// Copy, scalar2239def : InstRW<[V2Write_5c_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]")>;2240 2241// Copy, scalar SIMD&FP or imm2242def : InstRW<[V2Write_2c_1V], (instregex "^CPY_ZPm[IV]_[BHSD]",2243 "^CPY_ZPzI_[BHSD]")>;2244 2245// Divides, 32 bit2246def : InstRW<[V2Write_12c_1V0], (instregex "^[SU]DIVR?_ZPmZ_S",2247 "^[SU]DIV_ZPZZ_S")>;2248 2249// Divides, 64 bit2250def : InstRW<[V2Write_20c_1V0], (instregex "^[SU]DIVR?_ZPmZ_D",2251 "^[SU]DIV_ZPZZ_D")>;2252 2253// Dot product, 8 bit2254def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_BtoS")>;2255 2256// Dot product, 8 bit, using signed and unsigned integers2257def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;2258 2259// Dot product, 16 bit2260def : InstRW<[V2Wr_ZDOTH, V2Rd_ZDOTH], (instregex "^[SU]DOT_ZZZI?_HtoD")>;2261 2262// Duplicate, immediate and indexed form2263def : InstRW<[V2Write_2c_1V], (instregex "^DUP_ZI_[BHSD]",2264 "^DUP_ZZI_[BHSDQ]")>;2265 2266// Duplicate, scalar form2267def : InstRW<[V2Write_3c_1M0], (instregex "^DUP_ZR_[BHSD]")>;2268 2269// Extend, sign or zero2270def : InstRW<[V2Write_2c_1V13], (instregex "^[SU]XTB_ZPmZ_[HSD]",2271 "^[SU]XTH_ZPmZ_[SD]",2272 "^[SU]XTW_ZPmZ_[D]")>;2273 2274// Extract2275def : InstRW<[V2Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;2276 2277// Extract narrow saturating2278def : InstRW<[V2Write_4c_1V13], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]",2279 "^SQXTUN[BT]_ZZ_[BHS]")>;2280 2281// Extract/insert operation, SIMD and FP scalar form2282def : InstRW<[V2Write_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]",2283 "^INSR_ZV_[BHSD]")>;2284 2285// Extract/insert operation, scalar2286def : InstRW<[V2Write_6c_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]",2287 "^INSR_ZR_[BHSD]")>;2288 2289// Histogram operations2290def : InstRW<[V2Write_2c_1V], (instregex "^HISTCNT_ZPzZZ_[SD]",2291 "^HISTSEG_ZZZ")>;2292 2293// Horizontal operations, B, H, S form, immediate operands only2294def : InstRW<[V2Write_4c_1V02], (instregex "^INDEX_II_[BHS]")>;2295 2296// Horizontal operations, B, H, S form, scalar, immediate operands/ scalar2297// operands only / immediate, scalar operands2298def : InstRW<[V2Write_7c_1M0_1V02], (instregex "^INDEX_(IR|RI|RR)_[BHS]")>;2299 2300// Horizontal operations, D form, immediate operands only2301def : InstRW<[V2Write_5c_2V02], (instrs INDEX_II_D)>;2302 2303// Horizontal operations, D form, scalar, immediate operands)/ scalar operands2304// only / immediate, scalar operands2305def : InstRW<[V2Write_8c_2M0_2V02], (instregex "^INDEX_(IR|RI|RR)_D")>;2306 2307// Logical2308def : InstRW<[V2Write_2c_1V],2309 (instregex "^(AND|EOR|ORR)_ZI",2310 "^(AND|BIC|EOR|ORR)_ZZZ",2311 "^EOR(BT|TB)_ZZZ_[BHSD]",2312 "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]",2313 "^NOT_ZPmZ_[BHSD]")>;2314 2315// Max/min, basic and pairwise2316def : InstRW<[V2Write_2c_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",2317 "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]",2318 "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>;2319 2320// Matching operations2321// FIXME: SOG p. 44, n. 5: If the consuming instruction has a flag source, the2322// latency for this instruction is 4 cycles.2323def : InstRW<[V2Write_2or3c_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]")>;2324 2325// Matrix multiply-accumulate2326def : InstRW<[V2Wr_ZMMA, V2Rd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;2327 2328// Move prefix2329def : InstRW<[V2Write_2c_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]",2330 "^MOVPRFX_ZZ")>;2331 2332// Multiply, B, H, S element size2333def : InstRW<[V2Write_4c_1V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]",2334 "^MUL_ZPZZ_[BHS]",2335 "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]",2336 "^[SU]MULH_ZPZZ_[BHS]")>;2337 2338// Multiply, D element size2339def : InstRW<[V2Write_5c_2V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D",2340 "^MUL_ZPZZ_D",2341 "^[SU]MULH_(ZPmZ|ZZZ)_D",2342 "^[SU]MULH_ZPZZ_D")>;2343 2344// Multiply long2345def : InstRW<[V2Write_4c_1V02], (instregex "^[SU]MULL[BT]_ZZZI_[SD]",2346 "^[SU]MULL[BT]_ZZZ_[HSD]")>;2347 2348// Multiply accumulate, B, H, S element size2349def : InstRW<[V2Wr_ZMABHS, V2Rd_ZMABHS],2350 (instregex "^ML[AS]_ZZZI_[HS]", "^ML[AS]_ZPZZZ_[BHS]")>;2351def : InstRW<[V2Wr_ZMABHS, ReadDefault, V2Rd_ZMABHS],2352 (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>;2353 2354// Multiply accumulate, D element size2355def : InstRW<[V2Wr_ZMAD, V2Rd_ZMAD],2356 (instregex "^ML[AS]_ZZZI_D", "^ML[AS]_ZPZZZ_D")>;2357def : InstRW<[V2Wr_ZMAD, ReadDefault, V2Rd_ZMAD],2358 (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;2359 2360// Multiply accumulate long2361def : InstRW<[V2Wr_ZMAL, V2Rd_ZMAL], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]",2362 "^[SU]ML[AS]L[BT]_ZZZI_[SD]")>;2363 2364// Multiply accumulate saturating doubling long regular2365def : InstRW<[V2Wr_ZMASQL, V2Rd_ZMASQ],2366 (instregex "^SQDML[AS]L(B|T|BT)_ZZZ_[HSD]",2367 "^SQDML[AS]L[BT]_ZZZI_[SD]")>;2368 2369// Multiply saturating doubling high, B, H, S element size2370def : InstRW<[V2Write_4c_1V02], (instregex "^SQDMULH_ZZZ_[BHS]",2371 "^SQDMULH_ZZZI_[HS]")>;2372 2373// Multiply saturating doubling high, D element size2374def : InstRW<[V2Write_5c_2V02], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>;2375 2376// Multiply saturating doubling long2377def : InstRW<[V2Write_4c_1V02], (instregex "^SQDMULL[BT]_ZZZ_[HSD]",2378 "^SQDMULL[BT]_ZZZI_[SD]")>;2379 2380// Multiply saturating rounding doubling regular/complex accumulate, B, H, S2381// element size2382def : InstRW<[V2Wr_ZMASQBHS, V2Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZ_[BHS]",2383 "^SQRDCMLAH_ZZZ_[BHS]",2384 "^SQRDML[AS]H_ZZZI_[HS]",2385 "^SQRDCMLAH_ZZZI_[HS]")>;2386 2387// Multiply saturating rounding doubling regular/complex accumulate, D element2388// size2389def : InstRW<[V2Wr_ZMASQD, V2Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZI?_D",2390 "^SQRDCMLAH_ZZZ_D")>;2391 2392// Multiply saturating rounding doubling regular/complex, B, H, S element size2393def : InstRW<[V2Write_4c_1V02], (instregex "^SQRDMULH_ZZZ_[BHS]",2394 "^SQRDMULH_ZZZI_[HS]")>;2395 2396// Multiply saturating rounding doubling regular/complex, D element size2397def : InstRW<[V2Write_5c_2V02], (instregex "^SQRDMULH_ZZZI?_D")>;2398 2399// Multiply/multiply long, (8x8) polynomial2400def : InstRW<[V2Write_2c_1V23], (instregex "^PMUL_ZZZ_B",2401 "^PMULL[BT]_ZZZ_[HDQ]")>;2402 2403// Predicate counting vector2404def : InstRW<[V2Write_2c_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI")>;2405 2406// Reciprocal estimate2407def : InstRW<[V2Write_4c_2V02], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;2408 2409// Reduction, arithmetic, B form2410def : InstRW<[V2Write_9c_2V_4V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;2411 2412// Reduction, arithmetic, H form2413def : InstRW<[V2Write_8c_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;2414 2415// Reduction, arithmetic, S form2416def : InstRW<[V2Write_6c_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;2417 2418// Reduction, arithmetic, D form2419def : InstRW<[V2Write_4c_2V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;2420 2421// Reduction, logical2422def : InstRW<[V2Write_6c_1V_1V13], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]")>;2423 2424// Reverse, vector2425def : InstRW<[V2Write_2c_1V], (instregex "^REV_ZZ_[BHSD]",2426 "^REVB_ZPmZ_[HSD]",2427 "^REVH_ZPmZ_[SD]",2428 "^REVW_ZPmZ_D")>;2429 2430// Select, vector form2431def : InstRW<[V2Write_2c_1V], (instregex "^SEL_ZPZZ_[BHSD]")>;2432 2433// Table lookup2434def : InstRW<[V2Write_2c_1V], (instregex "^TBL_ZZZZ?_[BHSD]")>;2435 2436// Table lookup extension2437def : InstRW<[V2Write_2c_1V], (instregex "^TBX_ZZZ_[BHSD]")>;2438 2439// Transpose, vector form2440def : InstRW<[V2Write_2c_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]")>;2441 2442// Unpack and extend2443def : InstRW<[V2Write_2c_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]")>;2444 2445// Zip/unzip2446def : InstRW<[V2Write_2c_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]")>;2447 2448// SVE floating-point instructions2449// -----------------------------------------------------------------------------2450 2451// Floating point absolute value/difference2452def : InstRW<[V2Write_2c_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]",2453 "^FABD_ZPZZ_[HSD]",2454 "^FABS_ZPmZ_[HSD]")>;2455 2456// Floating point arithmetic2457def : InstRW<[V2Write_2c_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",2458 "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",2459 "^FADDP_ZPmZZ_[HSD]",2460 "^FNEG_ZPmZ_[HSD]",2461 "^FSUBR_ZPm[IZ]_[HSD]",2462 "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;2463 2464// Floating point associative add, F162465def : InstRW<[V2Write_10c_1V1_9rc], (instrs FADDA_VPZ_H)>;2466 2467// Floating point associative add, F322468def : InstRW<[V2Write_6c_1V1_5rc], (instrs FADDA_VPZ_S)>;2469 2470// Floating point associative add, F642471def : InstRW<[V2Write_4c_1V], (instrs FADDA_VPZ_D)>;2472 2473// Floating point compare2474def : InstRW<[V2Write_2c_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]",2475 "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]",2476 "^FCM(LE|LT)_PPzZ0_[HSD]",2477 "^FCMUO_PPzZZ_[HSD]")>;2478 2479// Floating point complex add2480def : InstRW<[V2Write_3c_1V], (instregex "^FCADD_ZPmZ_[HSD]")>;2481 2482// Floating point complex multiply add2483def : InstRW<[V2Wr_ZFCMA, ReadDefault, V2Rd_ZFCMA], (instregex "^FCMLA_ZPmZZ_[HSD]")>;2484def : InstRW<[V2Wr_ZFCMA, V2Rd_ZFCMA], (instregex "^FCMLA_ZZZI_[HS]")>;2485 2486// Floating point convert, long or narrow (F16 to F32 or F32 to F16)2487def : InstRW<[V2Write_4c_2V02], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",2488 "^FCVTLT_ZPmZ_HtoS",2489 "^FCVTNT_ZPmZ_StoH")>;2490 2491// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F322492// or F64 to F16)2493def : InstRW<[V2Write_3c_1V02], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",2494 "^FCVTLT_ZPmZ_StoD",2495 "^FCVTNT_ZPmZ_DtoS")>;2496 2497// Floating point convert, round to odd2498def : InstRW<[V2Write_3c_1V02], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>;2499 2500// Floating point base2 log, F162501def : InstRW<[V2Write_6c_4V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;2502 2503// Floating point base2 log, F322504def : InstRW<[V2Write_4c_2V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;2505 2506// Floating point base2 log, F642507def : InstRW<[V2Write_3c_1V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;2508 2509// Floating point convert to integer, F162510def : InstRW<[V2Write_6c_4V02], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;2511 2512// Floating point convert to integer, F322513def : InstRW<[V2Write_4c_2V02], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;2514 2515// Floating point convert to integer, F642516def : InstRW<[V2Write_3c_1V02],2517 (instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>;2518 2519// Floating point copy2520def : InstRW<[V2Write_2c_1V], (instregex "^FCPY_ZPmI_[HSD]",2521 "^FDUP_ZI_[HSD]")>;2522 2523// Floating point divide, F162524def : InstRW<[V2Write_13c_1V02_12rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;2525 2526// Floating point divide, F322527def : InstRW<[V2Write_10c_1V02_9rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;2528 2529// Floating point divide, F642530def : InstRW<[V2Write_15c_1V02_14rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;2531 2532// Floating point min/max pairwise2533def : InstRW<[V2Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;2534 2535// Floating point min/max2536def : InstRW<[V2Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",2537 "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;2538 2539// Floating point multiply2540def : InstRW<[V2Write_3c_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",2541 "^FMULX_ZPZZ_[HSD]",2542 "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",2543 "^FMUL_ZPZ[IZ]_[HSD]")>;2544 2545// Floating point multiply accumulate2546def : InstRW<[V2Wr_ZFMA, ReadDefault, V2Rd_ZFMA],2547 (instregex "^FN?ML[AS]_ZPmZZ_[HSD]",2548 "^FN?(MAD|MSB)_ZPmZZ_[HSD]")>;2549def : InstRW<[V2Wr_ZFMA, V2Rd_ZFMA],2550 (instregex "^FML[AS]_ZZZI_[HSD]",2551 "^FN?ML[AS]_ZPZZZ_[HSD]")>;2552 2553// Floating point multiply add/sub accumulate long2554def : InstRW<[V2Wr_ZFMAL, V2Rd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH")>;2555 2556// Floating point reciprocal estimate, F162557def : InstRW<[V2Write_6c_4V02], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;2558 2559// Floating point reciprocal estimate, F322560def : InstRW<[V2Write_4c_2V02], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>;2561 2562// Floating point reciprocal estimate, F642563def : InstRW<[V2Write_3c_1V02], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>;2564 2565// Floating point reciprocal step2566def : InstRW<[V2Write_4c_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]")>;2567 2568// Floating point reduction, F162569def : InstRW<[V2Write_8c_4V],2570 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H")>;2571 2572// Floating point reduction, F322573def : InstRW<[V2Write_6c_3V],2574 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S")>;2575 2576// Floating point reduction, F642577def : InstRW<[V2Write_4c_2V],2578 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D")>;2579 2580// Floating point round to integral, F162581def : InstRW<[V2Write_6c_4V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;2582 2583// Floating point round to integral, F322584def : InstRW<[V2Write_4c_2V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;2585 2586// Floating point round to integral, F642587def : InstRW<[V2Write_3c_1V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;2588 2589// Floating point square root, F162590def : InstRW<[V2Write_13c_1V02_12rc], (instregex "^FSQRT_ZPmZ_H")>;2591 2592// Floating point square root, F322593def : InstRW<[V2Write_10c_1V02_9rc], (instregex "^FSQRT_ZPmZ_S")>;2594 2595// Floating point square root, F642596def : InstRW<[V2Write_16c_1V02_14rc], (instregex "^FSQRT_ZPmZ_D")>;2597 2598// Floating point trigonometric exponentiation2599def : InstRW<[V2Write_3c_1V1], (instregex "^FEXPA_ZZ_[HSD]")>;2600 2601// Floating point trigonometric multiply add2602def : InstRW<[V2Write_4c_1V], (instregex "^FTMAD_ZZI_[HSD]")>;2603 2604// Floating point trigonometric, miscellaneous2605def : InstRW<[V2Write_3c_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]")>;2606 2607// SVE BFloat16 (BF16) instructions2608// -----------------------------------------------------------------------------2609 2610// Convert, F32 to BF162611def : InstRW<[V2Write_4c_1V02], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;2612 2613// Dot product2614def : InstRW<[V2Wr_ZBFDOT, V2Rd_ZBFDOT], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;2615 2616// Matrix multiply accumulate2617def : InstRW<[V2Wr_ZBFMMA, V2Rd_ZBFMMA], (instrs BFMMLA_ZZZ_HtoS)>;2618 2619// Multiply accumulate long2620def : InstRW<[V2Wr_ZBFMAL, V2Rd_ZBFMAL], (instregex "^BFMLAL[BT]_ZZZI?")>;2621 2622// SVE Load instructions2623// -----------------------------------------------------------------------------2624 2625// Load vector2626def : InstRW<[V2Write_6c_1L], (instrs LDR_ZXI)>;2627 2628// Load predicate2629def : InstRW<[V2Write_6c_1L_1M], (instrs LDR_PXI)>;2630 2631// Contiguous load, scalar + imm2632def : InstRW<[V2Write_6c_1L], (instregex "^LD1[BHWD]_IMM$",2633 "^LD1S?B_[HSD]_IMM$",2634 "^LD1S?H_[SD]_IMM$",2635 "^LD1S?W_D_IMM$" )>;2636// Contiguous load, scalar + scalar2637def : InstRW<[V2Write_6c_1L], (instregex "^LD1[BHWD]$",2638 "^LD1S?B_[HSD]$",2639 "^LD1S?H_[SD]$",2640 "^LD1S?W_D$" )>;2641 2642// Contiguous load broadcast, scalar + imm2643def : InstRW<[V2Write_6c_1L], (instregex "^LD1R[BHWD]_IMM$",2644 "^LD1RS?B_[HSD]_IMM$",2645 "^LD1RS?H_[SD]_IMM$",2646 "^LD1RW_D_IMM$",2647 "^LD1RSW_IMM$",2648 "^LD1RQ_[BHWD]_IMM$")>;2649 2650// Contiguous load broadcast, scalar + scalar2651def : InstRW<[V2Write_6c_1L], (instregex "^LD1RQ_[BHWD]$")>;2652 2653// Non temporal load, scalar + imm2654// Non temporal load, scalar + scalar2655def : InstRW<[V2Write_6c_1L], (instregex "^LDNT1[BHWD]_ZR[IR]$")>;2656 2657// Non temporal gather load, vector + scalar 32-bit element size2658def : InstRW<[V2Write_9c_2L_4V], (instregex "^LDNT1[BHW]_ZZR_S$",2659 "^LDNT1S[BH]_ZZR_S$")>;2660 2661// Non temporal gather load, vector + scalar 64-bit element size2662def : InstRW<[V2Write_9c_2L_2V1], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;2663def : InstRW<[V2Write_9c_2L_2V1], (instrs LDNT1D_ZZR_D)>;2664 2665// Contiguous first faulting load, scalar + scalar2666def : InstRW<[V2Write_6c_1L_1S], (instregex "^LDFF1[BHWD]$",2667 "^LDFF1S?B_[HSD]$",2668 "^LDFF1S?H_[SD]$",2669 "^LDFF1S?W_D$")>;2670 2671// Contiguous non faulting load, scalar + imm2672def : InstRW<[V2Write_6c_1L], (instregex "^LDNF1[BHWD]_IMM$",2673 "^LDNF1S?B_[HSD]_IMM$",2674 "^LDNF1S?H_[SD]_IMM$",2675 "^LDNF1S?W_D_IMM$")>;2676 2677// Contiguous Load two structures to two vectors, scalar + imm2678def : InstRW<[V2Write_8c_2L_2V], (instregex "^LD2[BHWD]_IMM$")>;2679 2680// Contiguous Load two structures to two vectors, scalar + scalar2681def : InstRW<[V2Write_9c_2L_2V_2S], (instregex "^LD2[BHWD]$")>;2682 2683// Contiguous Load three structures to three vectors, scalar + imm2684def : InstRW<[V2Write_9c_3L_3V], (instregex "^LD3[BHWD]_IMM$")>;2685 2686// Contiguous Load three structures to three vectors, scalar + scalar2687def : InstRW<[V2Write_10c_3V_3L_3S], (instregex "^LD3[BHWD]$")>;2688 2689// Contiguous Load four structures to four vectors, scalar + imm2690def : InstRW<[V2Write_9c_4L_8V], (instregex "^LD4[BHWD]_IMM$")>;2691 2692// Contiguous Load four structures to four vectors, scalar + scalar2693def : InstRW<[V2Write_10c_4L_8V_4S], (instregex "^LD4[BHWD]$")>;2694 2695// Gather load, vector + imm, 32-bit element size2696def : InstRW<[V2Write_9c_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",2697 "^GLD(FF)?1W_IMM$")>;2698 2699// Gather load, vector + imm, 64-bit element size2700def : InstRW<[V2Write_9c_1L_4V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",2701 "^GLD(FF)?1D_IMM$")>;2702 2703// Gather load, 32-bit scaled offset2704def : InstRW<[V2Write_10c_1L_8V],2705 (instregex "^GLD(FF)?1S?H_S_[SU]XTW_SCALED$",2706 "^GLD(FF)?1W_[SU]XTW_SCALED")>;2707 2708// Gather load, 64-bit scaled offset2709// NOTE: These instructions are not specified in the SOG.2710def : InstRW<[V2Write_10c_1L_4V],2711 (instregex "^GLD(FF)?1S?[HW]_D_([SU]XTW_)?SCALED$",2712 "^GLD(FF)?1D_([SU]XTW_)?SCALED$")>;2713 2714// Gather load, 32-bit unpacked unscaled offset2715def : InstRW<[V2Write_9c_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",2716 "^GLD(FF)?1W_[SU]XTW$")>;2717 2718// Gather load, 64-bit unpacked unscaled offset2719// NOTE: These instructions are not specified in the SOG.2720def : InstRW<[V2Write_9c_1L_2V],2721 (instregex "^GLD(FF)?1S?[BHW]_D(_[SU]XTW)?$",2722 "^GLD(FF)?1D(_[SU]XTW)?$")>;2723 2724// SVE Store instructions2725// -----------------------------------------------------------------------------2726 2727// Store from predicate reg2728def : InstRW<[V2Write_1c_1L01], (instrs STR_PXI)>;2729 2730// Store from vector reg2731def : InstRW<[V2Write_2c_1L01_1V01], (instrs STR_ZXI)>;2732 2733// Contiguous store, scalar + imm2734def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^ST1[BHWD]_IMM$",2735 "^ST1B_[HSD]_IMM$",2736 "^ST1H_[SD]_IMM$",2737 "^ST1W_D_IMM$")>;2738 2739// Contiguous store, scalar + scalar2740def : InstRW<[V2Write_2c_1L01_1S_1V01], (instregex "^ST1H(_[SD])?$")>;2741def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^ST1[BWD]$",2742 "^ST1B_[HSD]$",2743 "^ST1W_D$")>;2744 2745// Contiguous store two structures from two vectors, scalar + imm2746def : InstRW<[V2Write_4c_1L01_1V01], (instregex "^ST2[BHWD]_IMM$")>;2747 2748// Contiguous store two structures from two vectors, scalar + scalar2749def : InstRW<[V2Write_4c_2L01_2S_2V01], (instrs ST2H)>;2750def : InstRW<[V2Write_4c_2L01_2V01], (instregex "^ST2[BWD]$")>;2751 2752// Contiguous store three structures from three vectors, scalar + imm2753def : InstRW<[V2Write_7c_9L01_9V01], (instregex "^ST3[BHWD]_IMM$")>;2754 2755// Contiguous store three structures from three vectors, scalar + scalar2756def : InstRW<[V2Write_7c_9L01_9S_9V01], (instregex "^ST3[BHWD]$")>;2757 2758// Contiguous store four structures from four vectors, scalar + imm2759def : InstRW<[V2Write_11c_18L01_18V01], (instregex "^ST4[BHWD]_IMM$")>;2760 2761// Contiguous store four structures from four vectors, scalar + scalar2762def : InstRW<[V2Write_11c_18L01_18S_18V01], (instregex "^ST4[BHWD]$")>;2763 2764// Non temporal store, scalar + imm2765def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^STNT1[BHWD]_ZRI$")>;2766 2767// Non temporal store, scalar + scalar2768def : InstRW<[V2Write_2c_1L01_1S_1V01], (instrs STNT1H_ZRR)>;2769def : InstRW<[V2Write_2c_1L01_1V01], (instregex "^STNT1[BWD]_ZRR$")>;2770 2771// Scatter non temporal store, vector + scalar 32-bit element size2772def : InstRW<[V2Write_4c_4L01_4V01], (instregex "^STNT1[BHW]_ZZR_S")>;2773 2774// Scatter non temporal store, vector + scalar 64-bit element size2775def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^STNT1[BHWD]_ZZR_D")>;2776 2777// Scatter store vector + imm 32-bit element size2778def : InstRW<[V2Write_4c_4L01_4V01], (instregex "^SST1[BH]_S_IMM$",2779 "^SST1W_IMM$")>;2780 2781// Scatter store vector + imm 64-bit element size2782def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^SST1[BHW]_D_IMM$",2783 "^SST1D_IMM$")>;2784 2785// Scatter store, 32-bit scaled offset2786def : InstRW<[V2Write_4c_4L01_4V01],2787 (instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>;2788 2789// Scatter store, 32-bit unpacked unscaled offset2790def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^SST1[BHW]_D_[SU]XTW$",2791 "^SST1D_[SU]XTW$")>;2792 2793// Scatter store, 32-bit unpacked scaled offset2794def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",2795 "^SST1D_[SU]XTW_SCALED$")>;2796 2797// Scatter store, 32-bit unscaled offset2798def : InstRW<[V2Write_4c_4L01_4V01], (instregex "^SST1[BH]_S_[SU]XTW$",2799 "^SST1W_[SU]XTW$")>;2800 2801// Scatter store, 64-bit scaled offset2802def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^SST1[HW]_D_SCALED$",2803 "^SST1D_SCALED$")>;2804 2805// Scatter store, 64-bit unscaled offset2806def : InstRW<[V2Write_2c_2L01_2V01], (instregex "^SST1[BHW]_D$",2807 "^SST1D$")>;2808 2809// SVE Miscellaneous instructions2810// -----------------------------------------------------------------------------2811 2812// Read first fault register, unpredicated2813def : InstRW<[V2Write_2c_1M0], (instrs RDFFR_P)>;2814 2815// Read first fault register, predicated2816def : InstRW<[V2Write_3or4c_1M0_1M], (instrs RDFFR_PPz)>;2817 2818// Read first fault register and set flags2819def : InstRW<[V2Write_4or5c_2M0_2M], (instrs RDFFRS_PPz)>;2820 2821// Set first fault register2822// Write to first fault register2823def : InstRW<[V2Write_2c_1M0], (instrs SETFFR, WRFFR)>;2824 2825// Prefetch2826// NOTE: This is not specified in the SOG.2827def : InstRW<[V2Write_4c_1L], (instregex "^PRF[BHWD]")>;2828 2829// SVE Cryptographic instructions2830// -----------------------------------------------------------------------------2831 2832// Crypto AES ops2833def : InstRW<[V2Write_2c_1V], (instregex "^AES[DE]_ZZZ_B$",2834 "^AESI?MC_ZZ_B$")>;2835 2836// Crypto SHA3 ops2837def : InstRW<[V2Write_2c_1V0], (instregex "^(BCAX|EOR3)_ZZZZ$",2838 "^RAX1_ZZZ_D$",2839 "^XAR_ZZZI_[BHSD]$")>;2840 2841// Crypto SM4 ops2842def : InstRW<[V2Write_4c_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;2843 2844}2845