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1//=- AArch64SchedNeoverseV3.td - NeoverseV3 Scheduling Defs --*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the scheduling model for the Arm Neoverse V3 processors.10// All information is taken from the V3 Software Optimization guide:11//12// https://developer.arm.com/documentation/109678/300/?lang=en13//14//===----------------------------------------------------------------------===//15 16def NeoverseV3Model : SchedMachineModel {17 let IssueWidth = 10; // Expect best value to be slightly higher than V218 let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. NOTE: Copied from Neoverse-V219 let LoadLatency = 4; // Optimistic load latency.20 let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.21 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.22 let CompleteModel = 1;23 24 list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,25 [HasSVE2p1, HasSVEB16B16,26 HasCPA, HasCSSC]);27}28 29//===----------------------------------------------------------------------===//30// Define each kind of processor resource and number available on Neoverse V3.31// Instructions are first fetched and then decoded into internal macro-ops32// (MOPs). From there, the MOPs proceed through register renaming and dispatch33// stages. A MOP can be split into two micro-ops further down the pipeline34// after the decode stage. Once dispatched, micro-ops wait for their operands35// and issue out-of-order to one of twenty-one issue pipelines. Each issue36// pipeline can accept one micro-op per cycle.37 38let SchedModel = NeoverseV3Model in {39 40// Define the (21) issue ports.41def V3UnitB : ProcResource<3>; // Branch 0/1/242def V3UnitS0 : ProcResource<1>; // Integer single-cycle 043def V3UnitS1 : ProcResource<1>; // Integer single-cycle 144def V3UnitS2 : ProcResource<1>; // Integer single-cycle 245def V3UnitS3 : ProcResource<1>; // Integer single-cycle 346def V3UnitS4 : ProcResource<1>; // Integer single-cycle 447def V3UnitS5 : ProcResource<1>; // Integer single-cycle 548def V3UnitM0 : ProcResource<1>; // Integer single/multicycle 049def V3UnitM1 : ProcResource<1>; // Integer single/multicycle 150def V3UnitV0 : ProcResource<1>; // FP/ASIMD 051def V3UnitV1 : ProcResource<1>; // FP/ASIMD 152def V3UnitV2 : ProcResource<1>; // FP/ASIMD 253def V3UnitV3 : ProcResource<1>; // FP/ASIMD 354def V3UnitLS0 : ProcResource<1>; // Load/Store 055def V3UnitL12 : ProcResource<2>; // Load 1/256def V3UnitST1 : ProcResource<1>; // Store 157def V3UnitD : ProcResource<2>; // Store data 0/158def V3UnitFlg : ProcResource<4>; // Flags59 60def V3UnitS : ProcResGroup<[V3UnitS0, V3UnitS1, V3UnitS2, V3UnitS3, V3UnitS4, V3UnitS5]>; // Integer single-cycle 0/1/2/3/4/561def V3UnitI : ProcResGroup<[V3UnitS0, V3UnitS1, V3UnitS2, V3UnitS3, V3UnitS4, V3UnitS5, V3UnitM0, V3UnitM1]>; // Integer single-cycle 0/1/2/3/4/5 and single/multicycle 0/162def V3UnitM : ProcResGroup<[V3UnitM0, V3UnitM1]>; // Integer single/multicycle 0/163def V3UnitLSA : ProcResGroup<[V3UnitLS0, V3UnitL12, V3UnitST1]>; // Supergroup of L+SA64def V3UnitL : ProcResGroup<[V3UnitLS0, V3UnitL12]>; // Load/Store 0 and Load 1/265def V3UnitSA : ProcResGroup<[V3UnitLS0, V3UnitST1]>; // Load/Store 0 and Store 166def V3UnitV : ProcResGroup<[V3UnitV0, V3UnitV1, V3UnitV2, V3UnitV3]>; // FP/ASIMD 0/1/2/367def V3UnitV01 : ProcResGroup<[V3UnitV0, V3UnitV1]>; // FP/ASIMD 0/168def V3UnitV02 : ProcResGroup<[V3UnitV0, V3UnitV2]>; // FP/ASIMD 0/269def V3UnitV13 : ProcResGroup<[V3UnitV1, V3UnitV3]>; // FP/ASIMD 1/370 71// Define commonly used read types.72 73// No forwarding is provided for these types.74def : ReadAdvance<ReadI, 0>;75def : ReadAdvance<ReadISReg, 0>;76def : ReadAdvance<ReadIEReg, 0>;77def : ReadAdvance<ReadIM, 0>;78def : ReadAdvance<ReadIMA, 0>;79def : ReadAdvance<ReadID, 0>;80def : ReadAdvance<ReadExtrHi, 0>;81def : ReadAdvance<ReadAdrBase, 0>;82def : ReadAdvance<ReadST, 0>;83def : ReadAdvance<ReadVLD, 0>;84 85// NOTE: Copied from N2.86def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }87def : WriteRes<WriteBarrier, []> { let Latency = 1; }88def : WriteRes<WriteHint, []> { let Latency = 1; }89def : WriteRes<WriteLDHi, []> { let Latency = 4; }90 91//===----------------------------------------------------------------------===//92// Define customized scheduler read/write types specific to the Neoverse V3.93 94//===----------------------------------------------------------------------===//95 96// Define generic 0 micro-op types97def V3Write_0c : SchedWriteRes<[]> { let Latency = 0; }98 99// Define generic 1 micro-op types100 101def V3Write_1c_1B : SchedWriteRes<[V3UnitB]> { let Latency = 1; }102def V3Write_1c_1F_1Flg : SchedWriteRes<[V3UnitI, V3UnitFlg]> { let Latency = 1; }103def V3Write_1c_1I : SchedWriteRes<[V3UnitI]> { let Latency = 1; }104def V3Write_1c_1M : SchedWriteRes<[V3UnitM]> { let Latency = 1; }105def V3Write_1c_1SA : SchedWriteRes<[V3UnitSA]> { let Latency = 1; }106def V3Write_2c_1M : SchedWriteRes<[V3UnitM]> { let Latency = 2; }107def V3Write_2c_1M_1Flg : SchedWriteRes<[V3UnitM, V3UnitFlg]> { let Latency = 2; }108def V3Write_3c_1M : SchedWriteRes<[V3UnitM]> { let Latency = 3; }109def V3Write_2c_1M0 : SchedWriteRes<[V3UnitM0]> { let Latency = 2; }110def V3Write_3c_1M0 : SchedWriteRes<[V3UnitM0]> { let Latency = 3; }111def V3Write_4c_1M0 : SchedWriteRes<[V3UnitM0]> { let Latency = 4; }112def V3Write_12c_1M0 : SchedWriteRes<[V3UnitM0]> { let Latency = 12;113 let ReleaseAtCycles = [12]; }114def V3Write_20c_1M0 : SchedWriteRes<[V3UnitM0]> { let Latency = 20;115 let ReleaseAtCycles = [20]; }116def V3Write_4c_1L : SchedWriteRes<[V3UnitL]> { let Latency = 4; }117def V3Write_6c_1L : SchedWriteRes<[V3UnitL]> { let Latency = 6; }118def V3Write_2c_1V : SchedWriteRes<[V3UnitV]> { let Latency = 2; }119def V3Write_2c_1V0 : SchedWriteRes<[V3UnitV0]> { let Latency = 2; }120def V3Write_3c_1V : SchedWriteRes<[V3UnitV]> { let Latency = 3; }121def V3Write_3c_1V01 : SchedWriteRes<[V3UnitV01]> { let Latency = 3;122 let ReleaseAtCycles = [2]; }123def V3Write_4c_1V : SchedWriteRes<[V3UnitV]> { let Latency = 4; }124def V3Write_5c_1V : SchedWriteRes<[V3UnitV]> { let Latency = 5; }125def V3Write_6c_1V : SchedWriteRes<[V3UnitV]> { let Latency = 6; }126def V3Write_12c_1V : SchedWriteRes<[V3UnitV]> { let Latency = 12; }127def V3Write_3c_1V0 : SchedWriteRes<[V3UnitV0]> { let Latency = 3; }128def V3Write_3c_1V02 : SchedWriteRes<[V3UnitV02]> { let Latency = 3; }129def V3Write_4c_1V0 : SchedWriteRes<[V3UnitV0]> { let Latency = 4; }130def V3Write_4c_1V02 : SchedWriteRes<[V3UnitV02]> { let Latency = 4; }131def V3Write_9c_1V0 : SchedWriteRes<[V3UnitV0]> { let Latency = 9; }132def V3Write_10c_1V0 : SchedWriteRes<[V3UnitV0]> { let Latency = 10; }133def V3Write_8c_1V1 : SchedWriteRes<[V3UnitV1]> { let Latency = 8; }134def V3Write_12c_1V0 : SchedWriteRes<[V3UnitV0]> { let Latency = 12;135 let ReleaseAtCycles = [11]; }136def V3Write_13c_1V0 : SchedWriteRes<[V3UnitV0]> { let Latency = 13; }137def V3Write_15c_1V0 : SchedWriteRes<[V3UnitV0]> { let Latency = 15; }138def V3Write_13c_1V1 : SchedWriteRes<[V3UnitV1]> { let Latency = 13; }139def V3Write_16c_1V0 : SchedWriteRes<[V3UnitV0]> { let Latency = 16; }140def V3Write_16c_1V02 : SchedWriteRes<[V3UnitV02]> { let Latency = 16;141 let ReleaseAtCycles = [8]; }142def V3Write_20c_1V0 : SchedWriteRes<[V3UnitV0]> { let Latency = 20;143 let ReleaseAtCycles = [20]; }144def V3Write_2c_1V1 : SchedWriteRes<[V3UnitV1]> { let Latency = 2; }145def V3Write_2c_1V13 : SchedWriteRes<[V3UnitV13]> { let Latency = 2; }146def V3Write_3c_1V1 : SchedWriteRes<[V3UnitV1]> { let Latency = 3; }147def V3Write_3c_1V13 : SchedWriteRes<[V3UnitV13]> { let Latency = 3; }148def V3Write_4c_1V1 : SchedWriteRes<[V3UnitV1]> { let Latency = 4; }149def V3Write_6c_1V1 : SchedWriteRes<[V3UnitV1]> { let Latency = 6; }150def V3Write_10c_1V1 : SchedWriteRes<[V3UnitV1]> { let Latency = 10; }151def V3Write_6c_1SA : SchedWriteRes<[V3UnitSA]> { let Latency = 6; }152 153//===----------------------------------------------------------------------===//154// Define generic 2 micro-op types155 156def V3Write_1c_1B_1S : SchedWriteRes<[V3UnitB, V3UnitS]> {157 let Latency = 1;158 let NumMicroOps = 2;159}160 161def V3Write_6c_1M0_1B : SchedWriteRes<[V3UnitM0, V3UnitB]> {162 let Latency = 6;163 let NumMicroOps = 2;164}165 166def V3Write_9c_1M0_1L : SchedWriteRes<[V3UnitM0, V3UnitL]> {167 let Latency = 9;168 let NumMicroOps = 2;169}170 171def V3Write_3c_1I_1M : SchedWriteRes<[V3UnitI, V3UnitM]> {172 let Latency = 3;173 let NumMicroOps = 2;174}175 176def V3Write_1c_2M : SchedWriteRes<[V3UnitM, V3UnitM]> {177 let Latency = 1;178 let NumMicroOps = 2;179}180 181def V3Write_3c_2M : SchedWriteRes<[V3UnitM, V3UnitM]> {182 let Latency = 3;183 let NumMicroOps = 2;184}185 186def V3Write_4c_2M : SchedWriteRes<[V3UnitM, V3UnitM]> {187 let Latency = 4;188 let NumMicroOps = 2;189}190 191def V3Write_5c_1L_1I : SchedWriteRes<[V3UnitL, V3UnitI]> {192 let Latency = 5;193 let NumMicroOps = 2;194}195 196def V3Write_6c_1I_1L : SchedWriteRes<[V3UnitI, V3UnitL]> {197 let Latency = 6;198 let NumMicroOps = 2;199}200 201def V3Write_7c_1I_1L : SchedWriteRes<[V3UnitI, V3UnitL]> {202 let Latency = 7;203 let NumMicroOps = 2;204}205 206def V3Write_1c_1SA_1D : SchedWriteRes<[V3UnitSA, V3UnitD]> {207 let Latency = 1;208 let NumMicroOps = 2;209}210 211def V3Write_5c_1M0_1V : SchedWriteRes<[V3UnitM0, V3UnitV]> {212 let Latency = 5;213 let NumMicroOps = 2;214}215 216def V3Write_2c_1SA_1V01 : SchedWriteRes<[V3UnitSA, V3UnitV01]> {217 let Latency = 2;218 let NumMicroOps = 2;219}220 221def V3Write_2c_2V01 : SchedWriteRes<[V3UnitV01, V3UnitV01]> {222 let Latency = 2;223 let NumMicroOps = 2;224}225 226def V3Write_4c_1SA_1V01 : SchedWriteRes<[V3UnitSA, V3UnitV01]> {227 let Latency = 4;228 let NumMicroOps = 2;229}230 231def V3Write_5c_1V13_1V : SchedWriteRes<[V3UnitV13, V3UnitV]> {232 let Latency = 5;233 let NumMicroOps = 2;234}235 236def V3Write_4c_2V0 : SchedWriteRes<[V3UnitV0, V3UnitV0]> {237 let Latency = 4;238 let NumMicroOps = 2;239}240 241def V3Write_4c_2V02 : SchedWriteRes<[V3UnitV02, V3UnitV02]> {242 let Latency = 4;243 let NumMicroOps = 2;244}245 246def V3Write_4c_2V : SchedWriteRes<[V3UnitV, V3UnitV]> {247 let Latency = 4;248 let NumMicroOps = 2;249}250 251def V3Write_6c_2V : SchedWriteRes<[V3UnitV, V3UnitV]> {252 let Latency = 6;253 let NumMicroOps = 2;254}255 256def V3Write_6c_2L : SchedWriteRes<[V3UnitL, V3UnitL]> {257 let Latency = 6;258 let NumMicroOps = 2;259}260 261def V3Write_8c_1L_1V : SchedWriteRes<[V3UnitL, V3UnitV]> {262 let Latency = 8;263 let NumMicroOps = 2;264}265 266def V3Write_4c_1SA_1V : SchedWriteRes<[V3UnitSA, V3UnitV]> {267 let Latency = 4;268 let NumMicroOps = 2;269}270 271def V3Write_3c_1M0_1M : SchedWriteRes<[V3UnitM0, V3UnitM]> {272 let Latency = 3;273 let NumMicroOps = 2;274}275 276def V3Write_4c_1M0_1M : SchedWriteRes<[V3UnitM0, V3UnitM]> {277 let Latency = 4;278 let NumMicroOps = 2;279}280 281def V3Write_1c_1M0_1M : SchedWriteRes<[V3UnitM0, V3UnitM]> {282 let Latency = 1;283 let NumMicroOps = 2;284}285 286def V3Write_2c_1M0_1M : SchedWriteRes<[V3UnitM0, V3UnitM]> {287 let Latency = 2;288 let NumMicroOps = 2;289}290 291def V3Write_6c_2V1 : SchedWriteRes<[V3UnitV1, V3UnitV1]> {292 let Latency = 6;293 let NumMicroOps = 2;294}295 296def V3Write_5c_2V0 : SchedWriteRes<[V3UnitV0, V3UnitV0]> {297 let Latency = 5;298 let NumMicroOps = 2;299}300 301def V3Write_5c_2V02 : SchedWriteRes<[V3UnitV02, V3UnitV02]> {302 let Latency = 5;303 let NumMicroOps = 2;304}305 306def V3Write_5c_1V1_1M0 : SchedWriteRes<[V3UnitV1, V3UnitM0]> {307 let Latency = 5;308 let NumMicroOps = 2;309}310 311def V3Write_6c_1V1_1M0 : SchedWriteRes<[V3UnitV1, V3UnitM0]> {312 let Latency = 6;313 let NumMicroOps = 2;314}315 316def V3Write_7c_1M0_1V02 : SchedWriteRes<[V3UnitM0, V3UnitV02]> {317 let Latency = 7;318 let NumMicroOps = 2;319}320 321def V3Write_2c_1V0_1M : SchedWriteRes<[V3UnitV0, V3UnitM]> {322 let Latency = 2;323 let NumMicroOps = 2;324}325 326def V3Write_3c_1V0_1M : SchedWriteRes<[V3UnitV0, V3UnitM]> {327 let Latency = 3;328 let NumMicroOps = 2;329}330 331def V3Write_6c_1V_1V13 : SchedWriteRes<[V3UnitV, V3UnitV13]> {332 let Latency = 6;333 let NumMicroOps = 2;334}335 336def V3Write_6c_1L_1M : SchedWriteRes<[V3UnitL, V3UnitM]> {337 let Latency = 6;338 let NumMicroOps = 2;339}340 341def V3Write_6c_1L_1I : SchedWriteRes<[V3UnitL, V3UnitI]> {342 let Latency = 6;343 let NumMicroOps = 2;344}345 346def V3Write_6c_2V13 : SchedWriteRes<[V3UnitV13, V3UnitV13]> {347 let Latency = 6;348 let NumMicroOps = 2;349}350 351def V3Write_8c_1M0_1V01 : SchedWriteRes<[V3UnitM0, V3UnitV01]> {352 let Latency = 8;353 let NumMicroOps = 2;354}355 356//===----------------------------------------------------------------------===//357// Define generic 3 micro-op types358 359def V3Write_1c_1SA_1D_1I : SchedWriteRes<[V3UnitSA, V3UnitD, V3UnitI]> {360 let Latency = 1;361 let NumMicroOps = 3;362}363 364def V3Write_2c_1SA_1V01_1I : SchedWriteRes<[V3UnitSA, V3UnitV01, V3UnitI]> {365 let Latency = 2;366 let NumMicroOps = 3;367}368 369def V3Write_2c_1SA_2V01 : SchedWriteRes<[V3UnitSA, V3UnitV01, V3UnitV01]> {370 let Latency = 2;371 let NumMicroOps = 3;372}373 374def V3Write_4c_1SA_2V01 : SchedWriteRes<[V3UnitSA, V3UnitV01, V3UnitV01]> {375 let Latency = 4;376 let NumMicroOps = 3;377}378 379def V3Write_9c_1L_2V : SchedWriteRes<[V3UnitL, V3UnitV, V3UnitV]> {380 let Latency = 9;381 let NumMicroOps = 3;382}383 384def V3Write_4c_3V : SchedWriteRes<[V3UnitV, V3UnitV, V3UnitV]> {385 let Latency = 4;386 let NumMicroOps = 3;387}388 389def V3Write_7c_1M_1M0_1V : SchedWriteRes<[V3UnitM, V3UnitM0, V3UnitV]> {390 let Latency = 7;391 let NumMicroOps = 3;392}393 394def V3Write_2c_1SA_1I_1V01 : SchedWriteRes<[V3UnitSA, V3UnitI, V3UnitV01]> {395 let Latency = 2;396 let NumMicroOps = 3;397}398 399def V3Write_6c_3L : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitL]> {400 let Latency = 6;401 let NumMicroOps = 3;402}403 404def V3Write_6c_3V : SchedWriteRes<[V3UnitV, V3UnitV, V3UnitV]> {405 let Latency = 6;406 let NumMicroOps = 3;407}408 409def V3Write_8c_1L_2V : SchedWriteRes<[V3UnitL, V3UnitV, V3UnitV]> {410 let Latency = 8;411 let NumMicroOps = 3;412}413 414//===----------------------------------------------------------------------===//415// Define generic 4 micro-op types416 417def V3Write_2c_1SA_2V01_1I : SchedWriteRes<[V3UnitSA, V3UnitV01, V3UnitV01,418 V3UnitI]> {419 let Latency = 2;420 let NumMicroOps = 4;421}422 423def V3Write_2c_2SA_2V01 : SchedWriteRes<[V3UnitSA, V3UnitSA,424 V3UnitV01, V3UnitV01]> {425 let Latency = 2;426 let NumMicroOps = 4;427}428 429def V3Write_4c_2SA_2V01 : SchedWriteRes<[V3UnitSA, V3UnitSA,430 V3UnitV01, V3UnitV01]> {431 let Latency = 4;432 let NumMicroOps = 4;433}434 435def V3Write_5c_1I_3L : SchedWriteRes<[V3UnitI, V3UnitL, V3UnitL, V3UnitL]> {436 let Latency = 5;437 let NumMicroOps = 4;438}439 440def V3Write_6c_4V0 : SchedWriteRes<[V3UnitV0, V3UnitV0, V3UnitV0, V3UnitV0]> {441 let Latency = 6;442 let NumMicroOps = 4;443}444 445def V3Write_8c_4V : SchedWriteRes<[V3UnitV, V3UnitV, V3UnitV, V3UnitV]> {446 let Latency = 8;447 let NumMicroOps = 4;448}449 450def V3Write_6c_2V_2V13 : SchedWriteRes<[V3UnitV, V3UnitV, V3UnitV13,451 V3UnitV13]> {452 let Latency = 6;453 let NumMicroOps = 4;454}455 456def V3Write_8c_2V_2V13 : SchedWriteRes<[V3UnitV, V3UnitV, V3UnitV13,457 V3UnitV13]> {458 let Latency = 8;459 let NumMicroOps = 4;460}461 462def V3Write_6c_4V02 : SchedWriteRes<[V3UnitV02, V3UnitV02, V3UnitV02,463 V3UnitV02]> {464 let Latency = 6;465 let NumMicroOps = 4;466}467 468def V3Write_6c_4V : SchedWriteRes<[V3UnitV, V3UnitV, V3UnitV, V3UnitV]> {469 let Latency = 6;470 let NumMicroOps = 4;471}472 473def V3Write_8c_2L_2V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitV, V3UnitV]> {474 let Latency = 8;475 let NumMicroOps = 4;476}477 478def V3Write_9c_2L_2V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitV, V3UnitV]> {479 let Latency = 9;480 let NumMicroOps = 4;481}482 483def V3Write_2c_2SA_2V : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitV,484 V3UnitV]> {485 let Latency = 2;486 let NumMicroOps = 4;487}488 489def V3Write_4c_2SA_2V : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitV,490 V3UnitV]> {491 let Latency = 4;492 let NumMicroOps = 4;493}494 495def V3Write_8c_2M0_2V02 : SchedWriteRes<[V3UnitM0, V3UnitM0, V3UnitV02,496 V3UnitV02]> {497 let Latency = 8;498 let NumMicroOps = 4;499}500 501def V3Write_8c_2V_2V1 : SchedWriteRes<[V3UnitV, V3UnitV, V3UnitV1,502 V3UnitV1]> {503 let Latency = 8;504 let NumMicroOps = 4;505}506 507def V3Write_4c_2M0_2M : SchedWriteRes<[V3UnitM0, V3UnitM0, V3UnitM,508 V3UnitM]> {509 let Latency = 4;510 let NumMicroOps = 4;511}512 513def V3Write_5c_2M0_2M : SchedWriteRes<[V3UnitM0, V3UnitM0, V3UnitM,514 V3UnitM]> {515 let Latency = 5;516 let NumMicroOps = 4;517}518 519def V3Write_6c_2I_2L : SchedWriteRes<[V3UnitI, V3UnitI, V3UnitL, V3UnitL]> {520 let Latency = 6;521 let NumMicroOps = 4;522}523 524def V3Write_7c_4L : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitL, V3UnitL]> {525 let Latency = 7;526 let NumMicroOps = 4;527}528 529def V3Write_6c_1SA_3V01 : SchedWriteRes<[V3UnitSA, V3UnitV01, V3UnitV01,530 V3UnitV01]> {531 let Latency = 6;532 let NumMicroOps = 4;533}534 535//===----------------------------------------------------------------------===//536// Define generic 5 micro-op types537 538def V3Write_2c_1SA_2V01_2I : SchedWriteRes<[V3UnitSA, V3UnitV01, V3UnitV01,539 V3UnitI, V3UnitI]> {540 let Latency = 2;541 let NumMicroOps = 5;542}543 544def V3Write_8c_2L_3V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitV, V3UnitV,545 V3UnitV]> {546 let Latency = 8;547 let NumMicroOps = 5;548}549 550def V3Write_9c_1L_4V : SchedWriteRes<[V3UnitL, V3UnitV, V3UnitV, V3UnitV,551 V3UnitV]> {552 let Latency = 9;553 let NumMicroOps = 5;554}555 556def V3Write_10c_1L_4V : SchedWriteRes<[V3UnitL, V3UnitV, V3UnitV, V3UnitV,557 V3UnitV]> {558 let Latency = 10;559 let NumMicroOps = 5;560}561 562def V3Write_6c_5V : SchedWriteRes<[V3UnitV, V3UnitV, V3UnitV, V3UnitV,563 V3UnitV]> {564 let Latency = 6;565 let NumMicroOps = 5;566}567 568//===----------------------------------------------------------------------===//569// Define generic 6 micro-op types570 571def V3Write_8c_3L_3V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitL,572 V3UnitV, V3UnitV, V3UnitV]> {573 let Latency = 8;574 let NumMicroOps = 6;575}576 577def V3Write_9c_3L_3V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitL,578 V3UnitV, V3UnitV, V3UnitV]> {579 let Latency = 9;580 let NumMicroOps = 6;581}582 583def V3Write_9c_2L_4V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitV,584 V3UnitV, V3UnitV, V3UnitV]> {585 let Latency = 9;586 let NumMicroOps = 6;587}588 589def V3Write_9c_2L_2V_2I : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitV,590 V3UnitV, V3UnitI, V3UnitI]> {591 let Latency = 9;592 let NumMicroOps = 6;593}594 595def V3Write_9c_2V_4V13 : SchedWriteRes<[V3UnitV, V3UnitV, V3UnitV13,596 V3UnitV13, V3UnitV13, V3UnitV13]> {597 let Latency = 9;598 let NumMicroOps = 6;599}600 601def V3Write_2c_3SA_3V : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,602 V3UnitV, V3UnitV, V3UnitV]> {603 let Latency = 2;604 let NumMicroOps = 6;605}606 607def V3Write_4c_2SA_4V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitV01,608 V3UnitV01, V3UnitV01, V3UnitV01]> {609 let Latency = 4;610 let NumMicroOps = 6;611}612 613def V3Write_5c_2SA_4V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitV01,614 V3UnitV01, V3UnitV01, V3UnitV01]> {615 let Latency = 5;616 let NumMicroOps = 6;617}618 619def V3Write_2c_3SA_3V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,620 V3UnitV01, V3UnitV01, V3UnitV01]> {621 let Latency = 2;622 let NumMicroOps = 6;623}624 625def V3Write_4c_2SA_2I_2V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitI,626 V3UnitI, V3UnitV01, V3UnitV01]> {627 let Latency = 4;628 let NumMicroOps = 6;629}630 631//===----------------------------------------------------------------------===//632// Define generic 7 micro-op types633 634def V3Write_8c_3L_4V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitL,635 V3UnitV, V3UnitV, V3UnitV, V3UnitV]> {636 let Latency = 8;637 let NumMicroOps = 7;638}639 640//===----------------------------------------------------------------------===//641// Define generic 8 micro-op types642 643def V3Write_2c_4SA_4V : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,644 V3UnitSA, V3UnitV, V3UnitV, V3UnitV,645 V3UnitV]> {646 let Latency = 2;647 let NumMicroOps = 8;648}649 650def V3Write_2c_4SA_4V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,651 V3UnitSA, V3UnitV01, V3UnitV01,652 V3UnitV01, V3UnitV01]> {653 let Latency = 2;654 let NumMicroOps = 8;655}656 657def V3Write_6c_2SA_6V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitV01,658 V3UnitV01, V3UnitV01, V3UnitV01,659 V3UnitV01, V3UnitV01]> {660 let Latency = 6;661 let NumMicroOps = 8;662}663 664def V3Write_8c_4L_4V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitL, V3UnitL,665 V3UnitV, V3UnitV, V3UnitV, V3UnitV]> {666 let Latency = 8;667 let NumMicroOps = 8;668}669 670//===----------------------------------------------------------------------===//671// Define generic 9 micro-op types672 673def V3Write_6c_3SA_6V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,674 V3UnitV01, V3UnitV01, V3UnitV01,675 V3UnitV01, V3UnitV01, V3UnitV01]> {676 let Latency = 6;677 let NumMicroOps = 9;678}679 680def V3Write_10c_1L_8V : SchedWriteRes<[V3UnitL, V3UnitV, V3UnitV, V3UnitV,681 V3UnitV, V3UnitV, V3UnitV, V3UnitV,682 V3UnitV]> {683 let Latency = 10;684 let NumMicroOps = 9;685}686 687def V3Write_10c_3V_3L_3I : SchedWriteRes<[V3UnitV, V3UnitV, V3UnitV,688 V3UnitL, V3UnitL, V3UnitL,689 V3UnitI, V3UnitI, V3UnitI]> {690 let Latency = 10;691 let NumMicroOps = 9;692}693 694//===----------------------------------------------------------------------===//695// Define generic 10 micro-op types696 697def V3Write_9c_6L_4V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitL, V3UnitL,698 V3UnitL, V3UnitL, V3UnitV, V3UnitV,699 V3UnitV, V3UnitV]> {700 let Latency = 9;701 let NumMicroOps = 10;702}703 704//===----------------------------------------------------------------------===//705// Define generic 12 micro-op types706 707def V3Write_5c_4SA_8V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,708 V3UnitSA, V3UnitV01, V3UnitV01,709 V3UnitV01, V3UnitV01, V3UnitV01,710 V3UnitV01, V3UnitV01, V3UnitV01]> {711 let Latency = 5;712 let NumMicroOps = 12;713}714 715def V3Write_9c_4L_8V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitL,716 V3UnitL, V3UnitV, V3UnitV,717 V3UnitV, V3UnitV, V3UnitV,718 V3UnitV, V3UnitV, V3UnitV]> {719 let Latency = 9;720 let NumMicroOps = 12;721}722 723def V3Write_10c_4L_8V : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitL,724 V3UnitL, V3UnitV, V3UnitV,725 V3UnitV, V3UnitV, V3UnitV,726 V3UnitV, V3UnitV, V3UnitV]> {727 let Latency = 10;728 let NumMicroOps = 12;729}730 731def V3Write_4c_6SA_6V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,732 V3UnitSA, V3UnitSA, V3UnitSA,733 V3UnitV01, V3UnitV01, V3UnitV01,734 V3UnitV01, V3UnitV01, V3UnitV01]> {735 let Latency = 4;736 let NumMicroOps = 12;737}738 739//===----------------------------------------------------------------------===//740// Define generic 16 micro-op types741 742def V3Write_7c_4SA_12V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,743 V3UnitSA, V3UnitV01, V3UnitV01,744 V3UnitV01, V3UnitV01, V3UnitV01,745 V3UnitV01, V3UnitV01, V3UnitV01,746 V3UnitV01, V3UnitV01, V3UnitV01,747 V3UnitV01]> {748 let Latency = 7;749 let NumMicroOps = 16;750}751 752def V3Write_10c_4L_8V_4I : SchedWriteRes<[V3UnitL, V3UnitL, V3UnitL,753 V3UnitL, V3UnitV, V3UnitV,754 V3UnitV, V3UnitV, V3UnitV,755 V3UnitV, V3UnitV, V3UnitV,756 V3UnitI, V3UnitI, V3UnitI,757 V3UnitI]> {758 let Latency = 10;759 let NumMicroOps = 16;760}761 762//===----------------------------------------------------------------------===//763// Define generic 18 micro-op types764 765def V3Write_7c_9SA_9V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,766 V3UnitSA, V3UnitSA, V3UnitSA,767 V3UnitSA, V3UnitSA, V3UnitSA,768 V3UnitV01, V3UnitV01, V3UnitV01,769 V3UnitV01, V3UnitV01, V3UnitV01,770 V3UnitV01, V3UnitV01, V3UnitV01]> {771 let Latency = 7;772 let NumMicroOps = 18;773}774 775//===----------------------------------------------------------------------===//776// Define generic 27 micro-op types777 778def V3Write_7c_9SA_9I_9V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,779 V3UnitSA, V3UnitSA, V3UnitSA,780 V3UnitSA, V3UnitSA, V3UnitSA,781 V3UnitI, V3UnitI, V3UnitI,782 V3UnitI, V3UnitI, V3UnitI,783 V3UnitI, V3UnitI, V3UnitI,784 V3UnitV01, V3UnitV01, V3UnitV01,785 V3UnitV01, V3UnitV01, V3UnitV01,786 V3UnitV01, V3UnitV01,787 V3UnitV01]> {788 let Latency = 7;789 let NumMicroOps = 27;790}791 792//===----------------------------------------------------------------------===//793// Define generic 36 micro-op types794 795def V3Write_11c_18SA_18V01 : SchedWriteRes<[V3UnitSA, V3UnitSA, V3UnitSA,796 V3UnitSA, V3UnitSA, V3UnitSA,797 V3UnitSA, V3UnitSA, V3UnitSA,798 V3UnitSA, V3UnitSA, V3UnitSA,799 V3UnitSA, V3UnitSA, V3UnitSA,800 V3UnitSA, V3UnitSA, V3UnitSA,801 V3UnitV01, V3UnitV01, V3UnitV01,802 V3UnitV01, V3UnitV01, V3UnitV01,803 V3UnitV01, V3UnitV01, V3UnitV01,804 V3UnitV01, V3UnitV01, V3UnitV01,805 V3UnitV01, V3UnitV01, V3UnitV01,806 V3UnitV01, V3UnitV01,807 V3UnitV01]> {808 let Latency = 11;809 let NumMicroOps = 36;810}811 812//===----------------------------------------------------------------------===//813// Define generic 54 micro-op types814 815def V3Write_11c_18SA_18I_18V01 : SchedWriteRes<[V3UnitSA, V3UnitSA,816 V3UnitSA, V3UnitSA,817 V3UnitSA, V3UnitSA,818 V3UnitSA, V3UnitSA,819 V3UnitSA, V3UnitSA,820 V3UnitSA, V3UnitSA,821 V3UnitSA, V3UnitSA,822 V3UnitSA, V3UnitSA,823 V3UnitSA, V3UnitSA,824 V3UnitI, V3UnitI, V3UnitI,825 V3UnitI, V3UnitI, V3UnitI,826 V3UnitI, V3UnitI, V3UnitI,827 V3UnitI, V3UnitI, V3UnitI,828 V3UnitI, V3UnitI, V3UnitI,829 V3UnitI, V3UnitI, V3UnitI,830 V3UnitV01, V3UnitV01,831 V3UnitV01, V3UnitV01,832 V3UnitV01, V3UnitV01,833 V3UnitV01, V3UnitV01,834 V3UnitV01, V3UnitV01,835 V3UnitV01, V3UnitV01,836 V3UnitV01, V3UnitV01,837 V3UnitV01, V3UnitV01,838 V3UnitV01, V3UnitV01]> {839 let Latency = 11;840 let NumMicroOps = 54;841}842 843//===----------------------------------------------------------------------===//844// Define predicate-controlled types845 846def V3Write_ArithI : SchedWriteVariant<[847 SchedVar<IsCheapLSL, [V3Write_1c_1I]>,848 SchedVar<NoSchedPred, [V3Write_2c_1M]>]>;849 850def V3Write_ArithF : SchedWriteVariant<[851 SchedVar<IsCheapLSL, [V3Write_1c_1F_1Flg]>,852 SchedVar<NoSchedPred, [V3Write_2c_1M_1Flg]>]>;853 854def V3Write_Logical : SchedWriteVariant<[855 SchedVar<NeoverseNoLSL, [V3Write_1c_1F_1Flg]>,856 SchedVar<NoSchedPred, [V3Write_2c_1M_1Flg]>]>;857 858def V3Write_Extr : SchedWriteVariant<[859 SchedVar<IsRORImmIdiomPred, [V3Write_1c_1I]>,860 SchedVar<NoSchedPred, [V3Write_3c_1I_1M]>]>;861 862def V3Write_LdrHQ : SchedWriteVariant<[863 SchedVar<NeoverseHQForm, [V3Write_7c_1I_1L]>,864 SchedVar<NoSchedPred, [V3Write_6c_1L]>]>;865 866def V3Write_StrHQ : SchedWriteVariant<[867 SchedVar<NeoverseHQForm, [V3Write_2c_1SA_1V01_1I]>,868 SchedVar<NoSchedPred, [V3Write_2c_1SA_1V01]>]>;869 870def V3Write_0or1c_1I : SchedWriteVariant<[871 SchedVar<NeoverseZeroMove, [V3Write_0c]>,872 SchedVar<NoSchedPred, [V3Write_1c_1I]>]>;873 874def V3Write_0or2c_1V : SchedWriteVariant<[875 SchedVar<NeoverseZeroMove, [V3Write_0c]>,876 SchedVar<NoSchedPred, [V3Write_2c_1V]>]>;877 878def V3Write_0or3c_1M0 : SchedWriteVariant<[879 SchedVar<NeoverseZeroMove, [V3Write_0c]>,880 SchedVar<NoSchedPred, [V3Write_3c_1M0]>]>;881 882def V3Write_2or3c_1M : SchedWriteVariant<[883 SchedVar<NeoversePdIsPg, [V3Write_3c_1M]>,884 SchedVar<NoSchedPred, [V3Write_2c_1M]>]>;885 886def V3Write_1or2c_1M : SchedWriteVariant<[887 SchedVar<NeoversePdIsPg, [V3Write_2c_1M]>,888 SchedVar<NoSchedPred, [V3Write_1c_1M]>]>;889 890def V3Write_3or4c_1M0_1M : SchedWriteVariant<[891 SchedVar<NeoversePdIsPg, [V3Write_4c_1M0_1M]>,892 SchedVar<NoSchedPred, [V3Write_3c_1M0_1M]>]>;893 894def V3Write_2or3c_1V0 : SchedWriteVariant<[895 SchedVar<NeoversePdIsPg, [V3Write_3c_1V0]>,896 SchedVar<NoSchedPred, [V3Write_2c_1V0]>]>;897 898def V3Write_2or3c_1V0_1M : SchedWriteVariant<[899 SchedVar<NeoversePdIsPg, [V3Write_3c_1V0_1M]>,900 SchedVar<NoSchedPred, [V3Write_2c_1V0_1M]>]>;901 902def V3Write_IncDec : SchedWriteVariant<[903 SchedVar<NeoverseCheapIncDec, [V3Write_1c_1I]>,904 SchedVar<NoSchedPred, [V3Write_2c_1M]>]>;905 906//===----------------------------------------------------------------------===//907// Define forwarded types908 909// NOTE: SOG, p. 16, n. 2: Accumulator forwarding is not supported for910// consumers of 64 bit multiply high operations?911def V3Wr_IM : SchedWriteRes<[V3UnitM]> { let Latency = 2; }912 913def V3Wr_FMA : SchedWriteRes<[V3UnitV]> { let Latency = 4; }914def V3Rd_FMA : SchedReadAdvance<2, [WriteFMul, V3Wr_FMA]>;915 916def V3Wr_VA : SchedWriteRes<[V3UnitV]> { let Latency = 4; }917def V3Rd_VA : SchedReadAdvance<3, [V3Wr_VA]>;918 919def V3Wr_VDOT : SchedWriteRes<[V3UnitV]> { let Latency = 3; }920def V3Rd_VDOT : SchedReadAdvance<2, [V3Wr_VDOT]>;921 922def V3Wr_VMMA : SchedWriteRes<[V3UnitV]> { let Latency = 3; }923def V3Rd_VMMA : SchedReadAdvance<2, [V3Wr_VMMA]>;924 925def V3Wr_VMA : SchedWriteRes<[V3UnitV02]> { let Latency = 4; }926def V3Rd_VMA : SchedReadAdvance<3, [V3Wr_VMA]>;927 928def V3Wr_VMAH : SchedWriteRes<[V3UnitV02, V3UnitV02]> { let Latency = 4; }929def V3Rd_VMAH : SchedReadAdvance<2, [V3Wr_VMAH]>;930 931def V3Wr_VMAL : SchedWriteRes<[V3UnitV02]> { let Latency = 4; }932def V3Rd_VMAL : SchedReadAdvance<3, [V3Wr_VMAL]>;933 934def V3Wr_VPA : SchedWriteRes<[V3UnitV]> { let Latency = 4; }935def V3Rd_VPA : SchedReadAdvance<3, [V3Wr_VPA]>;936 937def V3Wr_VSA : SchedWriteRes<[V3UnitV]> { let Latency = 4; }938def V3Rd_VSA : SchedReadAdvance<3, [V3Wr_VSA]>;939 940def V3Wr_VFCMA : SchedWriteRes<[V3UnitV]> { let Latency = 4; }941def V3Rd_VFCMA : SchedReadAdvance<2, [V3Wr_VFCMA]>;942 943def V3Wr_VFM : SchedWriteRes<[V3UnitV]> { let Latency = 3; }944def V3Wr_VFMA : SchedWriteRes<[V3UnitV]> { let Latency = 4; }945def V3Rd_VFMA : SchedReadAdvance<2, [V3Wr_VFM, V3Wr_VFMA]>;946 947def V3Wr_VFMAL : SchedWriteRes<[V3UnitV]> { let Latency = 4; }948def V3Rd_VFMAL : SchedReadAdvance<2, [V3Wr_VFMAL]>;949 950def V3Wr_VBFDOT : SchedWriteRes<[V3UnitV]> { let Latency = 5; }951def V3Rd_VBFDOT : SchedReadAdvance<2, [V3Wr_VBFDOT]>;952def V3Wr_VBFMMA : SchedWriteRes<[V3UnitV]> { let Latency = 6; }953def V3Rd_VBFMMA : SchedReadAdvance<2, [V3Wr_VBFMMA]>;954def V3Wr_VBFMAL : SchedWriteRes<[V3UnitV]> { let Latency = 5; }955def V3Rd_VBFMAL : SchedReadAdvance<3, [V3Wr_VBFMAL]>;956 957def V3Wr_CRC : SchedWriteRes<[V3UnitM0]> { let Latency = 2; }958def V3Rd_CRC : SchedReadAdvance<1, [V3Wr_CRC]>;959 960def V3Wr_ZA : SchedWriteRes<[V3UnitV]> { let Latency = 4; }961def V3Rd_ZA : SchedReadAdvance<3, [V3Wr_ZA]>;962def V3Wr_ZPA : SchedWriteRes<[V3UnitV]> { let Latency = 4; }963def V3Rd_ZPA : SchedReadAdvance<3, [V3Wr_ZPA]>;964def V3Wr_ZSA : SchedWriteRes<[V3UnitV13]> { let Latency = 4; }965def V3Rd_ZSA : SchedReadAdvance<3, [V3Wr_ZSA]>;966 967def V3Wr_ZDOTB : SchedWriteRes<[V3UnitV]> { let Latency = 3; }968def V3Rd_ZDOTB : SchedReadAdvance<2, [V3Wr_ZDOTB]>;969def V3Wr_ZDOTH : SchedWriteRes<[V3UnitV02]> { let Latency = 3; }970def V3Rd_ZDOTH : SchedReadAdvance<2, [V3Wr_ZDOTH]>;971 972// NOTE: SOG p. 43: Complex multiply-add B, H, S element size: How to reduce973// throughput to 1 in case of forwarding?974def V3Wr_ZCMABHS : SchedWriteRes<[V3UnitV02]> { let Latency = 4; }975def V3Rd_ZCMABHS : SchedReadAdvance<3, [V3Wr_ZCMABHS]>;976def V3Wr_ZCMAD : SchedWriteRes<[V3UnitV02, V3UnitV02]> { let Latency = 5; }977def V3Rd_ZCMAD : SchedReadAdvance<2, [V3Wr_ZCMAD]>;978 979def V3Wr_ZMMA : SchedWriteRes<[V3UnitV]> { let Latency = 3; }980def V3Rd_ZMMA : SchedReadAdvance<2, [V3Wr_ZMMA]>;981 982def V3Wr_ZMABHS : SchedWriteRes<[V3UnitV02]> { let Latency = 4; }983def V3Rd_ZMABHS : SchedReadAdvance<3, [V3Wr_ZMABHS]>;984def V3Wr_ZMAD : SchedWriteRes<[V3UnitV02, V3UnitV02]> { let Latency = 5; }985def V3Rd_ZMAD : SchedReadAdvance<2, [V3Wr_ZMAD]>;986 987def V3Wr_ZMAL : SchedWriteRes<[V3UnitV02]> { let Latency = 4; }988def V3Rd_ZMAL : SchedReadAdvance<3, [V3Wr_ZMAL]>;989 990def V3Wr_ZMASQL : SchedWriteRes<[V3UnitV02]> { let Latency = 4; }991def V3Wr_ZMASQBHS : SchedWriteRes<[V3UnitV02]> { let Latency = 4; }992def V3Wr_ZMASQD : SchedWriteRes<[V3UnitV02, V3UnitV02]> { let Latency = 5; }993def V3Rd_ZMASQ : SchedReadAdvance<2, [V3Wr_ZMASQL, V3Wr_ZMASQBHS,994 V3Wr_ZMASQD]>;995 996def V3Wr_ZFCMA : SchedWriteRes<[V3UnitV]> { let Latency = 5; }997def V3Rd_ZFCMA : SchedReadAdvance<3, [V3Wr_ZFCMA]>;998 999def V3Wr_ZFMA : SchedWriteRes<[V3UnitV]> { let Latency = 4; }1000def V3Rd_ZFMA : SchedReadAdvance<2, [V3Wr_ZFMA]>;1001 1002def V3Wr_ZFMAL : SchedWriteRes<[V3UnitV]> { let Latency = 4; }1003def V3Rd_ZFMAL : SchedReadAdvance<2, [V3Wr_ZFMAL]>;1004 1005def V3Wr_ZBFDOT : SchedWriteRes<[V3UnitV]> { let Latency = 5; }1006def V3Rd_ZBFDOT : SchedReadAdvance<2, [V3Wr_ZBFDOT]>;1007def V3Wr_ZBFMMA : SchedWriteRes<[V3UnitV]> { let Latency = 6; }1008def V3Rd_ZBFMMA : SchedReadAdvance<2, [V3Wr_ZBFMMA]>;1009def V3Wr_ZBFMAL : SchedWriteRes<[V3UnitV]> { let Latency = 5; }1010def V3Rd_ZBFMAL : SchedReadAdvance<3, [V3Wr_ZBFMAL]>;1011 1012//===----------------------------------------------------------------------===//1013// Define types with long resource cycles (rc)1014 1015def V3Write_6c_1V1_5rc : SchedWriteRes<[V3UnitV1]> { let Latency = 6; let ReleaseAtCycles = [ 5]; }1016def V3Write_9c_1V1_2rc : SchedWriteRes<[V3UnitV1]> { let Latency = 9; let ReleaseAtCycles = [ 2]; }1017def V3Write_9c_1V1_4rc : SchedWriteRes<[V3UnitV1]> { let Latency = 9; let ReleaseAtCycles = [ 4]; }1018def V3Write_10c_1V1_9rc : SchedWriteRes<[V3UnitV1]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }1019def V3Write_11c_1V1_4rc : SchedWriteRes<[V3UnitV1]> { let Latency = 11; let ReleaseAtCycles = [ 4]; }1020def V3Write_13c_1V1_8rc : SchedWriteRes<[V3UnitV1]> { let Latency = 13; let ReleaseAtCycles = [8]; }1021def V3Write_14c_1V1_2rc : SchedWriteRes<[V3UnitV1]> { let Latency = 14; let ReleaseAtCycles = [2]; }1022 1023// Miscellaneous1024// -----------------------------------------------------------------------------1025 1026def : InstRW<[WriteI], (instrs COPY)>;1027 1028// §3.3 Branch instructions1029// -----------------------------------------------------------------------------1030 1031// Branch, immed1032// Compare and branch1033def : SchedAlias<WriteBr, V3Write_1c_1B>;1034 1035// Branch, register1036def : SchedAlias<WriteBrReg, V3Write_1c_1B>;1037 1038// Branch and link, immed1039// Branch and link, register1040def : InstRW<[V3Write_1c_1B_1S], (instrs BL, BLR)>;1041 1042// §3.4 Arithmetic and Logical Instructions1043// -----------------------------------------------------------------------------1044 1045// ALU, basic1046def : SchedAlias<WriteI, V3Write_1c_1I>;1047 1048// ALU, basic, flagset1049def : InstRW<[V3Write_1c_1F_1Flg],1050 (instregex "^(ADD|SUB)S[WX]r[ir]$",1051 "^(ADC|SBC)S[WX]r$",1052 "^ANDS[WX]ri$",1053 "^(AND|BIC)S[WX]rr$")>;1054def : InstRW<[V3Write_0or1c_1I], (instregex "^MOVZ[WX]i$")>;1055 1056// ALU, extend and shift1057def : SchedAlias<WriteIEReg, V3Write_2c_1M>;1058 1059// Arithmetic, LSL shift, shift <= 41060// Arithmetic, flagset, LSL shift, shift <= 41061// Arithmetic, LSR/ASR/ROR shift or LSL shift > 41062def : SchedAlias<WriteISReg, V3Write_ArithI>;1063def : InstRW<[V3Write_ArithF],1064 (instregex "^(ADD|SUB)S[WX]rs$")>;1065 1066// Arithmetic, immediate to logical address tag1067def : InstRW<[V3Write_2c_1M], (instrs ADDG, SUBG)>;1068 1069// Conditional compare1070def : InstRW<[V3Write_1c_1F_1Flg], (instregex "^CCM[NP][WX][ir]")>;1071 1072// Convert floating-point condition flags1073// Flag manipulation instructions1074def : WriteRes<WriteSys, []> { let Latency = 1; }1075 1076// Insert Random Tags1077def : InstRW<[V3Write_2c_1M], (instrs IRG, IRGstack)>;1078 1079// Insert Tag Mask1080// Subtract Pointer1081def : InstRW<[V3Write_1c_1I], (instrs GMI, SUBP)>;1082 1083// Subtract Pointer, flagset1084def : InstRW<[V3Write_1c_1F_1Flg], (instrs SUBPS)>;1085 1086// Logical, shift, no flagset1087def : InstRW<[V3Write_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;1088def : InstRW<[V3Write_0or1c_1I], (instregex "^ORR[WX]rs$")>;1089 1090// Logical, shift, flagset1091def : InstRW<[V3Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;1092 1093// Move and shift instructions1094// -----------------------------------------------------------------------------1095 1096def : SchedAlias<WriteImm, V3Write_1c_1I>;1097 1098// §3.5 Divide and multiply instructions1099// -----------------------------------------------------------------------------1100 1101// SDIV, UDIV1102def : SchedAlias<WriteID32, V3Write_12c_1M0>;1103def : SchedAlias<WriteID64, V3Write_20c_1M0>;1104 1105def : SchedAlias<WriteIM32, V3Write_2c_1M>;1106def : SchedAlias<WriteIM64, V3Write_2c_1M>;1107 1108// Multiply1109// Multiply accumulate, W-form1110// Multiply accumulate, X-form1111def : InstRW<[V3Wr_IM], (instregex "^M(ADD|SUB)[WX]rrr$")>;1112 1113// Multiply accumulate long1114// Multiply long1115def : InstRW<[V3Wr_IM], (instregex "^(S|U)M(ADD|SUB)Lrrr$")>;1116 1117// Multiply high1118def : InstRW<[V3Write_3c_1M], (instrs SMULHrr, UMULHrr)>;1119 1120// §3.6 Pointer Authentication Instructions (v8.3 PAC)1121// -----------------------------------------------------------------------------1122 1123// Authenticate data address1124// Authenticate instruction address1125// Compute pointer authentication code for data address1126// Compute pointer authentication code, using generic key1127// Compute pointer authentication code for instruction address1128def : InstRW<[V3Write_4c_1M0], (instregex "^AUT", "^PAC")>;1129 1130// Branch and link, register, with pointer authentication1131// Branch, register, with pointer authentication1132// Branch, return, with pointer authentication1133def : InstRW<[V3Write_6c_1M0_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA,1134 BRAAZ, BRAB, BRABZ, RETAA, RETAB,1135 ERETAA, ERETAB)>;1136 1137 1138// Load register, with pointer authentication1139def : InstRW<[V3Write_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;1140 1141// Strip pointer authentication code1142def : InstRW<[V3Write_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;1143 1144// §3.7 Miscellaneous data-processing instructions1145// -----------------------------------------------------------------------------1146 1147// Address generation1148def : InstRW<[V3Write_1c_1I], (instrs ADR, ADRP)>;1149 1150// Bitfield extract, one reg1151// Bitfield extract, two regs1152def : SchedAlias<WriteExtr, V3Write_Extr>;1153def : InstRW<[V3Write_Extr], (instrs EXTRWrri, EXTRXrri)>;1154 1155// Bitfield move, basic1156def : SchedAlias<WriteIS, V3Write_1c_1I>;1157 1158// Bitfield move, insert1159def : InstRW<[V3Write_2c_1M], (instregex "^BFM[WX]ri$")>;1160 1161// §3.8 Load instructions1162// -----------------------------------------------------------------------------1163 1164// NOTE: SOG p. 19: Throughput of LDN?P X-form should be 2, but reported as 3.1165 1166def : SchedAlias<WriteLD, V3Write_4c_1L>;1167def : SchedAlias<WriteLDIdx, V3Write_4c_1L>;1168 1169// Load register, literal1170def : InstRW<[V3Write_5c_1L_1I], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>;1171 1172// Load pair, signed immed offset, signed words1173def : InstRW<[V3Write_5c_1I_3L, WriteLDHi], (instrs LDPSWi)>;1174 1175// Load pair, immed post-index or immed pre-index, signed words1176def : InstRW<[WriteAdr, V3Write_5c_1I_3L, WriteLDHi],1177 (instregex "^LDPSW(post|pre)$")>;1178 1179// §3.9 Store instructions1180// -----------------------------------------------------------------------------1181 1182// NOTE: SOG, p. 20: Unsure if STRH uses pipeline I.1183 1184def : SchedAlias<WriteST, V3Write_1c_1SA_1D>;1185def : SchedAlias<WriteSTIdx, V3Write_1c_1SA_1D>;1186def : SchedAlias<WriteSTP, V3Write_1c_1SA_1D>;1187def : SchedAlias<WriteAdr, V3Write_1c_1I>;1188 1189// §3.10 Tag load instructions1190// -----------------------------------------------------------------------------1191 1192// Load allocation tag1193// Load multiple allocation tags1194def : InstRW<[V3Write_4c_1L], (instrs LDG, LDGM)>;1195 1196// §3.11 Tag store instructions1197// -----------------------------------------------------------------------------1198 1199// Store allocation tags to one or two granules, post-index1200// Store allocation tags to one or two granules, pre-index1201// Store allocation tag to one or two granules, zeroing, post-index1202// Store Allocation Tag to one or two granules, zeroing, pre-index1203// Store allocation tag and reg pair to memory, post-Index1204// Store allocation tag and reg pair to memory, pre-Index1205def : InstRW<[V3Write_1c_1SA_1D_1I], (instrs STGPreIndex, STGPostIndex,1206 ST2GPreIndex, ST2GPostIndex,1207 STZGPreIndex, STZGPostIndex,1208 STZ2GPreIndex, STZ2GPostIndex,1209 STGPpre, STGPpost)>;1210 1211// Store allocation tags to one or two granules, signed offset1212// Store allocation tag to two granules, zeroing, signed offset1213// Store allocation tag and reg pair to memory, signed offset1214// Store multiple allocation tags1215def : InstRW<[V3Write_1c_1SA_1D], (instrs STGi, ST2Gi, STZGi,1216 STZ2Gi, STGPi, STGM, STZGM)>;1217 1218// §3.12 FP data processing instructions1219// -----------------------------------------------------------------------------1220 1221// FP absolute value1222// FP arithmetic1223// FP min/max1224// FP negate1225// FP select1226def : SchedAlias<WriteF, V3Write_2c_1V>;1227 1228// FP compare1229def : SchedAlias<WriteFCmp, V3Write_2c_1V0>;1230 1231// FP divide, square root1232def : SchedAlias<WriteFDiv, V3Write_6c_1V1>;1233 1234// FP divide, H-form1235def : InstRW<[V3Write_6c_1V1], (instrs FDIVHrr)>;1236// FP divide, S-form1237def : InstRW<[V3Write_8c_1V1], (instrs FDIVSrr)>;1238// FP divide, D-form1239def : InstRW<[V3Write_13c_1V1], (instrs FDIVDrr)>;1240 1241// FP square root, H-form1242def : InstRW<[V3Write_6c_1V1], (instrs FSQRTHr)>;1243// FP square root, S-form1244def : InstRW<[V3Write_8c_1V1], (instrs FSQRTSr)>;1245// FP square root, D-form1246def : InstRW<[V3Write_13c_1V1], (instrs FSQRTDr)>;1247 1248// FP multiply1249def : WriteRes<WriteFMul, [V3UnitV]> { let Latency = 3; }1250 1251// FP multiply accumulate1252def : InstRW<[V3Wr_FMA, ReadDefault, ReadDefault, V3Rd_FMA],1253 (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;1254 1255// FP round to integral1256def : InstRW<[V3Write_3c_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$",1257 "^FRINT(32|64)[XZ][SD]r$")>;1258 1259// §3.13 FP miscellaneous instructions1260// -----------------------------------------------------------------------------1261 1262// FP convert, from gen to vec reg1263def : InstRW<[V3Write_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;1264 1265// FP convert, from vec to gen reg1266def : InstRW<[V3Write_3c_1V01],1267 (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]ri?$")>;1268 1269// FP convert, Javascript from vec to gen reg1270def : SchedAlias<WriteFCvt, V3Write_3c_1V0>;1271 1272// FP convert, from vec to vec reg1273def : InstRW<[V3Write_3c_1V02], (instrs FCVTSHr, FCVTDHr, FCVTHSr, FCVTDSr,1274 FCVTHDr, FCVTSDr, FCVTXNv1i64)>;1275 1276// FP move, immed1277// FP move, register1278def : SchedAlias<WriteFImm, V3Write_2c_1V>;1279 1280// FP transfer, from gen to low half of vec reg1281def : InstRW<[V3Write_0or3c_1M0],1282 (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;1283 1284// FP transfer, from gen to high half of vec reg1285def : InstRW<[V3Write_5c_1M0_1V], (instrs FMOVXDHighr)>;1286 1287// FP transfer, from vec to gen reg1288def : SchedAlias<WriteFCopy, V3Write_2c_2V01>;1289 1290// §3.14 FP load instructions1291// -----------------------------------------------------------------------------1292 1293// Load vector reg, literal, S/D/Q forms1294def : InstRW<[V3Write_7c_1I_1L], (instregex "^LDR[SDQ]l$")>;1295 1296// Load vector reg, unscaled immed1297def : InstRW<[V3Write_6c_1L], (instregex "^LDUR[BHSDQ]i$")>;1298 1299// Load vector reg, immed post-index1300// Load vector reg, immed pre-index1301def : InstRW<[WriteAdr, V3Write_6c_1I_1L],1302 (instregex "^LDR[BHSDQ](pre|post)$")>;1303 1304// Load vector reg, unsigned immed1305def : InstRW<[V3Write_6c_1L], (instregex "^LDR[BHSDQ]ui$")>;1306 1307// Load vector reg, register offset, basic1308// Load vector reg, register offset, scale, S/D-form1309// Load vector reg, register offset, scale, H/Q-form1310// Load vector reg, register offset, extend1311// Load vector reg, register offset, extend, scale, S/D-form1312// Load vector reg, register offset, extend, scale, H/Q-form1313def : InstRW<[V3Write_LdrHQ, ReadAdrBase], (instregex "^LDR[BHSDQ]ro[WX]$")>;1314 1315// Load vector pair, immed offset, S/D-form1316def : InstRW<[V3Write_6c_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>;1317 1318// Load vector pair, immed offset, Q-form1319def : InstRW<[V3Write_6c_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;1320 1321// Load vector pair, immed post-index, S/D-form1322// Load vector pair, immed pre-index, S/D-form1323def : InstRW<[WriteAdr, V3Write_6c_1I_1L, WriteLDHi],1324 (instregex "^LDP[SD](pre|post)$")>;1325 1326// Load vector pair, immed post-index, Q-form1327// Load vector pair, immed pre-index, Q-form1328def : InstRW<[WriteAdr, V3Write_6c_2I_2L, WriteLDHi], (instrs LDPQpost,1329 LDPQpre)>;1330 1331// §3.15 FP store instructions1332// -----------------------------------------------------------------------------1333 1334// Store vector reg, unscaled immed, B/H/S/D-form1335// Store vector reg, unscaled immed, Q-form1336def : InstRW<[V3Write_2c_1SA_1V01], (instregex "^STUR[BHSDQ]i$")>;1337 1338// Store vector reg, immed post-index, B/H/S/D-form1339// Store vector reg, immed post-index, Q-form1340// Store vector reg, immed pre-index, B/H/S/D-form1341// Store vector reg, immed pre-index, Q-form1342def : InstRW<[WriteAdr, V3Write_2c_1SA_1V01_1I],1343 (instregex "^STR[BHSDQ](pre|post)$")>;1344 1345// Store vector reg, unsigned immed, B/H/S/D-form1346// Store vector reg, unsigned immed, Q-form1347def : InstRW<[V3Write_2c_1SA_1V01], (instregex "^STR[BHSDQ]ui$")>;1348 1349// Store vector reg, register offset, basic, B/H/S/D-form1350// Store vector reg, register offset, basic, Q-form1351// Store vector reg, register offset, scale, H-form1352// Store vector reg, register offset, scale, S/D-form1353// Store vector reg, register offset, scale, Q-form1354// Store vector reg, register offset, extend, B/H/S/D-form1355// Store vector reg, register offset, extend, Q-form1356// Store vector reg, register offset, extend, scale, H-form1357// Store vector reg, register offset, extend, scale, S/D-form1358// Store vector reg, register offset, extend, scale, Q-form1359def : InstRW<[V3Write_StrHQ, ReadAdrBase],1360 (instregex "^STR[BHSDQ]ro[WX]$")>;1361 1362// Store vector pair, immed offset, S-form1363// Store vector pair, immed offset, D-form1364def : InstRW<[V3Write_2c_1SA_1V01], (instregex "^STN?P[SD]i$")>;1365 1366// Store vector pair, immed offset, Q-form1367def : InstRW<[V3Write_2c_1SA_2V01], (instrs STPQi, STNPQi)>;1368 1369// Store vector pair, immed post-index, S-form1370// Store vector pair, immed post-index, D-form1371// Store vector pair, immed pre-index, S-form1372// Store vector pair, immed pre-index, D-form1373def : InstRW<[WriteAdr, V3Write_2c_1SA_1V01_1I],1374 (instregex "^STP[SD](pre|post)$")>;1375 1376// Store vector pair, immed post-index, Q-form1377def : InstRW<[V3Write_2c_1SA_2V01_1I], (instrs STPQpost)>;1378 1379// Store vector pair, immed pre-index, Q-form1380def : InstRW<[V3Write_2c_1SA_2V01_2I], (instrs STPQpre)>;1381 1382// §3.16 ASIMD integer instructions1383// -----------------------------------------------------------------------------1384 1385// ASIMD absolute diff1386// ASIMD absolute diff long1387// ASIMD arith, basic1388// ASIMD arith, complex1389// ASIMD arith, pair-wise1390// ASIMD compare1391// ASIMD logical1392// ASIMD max/min, basic and pair-wise1393def : SchedAlias<WriteVd, V3Write_2c_1V>;1394def : SchedAlias<WriteVq, V3Write_2c_1V>;1395 1396// ASIMD absolute diff accum1397// ASIMD absolute diff accum long1398def : InstRW<[V3Wr_VA, V3Rd_VA], (instregex "^[SU]ABAL?v")>;1399 1400// ASIMD arith, reduce, 4H/4S1401def : InstRW<[V3Write_3c_1V13], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>;1402 1403// ASIMD arith, reduce, 8B/8H1404def : InstRW<[V3Write_5c_1V13_1V],1405 (instregex "^(ADDV|[SU]ADDLV)v8(i8|i16)v$")>;1406 1407// ASIMD arith, reduce, 16B1408def : InstRW<[V3Write_6c_2V13], (instregex "^(ADDV|[SU]ADDLV)v16i8v$")>;1409 1410// ASIMD dot product1411// ASIMD dot product using signed and unsigned integers1412def : InstRW<[V3Wr_VDOT, V3Rd_VDOT],1413 (instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>;1414 1415// ASIMD matrix multiply-accumulate1416def : InstRW<[V3Wr_VMMA, V3Rd_VMMA], (instrs SMMLA, UMMLA, USMMLA)>;1417 1418// ASIMD max/min, reduce, 4H/4S1419def : InstRW<[V3Write_3c_1V13], (instregex "^[SU](MAX|MIN)Vv4i16v$",1420 "^[SU](MAX|MIN)Vv4i32v$")>;1421 1422// ASIMD max/min, reduce, 8B/8H1423def : InstRW<[V3Write_5c_1V13_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$",1424 "^[SU](MAX|MIN)Vv8i16v$")>;1425 1426// ASIMD max/min, reduce, 16B1427def : InstRW<[V3Write_6c_2V13], (instregex "[SU](MAX|MIN)Vv16i8v$")>;1428 1429// ASIMD multiply1430def : InstRW<[V3Write_4c_1V02], (instregex "^MULv", "^SQ(R)?DMULHv")>;1431 1432// ASIMD multiply accumulate1433def : InstRW<[V3Wr_VMA, V3Rd_VMA], (instregex "^MLAv", "^MLSv")>;1434 1435// ASIMD multiply accumulate high1436def : InstRW<[V3Wr_VMAH, V3Rd_VMAH], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;1437 1438// ASIMD multiply accumulate long1439def : InstRW<[V3Wr_VMAL, V3Rd_VMAL], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;1440 1441// ASIMD multiply accumulate saturating long1442def : InstRW<[V3Write_4c_1V02], (instregex "^SQDML[AS]L[iv]")>;1443 1444// ASIMD multiply/multiply long (8x8) polynomial, D-form1445// ASIMD multiply/multiply long (8x8) polynomial, Q-form1446def : InstRW<[V3Write_3c_1V], (instregex "^PMULL?(v8i8|v16i8)$")>;1447 1448// ASIMD multiply long1449def : InstRW<[V3Write_3c_1V02], (instregex "^[SU]MULLv", "^SQDMULL[iv]")>;1450 1451// ASIMD pairwise add and accumulate long1452def : InstRW<[V3Wr_VPA, V3Rd_VPA], (instregex "^[SU]ADALPv")>;1453 1454// ASIMD shift accumulate1455def : InstRW<[V3Wr_VSA, V3Rd_VSA], (instregex "^[SU]SRA[dv]", "^[SU]RSRA[dv]")>;1456 1457// ASIMD shift by immed, basic1458def : InstRW<[V3Write_2c_1V], (instregex "^SHL[dv]", "^SHLLv", "^SHRNv",1459 "^SSHLLv", "^SSHR[dv]", "^USHLLv",1460 "^USHR[dv]")>;1461 1462// ASIMD shift by immed and insert, basic1463def : InstRW<[V3Write_2c_1V], (instregex "^SLI[dv]", "^SRI[dv]")>;1464 1465// ASIMD shift by immed, complex1466def : InstRW<[V3Write_4c_1V],1467 (instregex "^RSHRNv", "^SQRSHRU?N[bhsv]", "^(SQSHLU?|UQSHL)[bhsd]$",1468 "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",1469 "^SQSHRU?N[bhsv]", "^SRSHR[dv]", "^UQRSHRN[bhsv]",1470 "^UQSHRN[bhsv]", "^URSHR[dv]")>;1471 1472// ASIMD shift by register, basic1473def : InstRW<[V3Write_2c_1V], (instregex "^[SU]SHLv")>;1474 1475// ASIMD shift by register, complex1476def : InstRW<[V3Write_4c_1V],1477 (instregex "^[SU]RSHLv", "^[SU]QRSHLv",1478 "^[SU]QSHL(v1i8|v1i16|v1i32|v1i64|v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)$")>;1479 1480// §3.17 ASIMD floating-point instructions1481// -----------------------------------------------------------------------------1482 1483// ASIMD FP absolute value/difference1484// ASIMD FP arith, normal1485// ASIMD FP compare1486// ASIMD FP complex add1487// ASIMD FP max/min, normal1488// ASIMD FP max/min, pairwise1489// ASIMD FP negate1490// Handled by SchedAlias<WriteV[dq], ...>1491 1492// ASIMD FP complex multiply add1493def : InstRW<[V3Wr_VFCMA, V3Rd_VFCMA], (instregex "^FCMLAv")>;1494 1495// ASIMD FP convert, long (F16 to F32)1496def : InstRW<[V3Write_4c_2V02], (instregex "^FCVTL(v4|v8)i16")>;1497 1498// ASIMD FP convert, long (F32 to F64)1499def : InstRW<[V3Write_3c_1V02], (instregex "^FCVTL(v2|v4)i32")>;1500 1501// ASIMD FP convert, narrow (F32 to F16)1502def : InstRW<[V3Write_4c_2V02], (instregex "^FCVTN(v4|v8)i16")>;1503 1504// ASIMD FP convert, narrow (F64 to F32)1505def : InstRW<[V3Write_3c_1V02], (instregex "^FCVTN(v2|v4)i32",1506 "^FCVTXN(v2|v4)f32")>;1507 1508// ASIMD FP convert, other, D-form F32 and Q-form F641509def : InstRW<[V3Write_3c_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$",1510 "^FCVT[AMNPZ][SU]v2i(32|64)_shift$",1511 "^FCVT[AMNPZ][SU]v1i64$",1512 "^FCVTZ[SU]d$",1513 "^[SU]CVTFv2f(32|64)$",1514 "^[SU]CVTFv2i(32|64)_shift$",1515 "^[SU]CVTFv1i64$",1516 "^[SU]CVTFd$")>;1517 1518// ASIMD FP convert, other, D-form F16 and Q-form F321519def : InstRW<[V3Write_4c_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$",1520 "^FCVT[AMNPZ][SU]v4i(16|32)_shift$",1521 "^FCVT[AMNPZ][SU]v1i32$",1522 "^FCVTZ[SU]s$",1523 "^[SU]CVTFv4f(16|32)$",1524 "^[SU]CVTFv4i(16|32)_shift$",1525 "^[SU]CVTFv1i32$",1526 "^[SU]CVTFs$")>;1527 1528// ASIMD FP convert, other, Q-form F161529def : InstRW<[V3Write_6c_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$",1530 "^FCVT[AMNPZ][SU]v8i16_shift$",1531 "^FCVT[AMNPZ][SU]v1f16$",1532 "^FCVTZ[SU]h$",1533 "^[SU]CVTFv8f16$",1534 "^[SU]CVTFv8i16_shift$",1535 "^[SU]CVTFv1i16$",1536 "^[SU]CVTFh$")>;1537 1538// ASIMD FP divide, D-form, F161539def : InstRW<[V3Write_9c_1V1_4rc], (instrs FDIVv4f16)>;1540 1541// ASIMD FP divide, D-form, F321542def : InstRW<[V3Write_9c_1V1_2rc], (instrs FDIVv2f32)>;1543 1544// ASIMD FP divide, Q-form, F161545def : InstRW<[V3Write_13c_1V1_8rc], (instrs FDIVv8f16)>;1546 1547// ASIMD FP divide, Q-form, F321548def : InstRW<[V3Write_11c_1V1_4rc], (instrs FDIVv4f32)>;1549 1550// ASIMD FP divide, Q-form, F641551def : InstRW<[V3Write_14c_1V1_2rc], (instrs FDIVv2f64)>;1552 1553// ASIMD FP max/min, reduce, F32 and D-form F161554def : InstRW<[V3Write_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;1555 1556// ASIMD FP max/min, reduce, Q-form F161557def : InstRW<[V3Write_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;1558 1559// ASIMD FP multiply1560def : InstRW<[V3Wr_VFM], (instregex "^FMULv", "^FMULXv")>;1561 1562// ASIMD FP multiply accumulate1563def : InstRW<[V3Wr_VFMA, V3Rd_VFMA], (instregex "^FMLAv", "^FMLSv")>;1564 1565// ASIMD FP multiply accumulate long1566def : InstRW<[V3Wr_VFMAL, V3Rd_VFMAL], (instregex "^FML[AS]L2?(lane)?v")>;1567 1568// ASIMD FP round, D-form F32 and Q-form F641569def : InstRW<[V3Write_3c_1V02],1570 (instregex "^FRINT[AIMNPXZ]v2f(32|64)$",1571 "^FRINT(32|64)[XZ]v2f(32|64)$")>;1572 1573// ASIMD FP round, D-form F16 and Q-form F321574def : InstRW<[V3Write_4c_2V02],1575 (instregex "^FRINT[AIMNPXZ]v4f(16|32)$",1576 "^FRINT(32|64)[XZ]v4f32$")>;1577 1578// ASIMD FP round, Q-form F161579def : InstRW<[V3Write_6c_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>;1580 1581// ASIMD FP square root, D-form, F161582def : InstRW<[V3Write_9c_1V1_4rc], (instrs FSQRTv4f16)>;1583 1584// ASIMD FP square root, D-form, F321585def : InstRW<[V3Write_9c_1V1_2rc], (instrs FSQRTv2f32)>;1586 1587// ASIMD FP square root, Q-form, F161588def : InstRW<[V3Write_13c_1V1_8rc], (instrs FSQRTv8f16)>;1589 1590// ASIMD FP square root, Q-form, F321591def : InstRW<[V3Write_11c_1V1_4rc], (instrs FSQRTv4f32)>;1592 1593// ASIMD FP square root, Q-form, F641594def : InstRW<[V3Write_14c_1V1_2rc], (instrs FSQRTv2f64)>;1595 1596// §3.18 ASIMD BFloat16 (BF16) instructions1597// -----------------------------------------------------------------------------1598 1599// ASIMD convert, F32 to BF161600def : InstRW<[V3Write_4c_2V02], (instrs BFCVTN, BFCVTN2)>;1601 1602// ASIMD dot product1603def : InstRW<[V3Wr_VBFDOT, V3Rd_VBFDOT], (instrs BFDOTv4bf16, BFDOTv8bf16)>;1604 1605// ASIMD matrix multiply accumulate1606def : InstRW<[V3Wr_VBFMMA, V3Rd_VBFMMA], (instrs BFMMLA)>;1607 1608// ASIMD multiply accumulate long1609def : InstRW<[V3Wr_VBFMAL, V3Rd_VBFMAL], (instrs BFMLALB, BFMLALBIdx, BFMLALT,1610 BFMLALTIdx)>;1611 1612// Scalar convert, F32 to BF161613def : InstRW<[V3Write_3c_1V02], (instrs BFCVT)>;1614 1615// §3.19 ASIMD miscellaneous instructions1616// -----------------------------------------------------------------------------1617 1618// ASIMD bit reverse1619// ASIMD bitwise insert1620// ASIMD count1621// ASIMD duplicate, element1622// ASIMD extract1623// ASIMD extract narrow1624// ASIMD insert, element to element1625// ASIMD move, FP immed1626// ASIMD move, integer immed1627// ASIMD reverse1628// ASIMD table lookup extension, 1 table reg1629// ASIMD transpose1630// ASIMD unzip/zip1631// Handled by SchedAlias<WriteV[dq], ...>1632def : InstRW<[V3Write_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>;1633 1634// ASIMD duplicate, gen reg1635def : InstRW<[V3Write_3c_1M0], (instregex "^DUPv.+gpr")>;1636 1637// ASIMD extract narrow, saturating1638def : InstRW<[V3Write_4c_1V], (instregex "^[SU]QXTNv", "^SQXTUNv")>;1639 1640// ASIMD reciprocal and square root estimate, D-form U321641def : InstRW<[V3Write_3c_1V02], (instrs URECPEv2i32, URSQRTEv2i32)>;1642 1643// ASIMD reciprocal and square root estimate, Q-form U321644def : InstRW<[V3Write_4c_2V02], (instrs URECPEv4i32, URSQRTEv4i32)>;1645 1646// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms1647def : InstRW<[V3Write_3c_1V02], (instrs FRECPEv1f16, FRECPEv1i32,1648 FRECPEv1i64, FRECPEv2f32,1649 FRSQRTEv1f16, FRSQRTEv1i32,1650 FRSQRTEv1i64, FRSQRTEv2f32)>;1651 1652// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F321653def : InstRW<[V3Write_4c_2V02], (instrs FRECPEv4f16, FRECPEv4f32,1654 FRSQRTEv4f16, FRSQRTEv4f32)>;1655 1656// ASIMD reciprocal and square root estimate, Q-form F161657def : InstRW<[V3Write_6c_4V02], (instrs FRECPEv8f16, FRSQRTEv8f16)>;1658 1659// ASIMD reciprocal exponent1660def : InstRW<[V3Write_3c_1V02], (instregex "^FRECPXv")>;1661 1662// ASIMD reciprocal step1663def : InstRW<[V3Write_4c_1V], (instregex "^FRECPS(32|64|v)",1664 "^FRSQRTS(32|64|v)")>;1665 1666// ASIMD table lookup, 1 or 2 table regs1667def : InstRW<[V3Write_2c_1V], (instrs TBLv8i8One, TBLv16i8One,1668 TBLv8i8Two, TBLv16i8Two)>;1669 1670// ASIMD table lookup, 3 table regs1671def : InstRW<[V3Write_4c_2V], (instrs TBLv8i8Three, TBLv16i8Three)>;1672 1673// ASIMD table lookup, 4 table regs1674def : InstRW<[V3Write_4c_3V], (instrs TBLv8i8Four, TBLv16i8Four)>;1675 1676// ASIMD table lookup extension, 2 table reg1677def : InstRW<[V3Write_4c_2V], (instrs TBXv8i8Two, TBXv16i8Two)>;1678 1679// ASIMD table lookup extension, 3 table reg1680def : InstRW<[V3Write_6c_3V], (instrs TBXv8i8Three, TBXv16i8Three)>;1681 1682// ASIMD table lookup extension, 4 table reg1683def : InstRW<[V3Write_6c_5V], (instrs TBXv8i8Four, TBXv16i8Four)>;1684 1685// ASIMD transfer, element to gen reg1686def : InstRW<[V3Write_2c_2V01], (instregex "^[SU]MOVv")>;1687 1688// ASIMD transfer, gen reg to element1689def : InstRW<[V3Write_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;1690 1691// §3.20 ASIMD load instructions1692// -----------------------------------------------------------------------------1693 1694// ASIMD load, 1 element, multiple, 1 reg, D-form1695def : InstRW<[V3Write_6c_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;1696def : InstRW<[WriteAdr, V3Write_6c_1L],1697 (instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>;1698 1699// ASIMD load, 1 element, multiple, 1 reg, Q-form1700def : InstRW<[V3Write_6c_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;1701def : InstRW<[WriteAdr, V3Write_6c_1L],1702 (instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>;1703 1704// ASIMD load, 1 element, multiple, 2 reg, D-form1705def : InstRW<[V3Write_6c_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;1706def : InstRW<[WriteAdr, V3Write_6c_2L],1707 (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;1708 1709// ASIMD load, 1 element, multiple, 2 reg, Q-form1710def : InstRW<[V3Write_6c_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;1711def : InstRW<[WriteAdr, V3Write_6c_2L],1712 (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;1713 1714// ASIMD load, 1 element, multiple, 3 reg, D-form1715def : InstRW<[V3Write_6c_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;1716def : InstRW<[WriteAdr, V3Write_6c_3L],1717 (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;1718 1719// ASIMD load, 1 element, multiple, 3 reg, Q-form1720def : InstRW<[V3Write_6c_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;1721def : InstRW<[WriteAdr, V3Write_6c_3L],1722 (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;1723 1724// ASIMD load, 1 element, multiple, 4 reg, D-form1725def : InstRW<[V3Write_7c_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;1726def : InstRW<[WriteAdr, V3Write_7c_4L],1727 (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;1728 1729// ASIMD load, 1 element, multiple, 4 reg, Q-form1730def : InstRW<[V3Write_7c_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;1731def : InstRW<[WriteAdr, V3Write_7c_4L],1732 (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;1733 1734// ASIMD load, 1 element, one lane, B/H/S1735// ASIMD load, 1 element, one lane, D1736def : InstRW<[V3Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)$")>;1737def : InstRW<[WriteAdr, V3Write_8c_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;1738 1739// ASIMD load, 1 element, all lanes, D-form, B/H/S1740// ASIMD load, 1 element, all lanes, D-form, D1741def : InstRW<[V3Write_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;1742def : InstRW<[WriteAdr, V3Write_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;1743 1744// ASIMD load, 1 element, all lanes, Q-form1745def : InstRW<[V3Write_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;1746def : InstRW<[WriteAdr, V3Write_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;1747 1748// ASIMD load, 2 element, multiple, D-form, B/H/S1749def : InstRW<[V3Write_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;1750def : InstRW<[WriteAdr, V3Write_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;1751 1752// ASIMD load, 2 element, multiple, Q-form, B/H/S1753// ASIMD load, 2 element, multiple, Q-form, D1754def : InstRW<[V3Write_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;1755def : InstRW<[WriteAdr, V3Write_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;1756 1757// ASIMD load, 2 element, one lane, B/H1758// ASIMD load, 2 element, one lane, S1759// ASIMD load, 2 element, one lane, D1760def : InstRW<[V3Write_8c_1L_2V], (instregex "LD2i(8|16|32|64)$")>;1761def : InstRW<[WriteAdr, V3Write_8c_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;1762 1763// ASIMD load, 2 element, all lanes, D-form, B/H/S1764// ASIMD load, 2 element, all lanes, D-form, D1765def : InstRW<[V3Write_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;1766def : InstRW<[WriteAdr, V3Write_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;1767 1768// ASIMD load, 2 element, all lanes, Q-form1769def : InstRW<[V3Write_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;1770def : InstRW<[WriteAdr, V3Write_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;1771 1772// ASIMD load, 3 element, multiple, D-form, B/H/S1773def : InstRW<[V3Write_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;1774def : InstRW<[WriteAdr, V3Write_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;1775 1776// ASIMD load, 3 element, multiple, Q-form, B/H/S1777// ASIMD load, 3 element, multiple, Q-form, D1778def : InstRW<[V3Write_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)$")>;1779def : InstRW<[WriteAdr, V3Write_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;1780 1781// ASIMD load, 3 element, one lane, B/H1782// ASIMD load, 3 element, one lane, S1783// ASIMD load, 3 element, one lane, D1784def : InstRW<[V3Write_8c_2L_3V], (instregex "LD3i(8|16|32|64)$")>;1785def : InstRW<[WriteAdr, V3Write_8c_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;1786 1787// ASIMD load, 3 element, all lanes, D-form, B/H/S1788// ASIMD load, 3 element, all lanes, D-form, D1789def : InstRW<[V3Write_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;1790def : InstRW<[WriteAdr, V3Write_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;1791 1792// ASIMD load, 3 element, all lanes, Q-form, B/H/S1793// ASIMD load, 3 element, all lanes, Q-form, D1794def : InstRW<[V3Write_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;1795def : InstRW<[WriteAdr, V3Write_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;1796 1797// ASIMD load, 4 element, multiple, D-form, B/H/S1798def : InstRW<[V3Write_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;1799def : InstRW<[WriteAdr, V3Write_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;1800 1801// ASIMD load, 4 element, multiple, Q-form, B/H/S1802// ASIMD load, 4 element, multiple, Q-form, D1803def : InstRW<[V3Write_9c_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;1804def : InstRW<[WriteAdr, V3Write_9c_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;1805 1806// ASIMD load, 4 element, one lane, B/H1807// ASIMD load, 4 element, one lane, S1808// ASIMD load, 4 element, one lane, D1809def : InstRW<[V3Write_8c_3L_4V], (instregex "LD4i(8|16|32|64)$")>;1810def : InstRW<[WriteAdr, V3Write_8c_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;1811 1812// ASIMD load, 4 element, all lanes, D-form, B/H/S1813// ASIMD load, 4 element, all lanes, D-form, D1814def : InstRW<[V3Write_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;1815def : InstRW<[WriteAdr, V3Write_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;1816 1817// ASIMD load, 4 element, all lanes, Q-form, B/H/S1818// ASIMD load, 4 element, all lanes, Q-form, D1819def : InstRW<[V3Write_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;1820def : InstRW<[WriteAdr, V3Write_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;1821 1822// §3.21 ASIMD store instructions1823// -----------------------------------------------------------------------------1824 1825// ASIMD store, 1 element, multiple, 1 reg, D-form1826def : InstRW<[V3Write_2c_1SA_1V01], (instregex "ST1Onev(8b|4h|2s|1d)$")>;1827def : InstRW<[WriteAdr, V3Write_2c_1SA_1V01], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;1828 1829// ASIMD store, 1 element, multiple, 1 reg, Q-form1830def : InstRW<[V3Write_2c_1SA_1V01], (instregex "ST1Onev(16b|8h|4s|2d)$")>;1831def : InstRW<[WriteAdr, V3Write_2c_1SA_1V01], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;1832 1833// ASIMD store, 1 element, multiple, 2 reg, D-form1834def : InstRW<[V3Write_2c_1SA_1V01], (instregex "ST1Twov(8b|4h|2s|1d)$")>;1835def : InstRW<[WriteAdr, V3Write_2c_1SA_1V01], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;1836 1837// ASIMD store, 1 element, multiple, 2 reg, Q-form1838def : InstRW<[V3Write_2c_2SA_2V01], (instregex "ST1Twov(16b|8h|4s|2d)$")>;1839def : InstRW<[WriteAdr, V3Write_2c_2SA_2V01], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;1840 1841// ASIMD store, 1 element, multiple, 3 reg, D-form1842def : InstRW<[V3Write_2c_2SA_2V01], (instregex "ST1Threev(8b|4h|2s|1d)$")>;1843def : InstRW<[WriteAdr, V3Write_2c_2SA_2V01], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;1844 1845// ASIMD store, 1 element, multiple, 3 reg, Q-form1846def : InstRW<[V3Write_2c_3SA_3V01], (instregex "ST1Threev(16b|8h|4s|2d)$")>;1847def : InstRW<[WriteAdr, V3Write_2c_3SA_3V01], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;1848 1849// ASIMD store, 1 element, multiple, 4 reg, D-form1850def : InstRW<[V3Write_2c_2SA_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;1851def : InstRW<[WriteAdr, V3Write_2c_2SA_2V01], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;1852 1853// ASIMD store, 1 element, multiple, 4 reg, Q-form1854def : InstRW<[V3Write_2c_4SA_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;1855def : InstRW<[WriteAdr, V3Write_2c_4SA_4V01], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;1856 1857// ASIMD store, 1 element, one lane, B/H/S1858// ASIMD store, 1 element, one lane, D1859def : InstRW<[V3Write_4c_1SA_2V01], (instregex "ST1i(8|16|32|64)$")>;1860def : InstRW<[WriteAdr, V3Write_4c_1SA_2V01], (instregex "ST1i(8|16|32|64)_POST$")>;1861 1862// ASIMD store, 2 element, multiple, D-form, B/H/S1863def : InstRW<[V3Write_4c_1SA_2V01], (instregex "ST2Twov(8b|4h|2s)$")>;1864def : InstRW<[WriteAdr, V3Write_4c_1SA_2V01], (instregex "ST2Twov(8b|4h|2s)_POST$")>;1865 1866// ASIMD store, 2 element, multiple, Q-form, B/H/S1867// ASIMD store, 2 element, multiple, Q-form, D1868def : InstRW<[V3Write_4c_2SA_4V01], (instregex "ST2Twov(16b|8h|4s|2d)$")>;1869def : InstRW<[WriteAdr, V3Write_4c_2SA_4V01], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;1870 1871// ASIMD store, 2 element, one lane, B/H/S1872// ASIMD store, 2 element, one lane, D1873def : InstRW<[V3Write_4c_1SA_2V01], (instregex "ST2i(8|16|32|64)$")>;1874def : InstRW<[WriteAdr, V3Write_4c_1SA_2V01], (instregex "ST2i(8|16|32|64)_POST$")>;1875 1876// ASIMD store, 3 element, multiple, D-form, B/H/S1877def : InstRW<[V3Write_5c_2SA_4V01], (instregex "ST3Threev(8b|4h|2s)$")>;1878def : InstRW<[WriteAdr, V3Write_5c_2SA_4V01], (instregex "ST3Threev(8b|4h|2s)_POST$")>;1879 1880// ASIMD store, 3 element, multiple, Q-form, B/H/S1881// ASIMD store, 3 element, multiple, Q-form, D1882def : InstRW<[V3Write_6c_3SA_6V01], (instregex "ST3Threev(16b|8h|4s|2d)$")>;1883def : InstRW<[WriteAdr, V3Write_6c_3SA_6V01], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;1884 1885// ASIMD store, 3 element, one lane, B/H1886// ASIMD store, 3 element, one lane, S1887// ASIMD store, 3 element, one lane, D1888def : InstRW<[V3Write_5c_2SA_4V01], (instregex "ST3i(8|16|32|64)$")>;1889def : InstRW<[WriteAdr, V3Write_5c_2SA_4V01], (instregex "ST3i(8|16|32|64)_POST$")>;1890 1891// ASIMD store, 4 element, multiple, D-form, B/H/S1892def : InstRW<[V3Write_6c_2SA_6V01], (instregex "ST4Fourv(8b|4h|2s)$")>;1893def : InstRW<[WriteAdr, V3Write_6c_2SA_6V01], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;1894 1895// ASIMD store, 4 element, multiple, Q-form, B/H/S1896def : InstRW<[V3Write_7c_4SA_12V01], (instregex "ST4Fourv(16b|8h|4s)$")>;1897def : InstRW<[WriteAdr, V3Write_7c_4SA_12V01], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;1898 1899// ASIMD store, 4 element, multiple, Q-form, D1900def : InstRW<[V3Write_5c_4SA_8V01], (instregex "ST4Fourv(2d)$")>;1901def : InstRW<[WriteAdr, V3Write_5c_4SA_8V01], (instregex "ST4Fourv(2d)_POST$")>;1902 1903// ASIMD store, 4 element, one lane, B/H/S1904def : InstRW<[V3Write_6c_1SA_3V01], (instregex "ST4i(8|16|32)$")>;1905def : InstRW<[WriteAdr, V3Write_6c_1SA_3V01], (instregex "ST4i(8|16|32)_POST$")>;1906 1907// ASIMD store, 4 element, one lane, D1908def : InstRW<[V3Write_4c_2SA_4V01], (instregex "ST4i(64)$")>;1909def : InstRW<[WriteAdr, V3Write_4c_2SA_4V01], (instregex "ST4i(64)_POST$")>;1910 1911// §3.22 Cryptography extensions1912// -----------------------------------------------------------------------------1913 1914// Crypto AES ops1915def : InstRW<[V3Write_2c_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;1916 1917// Crypto polynomial (64x64) multiply long1918def : InstRW<[V3Write_2c_1V], (instrs PMULLv1i64, PMULLv2i64)>;1919 1920// Crypto SHA1 hash acceleration op1921// Crypto SHA1 schedule acceleration ops1922def : InstRW<[V3Write_2c_1V0], (instregex "^SHA1(H|SU0|SU1)")>;1923 1924// Crypto SHA1 hash acceleration ops1925// Crypto SHA256 hash acceleration ops1926def : InstRW<[V3Write_4c_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>;1927 1928// Crypto SHA256 schedule acceleration ops1929def : InstRW<[V3Write_2c_1V0], (instregex "^SHA256SU[01]")>;1930 1931// Crypto SHA512 hash acceleration ops1932def : InstRW<[V3Write_2c_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>;1933 1934// Crypto SHA3 ops1935def : InstRW<[V3Write_2c_1V], (instrs BCAX, EOR3, RAX1, XAR)>;1936 1937// Crypto SM3 ops1938def : InstRW<[V3Write_2c_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$",1939 "^SM3TT[12][AB]$")>;1940 1941// Crypto SM4 ops1942def : InstRW<[V3Write_4c_1V0], (instrs SM4E, SM4ENCKEY)>;1943 1944// §3.23 CRC1945// -----------------------------------------------------------------------------1946 1947def : InstRW<[V3Wr_CRC, V3Rd_CRC], (instregex "^CRC32")>;1948 1949// §3.24 SVE Predicate instructions1950// -----------------------------------------------------------------------------1951 1952// Loop control, based on predicate1953def : InstRW<[V3Write_2or3c_1M], (instrs BRKA_PPmP, BRKA_PPzP,1954 BRKB_PPmP, BRKB_PPzP)>;1955 1956// Loop control, based on predicate and flag setting1957def : InstRW<[V3Write_2or3c_1M], (instrs BRKAS_PPzP, BRKBS_PPzP)>;1958 1959// Loop control, propagating1960def : InstRW<[V3Write_2or3c_1M], (instrs BRKN_PPzP, BRKPA_PPzPP,1961 BRKPB_PPzPP)>;1962 1963// Loop control, propagating and flag setting1964def : InstRW<[V3Write_2or3c_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP,1965 BRKPBS_PPzPP)>;1966 1967// Loop control, based on GPR1968def : InstRW<[V3Write_3c_2M],1969 (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]")>;1970def : InstRW<[V3Write_3c_2M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]")>;1971 1972// Loop terminate1973def : InstRW<[V3Write_1c_2M], (instregex "^CTERM(EQ|NE)_(WW|XX)")>;1974 1975// Predicate counting scalar1976def : InstRW<[V3Write_2c_1M], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;1977def : InstRW<[V3Write_2c_1M],1978 (instregex "^(CNT|SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI",1979 "^SQ(DEC|INC)[BHWD]_XPiWdI",1980 "^UQ(DEC|INC)[BHWD]_WPiI")>;1981 1982// Predicate counting scalar, ALL, {1,2,4}1983def : InstRW<[V3Write_IncDec], (instregex "^(DEC|INC)[BHWD]_XPiI")>;1984 1985// Predicate counting scalar, active predicate1986def : InstRW<[V3Write_2c_1M],1987 (instregex "^CNTP_XPP_[BHSD]",1988 "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]",1989 "^(UQDEC|UQINC)P_WP_[BHSD]",1990 "^(SQDEC|SQINC)P_XPWd_[BHSD]")>;1991 1992// Predicate counting vector, active predicate1993def : InstRW<[V3Write_7c_1M_1M0_1V],1994 (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]")>;1995 1996// Predicate logical1997def : InstRW<[V3Write_1or2c_1M],1998 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP")>;1999 2000// Predicate logical, flag setting2001def : InstRW<[V3Write_1or2c_1M],2002 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;2003 2004// Predicate reverse2005def : InstRW<[V3Write_2c_1M], (instregex "^REV_PP_[BHSD]")>;2006 2007// Predicate select2008def : InstRW<[V3Write_1c_1M], (instrs SEL_PPPP)>;2009 2010// Predicate set2011def : InstRW<[V3Write_2c_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;2012 2013// Predicate set/initialize, set flags2014def : InstRW<[V3Write_2c_1M], (instregex "^PTRUES_[BHSD]")>;2015 2016// Predicate find first/next2017def : InstRW<[V3Write_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;2018 2019// Predicate test2020def : InstRW<[V3Write_1c_1M], (instrs PTEST_PP)>;2021 2022// Predicate transpose2023def : InstRW<[V3Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;2024 2025// Predicate unpack and widen2026def : InstRW<[V3Write_2c_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>;2027 2028// Predicate zip/unzip2029def : InstRW<[V3Write_2c_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]")>;2030 2031// §3.25 SVE integer instructions2032// -----------------------------------------------------------------------------2033 2034// Arithmetic, absolute diff2035def : InstRW<[V3Write_2c_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",2036 "^[SU]ABD_ZPZZ_[BHSD]")>;2037 2038// Arithmetic, absolute diff accum2039def : InstRW<[V3Wr_ZA, V3Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]")>;2040 2041// Arithmetic, absolute diff accum long2042def : InstRW<[V3Wr_ZA, V3Rd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]")>;2043 2044// Arithmetic, absolute diff long2045def : InstRW<[V3Write_2c_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]")>;2046 2047// Arithmetic, basic2048def : InstRW<[V3Write_2c_1V],2049 (instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]",2050 "^(ADD|SUB)_ZZZ_[BHSD]",2051 "^(ADD|SUB|SUBR)_ZPZZ_[BHSD]",2052 "^(ADD|SUB|SUBR)_ZI_[BHSD]",2053 "^ADR_[SU]XTW_ZZZ_D_[0123]",2054 "^ADR_LSL_ZZZ_[SD]_[0123]",2055 "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",2056 "^SADDLBT_ZZZ_[HSD]",2057 "^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",2058 "^SSUBL(BT|TB)_ZZZ_[HSD]")>;2059 2060// Arithmetic, complex2061def : InstRW<[V3Write_2c_1V],2062 (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]",2063 "^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]",2064 "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]",2065 "^[SU]Q(ADD|SUB)_ZI_[BHSD]",2066 "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]",2067 "^(UQSUB|UQSUBR)_ZPmZ_[BHSD]")>;2068 2069// Arithmetic, large integer2070def : InstRW<[V3Write_2c_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]")>;2071 2072// Arithmetic, pairwise add2073def : InstRW<[V3Write_2c_1V], (instregex "^ADDP_ZPmZ_[BHSD]")>;2074 2075// Arithmetic, pairwise add and accum long2076def : InstRW<[V3Wr_ZPA, ReadDefault, V3Rd_ZPA],2077 (instregex "^[SU]ADALP_ZPmZ_[HSD]")>;2078 2079// Arithmetic, shift2080def : InstRW<[V3Write_2c_1V13],2081 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",2082 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",2083 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",2084 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",2085 "^(ASR|LSL|LSR)_ZZI_[BHSD]",2086 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",2087 "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>;2088 2089// Arithmetic, shift and accumulate2090def : InstRW<[V3Wr_ZSA, V3Rd_ZSA], (instregex "^[SU]R?SRA_ZZI_[BHSD]")>;2091 2092// Arithmetic, shift by immediate2093def : InstRW<[V3Write_2c_1V], (instregex "^SHRN[BT]_ZZI_[BHS]",2094 "^[SU]SHLL[BT]_ZZI_[HSD]")>;2095 2096// Arithmetic, shift by immediate and insert2097def : InstRW<[V3Write_2c_1V], (instregex "^(SLI|SRI)_ZZI_[BHSD]")>;2098 2099// Arithmetic, shift complex2100def : InstRW<[V3Write_4c_1V],2101 (instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]",2102 "^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]",2103 "^[SU]QR?SHL_ZPZZ_[BHSD]",2104 "^(SQSHL|SQSHLU|UQSHL)_(ZPmI|ZPZI)_[BHSD]",2105 "^SQSHRU?N[BT]_ZZI_[BHS]",2106 "^UQR?SHRN[BT]_ZZI_[BHS]")>;2107 2108// Arithmetic, shift right for divide2109def : InstRW<[V3Write_4c_1V], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;2110 2111// Arithmetic, shift rounding2112def : InstRW<[V3Write_4c_1V], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]",2113 "^[SU]RSHL_ZPZZ_[BHSD]",2114 "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>;2115 2116// Bit manipulation2117def : InstRW<[V3Write_6c_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>;2118 2119// Bitwise select2120def : InstRW<[V3Write_2c_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ")>;2121 2122// Count/reverse bits2123def : InstRW<[V3Write_2c_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;2124 2125// Broadcast logical bitmask immediate to vector2126def : InstRW<[V3Write_2c_1V], (instrs DUPM_ZI)>;2127 2128// Compare and set flags2129def : InstRW<[V3Write_2or3c_1V0],2130 (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]",2131 "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]")>;2132 2133// Complex add2134def : InstRW<[V3Write_2c_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]")>;2135 2136// Complex dot product 8-bit element2137def : InstRW<[V3Wr_ZDOTB, V3Rd_ZDOTB], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;2138 2139// Complex dot product 16-bit element2140def : InstRW<[V3Wr_ZDOTH, V3Rd_ZDOTH], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;2141 2142// Complex multiply-add B, H, S element size2143def : InstRW<[V3Wr_ZCMABHS, V3Rd_ZCMABHS], (instregex "^CMLA_ZZZ_[BHS]",2144 "^CMLA_ZZZI_[HS]")>;2145 2146// Complex multiply-add D element size2147def : InstRW<[V3Wr_ZCMAD, V3Rd_ZCMAD], (instrs CMLA_ZZZ_D)>;2148 2149// Conditional extract operations, scalar form2150def : InstRW<[V3Write_8c_1M0_1V01], (instregex "^CLAST[AB]_RPZ_[BHSD]")>;2151 2152// Conditional extract operations, SIMD&FP scalar and vector forms2153def : InstRW<[V3Write_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]",2154 "^COMPACT_ZPZ_[SD]",2155 "^SPLICE_ZPZZ?_[BHSD]")>;2156 2157// Convert to floating point, 64b to float or convert to double2158def : InstRW<[V3Write_3c_1V02], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",2159 "^[SU]CVTF_ZPmZ_StoD")>;2160 2161// Convert to floating point, 32b to single or half2162def : InstRW<[V3Write_4c_2V02], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;2163 2164// Convert to floating point, 16b to half2165def : InstRW<[V3Write_6c_4V02], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;2166 2167// Copy, scalar2168def : InstRW<[V3Write_5c_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]")>;2169 2170// Copy, scalar SIMD&FP or imm2171def : InstRW<[V3Write_2c_1V], (instregex "^CPY_ZPm[IV]_[BHSD]",2172 "^CPY_ZPzI_[BHSD]")>;2173 2174// Divides, 32 bit2175def : InstRW<[V3Write_12c_1V0], (instregex "^[SU]DIVR?_ZPmZ_S",2176 "^[SU]DIV_ZPZZ_S")>;2177 2178// Divides, 64 bit2179def : InstRW<[V3Write_20c_1V0], (instregex "^[SU]DIVR?_ZPmZ_D",2180 "^[SU]DIV_ZPZZ_D")>;2181 2182// Dot product, 8 bit2183def : InstRW<[V3Wr_ZDOTB, V3Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_BtoS")>;2184 2185// Dot product, 8 bit, using signed and unsigned integers2186def : InstRW<[V3Wr_ZDOTB, V3Rd_ZDOTB], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;2187 2188// Dot product, 16 bit2189def : InstRW<[V3Wr_ZDOTH, V3Rd_ZDOTH], (instregex "^[SU]DOT_ZZZI?_HtoD")>;2190 2191// Duplicate, immediate and indexed form2192def : InstRW<[V3Write_2c_1V], (instregex "^DUP_ZI_[BHSD]",2193 "^DUP_ZZI_[BHSDQ]")>;2194 2195// Duplicate, scalar form2196def : InstRW<[V3Write_3c_1M0], (instregex "^DUP_ZR_[BHSD]")>;2197 2198// Extend, sign or zero2199def : InstRW<[V3Write_2c_1V], (instregex "^[SU]XTB_ZPmZ_[HSD]",2200 "^[SU]XTH_ZPmZ_[SD]",2201 "^[SU]XTW_ZPmZ_[D]")>;2202 2203// Extract2204def : InstRW<[V3Write_2c_1V], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;2205 2206// Extract narrow saturating2207def : InstRW<[V3Write_4c_1V], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]",2208 "^SQXTUN[BT]_ZZ_[BHS]")>;2209 2210// Extract operation, SIMD and FP scalar form2211def : InstRW<[V3Write_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]")>;2212 2213// Extract operation, scalar2214def : InstRW<[V3Write_6c_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]")>;2215 2216// Histogram operations2217def : InstRW<[V3Write_2c_1V], (instregex "^HISTCNT_ZPzZZ_[SD]",2218 "^HISTSEG_ZZZ")>;2219 2220// Horizontal operations, B, H, S form, immediate operands only2221def : InstRW<[V3Write_4c_1V02], (instregex "^INDEX_II_[BHS]")>;2222 2223// Horizontal operations, B, H, S form, scalar, immediate operands/ scalar2224// operands only / immediate, scalar operands2225def : InstRW<[V3Write_7c_1M0_1V02], (instregex "^INDEX_(IR|RI|RR)_[BHS]")>;2226 2227// Horizontal operations, D form, immediate operands only2228def : InstRW<[V3Write_5c_2V02], (instrs INDEX_II_D)>;2229 2230// Horizontal operations, D form, scalar, immediate operands)/ scalar operands2231// only / immediate, scalar operands2232def : InstRW<[V3Write_8c_2M0_2V02], (instregex "^INDEX_(IR|RI|RR)_D")>;2233 2234// insert operation, SIMD and FP scalar form2235def : InstRW<[V3Write_2c_1V], (instregex "^INSR_ZV_[BHSD]")>;2236 2237// insert operation, scalar2238def : InstRW<[V3Write_5c_1V1_1M0], (instregex "^INSR_ZR_[BHSD]")>;2239 2240// Logical2241def : InstRW<[V3Write_2c_1V],2242 (instregex "^(AND|EOR|ORR)_ZI",2243 "^(AND|BIC|EOR|ORR)_ZZZ",2244 "^EOR(BT|TB)_ZZZ_[BHSD]",2245 "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]",2246 "^NOT_ZPmZ_[BHSD]")>;2247 2248// Max/min, basic and pairwise2249def : InstRW<[V3Write_2c_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",2250 "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]",2251 "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>;2252 2253// Matching operations2254// FIXME: SOG p. 44, n. 5: If the consuming instruction has a flag source, the2255// latency for this instruction is 4 cycles.2256def : InstRW<[V3Write_2or3c_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]")>;2257 2258// Matrix multiply-accumulate2259def : InstRW<[V3Wr_ZMMA, V3Rd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;2260 2261// Move prefix2262def : InstRW<[V3Write_2c_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]",2263 "^MOVPRFX_ZZ")>;2264 2265// Multiply, B, H, S element size2266def : InstRW<[V3Write_4c_1V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]",2267 "^MUL_ZPZZ_[BHS]",2268 "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]",2269 "^[SU]MULH_ZPZZ_[BHS]")>;2270 2271// Multiply, D element size2272def : InstRW<[V3Write_5c_2V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D",2273 "^MUL_ZPZZ_D",2274 "^[SU]MULH_(ZPmZ|ZZZ)_D",2275 "^[SU]MULH_ZPZZ_D")>;2276 2277// Multiply long2278def : InstRW<[V3Write_4c_1V02], (instregex "^[SU]MULL[BT]_ZZZI_[SD]",2279 "^[SU]MULL[BT]_ZZZ_[HSD]")>;2280 2281// Multiply accumulate, B, H, S element size2282def : InstRW<[V3Wr_ZMABHS, V3Rd_ZMABHS],2283 (instregex "^ML[AS]_ZZZI_[HS]", "^ML[AS]_ZPZZZ_[BHS]")>;2284def : InstRW<[V3Wr_ZMABHS, ReadDefault, V3Rd_ZMABHS],2285 (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>;2286 2287// Multiply accumulate, D element size2288def : InstRW<[V3Wr_ZMAD, V3Rd_ZMAD],2289 (instregex "^ML[AS]_ZZZI_D", "^ML[AS]_ZPZZZ_D")>;2290def : InstRW<[V3Wr_ZMAD, ReadDefault, V3Rd_ZMAD],2291 (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;2292 2293// Multiply accumulate long2294def : InstRW<[V3Wr_ZMAL, V3Rd_ZMAL], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]",2295 "^[SU]ML[AS]L[BT]_ZZZI_[SD]")>;2296 2297// Multiply accumulate saturating doubling long regular2298def : InstRW<[V3Wr_ZMASQL, V3Rd_ZMASQ],2299 (instregex "^SQDML[AS]L(B|T|BT)_ZZZ_[HSD]",2300 "^SQDML[AS]L[BT]_ZZZI_[SD]")>;2301 2302// Multiply saturating doubling high, B, H, S element size2303def : InstRW<[V3Write_4c_1V02], (instregex "^SQDMULH_ZZZ_[BHS]",2304 "^SQDMULH_ZZZI_[HS]")>;2305 2306// Multiply saturating doubling high, D element size2307def : InstRW<[V3Write_5c_2V02], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>;2308 2309// Multiply saturating doubling long2310def : InstRW<[V3Write_4c_1V02], (instregex "^SQDMULL[BT]_ZZZ_[HSD]",2311 "^SQDMULL[BT]_ZZZI_[SD]")>;2312 2313// Multiply saturating rounding doubling regular/complex accumulate, B, H, S2314// element size2315def : InstRW<[V3Wr_ZMASQBHS, V3Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZ_[BHS]",2316 "^SQRDCMLAH_ZZZ_[BHS]",2317 "^SQRDML[AS]H_ZZZI_[HS]",2318 "^SQRDCMLAH_ZZZI_[HS]")>;2319 2320// Multiply saturating rounding doubling regular/complex accumulate, D element2321// size2322def : InstRW<[V3Wr_ZMASQD, V3Rd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZI?_D",2323 "^SQRDCMLAH_ZZZ_D")>;2324 2325// Multiply saturating rounding doubling regular/complex, B, H, S element size2326def : InstRW<[V3Write_4c_1V02], (instregex "^SQRDMULH_ZZZ_[BHS]",2327 "^SQRDMULH_ZZZI_[HS]")>;2328 2329// Multiply saturating rounding doubling regular/complex, D element size2330def : InstRW<[V3Write_5c_2V02], (instregex "^SQRDMULH_ZZZI?_D")>;2331 2332// Multiply/multiply long, (8x8) polynomial2333def : InstRW<[V3Write_2c_1V], (instregex "^PMUL_ZZZ_B",2334 "^PMULL[BT]_ZZZ_[HDQ]")>;2335 2336// Predicate counting vector2337def : InstRW<[V3Write_2c_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI")>;2338 2339// Reciprocal estimate2340def : InstRW<[V3Write_4c_2V02], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;2341 2342// Reduction, arithmetic, B form2343def : InstRW<[V3Write_9c_2V_4V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;2344 2345// Reduction, arithmetic, H form2346def : InstRW<[V3Write_8c_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;2347 2348// Reduction, arithmetic, S form2349def : InstRW<[V3Write_6c_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;2350 2351// Reduction, arithmetic, D form2352def : InstRW<[V3Write_4c_2V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;2353 2354// Reduction, logical2355def : InstRW<[V3Write_6c_1V_1V13], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]")>;2356 2357// Reverse, vector2358def : InstRW<[V3Write_2c_1V], (instregex "^REV_ZZ_[BHSD]",2359 "^REVB_ZPmZ_[HSD]",2360 "^REVH_ZPmZ_[SD]",2361 "^REVW_ZPmZ_D")>;2362 2363// Select, vector form2364def : InstRW<[V3Write_2c_1V], (instregex "^SEL_ZPZZ_[BHSD]")>;2365 2366// Table lookup2367def : InstRW<[V3Write_2c_1V], (instregex "^TBL_ZZZZ?_[BHSD]")>;2368 2369// Table lookup extension2370def : InstRW<[V3Write_2c_1V], (instregex "^TBX_ZZZ_[BHSD]")>;2371 2372// Transpose, vector form2373def : InstRW<[V3Write_2c_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]")>;2374 2375// Unpack and extend2376def : InstRW<[V3Write_2c_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]")>;2377 2378// Zip/unzip2379def : InstRW<[V3Write_2c_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]")>;2380 2381// §3.26 SVE floating-point instructions2382// -----------------------------------------------------------------------------2383 2384// Floating point absolute value/difference2385def : InstRW<[V3Write_2c_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]",2386 "^FABD_ZPZZ_[HSD]",2387 "^FABS_ZPmZ_[HSD]")>;2388 2389// Floating point arithmetic2390def : InstRW<[V3Write_2c_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",2391 "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",2392 "^FADDP_ZPmZZ_[HSD]",2393 "^FNEG_ZPmZ_[HSD]",2394 "^FSUBR_ZPm[IZ]_[HSD]",2395 "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;2396 2397// Floating point associative add, F162398def : InstRW<[V3Write_10c_1V1_9rc], (instrs FADDA_VPZ_H)>;2399 2400// Floating point associative add, F322401def : InstRW<[V3Write_6c_1V1_5rc], (instrs FADDA_VPZ_S)>;2402 2403// Floating point associative add, F642404def : InstRW<[V3Write_4c_1V], (instrs FADDA_VPZ_D)>;2405 2406// Floating point compare2407def : InstRW<[V3Write_2c_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]",2408 "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]",2409 "^FCM(LE|LT)_PPzZ0_[HSD]",2410 "^FCMUO_PPzZZ_[HSD]")>;2411 2412// Floating point complex add2413def : InstRW<[V3Write_3c_1V], (instregex "^FCADD_ZPmZ_[HSD]")>;2414 2415// Floating point complex multiply add2416def : InstRW<[V3Wr_ZFCMA, ReadDefault, V3Rd_ZFCMA], (instregex "^FCMLA_ZPmZZ_[HSD]")>;2417def : InstRW<[V3Wr_ZFCMA, V3Rd_ZFCMA], (instregex "^FCMLA_ZZZI_[HS]")>;2418 2419// Floating point convert, long or narrow (F16 to F32 or F32 to F16)2420def : InstRW<[V3Write_4c_2V02], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",2421 "^FCVTLT_ZPmZ_HtoS",2422 "^FCVTNT_ZPmZ_StoH")>;2423 2424// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F322425// or F64 to F16)2426def : InstRW<[V3Write_3c_1V02], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",2427 "^FCVTLT_ZPmZ_StoD",2428 "^FCVTNT_ZPmZ_DtoS")>;2429 2430// Floating point convert, round to odd2431def : InstRW<[V3Write_3c_1V02], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>;2432 2433// Floating point base2 log, F162434def : InstRW<[V3Write_6c_4V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;2435 2436// Floating point base2 log, F322437def : InstRW<[V3Write_4c_2V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;2438 2439// Floating point base2 log, F642440def : InstRW<[V3Write_3c_1V02], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;2441 2442// Floating point convert to integer, F162443def : InstRW<[V3Write_6c_4V02], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;2444 2445// Floating point convert to integer, F322446def : InstRW<[V3Write_4c_2V02], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;2447 2448// Floating point convert to integer, F642449def : InstRW<[V3Write_3c_1V02],2450 (instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>;2451 2452// Floating point copy2453def : InstRW<[V3Write_2c_1V], (instregex "^FCPY_ZPmI_[HSD]",2454 "^FDUP_ZI_[HSD]")>;2455 2456// Floating point divide, F162457def : InstRW<[V3Write_13c_1V1_8rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;2458 2459// Floating point divide, F322460def : InstRW<[V3Write_11c_1V1_4rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;2461 2462// Floating point divide, F642463def : InstRW<[V3Write_14c_1V1_2rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;2464 2465// Floating point min/max pairwise2466def : InstRW<[V3Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;2467 2468// Floating point min/max2469def : InstRW<[V3Write_2c_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",2470 "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;2471 2472// Floating point multiply2473def : InstRW<[V3Write_3c_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",2474 "^FMULX_ZPZZ_[HSD]",2475 "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",2476 "^FMUL_ZPZ[IZ]_[HSD]")>;2477 2478// Floating point multiply accumulate2479def : InstRW<[V3Wr_ZFMA, ReadDefault, V3Rd_ZFMA],2480 (instregex "^FN?ML[AS]_ZPmZZ_[HSD]",2481 "^FN?(MAD|MSB)_ZPmZZ_[HSD]")>;2482def : InstRW<[V3Wr_ZFMA, V3Rd_ZFMA],2483 (instregex "^FML[AS]_ZZZI_[HSD]",2484 "^FN?ML[AS]_ZPZZZ_[HSD]")>;2485 2486// Floating point multiply add/sub accumulate long2487def : InstRW<[V3Wr_ZFMAL, V3Rd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH")>;2488 2489// Floating point reciprocal estimate, F162490def : InstRW<[V3Write_6c_4V02], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;2491 2492// Floating point reciprocal estimate, F322493def : InstRW<[V3Write_4c_2V02], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>;2494 2495// Floating point reciprocal estimate, F642496def : InstRW<[V3Write_3c_1V02], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>;2497 2498// Floating point reciprocal step2499def : InstRW<[V3Write_4c_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]")>;2500 2501// Floating point reduction, F162502def : InstRW<[V3Write_8c_4V],2503 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H")>;2504 2505// Floating point reduction, F322506def : InstRW<[V3Write_6c_3V],2507 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S")>;2508 2509// Floating point reduction, F642510def : InstRW<[V3Write_4c_2V],2511 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D")>;2512 2513// Floating point round to integral, F162514def : InstRW<[V3Write_6c_4V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;2515 2516// Floating point round to integral, F322517def : InstRW<[V3Write_4c_2V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;2518 2519// Floating point round to integral, F642520def : InstRW<[V3Write_3c_1V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;2521 2522// Floating point square root, F162523def : InstRW<[V3Write_13c_1V1_8rc], (instregex "^FSQRT_ZPmZ_H")>;2524 2525// Floating point square root, F322526def : InstRW<[V3Write_11c_1V1_4rc], (instregex "^FSQRT_ZPmZ_S")>;2527 2528// Floating point square root, F642529def : InstRW<[V3Write_14c_1V1_2rc], (instregex "^FSQRT_ZPmZ_D")>;2530 2531// Floating point trigonometric exponentiation2532def : InstRW<[V3Write_3c_1V1], (instregex "^FEXPA_ZZ_[HSD]")>;2533 2534// Floating point trigonometric multiply add2535def : InstRW<[V3Write_4c_1V], (instregex "^FTMAD_ZZI_[HSD]")>;2536 2537// Floating point trigonometric, miscellaneous2538def : InstRW<[V3Write_3c_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]")>;2539 2540// §3.27 SVE BFloat16 (BF16) instructions2541// -----------------------------------------------------------------------------2542 2543// Convert, F32 to BF162544def : InstRW<[V3Write_4c_1V02], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;2545 2546// Dot product2547def : InstRW<[V3Wr_ZBFDOT, V3Rd_ZBFDOT], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;2548 2549// Matrix multiply accumulate2550def : InstRW<[V3Wr_ZBFMMA, V3Rd_ZBFMMA], (instrs BFMMLA_ZZZ_HtoS)>;2551 2552// Multiply accumulate long2553def : InstRW<[V3Wr_ZBFMAL, V3Rd_ZBFMAL], (instregex "^BFMLAL[BT]_ZZZI?")>;2554 2555// §3.28 SVE Load instructions2556// -----------------------------------------------------------------------------2557 2558// Load vector2559def : InstRW<[V3Write_6c_1L], (instrs LDR_ZXI)>;2560 2561// Load predicate2562def : InstRW<[V3Write_6c_1L_1M], (instrs LDR_PXI)>;2563 2564// Contiguous load, scalar + imm2565def : InstRW<[V3Write_6c_1L], (instregex "^LD1[BHWD]_IMM$",2566 "^LD1S?B_[HSD]_IMM$",2567 "^LD1S?H_[SD]_IMM$",2568 "^LD1S?W_D_IMM$" )>;2569// Contiguous load, scalar + scalar2570def : InstRW<[V3Write_6c_1L], (instregex "^LD1[BHWD]$",2571 "^LD1S?B_[HSD]$",2572 "^LD1S?H_[SD]$",2573 "^LD1S?W_D$" )>;2574 2575// Contiguous load broadcast, scalar + imm2576def : InstRW<[V3Write_6c_1L], (instregex "^LD1R[BHWD]_IMM$",2577 "^LD1RS?B_[HSD]_IMM$",2578 "^LD1RS?H_[SD]_IMM$",2579 "^LD1RW_D_IMM$",2580 "^LD1RSW_IMM$",2581 "^LD1RQ_[BHWD]_IMM$")>;2582 2583// Contiguous load broadcast, scalar + scalar2584def : InstRW<[V3Write_6c_1L], (instregex "^LD1RQ_[BHWD]$")>;2585 2586// Non temporal load, scalar + imm2587// Non temporal load, scalar + scalar2588def : InstRW<[V3Write_6c_1L], (instregex "^LDNT1[BHWD]_ZR[IR]$")>;2589 2590// Non temporal gather load, vector + scalar 32-bit element size2591def : InstRW<[V3Write_9c_2L_4V], (instregex "^LDNT1[BHW]_ZZR_S$",2592 "^LDNT1S[BH]_ZZR_S$")>;2593 2594// Non temporal gather load, vector + scalar 64-bit element size2595def : InstRW<[V3Write_9c_2L_2V], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;2596def : InstRW<[V3Write_9c_2L_2V], (instrs LDNT1D_ZZR_D)>;2597 2598// Contiguous first faulting load, scalar + scalar2599def : InstRW<[V3Write_6c_1L_1I], (instregex "^LDFF1[BHWD]$",2600 "^LDFF1S?B_[HSD]$",2601 "^LDFF1S?H_[SD]$",2602 "^LDFF1S?W_D$")>;2603 2604// Contiguous non faulting load, scalar + imm2605def : InstRW<[V3Write_6c_1L], (instregex "^LDNF1[BHWD]_IMM$",2606 "^LDNF1S?B_[HSD]_IMM$",2607 "^LDNF1S?H_[SD]_IMM$",2608 "^LDNF1S?W_D_IMM$")>;2609 2610// Contiguous Load two structures to two vectors, scalar + imm2611def : InstRW<[V3Write_8c_2L_2V], (instregex "^LD2[BHWD]_IMM$")>;2612 2613// Contiguous Load two structures to two vectors, scalar + scalar2614def : InstRW<[V3Write_9c_2L_2V_2I], (instregex "^LD2[BHWD]$")>;2615 2616// Contiguous Load three structures to three vectors, scalar + imm2617def : InstRW<[V3Write_9c_3L_3V], (instregex "^LD3[BHWD]_IMM$")>;2618 2619// Contiguous Load three structures to three vectors, scalar + scalar2620def : InstRW<[V3Write_10c_3V_3L_3I], (instregex "^LD3[BHWD]$")>;2621 2622// Contiguous Load four structures to four vectors, scalar + imm2623def : InstRW<[V3Write_9c_4L_8V], (instregex "^LD4[BHWD]_IMM$")>;2624 2625// Contiguous Load four structures to four vectors, scalar + scalar2626def : InstRW<[V3Write_10c_4L_8V_4I], (instregex "^LD4[BHWD]$")>;2627 2628// Gather load, vector + imm, 32-bit element size2629def : InstRW<[V3Write_9c_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",2630 "^GLD(FF)?1W_IMM$")>;2631 2632// Gather load, vector + imm, 64-bit element size2633def : InstRW<[V3Write_9c_1L_4V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",2634 "^GLD(FF)?1D_IMM$")>;2635 2636// Gather load, 32-bit scaled offset2637def : InstRW<[V3Write_10c_1L_8V],2638 (instregex "^GLD(FF)?1S?H_S_[SU]XTW_SCALED$",2639 "^GLD(FF)?1W_[SU]XTW_SCALED")>;2640 2641// Gather load, 64-bit scaled offset2642// NOTE: These instructions are not specified in the SOG.2643def : InstRW<[V3Write_10c_1L_4V],2644 (instregex "^GLD(FF)?1S?[HW]_D_([SU]XTW_)?SCALED$",2645 "^GLD(FF)?1D_([SU]XTW_)?SCALED$")>;2646 2647// Gather load, 32-bit unpacked unscaled offset2648def : InstRW<[V3Write_9c_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",2649 "^GLD(FF)?1W_[SU]XTW$")>;2650 2651// Gather load, 64-bit unpacked unscaled offset2652// NOTE: These instructions are not specified in the SOG.2653def : InstRW<[V3Write_9c_1L_2V],2654 (instregex "^GLD(FF)?1S?[BHW]_D(_[SU]XTW)?$",2655 "^GLD(FF)?1D(_[SU]XTW)?$")>;2656 2657// §3.29 SVE Store instructions2658// -----------------------------------------------------------------------------2659 2660// Store from predicate reg2661def : InstRW<[V3Write_1c_1SA], (instrs STR_PXI)>;2662 2663// Store from vector reg2664def : InstRW<[V3Write_2c_1SA_1V01], (instrs STR_ZXI)>;2665 2666// Contiguous store, scalar + imm2667def : InstRW<[V3Write_2c_1SA_1V01], (instregex "^ST1[BHWD]_IMM$",2668 "^ST1B_[HSD]_IMM$",2669 "^ST1H_[SD]_IMM$",2670 "^ST1W_D_IMM$")>;2671 2672// Contiguous store, scalar + scalar2673def : InstRW<[V3Write_2c_1SA_1I_1V01], (instregex "^ST1H(_[SD])?$")>;2674def : InstRW<[V3Write_2c_1SA_1V01], (instregex "^ST1[BWD]$",2675 "^ST1B_[HSD]$",2676 "^ST1W_D$")>;2677 2678// Contiguous store two structures from two vectors, scalar + imm2679def : InstRW<[V3Write_4c_1SA_1V01], (instregex "^ST2[BHWD]_IMM$")>;2680 2681// Contiguous store two structures from two vectors, scalar + scalar2682def : InstRW<[V3Write_4c_2SA_2I_2V01], (instrs ST2H)>;2683def : InstRW<[V3Write_4c_2SA_2V01], (instregex "^ST2[BWD]$")>;2684 2685// Contiguous store three structures from three vectors, scalar + imm2686def : InstRW<[V3Write_7c_9SA_9V01], (instregex "^ST3[BHWD]_IMM$")>;2687 2688// Contiguous store three structures from three vectors, scalar + scalar2689def : InstRW<[V3Write_7c_9SA_9I_9V01], (instregex "^ST3[BHWD]$")>;2690 2691// Contiguous store four structures from four vectors, scalar + imm2692def : InstRW<[V3Write_11c_18SA_18V01], (instregex "^ST4[BHWD]_IMM$")>;2693 2694// Contiguous store four structures from four vectors, scalar + scalar2695def : InstRW<[V3Write_11c_18SA_18I_18V01], (instregex "^ST4[BHWD]$")>;2696 2697// Non temporal store, scalar + imm2698def : InstRW<[V3Write_2c_1SA_1V01], (instregex "^STNT1[BHWD]_ZRI$")>;2699 2700// Non temporal store, scalar + scalar2701def : InstRW<[V3Write_2c_1SA_1I_1V01], (instrs STNT1H_ZRR)>;2702def : InstRW<[V3Write_2c_1SA_1V01], (instregex "^STNT1[BWD]_ZRR$")>;2703 2704// Scatter non temporal store, vector + scalar 32-bit element size2705def : InstRW<[V3Write_4c_6SA_6V01], (instregex "^STNT1[BHW]_ZZR_S")>;2706 2707// Scatter non temporal store, vector + scalar 64-bit element size2708def : InstRW<[V3Write_2c_3SA_3V01], (instregex "^STNT1[BHWD]_ZZR_D")>;2709 2710// Scatter store vector + imm 32-bit element size2711def : InstRW<[V3Write_4c_6SA_6V01], (instregex "^SST1[BH]_S_IMM$",2712 "^SST1W_IMM$")>;2713 2714// Scatter store vector + imm 64-bit element size2715def : InstRW<[V3Write_2c_3SA_3V01], (instregex "^SST1[BHW]_D_IMM$",2716 "^SST1D_IMM$")>;2717 2718// Scatter store, 32-bit scaled offset2719def : InstRW<[V3Write_4c_6SA_6V01],2720 (instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>;2721 2722// Scatter store, 32-bit unpacked unscaled offset2723def : InstRW<[V3Write_2c_3SA_3V01], (instregex "^SST1[BHW]_D_[SU]XTW$",2724 "^SST1D_[SU]XTW$")>;2725 2726// Scatter store, 32-bit unpacked scaled offset2727def : InstRW<[V3Write_2c_3SA_3V01], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",2728 "^SST1D_[SU]XTW_SCALED$")>;2729 2730// Scatter store, 32-bit unscaled offset2731def : InstRW<[V3Write_4c_6SA_6V01], (instregex "^SST1[BH]_S_[SU]XTW$",2732 "^SST1W_[SU]XTW$")>;2733 2734// Scatter store, 64-bit scaled offset2735def : InstRW<[V3Write_2c_3SA_3V01], (instregex "^SST1[HW]_D_SCALED$",2736 "^SST1D_SCALED$")>;2737 2738// Scatter store, 64-bit unscaled offset2739def : InstRW<[V3Write_2c_3SA_3V01], (instregex "^SST1[BHW]_D$",2740 "^SST1D$")>;2741 2742// §3.30 SVE Miscellaneous instructions2743// -----------------------------------------------------------------------------2744 2745// Read first fault register, unpredicated2746def : InstRW<[V3Write_2c_1M0], (instrs RDFFR_P)>;2747 2748// Read first fault register, predicated2749def : InstRW<[V3Write_3or4c_1M0_1M], (instrs RDFFR_PPz)>;2750 2751// Read first fault register and set flags2752def : InstRW<[V3Write_3or4c_1M0_1M], (instrs RDFFRS_PPz)>;2753 2754// Set first fault register2755// Write to first fault register2756def : InstRW<[V3Write_2c_1M0], (instrs SETFFR, WRFFR)>;2757 2758// Prefetch2759// NOTE: This is not specified in the SOG.2760def : InstRW<[V3Write_4c_1L], (instregex "^PRF[BHWD]")>;2761 2762// §3.31 SVE Cryptographic instructions2763// -----------------------------------------------------------------------------2764 2765// Crypto AES ops2766def : InstRW<[V3Write_2c_1V], (instregex "^AES[DE]_ZZZ_B$",2767 "^AESI?MC_ZZ_B$")>;2768 2769// Crypto SHA3 ops2770def : InstRW<[V3Write_2c_1V], (instregex "^(BCAX|EOR3)_ZZZZ$",2771 "^RAX1_ZZZ_D$",2772 "^XAR_ZZZI_[BHSD]$")>;2773 2774// Crypto SM4 ops2775def : InstRW<[V3Write_4c_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;2776 2777}2778