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1//=- AArch64SchedNeoverseV3AE.td - NeoverseV3AE Scheduling Defs --*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the scheduling model for the Arm Neoverse V3AE processors.10// All information is taken from the V3AE Software Optimisation guide:11//12// https://developer.arm.com/documentation/109703/300/?lang=en13//14//===----------------------------------------------------------------------===//15 16def NeoverseV3AEModel : SchedMachineModel {17 let IssueWidth = 10; // Expect best value to be slightly higher than V218 let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. NOTE: Copied from Neoverse-V219 let LoadLatency = 4; // Optimistic load latency.20 let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.21 let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.22 let CompleteModel = 1;23 24 list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,25 [HasSVE2p1, HasSVEB16B16,26 HasCPA, HasCSSC]);27}28 29//===----------------------------------------------------------------------===//30// Define each kind of processor resource and number available on Neoverse V3AE.31// Instructions are first fetched and then decoded into internal macro-ops32// (MOPs). From there, the MOPs proceed through register renaming and dispatch33// stages. A MOP can be split into two micro-ops further down the pipeline34// after the decode stage. Once dispatched, micro-ops wait for their operands35// and issue out-of-order to one of nineteen issue pipelines. Each issue36// pipeline can accept one micro-op per cycle.37 38let SchedModel = NeoverseV3AEModel in {39 40// Define the (19) issue ports.41def V3AEUnitB : ProcResource<3>; // Branch 0/1/242def V3AEUnitS0 : ProcResource<1>; // Integer single-cycle 043def V3AEUnitS1 : ProcResource<1>; // Integer single-cycle 144def V3AEUnitS2 : ProcResource<1>; // Integer single-cycle 245def V3AEUnitS3 : ProcResource<1>; // Integer single-cycle 346def V3AEUnitS4 : ProcResource<1>; // Integer single-cycle 447def V3AEUnitS5 : ProcResource<1>; // Integer single-cycle 548def V3AEUnitM0 : ProcResource<1>; // Integer single/multicycle 049def V3AEUnitM1 : ProcResource<1>; // Integer single/multicycle 150def V3AEUnitV0 : ProcResource<1>; // FP/ASIMD 051def V3AEUnitV1 : ProcResource<1>; // FP/ASIMD 152def V3AEUnitLS0 : ProcResource<1>; // Load/Store 053def V3AEUnitL12 : ProcResource<2>; // Load 1/254def V3AEUnitST1 : ProcResource<1>; // Store 155def V3AEUnitD : ProcResource<2>; // Store data 0/156def V3AEUnitFlg : ProcResource<4>; // Flags57 58def V3AEUnitS : ProcResGroup<[V3AEUnitS0, V3AEUnitS1, V3AEUnitS2, V3AEUnitS3, V3AEUnitS4, V3AEUnitS5]>; // Integer single-cycle 0/1/2/3/4/559def V3AEUnitI : ProcResGroup<[V3AEUnitS0, V3AEUnitS1, V3AEUnitS2, V3AEUnitS3, V3AEUnitS4, V3AEUnitS5, V3AEUnitM0, V3AEUnitM1]>; // Integer single-cycle 0/1/2/3/4/5 and single/multicycle 0/160def V3AEUnitM : ProcResGroup<[V3AEUnitM0, V3AEUnitM1]>; // Integer single/multicycle 0/161def V3AEUnitLSA : ProcResGroup<[V3AEUnitLS0, V3AEUnitL12, V3AEUnitST1]>; // Supergroup of L+SA62def V3AEUnitL : ProcResGroup<[V3AEUnitLS0, V3AEUnitL12]>; // Load/Store 0 and Load 1/263def V3AEUnitSA : ProcResGroup<[V3AEUnitLS0, V3AEUnitST1]>; // Load/Store 0 and Store 164def V3AEUnitV : ProcResGroup<[V3AEUnitV0, V3AEUnitV1]>; // FP/ASIMD 0/165 66// Define commonly used read types.67 68// No forwarding is provided for these types.69def : ReadAdvance<ReadI, 0>;70def : ReadAdvance<ReadISReg, 0>;71def : ReadAdvance<ReadIEReg, 0>;72def : ReadAdvance<ReadIM, 0>;73def : ReadAdvance<ReadIMA, 0>;74def : ReadAdvance<ReadID, 0>;75def : ReadAdvance<ReadExtrHi, 0>;76def : ReadAdvance<ReadAdrBase, 0>;77def : ReadAdvance<ReadST, 0>;78def : ReadAdvance<ReadVLD, 0>;79 80// NOTE: Copied from N2.81def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }82def : WriteRes<WriteBarrier, []> { let Latency = 1; }83def : WriteRes<WriteHint, []> { let Latency = 1; }84def : WriteRes<WriteLDHi, []> { let Latency = 4; }85 86//===----------------------------------------------------------------------===//87// Define customized scheduler read/write types specific to the Neoverse V3AE.88 89//===----------------------------------------------------------------------===//90 91// Define generic 0 micro-op types92def V3AEWrite_0c : SchedWriteRes<[]> { let Latency = 0; }93 94// Define generic 1 micro-op types95 96def V3AEWrite_1c_1B : SchedWriteRes<[V3AEUnitB]> { let Latency = 1; }97def V3AEWrite_1c_1F_1Flg : SchedWriteRes<[V3AEUnitI, V3AEUnitFlg]> { let Latency = 1; }98def V3AEWrite_1c_1I : SchedWriteRes<[V3AEUnitI]> { let Latency = 1; }99def V3AEWrite_1c_1M : SchedWriteRes<[V3AEUnitM]> { let Latency = 1; }100def V3AEWrite_1c_1SA : SchedWriteRes<[V3AEUnitSA]> { let Latency = 1; }101def V3AEWrite_2c_1M : SchedWriteRes<[V3AEUnitM]> { let Latency = 2; }102def V3AEWrite_2c_1M_1Flg : SchedWriteRes<[V3AEUnitM, V3AEUnitFlg]> { let Latency = 2; }103def V3AEWrite_3c_1M : SchedWriteRes<[V3AEUnitM]> { let Latency = 3; }104def V3AEWrite_2c_1M0 : SchedWriteRes<[V3AEUnitM0]> { let Latency = 2; }105def V3AEWrite_3c_1M0 : SchedWriteRes<[V3AEUnitM0]> { let Latency = 3; }106def V3AEWrite_4c_1M0 : SchedWriteRes<[V3AEUnitM0]> { let Latency = 4; }107def V3AEWrite_12c_1M0 : SchedWriteRes<[V3AEUnitM0]> { let Latency = 12;108 let ReleaseAtCycles = [12]; }109def V3AEWrite_20c_1M0 : SchedWriteRes<[V3AEUnitM0]> { let Latency = 20;110 let ReleaseAtCycles = [20]; }111def V3AEWrite_4c_1L : SchedWriteRes<[V3AEUnitL]> { let Latency = 4; }112def V3AEWrite_6c_1L : SchedWriteRes<[V3AEUnitL]> { let Latency = 6; }113def V3AEWrite_2c_1V : SchedWriteRes<[V3AEUnitV]> { let Latency = 2; }114def V3AEWrite_2c_1V0 : SchedWriteRes<[V3AEUnitV0]> { let Latency = 2; }115def V3AEWrite_3c_1V : SchedWriteRes<[V3AEUnitV]> { let Latency = 3; }116def V3AEWrite_4c_1V : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }117def V3AEWrite_5c_1V : SchedWriteRes<[V3AEUnitV]> { let Latency = 5; }118def V3AEWrite_6c_1V : SchedWriteRes<[V3AEUnitV]> { let Latency = 6; }119def V3AEWrite_12c_1V : SchedWriteRes<[V3AEUnitV]> { let Latency = 12; }120def V3AEWrite_3c_1V0 : SchedWriteRes<[V3AEUnitV0]> { let Latency = 3; }121def V3AEWrite_4c_1V0 : SchedWriteRes<[V3AEUnitV0]> { let Latency = 4; }122def V3AEWrite_9c_1V0 : SchedWriteRes<[V3AEUnitV0]> { let Latency = 9; }123def V3AEWrite_10c_1V0 : SchedWriteRes<[V3AEUnitV0]> { let Latency = 10; }124def V3AEWrite_8c_1V1 : SchedWriteRes<[V3AEUnitV1]> { let Latency = 8; }125def V3AEWrite_12c_1V0 : SchedWriteRes<[V3AEUnitV0]> { let Latency = 12;126 let ReleaseAtCycles = [11]; }127def V3AEWrite_13c_1V0 : SchedWriteRes<[V3AEUnitV0]> { let Latency = 13; }128def V3AEWrite_15c_1V0 : SchedWriteRes<[V3AEUnitV0]> { let Latency = 15; }129def V3AEWrite_13c_1V1 : SchedWriteRes<[V3AEUnitV1]> { let Latency = 13;130 let ReleaseAtCycles = [8]; }131def V3AEWrite_16c_1V0 : SchedWriteRes<[V3AEUnitV0]> { let Latency = 16; }132def V3AEWrite_20c_1V0 : SchedWriteRes<[V3AEUnitV0]> { let Latency = 20;133 let ReleaseAtCycles = [20]; }134def V3AEWrite_2c_1V1 : SchedWriteRes<[V3AEUnitV1]> { let Latency = 2; }135def V3AEWrite_3c_1V1 : SchedWriteRes<[V3AEUnitV1]> { let Latency = 3; }136def V3AEWrite_4c_1V1 : SchedWriteRes<[V3AEUnitV1]> { let Latency = 4; }137def V3AEWrite_6c_1V1 : SchedWriteRes<[V3AEUnitV1]> { let Latency = 6; }138def V3AEWrite_10c_1V1 : SchedWriteRes<[V3AEUnitV1]> { let Latency = 10; }139def V3AEWrite_6c_1SA : SchedWriteRes<[V3AEUnitSA]> { let Latency = 6; }140 141//===----------------------------------------------------------------------===//142// Define generic 2 micro-op types143 144def V3AEWrite_1c_1B_1S : SchedWriteRes<[V3AEUnitB, V3AEUnitS]> {145 let Latency = 1;146 let NumMicroOps = 2;147}148 149def V3AEWrite_6c_1M0_1B : SchedWriteRes<[V3AEUnitM0, V3AEUnitB]> {150 let Latency = 6;151 let NumMicroOps = 2;152}153 154def V3AEWrite_9c_1M0_1L : SchedWriteRes<[V3AEUnitM0, V3AEUnitL]> {155 let Latency = 9;156 let NumMicroOps = 2;157}158 159def V3AEWrite_3c_1I_1M : SchedWriteRes<[V3AEUnitI, V3AEUnitM]> {160 let Latency = 3;161 let NumMicroOps = 2;162}163 164def V3AEWrite_1c_2M : SchedWriteRes<[V3AEUnitM, V3AEUnitM]> {165 let Latency = 1;166 let NumMicroOps = 2;167}168 169def V3AEWrite_3c_2M : SchedWriteRes<[V3AEUnitM, V3AEUnitM]> {170 let Latency = 3;171 let NumMicroOps = 2;172}173 174def V3AEWrite_4c_2M : SchedWriteRes<[V3AEUnitM, V3AEUnitM]> {175 let Latency = 4;176 let NumMicroOps = 2;177}178 179def V3AEWrite_5c_1L_1I : SchedWriteRes<[V3AEUnitL, V3AEUnitI]> {180 let Latency = 5;181 let NumMicroOps = 2;182}183 184def V3AEWrite_6c_1I_1L : SchedWriteRes<[V3AEUnitI, V3AEUnitL]> {185 let Latency = 6;186 let NumMicroOps = 2;187}188 189def V3AEWrite_7c_1I_1L : SchedWriteRes<[V3AEUnitI, V3AEUnitL]> {190 let Latency = 7;191 let NumMicroOps = 2;192}193 194def V3AEWrite_1c_1SA_1D : SchedWriteRes<[V3AEUnitSA, V3AEUnitD]> {195 let Latency = 1;196 let NumMicroOps = 2;197}198 199def V3AEWrite_5c_1M0_1V : SchedWriteRes<[V3AEUnitM0, V3AEUnitV]> {200 let Latency = 5;201 let NumMicroOps = 2;202}203 204def V3AEWrite_2c_1SA_1V : SchedWriteRes<[V3AEUnitSA, V3AEUnitV]> {205 let Latency = 2;206 let NumMicroOps = 2;207}208 209def V3AEWrite_2c_2V : SchedWriteRes<[V3AEUnitV, V3AEUnitV]> {210 let Latency = 2;211 let NumMicroOps = 2;212}213 214def V3AEWrite_5c_1V1_1V : SchedWriteRes<[V3AEUnitV1, V3AEUnitV]> {215 let Latency = 5;216 let NumMicroOps = 2;217}218 219def V3AEWrite_4c_2V0 : SchedWriteRes<[V3AEUnitV0, V3AEUnitV0]> {220 let Latency = 4;221 let NumMicroOps = 2;222}223 224def V3AEWrite_4c_2V : SchedWriteRes<[V3AEUnitV, V3AEUnitV]> {225 let Latency = 4;226 let NumMicroOps = 2;227}228 229def V3AEWrite_6c_2V : SchedWriteRes<[V3AEUnitV, V3AEUnitV]> {230 let Latency = 6;231 let NumMicroOps = 2;232}233 234def V3AEWrite_6c_2L : SchedWriteRes<[V3AEUnitL, V3AEUnitL]> {235 let Latency = 6;236 let NumMicroOps = 2;237}238 239def V3AEWrite_8c_1L_1V : SchedWriteRes<[V3AEUnitL, V3AEUnitV]> {240 let Latency = 8;241 let NumMicroOps = 2;242}243 244def V3AEWrite_4c_1SA_1V : SchedWriteRes<[V3AEUnitSA, V3AEUnitV]> {245 let Latency = 4;246 let NumMicroOps = 2;247}248 249def V3AEWrite_3c_1M0_1M : SchedWriteRes<[V3AEUnitM0, V3AEUnitM]> {250 let Latency = 3;251 let NumMicroOps = 2;252}253 254def V3AEWrite_4c_1M0_1M : SchedWriteRes<[V3AEUnitM0, V3AEUnitM]> {255 let Latency = 4;256 let NumMicroOps = 2;257}258 259def V3AEWrite_1c_1M0_1M : SchedWriteRes<[V3AEUnitM0, V3AEUnitM]> {260 let Latency = 1;261 let NumMicroOps = 2;262}263 264def V3AEWrite_2c_1M0_1M : SchedWriteRes<[V3AEUnitM0, V3AEUnitM]> {265 let Latency = 2;266 let NumMicroOps = 2;267}268 269def V3AEWrite_6c_2V1 : SchedWriteRes<[V3AEUnitV1, V3AEUnitV1]> {270 let Latency = 6;271 let NumMicroOps = 2;272}273 274def V3AEWrite_5c_2V0 : SchedWriteRes<[V3AEUnitV0, V3AEUnitV0]> {275 let Latency = 5;276 let NumMicroOps = 2;277}278 279def V3AEWrite_5c_1V1_1M0 : SchedWriteRes<[V3AEUnitV1, V3AEUnitM0]> {280 let Latency = 5;281 let NumMicroOps = 2;282}283 284def V3AEWrite_6c_1V1_1M0 : SchedWriteRes<[V3AEUnitV1, V3AEUnitM0]> {285 let Latency = 6;286 let NumMicroOps = 2;287}288 289def V3AEWrite_7c_1M0_1V0 : SchedWriteRes<[V3AEUnitM0, V3AEUnitV0]> {290 let Latency = 7;291 let NumMicroOps = 2;292}293 294def V3AEWrite_2c_1V0_1M : SchedWriteRes<[V3AEUnitV0, V3AEUnitM]> {295 let Latency = 2;296 let NumMicroOps = 2;297}298 299def V3AEWrite_3c_1V0_1M : SchedWriteRes<[V3AEUnitV0, V3AEUnitM]> {300 let Latency = 3;301 let NumMicroOps = 2;302}303 304def V3AEWrite_6c_1V_1V1 : SchedWriteRes<[V3AEUnitV, V3AEUnitV1]> {305 let Latency = 6;306 let NumMicroOps = 2;307}308 309def V3AEWrite_6c_1L_1M : SchedWriteRes<[V3AEUnitL, V3AEUnitM]> {310 let Latency = 6;311 let NumMicroOps = 2;312}313 314def V3AEWrite_6c_1L_1I : SchedWriteRes<[V3AEUnitL, V3AEUnitI]> {315 let Latency = 6;316 let NumMicroOps = 2;317}318 319def V3AEWrite_8c_1M0_1V : SchedWriteRes<[V3AEUnitM0, V3AEUnitV]> {320 let Latency = 8;321 let NumMicroOps = 2;322}323 324//===----------------------------------------------------------------------===//325// Define generic 3 micro-op types326 327def V3AEWrite_1c_1SA_1D_1I : SchedWriteRes<[V3AEUnitSA, V3AEUnitD, V3AEUnitI]> {328 let Latency = 1;329 let NumMicroOps = 3;330}331 332def V3AEWrite_2c_1SA_1V_1I : SchedWriteRes<[V3AEUnitSA, V3AEUnitV, V3AEUnitI]> {333 let Latency = 2;334 let NumMicroOps = 3;335}336 337def V3AEWrite_2c_1SA_2V : SchedWriteRes<[V3AEUnitSA, V3AEUnitV, V3AEUnitV]> {338 let Latency = 2;339 let NumMicroOps = 3;340}341 342def V3AEWrite_4c_1SA_2V : SchedWriteRes<[V3AEUnitSA, V3AEUnitV, V3AEUnitV]> {343 let Latency = 4;344 let NumMicroOps = 3;345}346 347def V3AEWrite_9c_1L_2V : SchedWriteRes<[V3AEUnitL, V3AEUnitV, V3AEUnitV]> {348 let Latency = 9;349 let NumMicroOps = 3;350}351 352def V3AEWrite_4c_3V : SchedWriteRes<[V3AEUnitV, V3AEUnitV, V3AEUnitV]> {353 let Latency = 4;354 let NumMicroOps = 3;355}356 357def V3AEWrite_7c_1M_1M0_1V : SchedWriteRes<[V3AEUnitM, V3AEUnitM0, V3AEUnitV]> {358 let Latency = 7;359 let NumMicroOps = 3;360}361 362def V3AEWrite_2c_1SA_1I_1V : SchedWriteRes<[V3AEUnitSA, V3AEUnitI, V3AEUnitV]> {363 let Latency = 2;364 let NumMicroOps = 3;365}366 367def V3AEWrite_6c_3L : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitL]> {368 let Latency = 6;369 let NumMicroOps = 3;370}371 372def V3AEWrite_6c_3V : SchedWriteRes<[V3AEUnitV, V3AEUnitV, V3AEUnitV]> {373 let Latency = 6;374 let NumMicroOps = 3;375}376 377def V3AEWrite_8c_1L_2V : SchedWriteRes<[V3AEUnitL, V3AEUnitV, V3AEUnitV]> {378 let Latency = 8;379 let NumMicroOps = 3;380}381 382//===----------------------------------------------------------------------===//383// Define generic 4 micro-op types384 385def V3AEWrite_2c_1SA_2V_1I : SchedWriteRes<[V3AEUnitSA, V3AEUnitV, V3AEUnitV,386 V3AEUnitI]> {387 let Latency = 2;388 let NumMicroOps = 4;389}390 391def V3AEWrite_5c_1I_3L : SchedWriteRes<[V3AEUnitI, V3AEUnitL, V3AEUnitL, V3AEUnitL]> {392 let Latency = 5;393 let NumMicroOps = 4;394}395 396def V3AEWrite_6c_4V0 : SchedWriteRes<[V3AEUnitV0, V3AEUnitV0, V3AEUnitV0, V3AEUnitV0]> {397 let Latency = 6;398 let NumMicroOps = 4;399}400 401def V3AEWrite_8c_4V : SchedWriteRes<[V3AEUnitV, V3AEUnitV, V3AEUnitV, V3AEUnitV]> {402 let Latency = 8;403 let NumMicroOps = 4;404}405 406def V3AEWrite_6c_2V_2V1 : SchedWriteRes<[V3AEUnitV, V3AEUnitV, V3AEUnitV1,407 V3AEUnitV1]> {408 let Latency = 6;409 let NumMicroOps = 4;410}411 412def V3AEWrite_6c_4V : SchedWriteRes<[V3AEUnitV, V3AEUnitV, V3AEUnitV, V3AEUnitV]> {413 let Latency = 6;414 let NumMicroOps = 4;415}416 417def V3AEWrite_8c_2L_2V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitV, V3AEUnitV]> {418 let Latency = 8;419 let NumMicroOps = 4;420}421 422def V3AEWrite_9c_2L_2V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitV, V3AEUnitV]> {423 let Latency = 9;424 let NumMicroOps = 4;425}426 427def V3AEWrite_2c_2SA_2V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitV,428 V3AEUnitV]> {429 let Latency = 2;430 let NumMicroOps = 4;431}432 433def V3AEWrite_4c_2SA_2V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitV,434 V3AEUnitV]> {435 let Latency = 4;436 let NumMicroOps = 4;437}438 439def V3AEWrite_8c_2M0_2V0 : SchedWriteRes<[V3AEUnitM0, V3AEUnitM0, V3AEUnitV0,440 V3AEUnitV0]> {441 let Latency = 8;442 let NumMicroOps = 4;443}444 445def V3AEWrite_8c_2V_2V1 : SchedWriteRes<[V3AEUnitV, V3AEUnitV, V3AEUnitV1,446 V3AEUnitV1]> {447 let Latency = 8;448 let NumMicroOps = 4;449}450 451def V3AEWrite_4c_2M0_2M : SchedWriteRes<[V3AEUnitM0, V3AEUnitM0, V3AEUnitM,452 V3AEUnitM]> {453 let Latency = 4;454 let NumMicroOps = 4;455}456 457def V3AEWrite_5c_2M0_2M : SchedWriteRes<[V3AEUnitM0, V3AEUnitM0, V3AEUnitM,458 V3AEUnitM]> {459 let Latency = 5;460 let NumMicroOps = 4;461}462 463def V3AEWrite_6c_2I_2L : SchedWriteRes<[V3AEUnitI, V3AEUnitI, V3AEUnitL, V3AEUnitL]> {464 let Latency = 6;465 let NumMicroOps = 4;466}467 468def V3AEWrite_7c_4L : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitL, V3AEUnitL]> {469 let Latency = 7;470 let NumMicroOps = 4;471}472 473def V3AEWrite_6c_1SA_3V : SchedWriteRes<[V3AEUnitSA, V3AEUnitV, V3AEUnitV,474 V3AEUnitV]> {475 let Latency = 6;476 let NumMicroOps = 4;477}478 479//===----------------------------------------------------------------------===//480// Define generic 5 micro-op types481 482def V3AEWrite_2c_1SA_2V_2I : SchedWriteRes<[V3AEUnitSA, V3AEUnitV, V3AEUnitV,483 V3AEUnitI, V3AEUnitI]> {484 let Latency = 2;485 let NumMicroOps = 5;486}487 488def V3AEWrite_8c_2L_3V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitV, V3AEUnitV,489 V3AEUnitV]> {490 let Latency = 8;491 let NumMicroOps = 5;492}493 494def V3AEWrite_9c_1L_4V : SchedWriteRes<[V3AEUnitL, V3AEUnitV, V3AEUnitV, V3AEUnitV,495 V3AEUnitV]> {496 let Latency = 9;497 let NumMicroOps = 5;498}499 500def V3AEWrite_10c_1L_4V : SchedWriteRes<[V3AEUnitL, V3AEUnitV, V3AEUnitV, V3AEUnitV,501 V3AEUnitV]> {502 let Latency = 10;503 let NumMicroOps = 5;504}505 506def V3AEWrite_6c_5V : SchedWriteRes<[V3AEUnitV, V3AEUnitV, V3AEUnitV, V3AEUnitV,507 V3AEUnitV]> {508 let Latency = 6;509 let NumMicroOps = 5;510}511 512//===----------------------------------------------------------------------===//513// Define generic 6 micro-op types514 515def V3AEWrite_8c_3L_3V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitL,516 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {517 let Latency = 8;518 let NumMicroOps = 6;519}520 521def V3AEWrite_9c_3L_3V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitL,522 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {523 let Latency = 9;524 let NumMicroOps = 6;525}526 527def V3AEWrite_9c_2L_4V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitV,528 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {529 let Latency = 9;530 let NumMicroOps = 6;531}532 533def V3AEWrite_9c_2L_2V_2I : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitV,534 V3AEUnitV, V3AEUnitI, V3AEUnitI]> {535 let Latency = 9;536 let NumMicroOps = 6;537}538 539def V3AEWrite_9c_2V_4V1 : SchedWriteRes<[V3AEUnitV, V3AEUnitV, V3AEUnitV1,540 V3AEUnitV1, V3AEUnitV1, V3AEUnitV1]> {541 let Latency = 9;542 let NumMicroOps = 6;543}544 545def V3AEWrite_2c_3SA_3V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,546 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {547 let Latency = 2;548 let NumMicroOps = 6;549}550 551def V3AEWrite_4c_2SA_4V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitV,552 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {553 let Latency = 4;554 let NumMicroOps = 6;555}556 557def V3AEWrite_5c_2SA_4V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitV,558 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {559 let Latency = 5;560 let NumMicroOps = 6;561}562 563def V3AEWrite_4c_2SA_2I_2V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitI,564 V3AEUnitI, V3AEUnitV, V3AEUnitV]> {565 let Latency = 4;566 let NumMicroOps = 6;567}568 569//===----------------------------------------------------------------------===//570// Define generic 7 micro-op types571 572def V3AEWrite_8c_3L_4V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitL,573 V3AEUnitV, V3AEUnitV, V3AEUnitV,574 V3AEUnitV]> {575 let Latency = 8;576 let NumMicroOps = 7;577}578 579//===----------------------------------------------------------------------===//580// Define generic 8 micro-op types581 582def V3AEWrite_2c_4SA_4V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,583 V3AEUnitSA, V3AEUnitV, V3AEUnitV, V3AEUnitV,584 V3AEUnitV]> {585 let Latency = 2;586 let NumMicroOps = 8;587}588 589def V3AEWrite_4c_4SA_4V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,590 V3AEUnitSA, V3AEUnitV, V3AEUnitV,591 V3AEUnitV, V3AEUnitV]> {592 let Latency = 4;593 let NumMicroOps = 8;594}595 596def V3AEWrite_6c_2SA_6V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitV,597 V3AEUnitV, V3AEUnitV, V3AEUnitV,598 V3AEUnitV, V3AEUnitV]> {599 let Latency = 6;600 let NumMicroOps = 8;601}602 603def V3AEWrite_8c_4L_4V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitL, V3AEUnitL,604 V3AEUnitV, V3AEUnitV, V3AEUnitV,605 V3AEUnitV]> {606 let Latency = 8;607 let NumMicroOps = 8;608}609 610//===----------------------------------------------------------------------===//611// Define generic 9 micro-op types612 613def V3AEWrite_6c_3SA_6V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,614 V3AEUnitV, V3AEUnitV, V3AEUnitV,615 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {616 let Latency = 6;617 let NumMicroOps = 9;618}619 620def V3AEWrite_10c_1L_8V : SchedWriteRes<[V3AEUnitL, V3AEUnitV, V3AEUnitV, V3AEUnitV,621 V3AEUnitV, V3AEUnitV, V3AEUnitV, V3AEUnitV,622 V3AEUnitV]> {623 let Latency = 10;624 let NumMicroOps = 9;625}626 627def V3AEWrite_10c_3V_3L_3I : SchedWriteRes<[V3AEUnitV, V3AEUnitV, V3AEUnitV,628 V3AEUnitL, V3AEUnitL, V3AEUnitL,629 V3AEUnitI, V3AEUnitI, V3AEUnitI]> {630 let Latency = 10;631 let NumMicroOps = 9;632}633 634//===----------------------------------------------------------------------===//635// Define generic 10 micro-op types636 637def V3AEWrite_9c_6L_4V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitL, V3AEUnitL,638 V3AEUnitL, V3AEUnitL, V3AEUnitV, V3AEUnitV,639 V3AEUnitV, V3AEUnitV]> {640 let Latency = 9;641 let NumMicroOps = 10;642}643 644//===----------------------------------------------------------------------===//645// Define generic 12 micro-op types646 647def V3AEWrite_5c_4SA_8V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,648 V3AEUnitSA, V3AEUnitV, V3AEUnitV,649 V3AEUnitV, V3AEUnitV, V3AEUnitV,650 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {651 let Latency = 5;652 let NumMicroOps = 12;653}654 655def V3AEWrite_9c_4L_8V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitL,656 V3AEUnitL, V3AEUnitV, V3AEUnitV,657 V3AEUnitV, V3AEUnitV, V3AEUnitV,658 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {659 let Latency = 9;660 let NumMicroOps = 12;661}662 663def V3AEWrite_10c_4L_8V : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitL,664 V3AEUnitL, V3AEUnitV, V3AEUnitV,665 V3AEUnitV, V3AEUnitV, V3AEUnitV,666 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {667 let Latency = 10;668 let NumMicroOps = 12;669}670 671//===----------------------------------------------------------------------===//672// Define generic 16 micro-op types673 674def V3AEWrite_7c_4SA_12V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,675 V3AEUnitSA, V3AEUnitV, V3AEUnitV,676 V3AEUnitV, V3AEUnitV, V3AEUnitV,677 V3AEUnitV, V3AEUnitV, V3AEUnitV,678 V3AEUnitV, V3AEUnitV, V3AEUnitV,679 V3AEUnitV]> {680 let Latency = 7;681 let NumMicroOps = 16;682}683 684def V3AEWrite_10c_4L_8V_4I : SchedWriteRes<[V3AEUnitL, V3AEUnitL, V3AEUnitL,685 V3AEUnitL, V3AEUnitV, V3AEUnitV,686 V3AEUnitV, V3AEUnitV, V3AEUnitV,687 V3AEUnitV, V3AEUnitV, V3AEUnitV,688 V3AEUnitI, V3AEUnitI, V3AEUnitI,689 V3AEUnitI]> {690 let Latency = 10;691 let NumMicroOps = 16;692}693 694//===----------------------------------------------------------------------===//695// Define generic 18 micro-op types696 697def V3AEWrite_7c_9SA_9V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,698 V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,699 V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,700 V3AEUnitV, V3AEUnitV, V3AEUnitV,701 V3AEUnitV, V3AEUnitV, V3AEUnitV,702 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {703 let Latency = 7;704 let NumMicroOps = 18;705}706 707//===----------------------------------------------------------------------===//708// Define generic 27 micro-op types709 710def V3AEWrite_7c_9SA_9I_9V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,711 V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,712 V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,713 V3AEUnitI, V3AEUnitI, V3AEUnitI,714 V3AEUnitI, V3AEUnitI, V3AEUnitI,715 V3AEUnitI, V3AEUnitI, V3AEUnitI,716 V3AEUnitV, V3AEUnitV, V3AEUnitV,717 V3AEUnitV, V3AEUnitV, V3AEUnitV,718 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {719 let Latency = 7;720 let NumMicroOps = 27;721}722 723//===----------------------------------------------------------------------===//724// Define generic 36 micro-op types725 726def V3AEWrite_11c_18SA_18V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,727 V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,728 V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,729 V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,730 V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,731 V3AEUnitSA, V3AEUnitSA, V3AEUnitSA,732 V3AEUnitV, V3AEUnitV, V3AEUnitV,733 V3AEUnitV, V3AEUnitV, V3AEUnitV,734 V3AEUnitV, V3AEUnitV, V3AEUnitV,735 V3AEUnitV, V3AEUnitV, V3AEUnitV,736 V3AEUnitV, V3AEUnitV, V3AEUnitV,737 V3AEUnitV, V3AEUnitV, V3AEUnitV]> {738 let Latency = 11;739 let NumMicroOps = 36;740}741 742//===----------------------------------------------------------------------===//743// Define generic 54 micro-op types744 745def V3AEWrite_11c_18SA_18I_18V : SchedWriteRes<[V3AEUnitSA, V3AEUnitSA,746 V3AEUnitSA, V3AEUnitSA,747 V3AEUnitSA, V3AEUnitSA,748 V3AEUnitSA, V3AEUnitSA,749 V3AEUnitSA, V3AEUnitSA,750 V3AEUnitSA, V3AEUnitSA,751 V3AEUnitSA, V3AEUnitSA,752 V3AEUnitSA, V3AEUnitSA,753 V3AEUnitSA, V3AEUnitSA,754 V3AEUnitI, V3AEUnitI, V3AEUnitI,755 V3AEUnitI, V3AEUnitI, V3AEUnitI,756 V3AEUnitI, V3AEUnitI, V3AEUnitI,757 V3AEUnitI, V3AEUnitI, V3AEUnitI,758 V3AEUnitI, V3AEUnitI, V3AEUnitI,759 V3AEUnitI, V3AEUnitI, V3AEUnitI,760 V3AEUnitV, V3AEUnitV, V3AEUnitV,761 V3AEUnitV, V3AEUnitV, V3AEUnitV,762 V3AEUnitV, V3AEUnitV, V3AEUnitV,763 V3AEUnitV, V3AEUnitV, V3AEUnitV,764 V3AEUnitV, V3AEUnitV, V3AEUnitV,765 V3AEUnitV, V3AEUnitV,766 V3AEUnitV]> {767 let Latency = 11;768 let NumMicroOps = 54;769}770 771//===----------------------------------------------------------------------===//772// Define predicate-controlled types773 774def V3AEWrite_ArithI : SchedWriteVariant<[775 SchedVar<IsCheapLSL, [V3AEWrite_1c_1I]>,776 SchedVar<NoSchedPred, [V3AEWrite_2c_1M]>]>;777 778def V3AEWrite_ArithF : SchedWriteVariant<[779 SchedVar<IsCheapLSL, [V3AEWrite_1c_1F_1Flg]>,780 SchedVar<NoSchedPred, [V3AEWrite_2c_1M_1Flg]>]>;781 782def V3AEWrite_Logical : SchedWriteVariant<[783 SchedVar<NeoverseNoLSL, [V3AEWrite_1c_1F_1Flg]>,784 SchedVar<NoSchedPred, [V3AEWrite_2c_1M_1Flg]>]>;785 786def V3AEWrite_Extr : SchedWriteVariant<[787 SchedVar<IsRORImmIdiomPred, [V3AEWrite_1c_1I]>,788 SchedVar<NoSchedPred, [V3AEWrite_3c_1I_1M]>]>;789 790def V3AEWrite_LdrHQ : SchedWriteVariant<[791 SchedVar<NeoverseHQForm, [V3AEWrite_7c_1I_1L]>,792 SchedVar<NoSchedPred, [V3AEWrite_6c_1L]>]>;793 794def V3AEWrite_StrHQ : SchedWriteVariant<[795 SchedVar<NeoverseHQForm, [V3AEWrite_2c_1SA_1V_1I]>,796 SchedVar<NoSchedPred, [V3AEWrite_2c_1SA_1V]>]>;797 798def V3AEWrite_0or1c_1I : SchedWriteVariant<[799 SchedVar<NeoverseZeroMove, [V3AEWrite_0c]>,800 SchedVar<NoSchedPred, [V3AEWrite_1c_1I]>]>;801 802def V3AEWrite_0or2c_1V : SchedWriteVariant<[803 SchedVar<NeoverseZeroMove, [V3AEWrite_0c]>,804 SchedVar<NoSchedPred, [V3AEWrite_2c_1V]>]>;805 806def V3AEWrite_0or3c_1M0 : SchedWriteVariant<[807 SchedVar<NeoverseZeroMove, [V3AEWrite_0c]>,808 SchedVar<NoSchedPred, [V3AEWrite_3c_1M0]>]>;809 810def V3AEWrite_2or3c_1M : SchedWriteVariant<[811 SchedVar<NeoversePdIsPg, [V3AEWrite_3c_1M]>,812 SchedVar<NoSchedPred, [V3AEWrite_2c_1M]>]>;813 814def V3AEWrite_1or2c_1M : SchedWriteVariant<[815 SchedVar<NeoversePdIsPg, [V3AEWrite_2c_1M]>,816 SchedVar<NoSchedPred, [V3AEWrite_1c_1M]>]>;817 818def V3AEWrite_3or4c_1M0_1M : SchedWriteVariant<[819 SchedVar<NeoversePdIsPg, [V3AEWrite_4c_1M0_1M]>,820 SchedVar<NoSchedPred, [V3AEWrite_3c_1M0_1M]>]>;821 822def V3AEWrite_2or3c_1V0 : SchedWriteVariant<[823 SchedVar<NeoversePdIsPg, [V3AEWrite_3c_1V0]>,824 SchedVar<NoSchedPred, [V3AEWrite_2c_1V0]>]>;825 826def V3AEWrite_2or3c_1V0_1M : SchedWriteVariant<[827 SchedVar<NeoversePdIsPg, [V3AEWrite_3c_1V0_1M]>,828 SchedVar<NoSchedPred, [V3AEWrite_2c_1V0_1M]>]>;829 830def V3AEWrite_IncDec : SchedWriteVariant<[831 SchedVar<NeoverseCheapIncDec, [V3AEWrite_1c_1I]>,832 SchedVar<NoSchedPred, [V3AEWrite_2c_1M]>]>;833 834//===----------------------------------------------------------------------===//835// Define forwarded types836 837// NOTE: SOG, p. 16, n. 2: Accumulator forwarding is not supported for838// consumers of 64 bit multiply high operations?839def V3AEWr_IM : SchedWriteRes<[V3AEUnitM]> { let Latency = 2; }840 841def V3AEWr_FMA : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }842def V3AERd_FMA : SchedReadAdvance<2, [WriteFMul, V3AEWr_FMA]>;843 844def V3AEWr_VA : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }845def V3AERd_VA : SchedReadAdvance<3, [V3AEWr_VA]>;846 847def V3AEWr_VDOT : SchedWriteRes<[V3AEUnitV]> { let Latency = 3; }848def V3AERd_VDOT : SchedReadAdvance<2, [V3AEWr_VDOT]>;849 850def V3AEWr_VMMA : SchedWriteRes<[V3AEUnitV]> { let Latency = 3; }851def V3AERd_VMMA : SchedReadAdvance<2, [V3AEWr_VMMA]>;852 853def V3AEWr_VMA : SchedWriteRes<[V3AEUnitV0]> { let Latency = 4; }854def V3AERd_VMA : SchedReadAdvance<3, [V3AEWr_VMA]>;855 856def V3AEWr_VMAH : SchedWriteRes<[V3AEUnitV0, V3AEUnitV0]> { let Latency = 4; }857def V3AERd_VMAH : SchedReadAdvance<2, [V3AEWr_VMAH]>;858 859def V3AEWr_VMAL : SchedWriteRes<[V3AEUnitV0]> { let Latency = 4; }860def V3AERd_VMAL : SchedReadAdvance<3, [V3AEWr_VMAL]>;861 862def V3AEWr_VPA : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }863def V3AERd_VPA : SchedReadAdvance<3, [V3AEWr_VPA]>;864 865def V3AEWr_VSA : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }866def V3AERd_VSA : SchedReadAdvance<3, [V3AEWr_VSA]>;867 868def V3AEWr_VFCMA : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }869def V3AERd_VFCMA : SchedReadAdvance<2, [V3AEWr_VFCMA]>;870 871def V3AEWr_VFM : SchedWriteRes<[V3AEUnitV]> { let Latency = 3; }872def V3AEWr_VFMA : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }873def V3AERd_VFMA : SchedReadAdvance<2, [V3AEWr_VFM, V3AEWr_VFMA]>;874 875def V3AEWr_VFMAL : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }876def V3AERd_VFMAL : SchedReadAdvance<2, [V3AEWr_VFMAL]>;877 878def V3AEWr_VBFDOT : SchedWriteRes<[V3AEUnitV]> { let Latency = 5; }879def V3AERd_VBFDOT : SchedReadAdvance<2, [V3AEWr_VBFDOT]>;880def V3AEWr_VBFMMA : SchedWriteRes<[V3AEUnitV]> { let Latency = 6; }881def V3AERd_VBFMMA : SchedReadAdvance<2, [V3AEWr_VBFMMA]>;882def V3AEWr_VBFMAL : SchedWriteRes<[V3AEUnitV]> { let Latency = 5; }883def V3AERd_VBFMAL : SchedReadAdvance<3, [V3AEWr_VBFMAL]>;884 885def V3AEWr_CRC : SchedWriteRes<[V3AEUnitM0]> { let Latency = 2; }886def V3AERd_CRC : SchedReadAdvance<1, [V3AEWr_CRC]>;887 888def V3AEWr_ZA : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }889def V3AERd_ZA : SchedReadAdvance<3, [V3AEWr_ZA]>;890def V3AEWr_ZPA : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }891def V3AERd_ZPA : SchedReadAdvance<3, [V3AEWr_ZPA]>;892def V3AEWr_ZSA : SchedWriteRes<[V3AEUnitV1]> { let Latency = 4; }893def V3AERd_ZSA : SchedReadAdvance<3, [V3AEWr_ZSA]>;894 895def V3AEWr_ZDOTB : SchedWriteRes<[V3AEUnitV]> { let Latency = 3; }896def V3AERd_ZDOTB : SchedReadAdvance<2, [V3AEWr_ZDOTB]>;897def V3AEWr_ZDOTH : SchedWriteRes<[V3AEUnitV0]> { let Latency = 3; }898def V3AERd_ZDOTH : SchedReadAdvance<2, [V3AEWr_ZDOTH]>;899 900// NOTE: SOG p. 43: Complex multiply-add B, H, S element size: How to reduce901// throughput to 1 in case of forwarding?902def V3AEWr_ZCMABHS : SchedWriteRes<[V3AEUnitV0]> { let Latency = 4; }903def V3AERd_ZCMABHS : SchedReadAdvance<3, [V3AEWr_ZCMABHS]>;904def V3AEWr_ZCMAD : SchedWriteRes<[V3AEUnitV0, V3AEUnitV0]> { let Latency = 5; }905def V3AERd_ZCMAD : SchedReadAdvance<2, [V3AEWr_ZCMAD]>;906 907def V3AEWr_ZMMA : SchedWriteRes<[V3AEUnitV]> { let Latency = 3; }908def V3AERd_ZMMA : SchedReadAdvance<2, [V3AEWr_ZMMA]>;909 910def V3AEWr_ZMABHS : SchedWriteRes<[V3AEUnitV0]> { let Latency = 4; }911def V3AERd_ZMABHS : SchedReadAdvance<3, [V3AEWr_ZMABHS]>;912def V3AEWr_ZMAD : SchedWriteRes<[V3AEUnitV0, V3AEUnitV0]> { let Latency = 5; }913def V3AERd_ZMAD : SchedReadAdvance<2, [V3AEWr_ZMAD]>;914 915def V3AEWr_ZMAL : SchedWriteRes<[V3AEUnitV0]> { let Latency = 4; }916def V3AERd_ZMAL : SchedReadAdvance<3, [V3AEWr_ZMAL]>;917 918def V3AEWr_ZMASQL : SchedWriteRes<[V3AEUnitV0]> { let Latency = 4; }919def V3AEWr_ZMASQBHS : SchedWriteRes<[V3AEUnitV0]> { let Latency = 4; }920def V3AEWr_ZMASQD : SchedWriteRes<[V3AEUnitV0, V3AEUnitV0]> { let Latency = 5; }921def V3AERd_ZMASQ : SchedReadAdvance<2, [V3AEWr_ZMASQL, V3AEWr_ZMASQBHS,922 V3AEWr_ZMASQD]>;923 924def V3AEWr_ZFCMA : SchedWriteRes<[V3AEUnitV]> { let Latency = 5; }925def V3AERd_ZFCMA : SchedReadAdvance<3, [V3AEWr_ZFCMA]>;926 927def V3AEWr_ZFMA : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }928def V3AERd_ZFMA : SchedReadAdvance<2, [V3AEWr_ZFMA]>;929 930def V3AEWr_ZFMAL : SchedWriteRes<[V3AEUnitV]> { let Latency = 4; }931def V3AERd_ZFMAL : SchedReadAdvance<2, [V3AEWr_ZFMAL]>;932 933def V3AEWr_ZBFDOT : SchedWriteRes<[V3AEUnitV]> { let Latency = 5; }934def V3AERd_ZBFDOT : SchedReadAdvance<2, [V3AEWr_ZBFDOT]>;935def V3AEWr_ZBFMMA : SchedWriteRes<[V3AEUnitV]> { let Latency = 6; }936def V3AERd_ZBFMMA : SchedReadAdvance<2, [V3AEWr_ZBFMMA]>;937def V3AEWr_ZBFMAL : SchedWriteRes<[V3AEUnitV]> { let Latency = 5; }938def V3AERd_ZBFMAL : SchedReadAdvance<3, [V3AEWr_ZBFMAL]>;939 940//===----------------------------------------------------------------------===//941// Define types with long resource cycles (rc)942 943def V3AEWrite_6c_1V1_5rc : SchedWriteRes<[V3AEUnitV1]> { let Latency = 6; let ReleaseAtCycles = [ 5]; }944def V3AEWrite_9c_1V1_2rc : SchedWriteRes<[V3AEUnitV1]> { let Latency = 9; let ReleaseAtCycles = [ 2]; }945def V3AEWrite_9c_1V1_4rc : SchedWriteRes<[V3AEUnitV1]> { let Latency = 9; let ReleaseAtCycles = [ 4]; }946def V3AEWrite_10c_1V1_9rc : SchedWriteRes<[V3AEUnitV1]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }947def V3AEWrite_11c_1V1_4rc : SchedWriteRes<[V3AEUnitV1]> { let Latency = 11; let ReleaseAtCycles = [ 4]; }948def V3AEWrite_13c_1V1_8rc : SchedWriteRes<[V3AEUnitV1]> { let Latency = 13; let ReleaseAtCycles = [8]; }949def V3AEWrite_14c_1V1_2rc : SchedWriteRes<[V3AEUnitV1]> { let Latency = 14; let ReleaseAtCycles = [2]; }950 951// Miscellaneous952// -----------------------------------------------------------------------------953 954def : InstRW<[WriteI], (instrs COPY)>;955 956// §3.3 Branch instructions957// -----------------------------------------------------------------------------958 959// Branch, immed960// Compare and branch961def : SchedAlias<WriteBr, V3AEWrite_1c_1B>;962 963// Branch, register964def : SchedAlias<WriteBrReg, V3AEWrite_1c_1B>;965 966// Branch and link, immed967// Branch and link, register968def : InstRW<[V3AEWrite_1c_1B_1S], (instrs BL, BLR)>;969 970// §3.4 Arithmetic and Logical Instructions971// -----------------------------------------------------------------------------972 973// ALU, basic974def : SchedAlias<WriteI, V3AEWrite_1c_1I>;975 976// ALU, basic, flagset977def : InstRW<[V3AEWrite_1c_1F_1Flg],978 (instregex "^(ADD|SUB)S[WX]r[ir]$",979 "^(ADC|SBC)S[WX]r$",980 "^ANDS[WX]ri$",981 "^(AND|BIC)S[WX]rr$")>;982def : InstRW<[V3AEWrite_0or1c_1I], (instregex "^MOVZ[WX]i$")>;983 984// ALU, extend and shift985def : SchedAlias<WriteIEReg, V3AEWrite_2c_1M>;986 987// Arithmetic, LSL shift, shift <= 4988// Arithmetic, flagset, LSL shift, shift <= 4989// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4990def : SchedAlias<WriteISReg, V3AEWrite_ArithI>;991def : InstRW<[V3AEWrite_ArithF],992 (instregex "^(ADD|SUB)S[WX]rs$")>;993 994// Arithmetic, immediate to logical address tag995def : InstRW<[V3AEWrite_2c_1M], (instrs ADDG, SUBG)>;996 997// Conditional compare998def : InstRW<[V3AEWrite_1c_1F_1Flg], (instregex "^CCM[NP][WX][ir]")>;999 1000// Convert floating-point condition flags1001// Flag manipulation instructions1002def : WriteRes<WriteSys, []> { let Latency = 1; }1003 1004// Insert Random Tags1005def : InstRW<[V3AEWrite_2c_1M], (instrs IRG, IRGstack)>;1006 1007// Insert Tag Mask1008// Subtract Pointer1009def : InstRW<[V3AEWrite_1c_1I], (instrs GMI, SUBP)>;1010 1011// Subtract Pointer, flagset1012def : InstRW<[V3AEWrite_1c_1F_1Flg], (instrs SUBPS)>;1013 1014// Logical, shift, no flagset1015def : InstRW<[V3AEWrite_1c_1I], (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;1016def : InstRW<[V3AEWrite_0or1c_1I], (instregex "^ORR[WX]rs$")>;1017 1018// Logical, shift, flagset1019def : InstRW<[V3AEWrite_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;1020 1021// Move and shift instructions1022// -----------------------------------------------------------------------------1023 1024def : SchedAlias<WriteImm, V3AEWrite_1c_1I>;1025 1026// §3.5 Divide and multiply instructions1027// -----------------------------------------------------------------------------1028 1029// SDIV, UDIV1030def : SchedAlias<WriteID32, V3AEWrite_12c_1M0>;1031def : SchedAlias<WriteID64, V3AEWrite_20c_1M0>;1032 1033def : SchedAlias<WriteIM32, V3AEWrite_2c_1M>;1034def : SchedAlias<WriteIM64, V3AEWrite_2c_1M>;1035 1036// Multiply1037// Multiply accumulate, W-form1038// Multiply accumulate, X-form1039def : InstRW<[V3AEWr_IM], (instregex "^M(ADD|SUB)[WX]rrr$")>;1040 1041// Multiply accumulate long1042// Multiply long1043def : InstRW<[V3AEWr_IM], (instregex "^(S|U)M(ADD|SUB)Lrrr$")>;1044 1045// Multiply high1046def : InstRW<[V3AEWrite_3c_1M], (instrs SMULHrr, UMULHrr)>;1047 1048// §3.6 Pointer Authentication Instructions (v8.3 PAC)1049// -----------------------------------------------------------------------------1050 1051// Authenticate data address1052// Authenticate instruction address1053// Compute pointer authentication code for data address1054// Compute pointer authentication code, using generic key1055// Compute pointer authentication code for instruction address1056def : InstRW<[V3AEWrite_4c_1M0], (instregex "^AUT", "^PAC")>;1057 1058// Branch and link, register, with pointer authentication1059// Branch, register, with pointer authentication1060// Branch, return, with pointer authentication1061def : InstRW<[V3AEWrite_6c_1M0_1B], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ, BRAA,1062 BRAAZ, BRAB, BRABZ, RETAA, RETAB,1063 ERETAA, ERETAB)>;1064 1065 1066// Load register, with pointer authentication1067def : InstRW<[V3AEWrite_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;1068 1069// Strip pointer authentication code1070def : InstRW<[V3AEWrite_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;1071 1072// §3.7 Miscellaneous data-processing instructions1073// -----------------------------------------------------------------------------1074 1075// Address generation1076def : InstRW<[V3AEWrite_1c_1I], (instrs ADR, ADRP)>;1077 1078// Bitfield extract, one reg1079// Bitfield extract, two regs1080def : SchedAlias<WriteExtr, V3AEWrite_Extr>;1081def : InstRW<[V3AEWrite_Extr], (instrs EXTRWrri, EXTRXrri)>;1082 1083// Bitfield move, basic1084def : SchedAlias<WriteIS, V3AEWrite_1c_1I>;1085 1086// Bitfield move, insert1087def : InstRW<[V3AEWrite_2c_1M], (instregex "^BFM[WX]ri$")>;1088 1089// §3.8 Load instructions1090// -----------------------------------------------------------------------------1091 1092// NOTE: SOG p. 19: Throughput of LDN?P X-form should be 2, but reported as 3.1093 1094def : SchedAlias<WriteLD, V3AEWrite_4c_1L>;1095def : SchedAlias<WriteLDIdx, V3AEWrite_4c_1L>;1096 1097// Load register, literal1098def : InstRW<[V3AEWrite_5c_1L_1I], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>;1099 1100// Load pair, signed immed offset, signed words1101def : InstRW<[V3AEWrite_5c_1I_3L, WriteLDHi], (instrs LDPSWi)>;1102 1103// Load pair, immed post-index or immed pre-index, signed words1104def : InstRW<[WriteAdr, V3AEWrite_5c_1I_3L, WriteLDHi],1105 (instregex "^LDPSW(post|pre)$")>;1106 1107// §3.9 Store instructions1108// -----------------------------------------------------------------------------1109 1110// NOTE: SOG, p. 20: Unsure if STRH uses pipeline I.1111 1112def : SchedAlias<WriteST, V3AEWrite_1c_1SA_1D>;1113def : SchedAlias<WriteSTIdx, V3AEWrite_1c_1SA_1D>;1114def : SchedAlias<WriteSTP, V3AEWrite_1c_1SA_1D>;1115def : SchedAlias<WriteAdr, V3AEWrite_1c_1I>;1116 1117// §3.10 Tag load instructions1118// -----------------------------------------------------------------------------1119 1120// Load allocation tag1121// Load multiple allocation tags1122def : InstRW<[V3AEWrite_4c_1L], (instrs LDG, LDGM)>;1123 1124// §3.11 Tag store instructions1125// -----------------------------------------------------------------------------1126 1127// Store allocation tags to one or two granules, post-index1128// Store allocation tags to one or two granules, pre-index1129// Store allocation tag to one or two granules, zeroing, post-index1130// Store Allocation Tag to one or two granules, zeroing, pre-index1131// Store allocation tag and reg pair to memory, post-Index1132// Store allocation tag and reg pair to memory, pre-Index1133def : InstRW<[V3AEWrite_1c_1SA_1D_1I], (instrs STGPreIndex, STGPostIndex,1134 ST2GPreIndex, ST2GPostIndex,1135 STZGPreIndex, STZGPostIndex,1136 STZ2GPreIndex, STZ2GPostIndex,1137 STGPpre, STGPpost)>;1138 1139// Store allocation tags to one or two granules, signed offset1140// Store allocation tag to two granules, zeroing, signed offset1141// Store allocation tag and reg pair to memory, signed offset1142// Store multiple allocation tags1143def : InstRW<[V3AEWrite_1c_1SA_1D], (instrs STGi, ST2Gi, STZGi,1144 STZ2Gi, STGPi, STGM, STZGM)>;1145 1146// §3.12 FP data processing instructions1147// -----------------------------------------------------------------------------1148 1149// FP absolute value1150// FP arithmetic1151// FP min/max1152// FP negate1153// FP select1154def : SchedAlias<WriteF, V3AEWrite_2c_1V>;1155 1156// FP compare1157def : SchedAlias<WriteFCmp, V3AEWrite_2c_1V0>;1158 1159// FP divide, square root1160def : SchedAlias<WriteFDiv, V3AEWrite_6c_1V1>;1161 1162// FP divide, H-form1163def : InstRW<[V3AEWrite_6c_1V1], (instrs FDIVHrr)>;1164// FP divide, S-form1165def : InstRW<[V3AEWrite_8c_1V1], (instrs FDIVSrr)>;1166// FP divide, D-form1167def : InstRW<[V3AEWrite_13c_1V1], (instrs FDIVDrr)>;1168 1169// FP square root, H-form1170def : InstRW<[V3AEWrite_6c_1V1], (instrs FSQRTHr)>;1171// FP square root, S-form1172def : InstRW<[V3AEWrite_8c_1V1], (instrs FSQRTSr)>;1173// FP square root, D-form1174def : InstRW<[V3AEWrite_13c_1V1], (instrs FSQRTDr)>;1175 1176// FP multiply1177def : WriteRes<WriteFMul, [V3AEUnitV]> { let Latency = 3; }1178 1179// FP multiply accumulate1180def : InstRW<[V3AEWr_FMA, ReadDefault, ReadDefault, V3AERd_FMA],1181 (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;1182 1183// FP round to integral1184def : InstRW<[V3AEWrite_3c_1V0], (instregex "^FRINT[AIMNPXZ][HSD]r$",1185 "^FRINT(32|64)[XZ][SD]r$")>;1186 1187// §3.13 FP miscellaneous instructions1188// -----------------------------------------------------------------------------1189 1190// FP convert, from gen to vec reg1191def : InstRW<[V3AEWrite_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;1192 1193// FP convert, from vec to gen reg1194def : InstRW<[V3AEWrite_3c_1V0],1195 (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]ri?$")>;1196 1197// FP convert, Javascript from vec to gen reg1198def : SchedAlias<WriteFCvt, V3AEWrite_3c_1V0>;1199 1200// FP convert, from vec to vec reg1201def : InstRW<[V3AEWrite_3c_1V], (instrs FCVTSHr, FCVTDHr, FCVTHSr, FCVTDSr,1202 FCVTHDr, FCVTSDr, FCVTXNv1i64)>;1203 1204// FP move, immed1205// FP move, register1206def : SchedAlias<WriteFImm, V3AEWrite_2c_1V>;1207 1208// FP transfer, from gen to low half of vec reg1209def : InstRW<[V3AEWrite_0or3c_1M0],1210 (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;1211 1212// FP transfer, from gen to high half of vec reg1213def : InstRW<[V3AEWrite_5c_1M0_1V], (instrs FMOVXDHighr)>;1214 1215// FP transfer, from vec to gen reg1216def : SchedAlias<WriteFCopy, V3AEWrite_2c_2V>;1217 1218// §3.14 FP load instructions1219// -----------------------------------------------------------------------------1220 1221// Load vector reg, literal, S/D/Q forms1222def : InstRW<[V3AEWrite_7c_1I_1L], (instregex "^LDR[SDQ]l$")>;1223 1224// Load vector reg, unscaled immed1225def : InstRW<[V3AEWrite_6c_1L], (instregex "^LDUR[BHSDQ]i$")>;1226 1227// Load vector reg, immed post-index1228// Load vector reg, immed pre-index1229def : InstRW<[WriteAdr, V3AEWrite_6c_1I_1L],1230 (instregex "^LDR[BHSDQ](pre|post)$")>;1231 1232// Load vector reg, unsigned immed1233def : InstRW<[V3AEWrite_6c_1L], (instregex "^LDR[BHSDQ]ui$")>;1234 1235// Load vector reg, register offset, basic1236// Load vector reg, register offset, scale, S/D-form1237// Load vector reg, register offset, scale, H/Q-form1238// Load vector reg, register offset, extend1239// Load vector reg, register offset, extend, scale, S/D-form1240// Load vector reg, register offset, extend, scale, H/Q-form1241def : InstRW<[V3AEWrite_LdrHQ, ReadAdrBase], (instregex "^LDR[BHSDQ]ro[WX]$")>;1242 1243// Load vector pair, immed offset, S/D-form1244def : InstRW<[V3AEWrite_6c_1L, WriteLDHi], (instregex "^LDN?P[SD]i$")>;1245 1246// Load vector pair, immed offset, Q-form1247def : InstRW<[V3AEWrite_6c_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;1248 1249// Load vector pair, immed post-index, S/D-form1250// Load vector pair, immed pre-index, S/D-form1251def : InstRW<[WriteAdr, V3AEWrite_6c_1I_1L, WriteLDHi],1252 (instregex "^LDP[SD](pre|post)$")>;1253 1254// Load vector pair, immed post-index, Q-form1255// Load vector pair, immed pre-index, Q-form1256def : InstRW<[WriteAdr, V3AEWrite_6c_2I_2L, WriteLDHi], (instrs LDPQpost,1257 LDPQpre)>;1258 1259// §3.15 FP store instructions1260// -----------------------------------------------------------------------------1261 1262// Store vector reg, unscaled immed, B/H/S/D-form1263// Store vector reg, unscaled immed, Q-form1264def : InstRW<[V3AEWrite_2c_1SA_1V], (instregex "^STUR[BHSDQ]i$")>;1265 1266// Store vector reg, immed post-index, B/H/S/D-form1267// Store vector reg, immed post-index, Q-form1268// Store vector reg, immed pre-index, B/H/S/D-form1269// Store vector reg, immed pre-index, Q-form1270def : InstRW<[WriteAdr, V3AEWrite_2c_1SA_1V_1I],1271 (instregex "^STR[BHSDQ](pre|post)$")>;1272 1273// Store vector reg, unsigned immed, B/H/S/D-form1274// Store vector reg, unsigned immed, Q-form1275def : InstRW<[V3AEWrite_2c_1SA_1V], (instregex "^STR[BHSDQ]ui$")>;1276 1277// Store vector reg, register offset, basic, B/H/S/D-form1278// Store vector reg, register offset, basic, Q-form1279// Store vector reg, register offset, scale, H-form1280// Store vector reg, register offset, scale, S/D-form1281// Store vector reg, register offset, scale, Q-form1282// Store vector reg, register offset, extend, B/H/S/D-form1283// Store vector reg, register offset, extend, Q-form1284// Store vector reg, register offset, extend, scale, H-form1285// Store vector reg, register offset, extend, scale, S/D-form1286// Store vector reg, register offset, extend, scale, Q-form1287def : InstRW<[V3AEWrite_StrHQ, ReadAdrBase],1288 (instregex "^STR[BHSDQ]ro[WX]$")>;1289 1290// Store vector pair, immed offset, S-form1291// Store vector pair, immed offset, D-form1292def : InstRW<[V3AEWrite_2c_1SA_1V], (instregex "^STN?P[SD]i$")>;1293 1294// Store vector pair, immed offset, Q-form1295def : InstRW<[V3AEWrite_2c_1SA_2V], (instrs STPQi, STNPQi)>;1296 1297// Store vector pair, immed post-index, S-form1298// Store vector pair, immed post-index, D-form1299// Store vector pair, immed pre-index, S-form1300// Store vector pair, immed pre-index, D-form1301def : InstRW<[WriteAdr, V3AEWrite_2c_1SA_1V_1I],1302 (instregex "^STP[SD](pre|post)$")>;1303 1304// Store vector pair, immed post-index, Q-form1305def : InstRW<[V3AEWrite_2c_1SA_2V_1I], (instrs STPQpost)>;1306 1307// Store vector pair, immed pre-index, Q-form1308def : InstRW<[V3AEWrite_2c_1SA_2V_2I], (instrs STPQpre)>;1309 1310// §3.16 ASIMD integer instructions1311// -----------------------------------------------------------------------------1312 1313// ASIMD absolute diff1314// ASIMD absolute diff long1315// ASIMD arith, basic1316// ASIMD arith, complex1317// ASIMD arith, pair-wise1318// ASIMD compare1319// ASIMD logical1320// ASIMD max/min, basic and pair-wise1321def : SchedAlias<WriteVd, V3AEWrite_2c_1V>;1322def : SchedAlias<WriteVq, V3AEWrite_2c_1V>;1323 1324// ASIMD absolute diff accum1325// ASIMD absolute diff accum long1326def : InstRW<[V3AEWr_VA, V3AERd_VA], (instregex "^[SU]ABAL?v")>;1327 1328// ASIMD arith, reduce, 4H/4S1329def : InstRW<[V3AEWrite_3c_1V1], (instregex "^(ADDV|[SU]ADDLV)v4(i16|i32)v$")>;1330 1331// ASIMD arith, reduce, 8B/8H1332def : InstRW<[V3AEWrite_5c_1V1_1V],1333 (instregex "^(ADDV|[SU]ADDLV)v8(i8|i16)v$")>;1334 1335// ASIMD arith, reduce, 16B1336def : InstRW<[V3AEWrite_6c_2V1], (instregex "^(ADDV|[SU]ADDLV)v16i8v$")>;1337 1338// ASIMD dot product1339// ASIMD dot product using signed and unsigned integers1340def : InstRW<[V3AEWr_VDOT, V3AERd_VDOT],1341 (instregex "^([SU]|SU|US)DOT(lane)?(v8|v16)i8$")>;1342 1343// ASIMD matrix multiply-accumulate1344def : InstRW<[V3AEWr_VMMA, V3AERd_VMMA], (instrs SMMLA, UMMLA, USMMLA)>;1345 1346// ASIMD max/min, reduce, 4H/4S1347def : InstRW<[V3AEWrite_3c_1V1], (instregex "^[SU](MAX|MIN)Vv4i16v$",1348 "^[SU](MAX|MIN)Vv4i32v$")>;1349 1350// ASIMD max/min, reduce, 8B/8H1351def : InstRW<[V3AEWrite_5c_1V1_1V], (instregex "^[SU](MAX|MIN)Vv8i8v$",1352 "^[SU](MAX|MIN)Vv8i16v$")>;1353 1354// ASIMD max/min, reduce, 16B1355def : InstRW<[V3AEWrite_6c_2V1], (instregex "[SU](MAX|MIN)Vv16i8v$")>;1356 1357// ASIMD multiply1358def : InstRW<[V3AEWrite_4c_1V0], (instregex "^MULv", "^SQ(R)?DMULHv")>;1359 1360// ASIMD multiply accumulate1361def : InstRW<[V3AEWr_VMA, V3AERd_VMA], (instregex "^MLAv", "^MLSv")>;1362 1363// ASIMD multiply accumulate high1364def : InstRW<[V3AEWr_VMAH, V3AERd_VMAH], (instregex "^SQRDMLAHv", "^SQRDMLSHv")>;1365 1366// ASIMD multiply accumulate long1367def : InstRW<[V3AEWr_VMAL, V3AERd_VMAL], (instregex "^[SU]MLALv", "^[SU]MLSLv")>;1368 1369// ASIMD multiply accumulate saturating long1370def : InstRW<[V3AEWrite_4c_1V0], (instregex "^SQDML[AS]L[iv]")>;1371 1372// ASIMD multiply/multiply long (8x8) polynomial, D-form1373// ASIMD multiply/multiply long (8x8) polynomial, Q-form1374def : InstRW<[V3AEWrite_3c_1V], (instregex "^PMULL?(v8i8|v16i8)$")>;1375 1376// ASIMD multiply long1377def : InstRW<[V3AEWrite_3c_1V0], (instregex "^[SU]MULLv", "^SQDMULL[iv]")>;1378 1379// ASIMD pairwise add and accumulate long1380def : InstRW<[V3AEWr_VPA, V3AERd_VPA], (instregex "^[SU]ADALPv")>;1381 1382// ASIMD shift accumulate1383def : InstRW<[V3AEWr_VSA, V3AERd_VSA], (instregex "^[SU]SRA[dv]", "^[SU]RSRA[dv]")>;1384 1385// ASIMD shift by immed, basic1386def : InstRW<[V3AEWrite_2c_1V], (instregex "^SHL[dv]", "^SHLLv", "^SHRNv",1387 "^SSHLLv", "^SSHR[dv]", "^USHLLv",1388 "^USHR[dv]")>;1389 1390// ASIMD shift by immed and insert, basic1391def : InstRW<[V3AEWrite_2c_1V], (instregex "^SLI[dv]", "^SRI[dv]")>;1392 1393// ASIMD shift by immed, complex1394def : InstRW<[V3AEWrite_4c_1V],1395 (instregex "^RSHRNv", "^SQRSHRU?N[bhsv]", "^(SQSHLU?|UQSHL)[bhsd]$",1396 "^(SQSHLU?|UQSHL)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)_shift$",1397 "^SQSHRU?N[bhsv]", "^SRSHR[dv]", "^UQRSHRN[bhsv]",1398 "^UQSHRN[bhsv]", "^URSHR[dv]")>;1399 1400// ASIMD shift by register, basic1401def : InstRW<[V3AEWrite_2c_1V], (instregex "^[SU]SHLv")>;1402 1403// ASIMD shift by register, complex1404def : InstRW<[V3AEWrite_4c_1V],1405 (instregex "^[SU]RSHLv", "^[SU]QRSHLv",1406 "^[SU]QSHL(v1i8|v1i16|v1i32|v1i64|v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v2i64)$")>;1407 1408// §3.17 ASIMD floating-point instructions1409// -----------------------------------------------------------------------------1410 1411// ASIMD FP absolute value/difference1412// ASIMD FP arith, normal1413// ASIMD FP compare1414// ASIMD FP complex add1415// ASIMD FP max/min, normal1416// ASIMD FP max/min, pairwise1417// ASIMD FP negate1418// Handled by SchedAlias<WriteV[dq], ...>1419 1420// ASIMD FP complex multiply add1421def : InstRW<[V3AEWr_VFCMA, V3AERd_VFCMA], (instregex "^FCMLAv")>;1422 1423// ASIMD FP convert, long (F16 to F32)1424def : InstRW<[V3AEWrite_4c_2V0], (instregex "^FCVTL(v4|v8)i16")>;1425 1426// ASIMD FP convert, long (F32 to F64)1427def : InstRW<[V3AEWrite_3c_1V0], (instregex "^FCVTL(v2|v4)i32")>;1428 1429// ASIMD FP convert, narrow (F32 to F16)1430def : InstRW<[V3AEWrite_4c_2V0], (instregex "^FCVTN(v4|v8)i16")>;1431 1432// ASIMD FP convert, narrow (F64 to F32)1433def : InstRW<[V3AEWrite_3c_1V0], (instregex "^FCVTN(v2|v4)i32",1434 "^FCVTXN(v2|v4)f32")>;1435 1436// ASIMD FP convert, other, D-form F32 and Q-form F641437def : InstRW<[V3AEWrite_3c_1V0], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$",1438 "^FCVT[AMNPZ][SU]v2i(32|64)_shift$",1439 "^FCVT[AMNPZ][SU]v1i64$",1440 "^FCVTZ[SU]d$",1441 "^[SU]CVTFv2f(32|64)$",1442 "^[SU]CVTFv2i(32|64)_shift$",1443 "^[SU]CVTFv1i64$",1444 "^[SU]CVTFd$")>;1445 1446// ASIMD FP convert, other, D-form F16 and Q-form F321447def : InstRW<[V3AEWrite_4c_2V0], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$",1448 "^FCVT[AMNPZ][SU]v4i(16|32)_shift$",1449 "^FCVT[AMNPZ][SU]v1i32$",1450 "^FCVTZ[SU]s$",1451 "^[SU]CVTFv4f(16|32)$",1452 "^[SU]CVTFv4i(16|32)_shift$",1453 "^[SU]CVTFv1i32$",1454 "^[SU]CVTFs$")>;1455 1456// ASIMD FP convert, other, Q-form F161457def : InstRW<[V3AEWrite_6c_4V0], (instregex "^FCVT[AMNPZ][SU]v8f16$",1458 "^FCVT[AMNPZ][SU]v8i16_shift$",1459 "^FCVT[AMNPZ][SU]v1f16$",1460 "^FCVTZ[SU]h$",1461 "^[SU]CVTFv8f16$",1462 "^[SU]CVTFv8i16_shift$",1463 "^[SU]CVTFv1i16$",1464 "^[SU]CVTFh$")>;1465 1466// ASIMD FP divide, D-form, F161467def : InstRW<[V3AEWrite_9c_1V1_4rc], (instrs FDIVv4f16)>;1468 1469// ASIMD FP divide, D-form, F321470def : InstRW<[V3AEWrite_9c_1V1_2rc], (instrs FDIVv2f32)>;1471 1472// ASIMD FP divide, Q-form, F161473def : InstRW<[V3AEWrite_13c_1V1_8rc], (instrs FDIVv8f16)>;1474 1475// ASIMD FP divide, Q-form, F321476def : InstRW<[V3AEWrite_11c_1V1_4rc], (instrs FDIVv4f32)>;1477 1478// ASIMD FP divide, Q-form, F641479def : InstRW<[V3AEWrite_14c_1V1_2rc], (instrs FDIVv2f64)>;1480 1481// ASIMD FP max/min, reduce, F32 and D-form F161482def : InstRW<[V3AEWrite_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;1483 1484// ASIMD FP max/min, reduce, Q-form F161485def : InstRW<[V3AEWrite_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;1486 1487// ASIMD FP multiply1488def : InstRW<[V3AEWr_VFM], (instregex "^FMULv", "^FMULXv")>;1489 1490// ASIMD FP multiply accumulate1491def : InstRW<[V3AEWr_VFMA, V3AERd_VFMA], (instregex "^FMLAv", "^FMLSv")>;1492 1493// ASIMD FP multiply accumulate long1494def : InstRW<[V3AEWr_VFMAL, V3AERd_VFMAL], (instregex "^FML[AS]L2?(lane)?v")>;1495 1496// ASIMD FP round, D-form F32 and Q-form F641497def : InstRW<[V3AEWrite_3c_1V0],1498 (instregex "^FRINT[AIMNPXZ]v2f(32|64)$",1499 "^FRINT(32|64)[XZ]v2f(32|64)$")>;1500 1501// ASIMD FP round, D-form F16 and Q-form F321502def : InstRW<[V3AEWrite_4c_2V0],1503 (instregex "^FRINT[AIMNPXZ]v4f(16|32)$",1504 "^FRINT(32|64)[XZ]v4f32$")>;1505 1506// ASIMD FP round, Q-form F161507def : InstRW<[V3AEWrite_6c_4V0], (instregex "^FRINT[AIMNPXZ]v8f16$")>;1508 1509// ASIMD FP square root, D-form, F161510def : InstRW<[V3AEWrite_9c_1V1_4rc], (instrs FSQRTv4f16)>;1511 1512// ASIMD FP square root, D-form, F321513def : InstRW<[V3AEWrite_9c_1V1_2rc], (instrs FSQRTv2f32)>;1514 1515// ASIMD FP square root, Q-form, F161516def : InstRW<[V3AEWrite_13c_1V1_8rc], (instrs FSQRTv8f16)>;1517 1518// ASIMD FP square root, Q-form, F321519def : InstRW<[V3AEWrite_11c_1V1_4rc], (instrs FSQRTv4f32)>;1520 1521// ASIMD FP square root, Q-form, F641522def : InstRW<[V3AEWrite_14c_1V1_2rc], (instrs FSQRTv2f64)>;1523 1524// §3.18 ASIMD BFloat16 (BF16) instructions1525// -----------------------------------------------------------------------------1526 1527// ASIMD convert, F32 to BF161528def : InstRW<[V3AEWrite_4c_2V0], (instrs BFCVTN, BFCVTN2)>;1529 1530// ASIMD dot product1531def : InstRW<[V3AEWr_VBFDOT, V3AERd_VBFDOT], (instrs BFDOTv4bf16, BFDOTv8bf16)>;1532 1533// ASIMD matrix multiply accumulate1534def : InstRW<[V3AEWr_VBFMMA, V3AERd_VBFMMA], (instrs BFMMLA)>;1535 1536// ASIMD multiply accumulate long1537def : InstRW<[V3AEWr_VBFMAL, V3AERd_VBFMAL], (instrs BFMLALB, BFMLALBIdx, BFMLALT,1538 BFMLALTIdx)>;1539 1540// Scalar convert, F32 to BF161541def : InstRW<[V3AEWrite_3c_1V0], (instrs BFCVT)>;1542 1543// §3.19 ASIMD miscellaneous instructions1544// -----------------------------------------------------------------------------1545 1546// ASIMD bit reverse1547// ASIMD bitwise insert1548// ASIMD count1549// ASIMD duplicate, element1550// ASIMD extract1551// ASIMD extract narrow1552// ASIMD insert, element to element1553// ASIMD move, FP immed1554// ASIMD move, integer immed1555// ASIMD reverse1556// ASIMD table lookup extension, 1 table reg1557// ASIMD transpose1558// ASIMD unzip/zip1559// Handled by SchedAlias<WriteV[dq], ...>1560def : InstRW<[V3AEWrite_0or2c_1V], (instrs MOVID, MOVIv2d_ns)>;1561 1562// ASIMD duplicate, gen reg1563def : InstRW<[V3AEWrite_3c_1M0], (instregex "^DUPv.+gpr")>;1564 1565// ASIMD extract narrow, saturating1566def : InstRW<[V3AEWrite_4c_1V], (instregex "^[SU]QXTNv", "^SQXTUNv")>;1567 1568// ASIMD reciprocal and square root estimate, D-form U321569def : InstRW<[V3AEWrite_3c_1V0], (instrs URECPEv2i32, URSQRTEv2i32)>;1570 1571// ASIMD reciprocal and square root estimate, Q-form U321572def : InstRW<[V3AEWrite_4c_2V0], (instrs URECPEv4i32, URSQRTEv4i32)>;1573 1574// ASIMD reciprocal and square root estimate, D-form F32 and scalar forms1575def : InstRW<[V3AEWrite_3c_1V0], (instrs FRECPEv1f16, FRECPEv1i32,1576 FRECPEv1i64, FRECPEv2f32,1577 FRSQRTEv1f16, FRSQRTEv1i32,1578 FRSQRTEv1i64, FRSQRTEv2f32)>;1579 1580// ASIMD reciprocal and square root estimate, D-form F16 and Q-form F321581def : InstRW<[V3AEWrite_4c_2V0], (instrs FRECPEv4f16, FRECPEv4f32,1582 FRSQRTEv4f16, FRSQRTEv4f32)>;1583 1584// ASIMD reciprocal and square root estimate, Q-form F161585def : InstRW<[V3AEWrite_6c_4V0], (instrs FRECPEv8f16, FRSQRTEv8f16)>;1586 1587// ASIMD reciprocal exponent1588def : InstRW<[V3AEWrite_3c_1V0], (instregex "^FRECPXv")>;1589 1590// ASIMD reciprocal step1591def : InstRW<[V3AEWrite_4c_1V], (instregex "^FRECPS(32|64|v)",1592 "^FRSQRTS(32|64|v)")>;1593 1594// ASIMD table lookup, 1 or 2 table regs1595def : InstRW<[V3AEWrite_2c_1V], (instrs TBLv8i8One, TBLv16i8One,1596 TBLv8i8Two, TBLv16i8Two)>;1597 1598// ASIMD table lookup, 3 table regs1599def : InstRW<[V3AEWrite_4c_2V], (instrs TBLv8i8Three, TBLv16i8Three)>;1600 1601// ASIMD table lookup, 4 table regs1602def : InstRW<[V3AEWrite_4c_3V], (instrs TBLv8i8Four, TBLv16i8Four)>;1603 1604// ASIMD table lookup extension, 2 table reg1605def : InstRW<[V3AEWrite_4c_2V], (instrs TBXv8i8Two, TBXv16i8Two)>;1606 1607// ASIMD table lookup extension, 3 table reg1608def : InstRW<[V3AEWrite_6c_3V], (instrs TBXv8i8Three, TBXv16i8Three)>;1609 1610// ASIMD table lookup extension, 4 table reg1611def : InstRW<[V3AEWrite_6c_5V], (instrs TBXv8i8Four, TBXv16i8Four)>;1612 1613// ASIMD transfer, element to gen reg1614def : InstRW<[V3AEWrite_2c_2V], (instregex "^[SU]MOVv")>;1615 1616// ASIMD transfer, gen reg to element1617def : InstRW<[V3AEWrite_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;1618 1619// §3.20 ASIMD load instructions1620// -----------------------------------------------------------------------------1621 1622// ASIMD load, 1 element, multiple, 1 reg, D-form1623def : InstRW<[V3AEWrite_6c_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;1624def : InstRW<[WriteAdr, V3AEWrite_6c_1L],1625 (instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>;1626 1627// ASIMD load, 1 element, multiple, 1 reg, Q-form1628def : InstRW<[V3AEWrite_6c_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;1629def : InstRW<[WriteAdr, V3AEWrite_6c_1L],1630 (instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>;1631 1632// ASIMD load, 1 element, multiple, 2 reg, D-form1633def : InstRW<[V3AEWrite_6c_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;1634def : InstRW<[WriteAdr, V3AEWrite_6c_2L],1635 (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;1636 1637// ASIMD load, 1 element, multiple, 2 reg, Q-form1638def : InstRW<[V3AEWrite_6c_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;1639def : InstRW<[WriteAdr, V3AEWrite_6c_2L],1640 (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;1641 1642// ASIMD load, 1 element, multiple, 3 reg, D-form1643def : InstRW<[V3AEWrite_6c_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;1644def : InstRW<[WriteAdr, V3AEWrite_6c_3L],1645 (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;1646 1647// ASIMD load, 1 element, multiple, 3 reg, Q-form1648def : InstRW<[V3AEWrite_6c_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;1649def : InstRW<[WriteAdr, V3AEWrite_6c_3L],1650 (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;1651 1652// ASIMD load, 1 element, multiple, 4 reg, D-form1653def : InstRW<[V3AEWrite_7c_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;1654def : InstRW<[WriteAdr, V3AEWrite_7c_4L],1655 (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;1656 1657// ASIMD load, 1 element, multiple, 4 reg, Q-form1658def : InstRW<[V3AEWrite_7c_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;1659def : InstRW<[WriteAdr, V3AEWrite_7c_4L],1660 (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;1661 1662// ASIMD load, 1 element, one lane, B/H/S1663// ASIMD load, 1 element, one lane, D1664def : InstRW<[V3AEWrite_8c_1L_1V], (instregex "LD1i(8|16|32|64)$")>;1665def : InstRW<[WriteAdr, V3AEWrite_8c_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;1666 1667// ASIMD load, 1 element, all lanes, D-form, B/H/S1668// ASIMD load, 1 element, all lanes, D-form, D1669def : InstRW<[V3AEWrite_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;1670def : InstRW<[WriteAdr, V3AEWrite_8c_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;1671 1672// ASIMD load, 1 element, all lanes, Q-form1673def : InstRW<[V3AEWrite_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;1674def : InstRW<[WriteAdr, V3AEWrite_8c_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;1675 1676// ASIMD load, 2 element, multiple, D-form, B/H/S1677def : InstRW<[V3AEWrite_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;1678def : InstRW<[WriteAdr, V3AEWrite_8c_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;1679 1680// ASIMD load, 2 element, multiple, Q-form, B/H/S1681// ASIMD load, 2 element, multiple, Q-form, D1682def : InstRW<[V3AEWrite_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;1683def : InstRW<[WriteAdr, V3AEWrite_8c_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;1684 1685// ASIMD load, 2 element, one lane, B/H1686// ASIMD load, 2 element, one lane, S1687// ASIMD load, 2 element, one lane, D1688def : InstRW<[V3AEWrite_8c_1L_2V], (instregex "LD2i(8|16|32|64)$")>;1689def : InstRW<[WriteAdr, V3AEWrite_8c_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;1690 1691// ASIMD load, 2 element, all lanes, D-form, B/H/S1692// ASIMD load, 2 element, all lanes, D-form, D1693def : InstRW<[V3AEWrite_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;1694def : InstRW<[WriteAdr, V3AEWrite_8c_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;1695 1696// ASIMD load, 2 element, all lanes, Q-form1697def : InstRW<[V3AEWrite_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;1698def : InstRW<[WriteAdr, V3AEWrite_8c_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;1699 1700// ASIMD load, 3 element, multiple, D-form, B/H/S1701def : InstRW<[V3AEWrite_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;1702def : InstRW<[WriteAdr, V3AEWrite_8c_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;1703 1704// ASIMD load, 3 element, multiple, Q-form, B/H/S1705// ASIMD load, 3 element, multiple, Q-form, D1706def : InstRW<[V3AEWrite_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)$")>;1707def : InstRW<[WriteAdr, V3AEWrite_8c_3L_3V], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;1708 1709// ASIMD load, 3 element, one lane, B/H1710// ASIMD load, 3 element, one lane, S1711// ASIMD load, 3 element, one lane, D1712def : InstRW<[V3AEWrite_8c_2L_3V], (instregex "LD3i(8|16|32|64)$")>;1713def : InstRW<[WriteAdr, V3AEWrite_8c_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;1714 1715// ASIMD load, 3 element, all lanes, D-form, B/H/S1716// ASIMD load, 3 element, all lanes, D-form, D1717def : InstRW<[V3AEWrite_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;1718def : InstRW<[WriteAdr, V3AEWrite_8c_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;1719 1720// ASIMD load, 3 element, all lanes, Q-form, B/H/S1721// ASIMD load, 3 element, all lanes, Q-form, D1722def : InstRW<[V3AEWrite_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;1723def : InstRW<[WriteAdr, V3AEWrite_8c_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;1724 1725// ASIMD load, 4 element, multiple, D-form, B/H/S1726def : InstRW<[V3AEWrite_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;1727def : InstRW<[WriteAdr, V3AEWrite_8c_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;1728 1729// ASIMD load, 4 element, multiple, Q-form, B/H/S1730// ASIMD load, 4 element, multiple, Q-form, D1731def : InstRW<[V3AEWrite_9c_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;1732def : InstRW<[WriteAdr, V3AEWrite_9c_6L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;1733 1734// ASIMD load, 4 element, one lane, B/H1735// ASIMD load, 4 element, one lane, S1736// ASIMD load, 4 element, one lane, D1737def : InstRW<[V3AEWrite_8c_3L_4V], (instregex "LD4i(8|16|32|64)$")>;1738def : InstRW<[WriteAdr, V3AEWrite_8c_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;1739 1740// ASIMD load, 4 element, all lanes, D-form, B/H/S1741// ASIMD load, 4 element, all lanes, D-form, D1742def : InstRW<[V3AEWrite_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;1743def : InstRW<[WriteAdr, V3AEWrite_8c_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;1744 1745// ASIMD load, 4 element, all lanes, Q-form, B/H/S1746// ASIMD load, 4 element, all lanes, Q-form, D1747def : InstRW<[V3AEWrite_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;1748def : InstRW<[WriteAdr, V3AEWrite_8c_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;1749 1750// §3.21 ASIMD store instructions1751// -----------------------------------------------------------------------------1752 1753// ASIMD store, 1 element, multiple, 1 reg, D-form1754def : InstRW<[V3AEWrite_2c_1SA_1V], (instregex "ST1Onev(8b|4h|2s|1d)$")>;1755def : InstRW<[WriteAdr, V3AEWrite_2c_1SA_1V], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;1756 1757// ASIMD store, 1 element, multiple, 1 reg, Q-form1758def : InstRW<[V3AEWrite_2c_1SA_1V], (instregex "ST1Onev(16b|8h|4s|2d)$")>;1759def : InstRW<[WriteAdr, V3AEWrite_2c_1SA_1V], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;1760 1761// ASIMD store, 1 element, multiple, 2 reg, D-form1762def : InstRW<[V3AEWrite_2c_1SA_1V], (instregex "ST1Twov(8b|4h|2s|1d)$")>;1763def : InstRW<[WriteAdr, V3AEWrite_2c_1SA_1V], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;1764 1765// ASIMD store, 1 element, multiple, 2 reg, Q-form1766def : InstRW<[V3AEWrite_2c_2SA_2V], (instregex "ST1Twov(16b|8h|4s|2d)$")>;1767def : InstRW<[WriteAdr, V3AEWrite_2c_2SA_2V], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;1768 1769// ASIMD store, 1 element, multiple, 3 reg, D-form1770def : InstRW<[V3AEWrite_2c_2SA_2V], (instregex "ST1Threev(8b|4h|2s|1d)$")>;1771def : InstRW<[WriteAdr, V3AEWrite_2c_2SA_2V], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;1772 1773// ASIMD store, 1 element, multiple, 3 reg, Q-form1774def : InstRW<[V3AEWrite_2c_3SA_3V], (instregex "ST1Threev(16b|8h|4s|2d)$")>;1775def : InstRW<[WriteAdr, V3AEWrite_2c_3SA_3V], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;1776 1777// ASIMD store, 1 element, multiple, 4 reg, D-form1778def : InstRW<[V3AEWrite_2c_2SA_2V], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;1779def : InstRW<[WriteAdr, V3AEWrite_2c_2SA_2V], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;1780 1781// ASIMD store, 1 element, multiple, 4 reg, Q-form1782def : InstRW<[V3AEWrite_2c_4SA_4V], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;1783def : InstRW<[WriteAdr, V3AEWrite_2c_4SA_4V], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;1784 1785// ASIMD store, 1 element, one lane, B/H/S1786// ASIMD store, 1 element, one lane, D1787def : InstRW<[V3AEWrite_4c_1SA_2V], (instregex "ST1i(8|16|32|64)$")>;1788def : InstRW<[WriteAdr, V3AEWrite_4c_1SA_2V], (instregex "ST1i(8|16|32|64)_POST$")>;1789 1790// ASIMD store, 2 element, multiple, D-form, B/H/S1791def : InstRW<[V3AEWrite_4c_1SA_2V], (instregex "ST2Twov(8b|4h|2s)$")>;1792def : InstRW<[WriteAdr, V3AEWrite_4c_1SA_2V], (instregex "ST2Twov(8b|4h|2s)_POST$")>;1793 1794// ASIMD store, 2 element, multiple, Q-form, B/H/S1795// ASIMD store, 2 element, multiple, Q-form, D1796def : InstRW<[V3AEWrite_4c_2SA_4V], (instregex "ST2Twov(16b|8h|4s|2d)$")>;1797def : InstRW<[WriteAdr, V3AEWrite_4c_2SA_4V], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;1798 1799// ASIMD store, 2 element, one lane, B/H/S1800// ASIMD store, 2 element, one lane, D1801def : InstRW<[V3AEWrite_4c_1SA_2V], (instregex "ST2i(8|16|32|64)$")>;1802def : InstRW<[WriteAdr, V3AEWrite_4c_1SA_2V], (instregex "ST2i(8|16|32|64)_POST$")>;1803 1804// ASIMD store, 3 element, multiple, D-form, B/H/S1805def : InstRW<[V3AEWrite_5c_2SA_4V], (instregex "ST3Threev(8b|4h|2s)$")>;1806def : InstRW<[WriteAdr, V3AEWrite_5c_2SA_4V], (instregex "ST3Threev(8b|4h|2s)_POST$")>;1807 1808// ASIMD store, 3 element, multiple, Q-form, B/H/S1809// ASIMD store, 3 element, multiple, Q-form, D1810def : InstRW<[V3AEWrite_6c_3SA_6V], (instregex "ST3Threev(16b|8h|4s|2d)$")>;1811def : InstRW<[WriteAdr, V3AEWrite_6c_3SA_6V], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;1812 1813// ASIMD store, 3 element, one lane, B/H1814// ASIMD store, 3 element, one lane, S1815// ASIMD store, 3 element, one lane, D1816def : InstRW<[V3AEWrite_5c_2SA_4V], (instregex "ST3i(8|16|32|64)$")>;1817def : InstRW<[WriteAdr, V3AEWrite_5c_2SA_4V], (instregex "ST3i(8|16|32|64)_POST$")>;1818 1819// ASIMD store, 4 element, multiple, D-form, B/H/S1820def : InstRW<[V3AEWrite_6c_2SA_6V], (instregex "ST4Fourv(8b|4h|2s)$")>;1821def : InstRW<[WriteAdr, V3AEWrite_6c_2SA_6V], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;1822 1823// ASIMD store, 4 element, multiple, Q-form, B/H/S1824def : InstRW<[V3AEWrite_7c_4SA_12V], (instregex "ST4Fourv(16b|8h|4s)$")>;1825def : InstRW<[WriteAdr, V3AEWrite_7c_4SA_12V], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;1826 1827// ASIMD store, 4 element, multiple, Q-form, D1828def : InstRW<[V3AEWrite_5c_4SA_8V], (instregex "ST4Fourv(2d)$")>;1829def : InstRW<[WriteAdr, V3AEWrite_5c_4SA_8V], (instregex "ST4Fourv(2d)_POST$")>;1830 1831// ASIMD store, 4 element, one lane, B/H/S1832def : InstRW<[V3AEWrite_6c_1SA_3V], (instregex "ST4i(8|16|32)$")>;1833def : InstRW<[WriteAdr, V3AEWrite_6c_1SA_3V], (instregex "ST4i(8|16|32)_POST$")>;1834 1835// ASIMD store, 4 element, one lane, D1836def : InstRW<[V3AEWrite_4c_2SA_4V], (instregex "ST4i(64)$")>;1837def : InstRW<[WriteAdr, V3AEWrite_4c_2SA_4V], (instregex "ST4i(64)_POST$")>;1838 1839// §3.22 Cryptography extensions1840// -----------------------------------------------------------------------------1841 1842// Crypto AES ops1843def : InstRW<[V3AEWrite_2c_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;1844 1845// Crypto polynomial (64x64) multiply long1846def : InstRW<[V3AEWrite_2c_1V], (instrs PMULLv1i64, PMULLv2i64)>;1847 1848// Crypto SHA1 hash acceleration op1849// Crypto SHA1 schedule acceleration ops1850def : InstRW<[V3AEWrite_2c_1V0], (instregex "^SHA1(H|SU0|SU1)")>;1851 1852// Crypto SHA1 hash acceleration ops1853// Crypto SHA256 hash acceleration ops1854def : InstRW<[V3AEWrite_4c_1V0], (instregex "^SHA1[CMP]", "^SHA256H2?")>;1855 1856// Crypto SHA256 schedule acceleration ops1857def : InstRW<[V3AEWrite_2c_1V0], (instregex "^SHA256SU[01]")>;1858 1859// Crypto SHA512 hash acceleration ops1860def : InstRW<[V3AEWrite_2c_1V0], (instregex "^SHA512(H|H2|SU0|SU1)")>;1861 1862// Crypto SHA3 ops1863def : InstRW<[V3AEWrite_2c_1V], (instrs BCAX, EOR3, RAX1, XAR)>;1864 1865// Crypto SM3 ops1866def : InstRW<[V3AEWrite_2c_1V0], (instregex "^SM3PARTW[12]$", "^SM3SS1$",1867 "^SM3TT[12][AB]$")>;1868 1869// Crypto SM4 ops1870def : InstRW<[V3AEWrite_4c_1V0], (instrs SM4E, SM4ENCKEY)>;1871 1872// §3.23 CRC1873// -----------------------------------------------------------------------------1874 1875def : InstRW<[V3AEWr_CRC, V3AERd_CRC], (instregex "^CRC32")>;1876 1877// §3.24 SVE Predicate instructions1878// -----------------------------------------------------------------------------1879 1880// Loop control, based on predicate1881def : InstRW<[V3AEWrite_2or3c_1M], (instrs BRKA_PPmP, BRKA_PPzP,1882 BRKB_PPmP, BRKB_PPzP)>;1883 1884// Loop control, based on predicate and flag setting1885def : InstRW<[V3AEWrite_2or3c_1M], (instrs BRKAS_PPzP, BRKBS_PPzP)>;1886 1887// Loop control, propagating1888def : InstRW<[V3AEWrite_2or3c_1M], (instrs BRKN_PPzP, BRKPA_PPzPP,1889 BRKPB_PPzPP)>;1890 1891// Loop control, propagating and flag setting1892def : InstRW<[V3AEWrite_2or3c_1M], (instrs BRKNS_PPzP, BRKPAS_PPzPP,1893 BRKPBS_PPzPP)>;1894 1895// Loop control, based on GPR1896def : InstRW<[V3AEWrite_3c_2M],1897 (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_P(WW|XX)_[BHSD]")>;1898def : InstRW<[V3AEWrite_3c_2M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]")>;1899 1900// Loop terminate1901def : InstRW<[V3AEWrite_1c_2M], (instregex "^CTERM(EQ|NE)_(WW|XX)")>;1902 1903// Predicate counting scalar1904def : InstRW<[V3AEWrite_2c_1M], (instrs ADDPL_XXI, ADDVL_XXI, RDVLI_XI)>;1905def : InstRW<[V3AEWrite_2c_1M],1906 (instregex "^(CNT|SQDEC|SQINC|UQDEC|UQINC)[BHWD]_XPiI",1907 "^SQ(DEC|INC)[BHWD]_XPiWdI",1908 "^UQ(DEC|INC)[BHWD]_WPiI")>;1909 1910// Predicate counting scalar, ALL, {1,2,4}1911def : InstRW<[V3AEWrite_IncDec], (instregex "^(DEC|INC)[BHWD]_XPiI")>;1912 1913// Predicate counting scalar, active predicate1914def : InstRW<[V3AEWrite_2c_1M],1915 (instregex "^CNTP_XPP_[BHSD]",1916 "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_XP_[BHSD]",1917 "^(UQDEC|UQINC)P_WP_[BHSD]",1918 "^(SQDEC|SQINC)P_XPWd_[BHSD]")>;1919 1920// Predicate counting vector, active predicate1921def : InstRW<[V3AEWrite_7c_1M_1M0_1V],1922 (instregex "^(DEC|INC|SQDEC|SQINC|UQDEC|UQINC)P_ZP_[HSD]")>;1923 1924// Predicate logical1925def : InstRW<[V3AEWrite_1or2c_1M],1926 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP")>;1927 1928// Predicate logical, flag setting1929def : InstRW<[V3AEWrite_1or2c_1M],1930 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;1931 1932// Predicate reverse1933def : InstRW<[V3AEWrite_2c_1M], (instregex "^REV_PP_[BHSD]")>;1934 1935// Predicate select1936def : InstRW<[V3AEWrite_1c_1M], (instrs SEL_PPPP)>;1937 1938// Predicate set1939def : InstRW<[V3AEWrite_2c_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;1940 1941// Predicate set/initialize, set flags1942def : InstRW<[V3AEWrite_2c_1M], (instregex "^PTRUES_[BHSD]")>;1943 1944// Predicate find first/next1945def : InstRW<[V3AEWrite_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;1946 1947// Predicate test1948def : InstRW<[V3AEWrite_1c_1M], (instrs PTEST_PP)>;1949 1950// Predicate transpose1951def : InstRW<[V3AEWrite_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;1952 1953// Predicate unpack and widen1954def : InstRW<[V3AEWrite_2c_1M], (instrs PUNPKHI_PP, PUNPKLO_PP)>;1955 1956// Predicate zip/unzip1957def : InstRW<[V3AEWrite_2c_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]")>;1958 1959// §3.25 SVE integer instructions1960// -----------------------------------------------------------------------------1961 1962// Arithmetic, absolute diff1963def : InstRW<[V3AEWrite_2c_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]",1964 "^[SU]ABD_ZPZZ_[BHSD]")>;1965 1966// Arithmetic, absolute diff accum1967def : InstRW<[V3AEWr_ZA, V3AERd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]")>;1968 1969// Arithmetic, absolute diff accum long1970def : InstRW<[V3AEWr_ZA, V3AERd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]")>;1971 1972// Arithmetic, absolute diff long1973def : InstRW<[V3AEWrite_2c_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]")>;1974 1975// Arithmetic, basic1976def : InstRW<[V3AEWrite_2c_1V],1977 (instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]",1978 "^(ADD|SUB)_ZZZ_[BHSD]",1979 "^(ADD|SUB|SUBR)_ZPZZ_[BHSD]",1980 "^(ADD|SUB|SUBR)_ZI_[BHSD]",1981 "^ADR_[SU]XTW_ZZZ_D_[0123]",1982 "^ADR_LSL_ZZZ_[SD]_[0123]",1983 "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",1984 "^SADDLBT_ZZZ_[HSD]",1985 "^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",1986 "^SSUBL(BT|TB)_ZZZ_[HSD]")>;1987 1988// Arithmetic, complex1989def : InstRW<[V3AEWrite_2c_1V],1990 (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]",1991 "^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]",1992 "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]",1993 "^[SU]Q(ADD|SUB)_ZI_[BHSD]",1994 "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]",1995 "^(UQSUB|UQSUBR)_ZPmZ_[BHSD]")>;1996 1997// Arithmetic, large integer1998def : InstRW<[V3AEWrite_2c_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]")>;1999 2000// Arithmetic, pairwise add2001def : InstRW<[V3AEWrite_2c_1V], (instregex "^ADDP_ZPmZ_[BHSD]")>;2002 2003// Arithmetic, pairwise add and accum long2004def : InstRW<[V3AEWr_ZPA, ReadDefault, V3AERd_ZPA],2005 (instregex "^[SU]ADALP_ZPmZ_[HSD]")>;2006 2007// Arithmetic, shift2008def : InstRW<[V3AEWrite_2c_1V1],2009 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",2010 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",2011 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",2012 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",2013 "^(ASR|LSL|LSR)_ZZI_[BHSD]",2014 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",2015 "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]")>;2016 2017// Arithmetic, shift and accumulate2018def : InstRW<[V3AEWr_ZSA, V3AERd_ZSA], (instregex "^[SU]R?SRA_ZZI_[BHSD]")>;2019 2020// Arithmetic, shift by immediate2021def : InstRW<[V3AEWrite_2c_1V], (instregex "^SHRN[BT]_ZZI_[BHS]",2022 "^[SU]SHLL[BT]_ZZI_[HSD]")>;2023 2024// Arithmetic, shift by immediate and insert2025def : InstRW<[V3AEWrite_2c_1V], (instregex "^(SLI|SRI)_ZZI_[BHSD]")>;2026 2027// Arithmetic, shift complex2028def : InstRW<[V3AEWrite_4c_1V],2029 (instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]",2030 "^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]",2031 "^[SU]QR?SHL_ZPZZ_[BHSD]",2032 "^(SQSHL|SQSHLU|UQSHL)_(ZPmI|ZPZI)_[BHSD]",2033 "^SQSHRU?N[BT]_ZZI_[BHS]",2034 "^UQR?SHRN[BT]_ZZI_[BHS]")>;2035 2036// Arithmetic, shift right for divide2037def : InstRW<[V3AEWrite_4c_1V], (instregex "^ASRD_(ZPmI|ZPZI)_[BHSD]")>;2038 2039// Arithmetic, shift rounding2040def : InstRW<[V3AEWrite_4c_1V], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]",2041 "^[SU]RSHL_ZPZZ_[BHSD]",2042 "^[SU]RSHR_(ZPmI|ZPZI)_[BHSD]")>;2043 2044// Bit manipulation2045def : InstRW<[V3AEWrite_6c_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]")>;2046 2047// Bitwise select2048def : InstRW<[V3AEWrite_2c_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ")>;2049 2050// Count/reverse bits2051def : InstRW<[V3AEWrite_2c_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]")>;2052 2053// Broadcast logical bitmask immediate to vector2054def : InstRW<[V3AEWrite_2c_1V], (instrs DUPM_ZI)>;2055 2056// Compare and set flags2057def : InstRW<[V3AEWrite_2or3c_1V0],2058 (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]",2059 "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]")>;2060 2061// Complex add2062def : InstRW<[V3AEWrite_2c_1V], (instregex "^(SQ)?CADD_ZZI_[BHSD]")>;2063 2064// Complex dot product 8-bit element2065def : InstRW<[V3AEWr_ZDOTB, V3AERd_ZDOTB], (instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;2066 2067// Complex dot product 16-bit element2068def : InstRW<[V3AEWr_ZDOTH, V3AERd_ZDOTH], (instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;2069 2070// Complex multiply-add B, H, S element size2071def : InstRW<[V3AEWr_ZCMABHS, V3AERd_ZCMABHS], (instregex "^CMLA_ZZZ_[BHS]",2072 "^CMLA_ZZZI_[HS]")>;2073 2074// Complex multiply-add D element size2075def : InstRW<[V3AEWr_ZCMAD, V3AERd_ZCMAD], (instrs CMLA_ZZZ_D)>;2076 2077// Conditional extract operations, scalar form2078def : InstRW<[V3AEWrite_8c_1M0_1V], (instregex "^CLAST[AB]_RPZ_[BHSD]")>;2079 2080// Conditional extract operations, SIMD&FP scalar and vector forms2081def : InstRW<[V3AEWrite_3c_1V1], (instregex "^CLAST[AB]_[VZ]PZ_[BHSD]",2082 "^COMPACT_ZPZ_[SD]",2083 "^SPLICE_ZPZZ?_[BHSD]")>;2084 2085// Convert to floating point, 64b to float or convert to double2086def : InstRW<[V3AEWrite_3c_1V0], (instregex "^[SU]CVTF_ZPmZ_Dto[HSD]",2087 "^[SU]CVTF_ZPmZ_StoD")>;2088 2089// Convert to floating point, 32b to single or half2090def : InstRW<[V3AEWrite_4c_2V0], (instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;2091 2092// Convert to floating point, 16b to half2093def : InstRW<[V3AEWrite_6c_4V0], (instregex "^[SU]CVTF_ZPmZ_HtoH")>;2094 2095// Copy, scalar2096def : InstRW<[V3AEWrite_5c_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]")>;2097 2098// Copy, scalar SIMD&FP or imm2099def : InstRW<[V3AEWrite_2c_1V], (instregex "^CPY_ZPm[IV]_[BHSD]",2100 "^CPY_ZPzI_[BHSD]")>;2101 2102// Divides, 32 bit2103def : InstRW<[V3AEWrite_12c_1V0], (instregex "^[SU]DIVR?_ZPmZ_S",2104 "^[SU]DIV_ZPZZ_S")>;2105 2106// Divides, 64 bit2107def : InstRW<[V3AEWrite_20c_1V0], (instregex "^[SU]DIVR?_ZPmZ_D",2108 "^[SU]DIV_ZPZZ_D")>;2109 2110// Dot product, 8 bit2111def : InstRW<[V3AEWr_ZDOTB, V3AERd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_BtoS")>;2112 2113// Dot product, 8 bit, using signed and unsigned integers2114def : InstRW<[V3AEWr_ZDOTB, V3AERd_ZDOTB], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;2115 2116// Dot product, 16 bit2117def : InstRW<[V3AEWr_ZDOTH, V3AERd_ZDOTH], (instregex "^[SU]DOT_ZZZI?_HtoD")>;2118 2119// Duplicate, immediate and indexed form2120def : InstRW<[V3AEWrite_2c_1V], (instregex "^DUP_ZI_[BHSD]",2121 "^DUP_ZZI_[BHSDQ]")>;2122 2123// Duplicate, scalar form2124def : InstRW<[V3AEWrite_3c_1M0], (instregex "^DUP_ZR_[BHSD]")>;2125 2126// Extend, sign or zero2127def : InstRW<[V3AEWrite_2c_1V], (instregex "^[SU]XTB_ZPmZ_[HSD]",2128 "^[SU]XTH_ZPmZ_[SD]",2129 "^[SU]XTW_ZPmZ_[D]")>;2130 2131// Extract2132def : InstRW<[V3AEWrite_2c_1V], (instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;2133 2134// Extract narrow saturating2135def : InstRW<[V3AEWrite_4c_1V], (instregex "^[SU]QXTN[BT]_ZZ_[BHS]",2136 "^SQXTUN[BT]_ZZ_[BHS]")>;2137 2138// Extract operation, SIMD and FP scalar form2139def : InstRW<[V3AEWrite_3c_1V1], (instregex "^LAST[AB]_VPZ_[BHSD]")>;2140 2141// Extract operation, scalar2142def : InstRW<[V3AEWrite_6c_1V1_1M0], (instregex "^LAST[AB]_RPZ_[BHSD]")>;2143 2144// Histogram operations2145def : InstRW<[V3AEWrite_2c_1V], (instregex "^HISTCNT_ZPzZZ_[SD]",2146 "^HISTSEG_ZZZ")>;2147 2148// Horizontal operations, B, H, S form, immediate operands only2149def : InstRW<[V3AEWrite_4c_1V0], (instregex "^INDEX_II_[BHS]")>;2150 2151// Horizontal operations, B, H, S form, scalar, immediate operands/ scalar2152// operands only / immediate, scalar operands2153def : InstRW<[V3AEWrite_7c_1M0_1V0], (instregex "^INDEX_(IR|RI|RR)_[BHS]")>;2154 2155// Horizontal operations, D form, immediate operands only2156def : InstRW<[V3AEWrite_5c_2V0], (instrs INDEX_II_D)>;2157 2158// Horizontal operations, D form, scalar, immediate operands)/ scalar operands2159// only / immediate, scalar operands2160def : InstRW<[V3AEWrite_8c_2M0_2V0], (instregex "^INDEX_(IR|RI|RR)_D")>;2161 2162// insert operation, SIMD and FP scalar form2163def : InstRW<[V3AEWrite_2c_1V], (instregex "^INSR_ZV_[BHSD]")>;2164 2165// insert operation, scalar2166def : InstRW<[V3AEWrite_5c_1V1_1M0], (instregex "^INSR_ZR_[BHSD]")>;2167 2168// Logical2169def : InstRW<[V3AEWrite_2c_1V],2170 (instregex "^(AND|EOR|ORR)_ZI",2171 "^(AND|BIC|EOR|ORR)_ZZZ",2172 "^EOR(BT|TB)_ZZZ_[BHSD]",2173 "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]",2174 "^NOT_ZPmZ_[BHSD]")>;2175 2176// Max/min, basic and pairwise2177def : InstRW<[V3AEWrite_2c_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]",2178 "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]",2179 "^[SU](MAX|MIN)_ZPZZ_[BHSD]")>;2180 2181// Matching operations2182// FIXME: SOG p. 44, n. 5: If the consuming instruction has a flag source, the2183// latency for this instruction is 4 cycles.2184def : InstRW<[V3AEWrite_2or3c_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]")>;2185 2186// Matrix multiply-accumulate2187def : InstRW<[V3AEWr_ZMMA, V3AERd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;2188 2189// Move prefix2190def : InstRW<[V3AEWrite_2c_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]",2191 "^MOVPRFX_ZZ")>;2192 2193// Multiply, B, H, S element size2194def : InstRW<[V3AEWrite_4c_1V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]",2195 "^MUL_ZPZZ_[BHS]",2196 "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]",2197 "^[SU]MULH_ZPZZ_[BHS]")>;2198 2199// Multiply, D element size2200def : InstRW<[V3AEWrite_5c_2V0], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D",2201 "^MUL_ZPZZ_D",2202 "^[SU]MULH_(ZPmZ|ZZZ)_D",2203 "^[SU]MULH_ZPZZ_D")>;2204 2205// Multiply long2206def : InstRW<[V3AEWrite_4c_1V0], (instregex "^[SU]MULL[BT]_ZZZI_[SD]",2207 "^[SU]MULL[BT]_ZZZ_[HSD]")>;2208 2209// Multiply accumulate, B, H, S element size2210def : InstRW<[V3AEWr_ZMABHS, V3AERd_ZMABHS],2211 (instregex "^ML[AS]_ZZZI_[HS]", "^ML[AS]_ZPZZZ_[BHS]")>;2212def : InstRW<[V3AEWr_ZMABHS, ReadDefault, V3AERd_ZMABHS],2213 (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]")>;2214 2215// Multiply accumulate, D element size2216def : InstRW<[V3AEWr_ZMAD, V3AERd_ZMAD],2217 (instregex "^ML[AS]_ZZZI_D", "^ML[AS]_ZPZZZ_D")>;2218def : InstRW<[V3AEWr_ZMAD, ReadDefault, V3AERd_ZMAD],2219 (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D")>;2220 2221// Multiply accumulate long2222def : InstRW<[V3AEWr_ZMAL, V3AERd_ZMAL], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]",2223 "^[SU]ML[AS]L[BT]_ZZZI_[SD]")>;2224 2225// Multiply accumulate saturating doubling long regular2226def : InstRW<[V3AEWr_ZMASQL, V3AERd_ZMASQ],2227 (instregex "^SQDML[AS]L(B|T|BT)_ZZZ_[HSD]",2228 "^SQDML[AS]L[BT]_ZZZI_[SD]")>;2229 2230// Multiply saturating doubling high, B, H, S element size2231def : InstRW<[V3AEWrite_4c_1V0], (instregex "^SQDMULH_ZZZ_[BHS]",2232 "^SQDMULH_ZZZI_[HS]")>;2233 2234// Multiply saturating doubling high, D element size2235def : InstRW<[V3AEWrite_5c_2V0], (instrs SQDMULH_ZZZ_D, SQDMULH_ZZZI_D)>;2236 2237// Multiply saturating doubling long2238def : InstRW<[V3AEWrite_4c_1V0], (instregex "^SQDMULL[BT]_ZZZ_[HSD]",2239 "^SQDMULL[BT]_ZZZI_[SD]")>;2240 2241// Multiply saturating rounding doubling regular/complex accumulate, B, H, S2242// element size2243def : InstRW<[V3AEWr_ZMASQBHS, V3AERd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZ_[BHS]",2244 "^SQRDCMLAH_ZZZ_[BHS]",2245 "^SQRDML[AS]H_ZZZI_[HS]",2246 "^SQRDCMLAH_ZZZI_[HS]")>;2247 2248// Multiply saturating rounding doubling regular/complex accumulate, D element2249// size2250def : InstRW<[V3AEWr_ZMASQD, V3AERd_ZMASQ], (instregex "^SQRDML[AS]H_ZZZI?_D",2251 "^SQRDCMLAH_ZZZ_D")>;2252 2253// Multiply saturating rounding doubling regular/complex, B, H, S element size2254def : InstRW<[V3AEWrite_4c_1V0], (instregex "^SQRDMULH_ZZZ_[BHS]",2255 "^SQRDMULH_ZZZI_[HS]")>;2256 2257// Multiply saturating rounding doubling regular/complex, D element size2258def : InstRW<[V3AEWrite_5c_2V0], (instregex "^SQRDMULH_ZZZI?_D")>;2259 2260// Multiply/multiply long, (8x8) polynomial2261def : InstRW<[V3AEWrite_2c_1V], (instregex "^PMUL_ZZZ_B",2262 "^PMULL[BT]_ZZZ_[HDQ]")>;2263 2264// Predicate counting vector2265def : InstRW<[V3AEWrite_2c_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI")>;2266 2267// Reciprocal estimate2268def : InstRW<[V3AEWrite_4c_2V0], (instregex "^URECPE_ZPmZ_S", "^URSQRTE_ZPmZ_S")>;2269 2270// Reduction, arithmetic, B form2271def : InstRW<[V3AEWrite_9c_2V_4V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;2272 2273// Reduction, arithmetic, H form2274def : InstRW<[V3AEWrite_8c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;2275 2276// Reduction, arithmetic, S form2277def : InstRW<[V3AEWrite_6c_2V_2V1], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_S")>;2278 2279// Reduction, arithmetic, D form2280def : InstRW<[V3AEWrite_4c_2V], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_D")>;2281 2282// Reduction, logical2283def : InstRW<[V3AEWrite_6c_1V_1V1], (instregex "^(AND|EOR|OR)V_VPZ_[BHSD]")>;2284 2285// Reverse, vector2286def : InstRW<[V3AEWrite_2c_1V], (instregex "^REV_ZZ_[BHSD]",2287 "^REVB_ZPmZ_[HSD]",2288 "^REVH_ZPmZ_[SD]",2289 "^REVW_ZPmZ_D")>;2290 2291// Select, vector form2292def : InstRW<[V3AEWrite_2c_1V], (instregex "^SEL_ZPZZ_[BHSD]")>;2293 2294// Table lookup2295def : InstRW<[V3AEWrite_2c_1V], (instregex "^TBL_ZZZZ?_[BHSD]")>;2296 2297// Table lookup extension2298def : InstRW<[V3AEWrite_2c_1V], (instregex "^TBX_ZZZ_[BHSD]")>;2299 2300// Transpose, vector form2301def : InstRW<[V3AEWrite_2c_1V], (instregex "^TRN[12]_ZZZ_[BHSDQ]")>;2302 2303// Unpack and extend2304def : InstRW<[V3AEWrite_2c_1V], (instregex "^[SU]UNPK(HI|LO)_ZZ_[HSD]")>;2305 2306// Zip/unzip2307def : InstRW<[V3AEWrite_2c_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]")>;2308 2309// §3.26 SVE floating-point instructions2310// -----------------------------------------------------------------------------2311 2312// Floating point absolute value/difference2313def : InstRW<[V3AEWrite_2c_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]",2314 "^FABD_ZPZZ_[HSD]",2315 "^FABS_ZPmZ_[HSD]")>;2316 2317// Floating point arithmetic2318def : InstRW<[V3AEWrite_2c_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]",2319 "^F(ADD|SUB)_ZPZ[IZ]_[HSD]",2320 "^FADDP_ZPmZZ_[HSD]",2321 "^FNEG_ZPmZ_[HSD]",2322 "^FSUBR_ZPm[IZ]_[HSD]",2323 "^FSUBR_(ZPZI|ZPZZ)_[HSD]")>;2324 2325// Floating point associative add, F162326def : InstRW<[V3AEWrite_10c_1V1_9rc], (instrs FADDA_VPZ_H)>;2327 2328// Floating point associative add, F322329def : InstRW<[V3AEWrite_6c_1V1_5rc], (instrs FADDA_VPZ_S)>;2330 2331// Floating point associative add, F642332def : InstRW<[V3AEWrite_4c_1V], (instrs FADDA_VPZ_D)>;2333 2334// Floating point compare2335def : InstRW<[V3AEWrite_2c_1V0], (instregex "^FACG[ET]_PPzZZ_[HSD]",2336 "^FCM(EQ|GE|GT|NE)_PPzZ[0Z]_[HSD]",2337 "^FCM(LE|LT)_PPzZ0_[HSD]",2338 "^FCMUO_PPzZZ_[HSD]")>;2339 2340// Floating point complex add2341def : InstRW<[V3AEWrite_3c_1V], (instregex "^FCADD_ZPmZ_[HSD]")>;2342 2343// Floating point complex multiply add2344def : InstRW<[V3AEWr_ZFCMA, ReadDefault, V3AERd_ZFCMA], (instregex "^FCMLA_ZPmZZ_[HSD]")>;2345def : InstRW<[V3AEWr_ZFCMA, V3AERd_ZFCMA], (instregex "^FCMLA_ZZZI_[HS]")>;2346 2347// Floating point convert, long or narrow (F16 to F32 or F32 to F16)2348def : InstRW<[V3AEWrite_4c_2V0], (instregex "^FCVT_ZPmZ_(HtoS|StoH)",2349 "^FCVTLT_ZPmZ_HtoS",2350 "^FCVTNT_ZPmZ_StoH")>;2351 2352// Floating point convert, long or narrow (F16 to F64, F32 to F64, F64 to F322353// or F64 to F16)2354def : InstRW<[V3AEWrite_3c_1V0], (instregex "^FCVT_ZPmZ_(HtoD|StoD|DtoS|DtoH)",2355 "^FCVTLT_ZPmZ_StoD",2356 "^FCVTNT_ZPmZ_DtoS")>;2357 2358// Floating point convert, round to odd2359def : InstRW<[V3AEWrite_3c_1V0], (instrs FCVTX_ZPmZ_DtoS, FCVTXNT_ZPmZ_DtoS)>;2360 2361// Floating point base2 log, F162362def : InstRW<[V3AEWrite_6c_4V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_H")>;2363 2364// Floating point base2 log, F322365def : InstRW<[V3AEWrite_4c_2V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_S")>;2366 2367// Floating point base2 log, F642368def : InstRW<[V3AEWrite_3c_1V0], (instregex "^FLOGB_(ZPmZ|ZPZZ)_D")>;2369 2370// Floating point convert to integer, F162371def : InstRW<[V3AEWrite_6c_4V0], (instregex "^FCVTZ[SU]_ZPmZ_HtoH")>;2372 2373// Floating point convert to integer, F322374def : InstRW<[V3AEWrite_4c_2V0], (instregex "^FCVTZ[SU]_ZPmZ_(HtoS|StoS)")>;2375 2376// Floating point convert to integer, F642377def : InstRW<[V3AEWrite_3c_1V0],2378 (instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)")>;2379 2380// Floating point copy2381def : InstRW<[V3AEWrite_2c_1V], (instregex "^FCPY_ZPmI_[HSD]",2382 "^FDUP_ZI_[HSD]")>;2383 2384// Floating point divide, F162385def : InstRW<[V3AEWrite_13c_1V1_8rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_H")>;2386 2387// Floating point divide, F322388def : InstRW<[V3AEWrite_11c_1V1_4rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_S")>;2389 2390// Floating point divide, F642391def : InstRW<[V3AEWrite_14c_1V1_2rc], (instregex "^FDIVR?_(ZPmZ|ZPZZ)_D")>;2392 2393// Floating point min/max pairwise2394def : InstRW<[V3AEWrite_2c_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]")>;2395 2396// Floating point min/max2397def : InstRW<[V3AEWrite_2c_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]",2398 "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]")>;2399 2400// Floating point multiply2401def : InstRW<[V3AEWrite_3c_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]",2402 "^FMULX_ZPZZ_[HSD]",2403 "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]",2404 "^FMUL_ZPZ[IZ]_[HSD]")>;2405 2406// Floating point multiply accumulate2407def : InstRW<[V3AEWr_ZFMA, ReadDefault, V3AERd_ZFMA],2408 (instregex "^FN?ML[AS]_ZPmZZ_[HSD]",2409 "^FN?(MAD|MSB)_ZPmZZ_[HSD]")>;2410def : InstRW<[V3AEWr_ZFMA, V3AERd_ZFMA],2411 (instregex "^FML[AS]_ZZZI_[HSD]",2412 "^FN?ML[AS]_ZPZZZ_[HSD]")>;2413 2414// Floating point multiply add/sub accumulate long2415def : InstRW<[V3AEWr_ZFMAL, V3AERd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH")>;2416 2417// Floating point reciprocal estimate, F162418def : InstRW<[V3AEWrite_6c_4V0], (instregex "^FR(ECP|SQRT)E_ZZ_H", "^FRECPX_ZPmZ_H")>;2419 2420// Floating point reciprocal estimate, F322421def : InstRW<[V3AEWrite_4c_2V0], (instregex "^FR(ECP|SQRT)E_ZZ_S", "^FRECPX_ZPmZ_S")>;2422 2423// Floating point reciprocal estimate, F642424def : InstRW<[V3AEWrite_3c_1V0], (instregex "^FR(ECP|SQRT)E_ZZ_D", "^FRECPX_ZPmZ_D")>;2425 2426// Floating point reciprocal step2427def : InstRW<[V3AEWrite_4c_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]")>;2428 2429// Floating point reduction, F162430def : InstRW<[V3AEWrite_8c_4V],2431 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H")>;2432 2433// Floating point reduction, F322434def : InstRW<[V3AEWrite_6c_3V],2435 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S")>;2436 2437// Floating point reduction, F642438def : InstRW<[V3AEWrite_4c_2V],2439 (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D")>;2440 2441// Floating point round to integral, F162442def : InstRW<[V3AEWrite_6c_4V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;2443 2444// Floating point round to integral, F322445def : InstRW<[V3AEWrite_4c_2V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;2446 2447// Floating point round to integral, F642448def : InstRW<[V3AEWrite_3c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;2449 2450// Floating point square root, F162451def : InstRW<[V3AEWrite_13c_1V1_8rc], (instregex "^FSQRT_ZPmZ_H")>;2452 2453// Floating point square root, F322454def : InstRW<[V3AEWrite_11c_1V1_4rc], (instregex "^FSQRT_ZPmZ_S")>;2455 2456// Floating point square root, F642457def : InstRW<[V3AEWrite_14c_1V1_2rc], (instregex "^FSQRT_ZPmZ_D")>;2458 2459// Floating point trigonometric exponentiation2460def : InstRW<[V3AEWrite_3c_1V1], (instregex "^FEXPA_ZZ_[HSD]")>;2461 2462// Floating point trigonometric multiply add2463def : InstRW<[V3AEWrite_4c_1V], (instregex "^FTMAD_ZZI_[HSD]")>;2464 2465// Floating point trigonometric, miscellaneous2466def : InstRW<[V3AEWrite_3c_1V], (instregex "^FTS(MUL|SEL)_ZZZ_[HSD]")>;2467 2468// §3.27 SVE BFloat16 (BF16) instructions2469// -----------------------------------------------------------------------------2470 2471// Convert, F32 to BF162472def : InstRW<[V3AEWrite_4c_1V], (instrs BFCVT_ZPmZ, BFCVTNT_ZPmZ)>;2473 2474// Dot product2475def : InstRW<[V3AEWr_ZBFDOT, V3AERd_ZBFDOT], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;2476 2477// Matrix multiply accumulate2478def : InstRW<[V3AEWr_ZBFMMA, V3AERd_ZBFMMA], (instrs BFMMLA_ZZZ_HtoS)>;2479 2480// Multiply accumulate long2481def : InstRW<[V3AEWr_ZBFMAL, V3AERd_ZBFMAL], (instregex "^BFMLAL[BT]_ZZZI?")>;2482 2483// §3.28 SVE Load instructions2484// -----------------------------------------------------------------------------2485 2486// Load vector2487def : InstRW<[V3AEWrite_6c_1L], (instrs LDR_ZXI)>;2488 2489// Load predicate2490def : InstRW<[V3AEWrite_6c_1L_1M], (instrs LDR_PXI)>;2491 2492// Contiguous load, scalar + imm2493def : InstRW<[V3AEWrite_6c_1L], (instregex "^LD1[BHWD]_IMM$",2494 "^LD1S?B_[HSD]_IMM$",2495 "^LD1S?H_[SD]_IMM$",2496 "^LD1S?W_D_IMM$" )>;2497// Contiguous load, scalar + scalar2498def : InstRW<[V3AEWrite_6c_1L], (instregex "^LD1[BHWD]$",2499 "^LD1S?B_[HSD]$",2500 "^LD1S?H_[SD]$",2501 "^LD1S?W_D$" )>;2502 2503// Contiguous load broadcast, scalar + imm2504def : InstRW<[V3AEWrite_6c_1L], (instregex "^LD1R[BHWD]_IMM$",2505 "^LD1RS?B_[HSD]_IMM$",2506 "^LD1RS?H_[SD]_IMM$",2507 "^LD1RW_D_IMM$",2508 "^LD1RSW_IMM$",2509 "^LD1RQ_[BHWD]_IMM$")>;2510 2511// Contiguous load broadcast, scalar + scalar2512def : InstRW<[V3AEWrite_6c_1L], (instregex "^LD1RQ_[BHWD]$")>;2513 2514// Non temporal load, scalar + imm2515// Non temporal load, scalar + scalar2516def : InstRW<[V3AEWrite_6c_1L], (instregex "^LDNT1[BHWD]_ZR[IR]$")>;2517 2518// Non temporal gather load, vector + scalar 32-bit element size2519def : InstRW<[V3AEWrite_9c_2L_4V], (instregex "^LDNT1[BHW]_ZZR_S$",2520 "^LDNT1S[BH]_ZZR_S$")>;2521 2522// Non temporal gather load, vector + scalar 64-bit element size2523def : InstRW<[V3AEWrite_9c_2L_2V], (instregex "^LDNT1S?[BHW]_ZZR_D$")>;2524def : InstRW<[V3AEWrite_9c_2L_2V], (instrs LDNT1D_ZZR_D)>;2525 2526// Contiguous first faulting load, scalar + scalar2527def : InstRW<[V3AEWrite_6c_1L_1I], (instregex "^LDFF1[BHWD]$",2528 "^LDFF1S?B_[HSD]$",2529 "^LDFF1S?H_[SD]$",2530 "^LDFF1S?W_D$")>;2531 2532// Contiguous non faulting load, scalar + imm2533def : InstRW<[V3AEWrite_6c_1L], (instregex "^LDNF1[BHWD]_IMM$",2534 "^LDNF1S?B_[HSD]_IMM$",2535 "^LDNF1S?H_[SD]_IMM$",2536 "^LDNF1S?W_D_IMM$")>;2537 2538// Contiguous Load two structures to two vectors, scalar + imm2539def : InstRW<[V3AEWrite_8c_2L_2V], (instregex "^LD2[BHWD]_IMM$")>;2540 2541// Contiguous Load two structures to two vectors, scalar + scalar2542def : InstRW<[V3AEWrite_9c_2L_2V_2I], (instregex "^LD2[BHWD]$")>;2543 2544// Contiguous Load three structures to three vectors, scalar + imm2545def : InstRW<[V3AEWrite_9c_3L_3V], (instregex "^LD3[BHWD]_IMM$")>;2546 2547// Contiguous Load three structures to three vectors, scalar + scalar2548def : InstRW<[V3AEWrite_10c_3V_3L_3I], (instregex "^LD3[BHWD]$")>;2549 2550// Contiguous Load four structures to four vectors, scalar + imm2551def : InstRW<[V3AEWrite_9c_4L_8V], (instregex "^LD4[BHWD]_IMM$")>;2552 2553// Contiguous Load four structures to four vectors, scalar + scalar2554def : InstRW<[V3AEWrite_10c_4L_8V_4I], (instregex "^LD4[BHWD]$")>;2555 2556// Gather load, vector + imm, 32-bit element size2557def : InstRW<[V3AEWrite_9c_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",2558 "^GLD(FF)?1W_IMM$")>;2559 2560// Gather load, vector + imm, 64-bit element size2561def : InstRW<[V3AEWrite_9c_1L_4V], (instregex "^GLD(FF)?1S?[BHW]_D_IMM$",2562 "^GLD(FF)?1D_IMM$")>;2563 2564// Gather load, 32-bit scaled offset2565def : InstRW<[V3AEWrite_10c_1L_8V],2566 (instregex "^GLD(FF)?1S?H_S_[SU]XTW_SCALED$",2567 "^GLD(FF)?1W_[SU]XTW_SCALED")>;2568 2569// Gather load, 64-bit scaled offset2570// NOTE: These instructions are not specified in the SOG.2571def : InstRW<[V3AEWrite_10c_1L_4V],2572 (instregex "^GLD(FF)?1S?[HW]_D_([SU]XTW_)?SCALED$",2573 "^GLD(FF)?1D_([SU]XTW_)?SCALED$")>;2574 2575// Gather load, 32-bit unpacked unscaled offset2576def : InstRW<[V3AEWrite_9c_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",2577 "^GLD(FF)?1W_[SU]XTW$")>;2578 2579// Gather load, 64-bit unpacked unscaled offset2580// NOTE: These instructions are not specified in the SOG.2581def : InstRW<[V3AEWrite_9c_1L_2V],2582 (instregex "^GLD(FF)?1S?[BHW]_D(_[SU]XTW)?$",2583 "^GLD(FF)?1D(_[SU]XTW)?$")>;2584 2585// §3.29 SVE Store instructions2586// -----------------------------------------------------------------------------2587 2588// Store from predicate reg2589def : InstRW<[V3AEWrite_1c_1SA], (instrs STR_PXI)>;2590 2591// Store from vector reg2592def : InstRW<[V3AEWrite_2c_1SA_1V], (instrs STR_ZXI)>;2593 2594// Contiguous store, scalar + imm2595def : InstRW<[V3AEWrite_2c_1SA_1V], (instregex "^ST1[BHWD]_IMM$",2596 "^ST1B_[HSD]_IMM$",2597 "^ST1H_[SD]_IMM$",2598 "^ST1W_D_IMM$")>;2599 2600// Contiguous store, scalar + scalar2601def : InstRW<[V3AEWrite_2c_1SA_1I_1V], (instregex "^ST1H(_[SD])?$")>;2602def : InstRW<[V3AEWrite_2c_1SA_1V], (instregex "^ST1[BWD]$",2603 "^ST1B_[HSD]$",2604 "^ST1W_D$")>;2605 2606// Contiguous store two structures from two vectors, scalar + imm2607def : InstRW<[V3AEWrite_4c_1SA_1V], (instregex "^ST2[BHWD]_IMM$")>;2608 2609// Contiguous store two structures from two vectors, scalar + scalar2610def : InstRW<[V3AEWrite_4c_2SA_2I_2V], (instrs ST2H)>;2611def : InstRW<[V3AEWrite_4c_2SA_2V], (instregex "^ST2[BWD]$")>;2612 2613// Contiguous store three structures from three vectors, scalar + imm2614def : InstRW<[V3AEWrite_7c_9SA_9V], (instregex "^ST3[BHWD]_IMM$")>;2615 2616// Contiguous store three structures from three vectors, scalar + scalar2617def : InstRW<[V3AEWrite_7c_9SA_9I_9V], (instregex "^ST3[BHWD]$")>;2618 2619// Contiguous store four structures from four vectors, scalar + imm2620def : InstRW<[V3AEWrite_11c_18SA_18V], (instregex "^ST4[BHWD]_IMM$")>;2621 2622// Contiguous store four structures from four vectors, scalar + scalar2623def : InstRW<[V3AEWrite_11c_18SA_18I_18V], (instregex "^ST4[BHWD]$")>;2624 2625// Non temporal store, scalar + imm2626def : InstRW<[V3AEWrite_2c_1SA_1V], (instregex "^STNT1[BHWD]_ZRI$")>;2627 2628// Non temporal store, scalar + scalar2629def : InstRW<[V3AEWrite_2c_1SA_1I_1V], (instrs STNT1H_ZRR)>;2630def : InstRW<[V3AEWrite_2c_1SA_1V], (instregex "^STNT1[BWD]_ZRR$")>;2631 2632// Scatter non temporal store, vector + scalar 32-bit element size2633def : InstRW<[V3AEWrite_4c_4SA_4V], (instregex "^STNT1[BHW]_ZZR_S")>;2634 2635// Scatter non temporal store, vector + scalar 64-bit element size2636def : InstRW<[V3AEWrite_2c_2SA_2V], (instregex "^STNT1[BHWD]_ZZR_D")>;2637 2638// Scatter store vector + imm 32-bit element size2639def : InstRW<[V3AEWrite_4c_4SA_4V], (instregex "^SST1[BH]_S_IMM$",2640 "^SST1W_IMM$")>;2641 2642// Scatter store vector + imm 64-bit element size2643def : InstRW<[V3AEWrite_2c_2SA_2V], (instregex "^SST1[BHW]_D_IMM$",2644 "^SST1D_IMM$")>;2645 2646// Scatter store, 32-bit scaled offset2647def : InstRW<[V3AEWrite_4c_4SA_4V],2648 (instregex "^SST1(H_S|W)_[SU]XTW_SCALED$")>;2649 2650// Scatter store, 32-bit unpacked unscaled offset2651def : InstRW<[V3AEWrite_2c_2SA_2V], (instregex "^SST1[BHW]_D_[SU]XTW$",2652 "^SST1D_[SU]XTW$")>;2653 2654// Scatter store, 32-bit unpacked scaled offset2655def : InstRW<[V3AEWrite_2c_2SA_2V], (instregex "^SST1[HW]_D_[SU]XTW_SCALED$",2656 "^SST1D_[SU]XTW_SCALED$")>;2657 2658// Scatter store, 32-bit unscaled offset2659def : InstRW<[V3AEWrite_4c_4SA_4V], (instregex "^SST1[BH]_S_[SU]XTW$",2660 "^SST1W_[SU]XTW$")>;2661 2662// Scatter store, 64-bit scaled offset2663def : InstRW<[V3AEWrite_2c_2SA_2V], (instregex "^SST1[HW]_D_SCALED$",2664 "^SST1D_SCALED$")>;2665 2666// Scatter store, 64-bit unscaled offset2667def : InstRW<[V3AEWrite_2c_2SA_2V], (instregex "^SST1[BHW]_D$",2668 "^SST1D$")>;2669 2670// §3.30 SVE Miscellaneous instructions2671// -----------------------------------------------------------------------------2672 2673// Read first fault register, unpredicated2674def : InstRW<[V3AEWrite_2c_1M0], (instrs RDFFR_P)>;2675 2676// Read first fault register, predicated2677def : InstRW<[V3AEWrite_3or4c_1M0_1M], (instrs RDFFR_PPz)>;2678 2679// Read first fault register and set flags2680def : InstRW<[V3AEWrite_3or4c_1M0_1M], (instrs RDFFRS_PPz)>;2681 2682// Set first fault register2683// Write to first fault register2684def : InstRW<[V3AEWrite_2c_1M0], (instrs SETFFR, WRFFR)>;2685 2686// Prefetch2687// NOTE: This is not specified in the SOG.2688def : InstRW<[V3AEWrite_4c_1L], (instregex "^PRF[BHWD]")>;2689 2690// §3.31 SVE Cryptographic instructions2691// -----------------------------------------------------------------------------2692 2693// Crypto AES ops2694def : InstRW<[V3AEWrite_2c_1V], (instregex "^AES[DE]_ZZZ_B$",2695 "^AESI?MC_ZZ_B$")>;2696 2697// Crypto SHA3 ops2698def : InstRW<[V3AEWrite_2c_1V], (instregex "^(BCAX|EOR3)_ZZZZ$",2699 "^RAX1_ZZZ_D$",2700 "^XAR_ZZZI_[BHSD]$")>;2701 2702// Crypto SM4 ops2703def : InstRW<[V3AEWrite_4c_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;2704 2705}2706