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1//===- AArch64SchedPredNeoverse.td - AArch64 Sched Preds -----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines scheduling predicate definitions that are used by the10// AArch64 Neoverse processors.11//12//===----------------------------------------------------------------------===//13 14// Auxiliary predicates.15 16// Check for LSL shift == 017def NeoverseNoLSL : MCSchedPredicate<18 CheckAll<[CheckShiftLSL,19 CheckShiftBy0]>>;20 21// Identify LDR/STR H/Q-form scaled (and potentially extended) FP instructions22def NeoverseHQForm : MCSchedPredicate<23 CheckAll<[24 CheckAny<[CheckHForm, CheckQForm]>,25 CheckImmOperand<4, 1>]>>;26 27// Check if <Pd> == <Pg>28def NeoversePdIsPgFn : TIIPredicate<29 "isNeoversePdSameAsPg",30 MCOpcodeSwitchStatement<31 [MCOpcodeSwitchCase<[BRKA_PPmP, BRKB_PPmP],32 MCReturnStatement<CheckSameRegOperand<1, 2>>>],33 MCReturnStatement<CheckSameRegOperand<0, 1>>>>;34def NeoversePdIsPg : MCSchedPredicate<NeoversePdIsPgFn>;35 36// Check if SVE INC/DEC (scalar), ALL, {1, 2, 4}37def NeoverseCheapIncDec : MCSchedPredicate<38 CheckAll<[CheckOpcode<[39 INCB_XPiI, INCH_XPiI,40 INCW_XPiI, INCD_XPiI,41 DECB_XPiI, DECH_XPiI,42 DECW_XPiI, DECD_XPiI]>,43 CheckImmOperand<2, 31>,44 CheckAny<[45 CheckImmOperand<3, 1>,46 CheckImmOperand<3, 2>,47 CheckImmOperand<3, 4>]>]>>;48 49// Identify "[SU]?(MADD|MSUB)L?" as the alias for "[SU]?(MUL|MNEG)L?".50def NeoverseMULIdiomPred : MCSchedPredicate< // <op> Rd, Rs, Rv, ZR51 CheckAll<[CheckOpcode<52 [MADDWrrr, MADDXrrr,53 MSUBWrrr, MSUBXrrr,54 SMADDLrrr, UMADDLrrr,55 SMSUBLrrr, UMSUBLrrr]>,56 CheckIsReg3Zero]>>;57 58def NeoverseZeroMove : MCSchedPredicate<59 CheckAny<[60 // MOV Wd, #061 // MOV Xd, #062 CheckAll<[CheckOpcode<[MOVZWi, MOVZXi]>,63 CheckIsImmOperand<1>,64 CheckImmOperand<1, 0>,65 CheckImmOperand<2, 0>]>,66 // MOV Wd, WZR67 // MOV Xd, XZR68 // MOV Wd, Wn69 // MOV Xd, Xn70 CheckAll<[CheckOpcode<[ORRWrs, ORRXrs]>,71 CheckAll<[CheckIsReg1Zero,72 CheckImmOperand<3, 0>]>]>,73 // FMOV Hd, WZR74 // FMOV Hd, XZR75 // FMOV Sd, WZR76 // FMOV Dd, XZR77 CheckAll<[CheckOpcode<[FMOVWHr, FMOVXHr,78 FMOVWSr, FMOVXDr]>,79 CheckIsReg1Zero]>,80 // MOVI Dd, #081 // MOVI Vd.2D, #082 CheckAll<[CheckOpcode<[MOVID, MOVIv2d_ns]>,83 CheckImmOperand<1, 0>]>,84 // MOV Zd, Zn85 CheckAll<[CheckOpcode<[ORR_ZZZ]>,86 CheckSameRegOperand<1, 2>]>,87 // MOV Vd, Vn88 CheckAll<[CheckOpcode<[ORRv16i8, ORRv8i8]>,89 CheckSameRegOperand<1, 2>]>,90 ]>>;91 92def NeoverseAllActivePredicate : MCSchedPredicate<93 CheckAny<[94 // PTRUE Pd, ALL95 // PTRUES Pd, ALL96 CheckAll<[97 CheckOpcode<[98 PTRUE_B, PTRUE_H, PTRUE_S, PTRUE_D,99 PTRUES_B, PTRUES_H, PTRUES_S, PTRUES_D]>,100 CheckIsImmOperand<1>,101 CheckImmOperand<1, 31>]>,102 ]>>;103