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1//=- AArch64SchedThunderX3T110.td - Marvell ThunderX3 T110 ---*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the scheduling model for Marvell ThunderX3T11010// family of processors.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// Pipeline Description.16 17def ThunderX3T110Model : SchedMachineModel {18 let IssueWidth = 4; // 4 micro-ops dispatched at a time.19 let MicroOpBufferSize = 70; // 70 entries in micro-op re-order buffer.20 let LoadLatency = 4; // Optimistic load latency.21 let MispredictPenalty = 12; // Extra cycles for mispredicted branch.22 // Determined via a mix of micro-arch details and experimentation.23 let LoopMicroOpBufferSize = 128; // FIXME: might be much bigger in TX3.24 let PostRAScheduler = 1; // Using PostRA sched.25 let CompleteModel = 1;26 27 list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,28 PAUnsupported.F,29 SMEUnsupported.F,30 [HasMTE, HasCSSC]);31 // FIXME: Remove when all errors have been fixed.32 let FullInstRWOverlapCheck = 0;33}34 35let SchedModel = ThunderX3T110Model in {36 37// Issue ports.38 39// Port 0: ALU.40def THX3T110P0 : ProcResource<1>;41 42// Port 1: ALU.43def THX3T110P1 : ProcResource<1>;44 45// Port 2: ALU/Branch.46def THX3T110P2 : ProcResource<1>;47 48// Port 3: ALU/Branch.49def THX3T110P3 : ProcResource<1>;50 51// Port 4: Load/Store.52def THX3T110P4 : ProcResource<1>;53 54// Port 5: Load/store.55def THX3T110P5 : ProcResource<1>;56 57// Port 6: FP/Neon/SIMD/Crypto.58def THX3T110P6FP0 : ProcResource<1>;59 60// Port 7: FP/Neon/SIMD/Crypto.61def THX3T110P7FP1 : ProcResource<1>;62 63// Port 8: FP/Neon/SIMD/Crypto.64def THX3T110P8FP2 : ProcResource<1>;65 66// Port 9: FP/Neon/SIMD/Crypto.67def THX3T110P9FP3 : ProcResource<1>;68 69// Port 10: Store Data Unit.70def THX3T110SD0 : ProcResource<1>;71 72// Define groups for the functional units on each issue port. Each group73// created will be used by a WriteRes.74 75// Integer divide/mulhi micro-ops only on port I1.76def THX3T110I1 : ProcResGroup<[THX3T110P1]>;77 78// Branch micro-ops on ports I2/I3.79def THX3T110I23 : ProcResGroup<[THX3T110P2, THX3T110P3]>;80 81// Branch micro-ops on ports I1/I2/I3.82def THX3T110I123 : ProcResGroup<[THX3T110P1, THX3T110P2, THX3T110P3]>;83 84// Integer micro-ops on ports I0/I1/I2.85def THX3T110I012 : ProcResGroup<[THX3T110P0, THX3T110P1, THX3T110P2]>;86 87// Integer micro-ops on ports I0/I1/I2/I3.88def THX3T110I0123 : ProcResGroup<[THX3T110P0, THX3T110P1,89 THX3T110P2, THX3T110P3]>;90 91// FP micro-ops on ports FP0/FP1/FP2/FP3.92def THX3T110FP0123 : ProcResGroup<[THX3T110P6FP0, THX3T110P7FP1,93 THX3T110P8FP2, THX3T110P9FP3]>;94 95// FP micro-ops on ports FP2/FP3.96def THX3T110FP23 : ProcResGroup<[THX3T110P8FP2, THX3T110P9FP3]>;97 98// ASIMD micro-ops on ports FP0/FP1/FP2/FP3.99def THX3T110SIMD : ProcResGroup<[THX3T110P6FP0, THX3T110P7FP1,100 THX3T110P8FP2, THX3T110P9FP3]>;101 102// Store data micro-ops only on port 10.103def THX3T110SD : ProcResGroup<[THX3T110SD0]>;104 105// Load/store micro-ops on ports P4/P5.106def THX3T110LS : ProcResGroup<[THX3T110P4, THX3T110P5]>;107 108// 70 entry unified scheduler.109def THX3T110ANY: ProcResGroup<[THX3T110P0, THX3T110P1, THX3T110P2,110 THX3T110P3, THX3T110P4, THX3T110P5,111 THX3T110P6FP0, THX3T110P7FP1,112 THX3T110P8FP2, THX3T110P9FP3]> {113 let BufferSize = 70;114}115 116// Define commonly used write types for InstRW specializations.117// All definitions follow the format: THX3T110Write_<NumCycles>Cyc_<Resources>.118 119// 3 cycles on I1.120def THX3T110Write_3Cyc_I1 : SchedWriteRes<[THX3T110I1]> {121 let Latency = 3;122 let NumMicroOps = 2;123}124 125// 4 cycles on I1.126def THX3T110Write_4Cyc_I1 : SchedWriteRes<[THX3T110I1]> {127 let Latency = 4;128 let NumMicroOps = 2;129}130 131// 5 cycles on I1.132def THX3T110Write_5Cyc_I1 : SchedWriteRes<[THX3T110I1]> {133 let Latency = 5;134 let NumMicroOps = 2;135}136 137// 7 cycles on I1.138def THX3T110Write_7Cyc_I1 : SchedWriteRes<[THX3T110I1]> {139 let Latency = 7;140 let NumMicroOps = 3;141}142 143// 23 cycles on I1.144def THX3T110Write_23Cyc_I1 : SchedWriteRes<[THX3T110I1]> {145 let Latency = 23;146 let ReleaseAtCycles = [13, 23];147 let NumMicroOps = 4;148}149 150// 39 cycles on I1.151def THX3T110Write_39Cyc_I1 : SchedWriteRes<[THX3T110I1]> {152 let Latency = 39;153 let ReleaseAtCycles = [13, 39];154 let NumMicroOps = 4;155}156 157// 1 cycle on I2/I3158def THX3T110Write_1Cyc_I23 : SchedWriteRes<[THX3T110I23]> {159 let Latency = 1;160 let NumMicroOps = 2;161}162 163// 8 cycles on I2/I3164def THX3T110Write_8Cyc_I23 : SchedWriteRes<[THX3T110I23]> {165 let Latency = 8;166 let NumMicroOps = 3;167}168 169// 1 cycle on I1/I2/I3170def THX3T110Write_1Cyc_I123 : SchedWriteRes<[THX3T110I123]> {171 let Latency = 1;172 let NumMicroOps = 2;173}174 175// 8 cycles on I1/I2/I3176def THX3T110Write_8Cyc_I123 : SchedWriteRes<[THX3T110I123]> {177 let Latency = 8;178 let NumMicroOps = 3;179}180 181// 1 cycle on I0/I1/I2/I3.182def THX3T110Write_1Cyc_I0123 : SchedWriteRes<[THX3T110I0123]> {183 let Latency = 1;184 let NumMicroOps = 2;185}186 187// 2 cycles on I0/I1/I2/I3.188def THX3T110Write_2Cyc_I0123 : SchedWriteRes<[THX3T110I0123]> {189 let Latency = 2;190 let NumMicroOps = 2;191}192 193// 3 cycles on I0/I1/I2/I3.194def THX3T110Write_3Cyc_I0123 : SchedWriteRes<[THX3T110I0123]> {195 let Latency = 3;196 let NumMicroOps = 2;197}198 199// 4 cycles on I0/I1/I2/I3.200def THX3T110Write_4Cyc_I0123 : SchedWriteRes<[THX3T110I0123]> {201 let Latency = 4;202 let NumMicroOps = 3;203}204 205// 5 cycles on I0/I1/I2/I3.206def THX3T110Write_5Cyc_I0123 : SchedWriteRes<[THX3T110I0123]> {207 let Latency = 5;208 let NumMicroOps = 3;209}210 211// 6 cycles on I0/I1/I2/I3.212def THX3T110Write_6Cyc_I0123 : SchedWriteRes<[THX3T110I0123]> {213 let Latency = 6;214 let NumMicroOps = 3;215}216 217// 8 cycles on I0/I1/I2/I3.218def THX3T110Write_8Cyc_I0123 : SchedWriteRes<[THX3T110I0123]> {219 let Latency = 8;220 let NumMicroOps = 4;221}222 223// 13 cycles on I0/I1/I2/I3.224def THX3T110Write_13Cyc_I0123 : SchedWriteRes<[THX3T110I0123]> {225 let Latency = 13;226 let NumMicroOps = 3;227}228 229// 23 cycles on I0/I1/I2/I3.230def THX3T110Write_23Cyc_I0123 : SchedWriteRes<[THX3T110I0123]> {231 let Latency = 23;232 let NumMicroOps = 3;233}234 235// 39 cycles on I0/I1/I2/I3.236def THX3T110Write_39Cyc_I0123 : SchedWriteRes<[THX3T110I0123]> {237 let Latency = 39;238 let NumMicroOps = 3;239}240 241// 4 cycles on F2/F3.242def THX3T110Write_4Cyc_F23 : SchedWriteRes<[THX3T110FP23]> {243 let Latency = 4;244 let NumMicroOps = 2;245}246 247// 5 cycles on F0/F1/F2/F3.248def THX3T110Write_5Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {249 let Latency = 5;250 let NumMicroOps = 2;251}252 253// 6 cycles on F0/F1/F2/F3.254def THX3T110Write_6Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {255 let Latency = 6;256 let NumMicroOps = 3;257}258 259// 7 cycles on F0/F1/F2/F3.260def THX3T110Write_7Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {261 let Latency = 7;262 let NumMicroOps = 3;263}264 265// 8 cycles on F0/F1/F2/F3.266def THX3T110Write_8Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {267 let Latency = 8;268 let NumMicroOps = 3;269}270 271// 10 cycles on F0/F1/F2/F3.272def THX3T110Write_10Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {273 let Latency = 10;274 let NumMicroOps = 3;275}276 277// 16 cycles on F0/F1/F2/F3.278def THX3T110Write_16Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {279 let Latency = 16;280 let NumMicroOps = 3;281 let ReleaseAtCycles = [8];282}283 284// 23 cycles on F0/F1/F2/F3.285def THX3T110Write_23Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {286 let Latency = 23;287 let NumMicroOps = 3;288 let ReleaseAtCycles = [11];289}290 291// 1 cycle on LS0/LS1.292def THX3T110Write_1Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {293 let Latency = 1;294 let NumMicroOps = 1;295}296 297// 2 cycles on LS0/LS1.298def THX3T110Write_2Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {299 let Latency = 2;300 let NumMicroOps = 2;301}302 303// 4 cycles on LS0/LS1.304def THX3T110Write_4Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {305 let Latency = 4;306 let NumMicroOps = 2;307 let ReleaseAtCycles = [2];308}309 310// 5 cycles on LS0/LS1.311def THX3T110Write_5Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {312 let Latency = 5;313 let NumMicroOps = 3;314}315 316// 6 cycles on LS0/LS1.317def THX3T110Write_6Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {318 let Latency = 6;319 let NumMicroOps = 3;320}321 322// 4 + 5 cycles on LS0/LS1.323// First resource is available after 4 cycles.324// Second resource is available after 5 cycles.325// Load vector pair, immed offset, Q-form [LDP/LDNP].326def THX3T110Write_4_5Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {327 let Latency = 4;328 let NumMicroOps = 2;329 let ReleaseAtCycles = [4, 5];330}331 332// 4 + 8 cycles on LS0/LS1.333// First resource is available after 4 cycles.334// Second resource is available after 8 cycles.335// Load vector pair, immed offset, S/D-form [LDP/LDNP].336def THX3T110Write_4_8Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {337 let Latency = 4;338 let NumMicroOps = 2;339 let ReleaseAtCycles = [4, 8];340}341 342// 11 cycles on LS0/LS1 and I1.343def THX3T110Write_11Cyc_LS01_I1 :344 SchedWriteRes<[THX3T110LS, THX3T110I1]> {345 let Latency = 11;346 let NumMicroOps = 4;347}348 349// 1 cycles on LS0/LS1 and I0/I1/I2/I3.350def THX3T110Write_1Cyc_LS01_I0123 :351 SchedWriteRes<[THX3T110LS, THX3T110I0123]> {352 let Latency = 1;353 let NumMicroOps = 2;354}355 356// 1 cycles on LS0/LS1 and 2 of I0/I1/I2/I3.357def THX3T110Write_1Cyc_LS01_I0123_I0123 :358 SchedWriteRes<[THX3T110LS, THX3T110I0123, THX3T110I0123]> {359 let Latency = 1;360 let NumMicroOps = 3;361}362 363// 4 cycles on LS0/LS1 and I0/I1/I2/I3.364def THX3T110Write_4Cyc_LS01_I0123 :365 SchedWriteRes<[THX3T110LS, THX3T110I0123]> {366 let Latency = 4;367 let NumMicroOps = 3;368}369 370// 4 cycles on LS0/LS1 and 2 of I0/I1/I2/I3.371def THX3T110Write_4Cyc_LS01_I0123_I0123 :372 SchedWriteRes<[THX3T110LS, THX3T110I0123, THX3T110I0123]> {373 let Latency = 4;374 let NumMicroOps = 3;375}376 377// 5 cycles on LS0/LS1 and I0/I1/I2/I3.378def THX3T110Write_5Cyc_LS01_I0123 :379 SchedWriteRes<[THX3T110LS, THX3T110I0123]> {380 let Latency = 5;381 let NumMicroOps = 3;382}383 384// 5 cycles on LS0/LS1 and 2 of I0/I1/I2/I3.385def THX3T110Write_5Cyc_LS01_I0123_I0123 :386 SchedWriteRes<[THX3T110LS, THX3T110I0123, THX3T110I0123]> {387 let Latency = 5;388 let NumMicroOps = 3;389}390 391// 6 cycles on LS0/LS1 and I0/I1/I2/I3.392def THX3T110Write_6Cyc_LS01_I012 :393 SchedWriteRes<[THX3T110LS, THX3T110I0123]> {394 let Latency = 6;395 let NumMicroOps = 4;396}397 398// 6 cycles on LS0/LS1 and 2 of I0/I1/I2/I3.399def THX3T110Write_6Cyc_LS01_I0123_I0123 :400 SchedWriteRes<[THX3T110LS, THX3T110I0123, THX3T110I0123]> {401 let Latency = 6;402 let NumMicroOps = 3;403}404 405// 1 cycle on LS0/LS1 and SD.406def THX3T110Write_1Cyc_LS01_SD :407 SchedWriteRes<[THX3T110LS, THX3T110SD]> {408 let Latency = 1;409 let NumMicroOps = 2;410}411 412// 2 cycles on LS0/LS1 and SD.413def THX3T110Write_2Cyc_LS01_SD :414 SchedWriteRes<[THX3T110LS, THX3T110SD]> {415 let Latency = 2;416 let NumMicroOps = 2;417}418 419// 4 cycles on LS0/LS1 and SD.420def THX3T110Write_4Cyc_LS01_SD :421 SchedWriteRes<[THX3T110LS, THX3T110SD]> {422 let Latency = 4;423 let NumMicroOps = 3;424}425 426// 5 cycles on LS0/LS1 and SD.427def THX3T110Write_5Cyc_LS01_SD :428 SchedWriteRes<[THX3T110LS, THX3T110SD]> {429 let Latency = 5;430 let NumMicroOps = 4;431}432 433// 6 cycles on LS0/LS1 and SD.434def THX3T110Write_6Cyc_LS01_SD :435 SchedWriteRes<[THX3T110LS, THX3T110SD]> {436 let Latency = 6;437 let NumMicroOps = 5;438}439 440// 1 cycle on LS0/LS1, SD and I0/I1/I2/I3.441def THX3T110Write_1Cyc_LS01_SD_I0123 :442 SchedWriteRes<[THX3T110LS, THX3T110SD, THX3T110I0123]> {443 let Latency = 1;444 let NumMicroOps = 2;445}446 447// 2 cycles on LS0/LS1, SD and I0/I1/I2/I3.448def THX3T110Write_2Cyc_LS01_SD_I0123 :449 SchedWriteRes<[THX3T110LS, THX3T110SD, THX3T110I0123]> {450 let Latency = 2;451 let NumMicroOps = 2;452}453 454// 4 cycles on LS0/LS1, SD and I0/I1/I2/I3.455def THX3T110Write_4Cyc_LS01_SD_I0123 :456 SchedWriteRes<[THX3T110LS, THX3T110SD, THX3T110I0123]> {457 let Latency = 4;458 let NumMicroOps = 3;459}460 461// 5 cycles on LS0/LS1, SD and I0/I1/I2/I3.462def THX3T110Write_5Cyc_LS01_SD_I0123 :463 SchedWriteRes<[THX3T110LS, THX3T110SD, THX3T110I0123]> {464 let Latency = 5;465 let NumMicroOps = 4;466}467 468// 6 cycles on LS0/LS1, SD and I0/I1/I2/I3.469def THX3T110Write_6Cyc_LS01_SD_I0123 :470 SchedWriteRes<[THX3T110LS, THX3T110SD, THX3T110I0123]> {471 let Latency = 6;472 let NumMicroOps = 5;473}474 475// 1 cycles on LS0/LS1 and F0/F1/F2/F3.476def THX3T110Write_1Cyc_LS01_F0123 :477 SchedWriteRes<[THX3T110LS, THX3T110FP0123]> {478 let Latency = 1;479 let NumMicroOps = 2;480}481 482// 5 cycles on LS0/LS1 and F0/F1/F2/F3.483def THX3T110Write_5Cyc_LS01_F0123 :484 SchedWriteRes<[THX3T110LS, THX3T110FP0123]> {485 let Latency = 5;486 let NumMicroOps = 3;487}488 489// 6 cycles on LS0/LS1 and F0/F1/F2/F3.490def THX3T110Write_6Cyc_LS01_F0123 :491 SchedWriteRes<[THX3T110LS, THX3T110FP0123]> {492 let Latency = 6;493 let NumMicroOps = 3;494}495 496// 7 cycles on LS0/LS1 and F0/F1/F2/F3.497def THX3T110Write_7Cyc_LS01_F0123 :498 SchedWriteRes<[THX3T110LS, THX3T110FP0123]> {499 let Latency = 7;500 let NumMicroOps = 3;501}502 503// 8 cycles on LS0/LS1 and F0/F1/F2/F3.504def THX3T110Write_8Cyc_LS01_F0123 :505 SchedWriteRes<[THX3T110LS, THX3T110FP0123]> {506 let Latency = 8;507 let NumMicroOps = 3;508}509 510// 8 cycles on LS0/LS1 and I0/I1/I2/I3.511def THX3T110Write_8Cyc_LS01_I0123 :512 SchedWriteRes<[THX3T110LS, THX3T110I0123]> {513 let Latency = 8;514 let NumMicroOps = 3;515}516 517// 12 cycles on LS0/LS1 and I0/I1/I2/I3.518def THX3T110Write_12Cyc_LS01_I0123 :519 SchedWriteRes<[THX3T110LS, THX3T110I0123]> {520 let Latency = 12;521 let NumMicroOps = 4;522}523 524// 16 cycles on LS0/LS1 and I0/I1/I2/I3.525def THX3T110Write_16Cyc_LS01_I0123 :526 SchedWriteRes<[THX3T110LS, THX3T110I0123]> {527 let Latency = 16;528 let NumMicroOps = 5;529}530 531// 24 cycles on LS0/LS1 and I0/I1/I2/I3.532def THX3T110Write_24Cyc_LS01_I0123 :533 SchedWriteRes<[THX3T110LS, THX3T110I0123]> {534 let Latency = 24;535 let NumMicroOps = 10;536}537 538// 32 cycles on LS0/LS1 and I0/I1/I2/I3.539def THX3T110Write_32Cyc_LS01_I0123 :540 SchedWriteRes<[THX3T110LS, THX3T110I0123]> {541 let Latency = 32;542 let NumMicroOps = 14;543}544 545// 3 cycles on F0/F1/F2/F3.546def THX3T110Write_3Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {547 let Latency = 3;548 let NumMicroOps = 2;549}550 551// 4 cycles on F0/F1/F2/F3.552def THX3T110Write_4Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {553 let Latency = 4;554 let NumMicroOps = 2;555}556 557// 5 cycles on F0/F1/F2/F3.558def THX3T110Write_5Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {559 let Latency = 5;560 let NumMicroOps = 2;561}562 563// 10 cycles on F0/F1/F2/F3.564def THX3T110Write_10Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {565 let Latency = 10;566 let NumMicroOps = 4;567}568 569// 15 cycles on F0/F1/F2/F3.570def THX3T110Write_15Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {571 let Latency = 15;572 let NumMicroOps = 7;573}574 575// 16 cycles on F0/F1/F2/F3.576def THX3T110Write_16Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {577 let Latency = 16;578 let NumMicroOps = 3;579}580 581// 18 cycles on F0/F1/F2/F3.582def THX3T110Write_18Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {583 let Latency = 18;584 let NumMicroOps = 3;585}586 587// 19 cycles on F0/F1/F2/F3.588def THX3T110Write_19Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {589 let Latency = 19;590 let NumMicroOps = 4;591}592 593// 20 cycles on F0/F1/F2/F3.594def THX3T110Write_20Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {595 let Latency = 20;596 let NumMicroOps = 4;597}598 599// 23 cycles on F0/F1/F2/F3.600def THX3T110Write_23Cyc_F0123 : SchedWriteRes<[THX3T110FP0123]> {601 let Latency = 23;602 let NumMicroOps = 4;603}604 605// 3 cycles on F2/F3 and 4 cycles on F0/F1/F2/F3.606def THX3T110Write_3_4Cyc_F23_F0123 :607 SchedWriteRes<[THX3T110FP23, THX3T110FP0123]> {608 let Latency = 3;609 let NumMicroOps = 2;610 let ReleaseAtCycles = [3, 4];611}612 613 614// Define commonly used read types.615 616// No forwarding is provided for these types.617def : ReadAdvance<ReadI, 0>;618def : ReadAdvance<ReadISReg, 0>;619def : ReadAdvance<ReadIEReg, 0>;620def : ReadAdvance<ReadIM, 0>;621def : ReadAdvance<ReadIMA, 0>;622def : ReadAdvance<ReadID, 0>;623def : ReadAdvance<ReadExtrHi, 0>;624def : ReadAdvance<ReadAdrBase, 0>;625def : ReadAdvance<ReadVLD, 0>;626def : ReadAdvance<ReadST, 0>;627 628//===----------------------------------------------------------------------===//629// 3. Instruction Tables.630 631//---632// 3.1 Branch Instructions633//---634 635// Branch, immed636// Branch and link, immed637// Compare and branch638def : WriteRes<WriteBr, [THX3T110I23]> {639 let Latency = 1;640 let NumMicroOps = 2;641}642 643// Branch, register644// Branch and link, register != LR645// Branch and link, register = LR646def : WriteRes<WriteBrReg, [THX3T110I23]> {647 let Latency = 1;648 let NumMicroOps = 2;649}650 651def : WriteRes<WriteSys, []> { let Latency = 1; }652def : WriteRes<WriteBarrier, []> { let Latency = 1; }653def : WriteRes<WriteHint, []> { let Latency = 1; }654 655def : WriteRes<WriteAtomic, []> {656 let Latency = 4;657 let NumMicroOps = 2;658}659 660//---661// Branch662//---663def : InstRW<[THX3T110Write_1Cyc_I23], (instrs B, BL, BR, BLR)>;664def : InstRW<[THX3T110Write_1Cyc_I23], (instrs Bcc)>;665def : InstRW<[THX3T110Write_1Cyc_I23], (instrs RET)>;666def : InstRW<[THX3T110Write_1Cyc_I23],667 (instrs CBZW, CBZX, CBNZW, CBNZX, TBZW, TBZX, TBNZW, TBNZX)>;668 669//---670// 3.2 Arithmetic and Logical Instructions671// 3.3 Move and Shift Instructions672//---673 674 675// ALU, basic676// Conditional compare677// Conditional select678// Address generation679def : WriteRes<WriteI, [THX3T110I0123]> {680 let Latency = 1;681 let ReleaseAtCycles = [1];682 let NumMicroOps = 2;683}684 685def : InstRW<[WriteI],686 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",687 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",688 "ADC(W|X)r",689 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",690 "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)",691 "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)",692 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",693 "SBCS(W|X)r", "CCMN(W|X)(i|r)",694 "CCMP(W|X)(i|r)", "CSEL(W|X)r",695 "CSINC(W|X)r", "CSINV(W|X)r",696 "CSNEG(W|X)r")>;697 698def : InstRW<[WriteI], (instrs COPY)>;699 700// ALU, extend and/or shift701def : WriteRes<WriteISReg, [THX3T110I0123]> {702 let Latency = 2;703 let ReleaseAtCycles = [2];704 let NumMicroOps = 2;705}706 707def : InstRW<[WriteISReg],708 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",709 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",710 "ADC(W|X)r",711 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",712 "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)",713 "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)",714 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",715 "SBCS(W|X)r", "CCMN(W|X)(i|r)",716 "CCMP(W|X)(i|r)", "CSEL(W|X)r",717 "CSINC(W|X)r", "CSINV(W|X)r",718 "CSNEG(W|X)r")>;719 720def : WriteRes<WriteIEReg, [THX3T110I0123]> {721 let Latency = 1;722 let ReleaseAtCycles = [1];723 let NumMicroOps = 2;724}725 726def : InstRW<[WriteIEReg],727 (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?",728 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",729 "ADC(W|X)r",730 "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)",731 "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)",732 "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)",733 "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r",734 "SBCS(W|X)r", "CCMN(W|X)(i|r)",735 "CCMP(W|X)(i|r)", "CSEL(W|X)r",736 "CSINC(W|X)r", "CSINV(W|X)r",737 "CSNEG(W|X)r")>;738 739// Move immed740def : WriteRes<WriteImm, [THX3T110I0123]> {741 let Latency = 1;742 let NumMicroOps = 2;743}744 745def : InstRW<[THX3T110Write_1Cyc_I0123],746 (instrs MOVKWi, MOVKXi, MOVNWi, MOVNXi, MOVZWi, MOVZXi)>;747 748def : InstRW<[THX3T110Write_1Cyc_I0123],749 (instrs ASRVWr, ASRVXr, LSLVWr, LSLVXr, RORVWr, RORVXr)>;750 751// Variable shift752def : WriteRes<WriteIS, [THX3T110I0123]> {753 let Latency = 1;754 let NumMicroOps = 2;755}756 757//---758// 3.4 Divide and Multiply Instructions759//---760 761// Divide, W-form762// Latency range of 13-23/13-39.763def : WriteRes<WriteID32, [THX3T110I1]> {764 let Latency = 39;765 let ReleaseAtCycles = [39];766 let NumMicroOps = 4;767}768 769// Divide, X-form770def : WriteRes<WriteID64, [THX3T110I1]> {771 let Latency = 23;772 let ReleaseAtCycles = [23];773 let NumMicroOps = 4;774}775 776// Multiply accumulate, W-form777def : WriteRes<WriteIM32, [THX3T110I0123]> {778 let Latency = 5;779 let NumMicroOps = 3;780}781 782// Multiply accumulate, X-form783def : WriteRes<WriteIM64, [THX3T110I0123]> {784 let Latency = 5;785 let NumMicroOps = 3;786}787 788//def : InstRW<[WriteIM32, ReadIM, ReadIM, ReadIMA, THX3T110Write_5Cyc_I012],789// (instrs MADDWrrr, MSUBWrrr)>;790def : InstRW<[WriteIM32], (instrs MADDWrrr, MSUBWrrr)>;791def : InstRW<[WriteIM32], (instrs MADDXrrr, MSUBXrrr)>;792def : InstRW<[THX3T110Write_5Cyc_I0123],793 (instregex "(S|U)(MADDL|MSUBL)rrr")>;794 795def : InstRW<[WriteID32], (instrs SDIVWr, UDIVWr)>;796def : InstRW<[WriteID64], (instrs SDIVXr, UDIVXr)>;797 798// Bitfield extract, two reg799def : WriteRes<WriteExtr, [THX3T110I0123]> {800 let Latency = 1;801 let NumMicroOps = 2;802}803 804// Multiply high805def : InstRW<[THX3T110Write_4Cyc_I1], (instrs SMULHrr, UMULHrr)>;806 807// Miscellaneous Data-Processing Instructions808// Bitfield extract809def : InstRW<[THX3T110Write_1Cyc_I0123], (instrs EXTRWrri, EXTRXrri)>;810 811// Bitifield move - basic812def : InstRW<[THX3T110Write_1Cyc_I0123],813 (instrs SBFMWri, SBFMXri, UBFMWri, UBFMXri)>;814 815// Bitfield move, insert816def : InstRW<[THX3T110Write_1Cyc_I0123], (instregex "^BFM")>;817def : InstRW<[THX3T110Write_1Cyc_I0123], (instregex "(S|U)?BFM.*")>;818 819// Count leading820def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123],821 (instregex "^CLS(W|X)r$", "^CLZ(W|X)r$")>;822 823// Reverse bits824def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123], (instrs RBITWr, RBITXr)>;825 826// Cryptography Extensions827def : InstRW<[THX3T110Write_4Cyc_F0123], (instregex "^AES[DE]")>;828def : InstRW<[THX3T110Write_4Cyc_F0123], (instregex "^AESI?MC")>;829def : InstRW<[THX3T110Write_4Cyc_F0123], (instregex "^PMULL")>;830def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SHA1SU0")>;831def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SHA1(H|SU1)")>;832def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SHA1[CMP]")>;833def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SHA256SU0")>;834def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SHA256(H|H2|SU1)")>;835 836// CRC Instructions837// def : InstRW<[THX3T110Write_4Cyc_I1], (instregex "^CRC32", "^CRC32C")>;838def : InstRW<[THX3T110Write_4Cyc_I1],839 (instrs CRC32Brr, CRC32Hrr, CRC32Wrr, CRC32Xrr)>;840 841def : InstRW<[THX3T110Write_4Cyc_I1],842 (instrs CRC32CBrr, CRC32CHrr, CRC32CWrr, CRC32CXrr)>;843 844// Reverse bits/bytes845// NOTE: Handled by WriteI.846 847//---848// 3.6 Load Instructions849// 3.10 FP Load Instructions850//---851 852// Load register, literal853// Load register, unscaled immed854// Load register, immed unprivileged855// Load register, unsigned immed856def : WriteRes<WriteLD, [THX3T110LS]> {857 let Latency = 4;858 let NumMicroOps = 4;859}860 861// Load register, immed post-index862// NOTE: Handled by WriteLD, WriteI.863// Load register, immed pre-index864// NOTE: Handled by WriteLD, WriteAdr.865def : WriteRes<WriteAdr, [THX3T110I0123]> {866 let Latency = 1;867 let NumMicroOps = 2;868}869 870// Load pair, immed offset, normal871// Load pair, immed offset, signed words, base != SP872// Load pair, immed offset signed words, base = SP873// LDP only breaks into *one* LS micro-op. Thus874// the resources are handled by WriteLD.875def : WriteRes<WriteLDHi, []> {876 let Latency = 4;877 let NumMicroOps = 4;878}879 880// Load register offset, basic881// Load register, register offset, scale by 4/8882// Load register, register offset, scale by 2883// Load register offset, extend884// Load register, register offset, extend, scale by 4/8885// Load register, register offset, extend, scale by 2886def THX3T110WriteLDIdx : SchedWriteVariant<[887 SchedVar<ScaledIdxPred, [THX3T110Write_4Cyc_LS01_I0123_I0123]>,888 SchedVar<NoSchedPred, [THX3T110Write_4Cyc_LS01_I0123]>]>;889def : SchedAlias<WriteLDIdx, THX3T110WriteLDIdx>;890 891def THX3T110ReadAdrBase : SchedReadVariant<[892 SchedVar<ScaledIdxPred, [ReadDefault]>,893 SchedVar<NoSchedPred, [ReadDefault]>]>;894def : SchedAlias<ReadAdrBase, THX3T110ReadAdrBase>;895 896// Load pair, immed pre-index, normal897// Load pair, immed pre-index, signed words898// Load pair, immed post-index, normal899// Load pair, immed post-index, signed words900def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDNPDi)>;901def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDNPQi)>;902def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDNPSi)>;903def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDNPWi)>;904def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDNPXi)>;905 906def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDPDi)>;907def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDPQi)>;908def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDPSi)>;909def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDPSWi)>;910def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDPWi)>;911def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, WriteLDHi], (instrs LDPXi)>;912 913def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDRBui)>;914def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDRDui)>;915def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDRHui)>;916def : InstRW<[THX3T110Write_5Cyc_LS01], (instrs LDRQui)>;917def : InstRW<[THX3T110Write_5Cyc_LS01], (instrs LDRSui)>;918 919def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDRDl)>;920def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDRQl)>;921def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDRWl)>;922def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDRXl)>;923 924def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDTRBi)>;925def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDTRHi)>;926def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDTRWi)>;927def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDTRXi)>;928 929def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDTRSBWi)>;930def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDTRSBXi)>;931def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDTRSHWi)>;932def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDTRSHXi)>;933def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDTRSWi)>;934 935def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteLDHi, WriteAdr],936 (instrs LDPDpre)>;937def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteLDHi, WriteAdr],938 (instrs LDPQpre)>;939def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteLDHi, WriteAdr],940 (instrs LDPSpre)>;941def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteLDHi, WriteAdr],942 (instrs LDPWpre)>;943def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteLDHi, WriteAdr],944 (instrs LDPWpre)>;945 946def : InstRW<[THX3T110Write_4Cyc_LS01, WriteAdr],947 (instrs LDRBpre, LDRDpre, LDRHpre, LDRQpre,948 LDRSpre, LDRWpre, LDRXpre,949 LDRSBWpre, LDRSBXpre, LDRSBWpost, LDRSBXpost,950 LDRSHWpre, LDRSHXpre, LDRSHWpost, LDRSHXpost,951 LDRBBpre, LDRBBpost, LDRHHpre, LDRHHpost)>;952 953def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteLDHi, WriteAdr],954 (instrs LDPDpost, LDPQpost, LDPSpost, LDPWpost, LDPXpost)>;955 956def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteI],957 (instrs LDRBpost, LDRDpost, LDRHpost,958 LDRQpost, LDRSpost, LDRWpost, LDRXpost)>;959 960def : InstRW<[THX3T110Write_4Cyc_LS01_I0123_I0123, WriteLDHi, WriteAdr],961 (instrs LDPDpre, LDPQpre, LDPSpre, LDPWpre, LDPXpre)>;962 963def : InstRW<[THX3T110Write_4Cyc_LS01_I0123_I0123, WriteAdr],964 (instrs LDRBpre, LDRDpre, LDRHpre, LDRQpre,965 LDRSpre, LDRWpre, LDRXpre)>;966 967def : InstRW<[THX3T110Write_4Cyc_LS01_I0123_I0123, WriteLDHi, WriteAdr],968 (instrs LDPDpost, LDPQpost, LDPSpost, LDPWpost, LDPXpost)>;969 970def : InstRW<[THX3T110Write_4Cyc_LS01_I0123_I0123, WriteI],971 (instrs LDRBpost, LDRDpost, LDRHpost, LDRQpost,972 LDRSpost, LDRWpost, LDRXpost)>;973 974def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRBroW)>;975def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRDroW)>;976def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRHroW)>;977def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRHHroW)>;978def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRQroW)>;979def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRSroW)>;980def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRSHWroW)>;981def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRSHXroW)>;982def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRWroW)>;983def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRXroW)>;984 985def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRBroX)>;986def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRDroX)>;987def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRHHroX)>;988def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRHroX)>;989def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRQroX)>;990def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRSroX)>;991def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRSHWroX)>;992def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRSHXroX)>;993def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRWroX)>;994def : InstRW<[THX3T110Write_4Cyc_LS01_I0123, ReadAdrBase], (instrs LDRXroX)>;995 996def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURBi)>;997def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURBBi)>;998def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURDi)>;999def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURHi)>;1000def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURHHi)>;1001def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURQi)>;1002def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURSi)>;1003def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURXi)>;1004def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURSBWi)>;1005def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURSBXi)>;1006def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURSHWi)>;1007def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURSHXi)>;1008def : InstRW<[THX3T110Write_4Cyc_LS01], (instrs LDURSWi)>;1009 1010// Load exclusive1011def : InstRW<[THX3T110Write_4Cyc_LS01], (instregex "^LDAR(B|H|W|X)$")>;1012def : InstRW<[THX3T110Write_4Cyc_LS01], (instregex "^LDAXR(B|H|W|X)$")>;1013def : InstRW<[THX3T110Write_4Cyc_LS01], (instregex "^LDXR(B|H|W|X)$")>;1014def : InstRW<[THX3T110Write_4Cyc_LS01], (instregex "^LDAXP(W|X)$")>;1015def : InstRW<[THX3T110Write_4Cyc_LS01], (instregex "^LDXP(W|X)$")>;1016 1017//---1018// Prefetch1019//---1020def : InstRW<[THX3T110Write_6Cyc_LS01_I012], (instrs PRFMl)>;1021def : InstRW<[THX3T110Write_6Cyc_LS01_I012], (instrs PRFUMi)>;1022def : InstRW<[THX3T110Write_6Cyc_LS01_I012], (instrs PRFMui)>;1023def : InstRW<[THX3T110Write_6Cyc_LS01_I012], (instrs PRFMroW)>;1024def : InstRW<[THX3T110Write_6Cyc_LS01_I012], (instrs PRFMroX)>;1025 1026//--1027// 3.7 Store Instructions1028// 3.11 FP Store Instructions1029//--1030 1031// Store register, unscaled immed1032// Store register, immed unprivileged1033// Store register, unsigned immed1034def : WriteRes<WriteST, [THX3T110LS, THX3T110SD]> {1035 let Latency = 1;1036 let NumMicroOps = 2;1037}1038 1039// Store register, immed post-index1040// NOTE: Handled by WriteAdr, WriteST, ReadAdrBase1041 1042// Store register, immed pre-index1043// NOTE: Handled by WriteAdr, WriteST1044 1045// Store register, register offset, basic1046// Store register, register offset, scaled by 4/81047// Store register, register offset, scaled by 21048// Store register, register offset, extend1049// Store register, register offset, extend, scale by 4/81050// Store register, register offset, extend, scale by 11051def : WriteRes<WriteSTIdx, [THX3T110LS, THX3T110SD, THX3T110I0123]> {1052 let Latency = 1;1053 let NumMicroOps = 2;1054}1055 1056// Store pair, immed offset, W-form1057// Store pair, immed offset, X-form1058def : WriteRes<WriteSTP, [THX3T110LS, THX3T110SD]> {1059 let Latency = 1;1060 let NumMicroOps = 2;1061}1062 1063// Store pair, immed post-index, W-form1064// Store pair, immed post-index, X-form1065// Store pair, immed pre-index, W-form1066// Store pair, immed pre-index, X-form1067// NOTE: Handled by WriteAdr, WriteSTP.1068def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STURBi)>;1069def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STURBBi)>;1070def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STURDi)>;1071def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STURHi)>;1072def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STURHHi)>;1073def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STURQi)>;1074def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STURSi)>;1075def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STURWi)>;1076def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STURXi)>;1077 1078def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_SD], (instrs STTRBi)>;1079def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_SD], (instrs STTRHi)>;1080def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_SD], (instrs STTRWi)>;1081def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_SD], (instrs STTRXi)>;1082 1083def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STNPDi)>;1084def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STNPQi)>;1085def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STNPXi)>;1086def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STNPWi)>;1087 1088def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STPDi)>;1089def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STPQi)>;1090def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STPXi)>;1091def : InstRW<[THX3T110Write_1Cyc_LS01_SD], (instrs STPWi)>;1092 1093def : InstRW<[THX3T110Write_1Cyc_LS01_I0123], (instrs STRBui)>;1094def : InstRW<[THX3T110Write_1Cyc_LS01_I0123], (instrs STRDui)>;1095def : InstRW<[THX3T110Write_1Cyc_LS01_I0123], (instrs STRHui)>;1096def : InstRW<[THX3T110Write_1Cyc_LS01_I0123], (instrs STRQui)>;1097def : InstRW<[THX3T110Write_1Cyc_LS01_I0123], (instrs STRXui)>;1098def : InstRW<[THX3T110Write_1Cyc_LS01_I0123], (instrs STRWui)>;1099 1100def : InstRW<[WriteSTP, THX3T110Write_1Cyc_LS01_SD], (instrs STRBui)>;1101def : InstRW<[WriteSTP, THX3T110Write_1Cyc_LS01_SD], (instrs STRDui)>;1102def : InstRW<[WriteSTP, THX3T110Write_1Cyc_LS01_SD], (instrs STRHui)>;1103def : InstRW<[WriteSTP, THX3T110Write_1Cyc_LS01_SD], (instrs STRQui)>;1104def : InstRW<[WriteSTP, THX3T110Write_1Cyc_LS01_SD], (instrs STRXui)>;1105def : InstRW<[WriteSTP, THX3T110Write_1Cyc_LS01_SD], (instrs STRWui)>;1106 1107def : InstRW<[WriteSTIdx, THX3T110Write_1Cyc_LS01_SD_I0123], (instrs STRBui)>;1108def : InstRW<[WriteSTIdx, THX3T110Write_1Cyc_LS01_SD_I0123], (instrs STRDui)>;1109def : InstRW<[WriteSTIdx, THX3T110Write_1Cyc_LS01_SD_I0123], (instrs STRHui)>;1110def : InstRW<[WriteSTIdx, THX3T110Write_1Cyc_LS01_SD_I0123], (instrs STRQui)>;1111def : InstRW<[WriteSTIdx, THX3T110Write_1Cyc_LS01_SD_I0123], (instrs STRXui)>;1112def : InstRW<[WriteSTIdx, THX3T110Write_1Cyc_LS01_SD_I0123], (instrs STRWui)>;1113 1114def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1115 (instrs STPDpre, STPDpost)>;1116def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1117 (instrs STPDpre, STPDpost)>;1118def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1119 (instrs STPQpre, STPQpost)>;1120def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1121 (instrs STPQpre, STPQpost)>;1122def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1123 (instrs STPSpre, STPSpost)>;1124def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1125 (instrs STPSpre, STPSpost)>;1126def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1127 (instrs STPWpre, STPWpost)>;1128def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1129 (instrs STPWpre, STPWpost)>;1130def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1131 (instrs STPXpre, STPXpost)>;1132def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1133 (instrs STPXpre, STPXpost)>;1134def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1135 (instrs STRBpre, STRBpost)>;1136def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1137 (instrs STRBpre, STRBpost)>;1138def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1139 (instrs STRBBpre, STRBBpost)>;1140def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1141 (instrs STRBBpre, STRBBpost)>;1142def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1143 (instrs STRDpre, STRDpost)>;1144def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1145 (instrs STRDpre, STRDpost)>;1146def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1147 (instrs STRHpre, STRHpost)>;1148def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1149 (instrs STRHpre, STRHpost)>;1150def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1151 (instrs STRHHpre, STRHHpost)>;1152def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1153 (instrs STRHHpre, STRHHpost)>;1154def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1155 (instrs STRQpre, STRQpost)>;1156def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1157 (instrs STRQpre, STRQpost)>;1158def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1159 (instrs STRSpre, STRSpost)>;1160def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1161 (instrs STRSpre, STRSpost)>;1162def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1163 (instrs STRWpre, STRWpost)>;1164def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1165 (instrs STRWpre, STRWpost)>;1166def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123],1167 (instrs STRXpre, STRXpost)>;1168def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1169 (instrs STRXpre, STRXpost)>;1170def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1171 (instrs STRBroW, STRBroX)>;1172def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1173 (instrs STRBBroW, STRBBroX)>;1174def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1175 (instrs STRDroW, STRDroX)>;1176def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1177 (instrs STRHroW, STRHroX)>;1178def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1179 (instrs STRHHroW, STRHHroX)>;1180def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1181 (instrs STRQroW, STRQroX)>;1182def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1183 (instrs STRSroW, STRSroX)>;1184def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1185 (instrs STRWroW, STRWroX)>;1186def : InstRW<[WriteAdr, THX3T110Write_1Cyc_LS01_I0123, ReadAdrBase],1187 (instrs STRXroW, STRXroX)>;1188 1189// Store exclusive1190def : InstRW<[THX3T110Write_4Cyc_LS01_SD], (instrs STNPWi, STNPXi)>;1191def : InstRW<[THX3T110Write_4Cyc_LS01_SD], (instregex "^STLR(B|H|W|X)$")>;1192def : InstRW<[THX3T110Write_4Cyc_LS01_SD], (instregex "^STXP(W|X)$")>;1193def : InstRW<[THX3T110Write_4Cyc_LS01_SD], (instregex "^STXR(B|H|W|X)$")>;1194def : InstRW<[THX3T110Write_4Cyc_LS01_SD], (instregex "^STLXP(W|X)$")>;1195def : InstRW<[THX3T110Write_4Cyc_LS01_SD], (instregex "^STLXR(B|H|W|X)$")>;1196 1197//---1198// 3.8 FP Data Processing Instructions1199//---1200 1201// FP absolute value1202// FP min/max1203// FP negate1204def : WriteRes<WriteF, [THX3T110FP0123]> {1205 let Latency = 5;1206 let NumMicroOps = 2;1207}1208 1209// FP arithmetic1210def : InstRW<[THX3T110Write_6Cyc_F01], (instregex "^FADD", "^FSUB")>;1211 1212// FP compare1213def : WriteRes<WriteFCmp, [THX3T110FP0123]> {1214 let Latency = 5;1215 let NumMicroOps = 2;1216}1217 1218// FP Mul, Div, Sqrt1219def : WriteRes<WriteFDiv, [THX3T110FP0123]> {1220 let Latency = 22;1221 let ReleaseAtCycles = [19];1222}1223 1224def THX3T110XWriteFDiv : SchedWriteRes<[THX3T110FP0123]> {1225 let Latency = 16;1226 let ReleaseAtCycles = [8];1227 let NumMicroOps = 4;1228}1229 1230def THX3T110XWriteFDivSP : SchedWriteRes<[THX3T110FP0123]> {1231 let Latency = 16;1232 let ReleaseAtCycles = [8];1233 let NumMicroOps = 4;1234}1235 1236def THX3T110XWriteFDivDP : SchedWriteRes<[THX3T110FP0123]> {1237 let Latency = 23;1238 let ReleaseAtCycles = [12];1239 let NumMicroOps = 4;1240}1241 1242def THX3T110XWriteFSqrtSP : SchedWriteRes<[THX3T110FP0123]> {1243 let Latency = 16;1244 let ReleaseAtCycles = [8];1245 let NumMicroOps = 4;1246}1247 1248def THX3T110XWriteFSqrtDP : SchedWriteRes<[THX3T110FP0123]> {1249 let Latency = 23;1250 let ReleaseAtCycles = [12];1251 let NumMicroOps = 4;1252}1253 1254// FP divide, S-form1255// FP square root, S-form1256def : InstRW<[THX3T110XWriteFDivSP], (instrs FDIVSrr)>;1257def : InstRW<[THX3T110XWriteFSqrtSP], (instrs FSQRTSr)>;1258def : InstRW<[THX3T110XWriteFDivSP], (instregex "^FDIVv.*32$")>;1259def : InstRW<[THX3T110XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>;1260def : InstRW<[THX3T110Write_16Cyc_F01], (instregex "^FDIVSrr", "^FSQRTSr")>;1261 1262// FP divide, D-form1263// FP square root, D-form1264def : InstRW<[THX3T110XWriteFDivDP], (instrs FDIVDrr)>;1265def : InstRW<[THX3T110XWriteFSqrtDP], (instrs FSQRTDr)>;1266def : InstRW<[THX3T110XWriteFDivDP], (instregex "^FDIVv.*64$")>;1267def : InstRW<[THX3T110XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>;1268def : InstRW<[THX3T110Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>;1269 1270// FP multiply1271// FP multiply accumulate1272def : WriteRes<WriteFMul, [THX3T110FP0123]> {1273 let Latency = 6;1274 let ReleaseAtCycles = [2];1275 let NumMicroOps = 3;1276}1277 1278def THX3T110XWriteFMul : SchedWriteRes<[THX3T110FP0123]> {1279 let Latency = 6;1280 let ReleaseAtCycles = [2];1281 let NumMicroOps = 3;1282}1283 1284def THX3T110XWriteFMulAcc : SchedWriteRes<[THX3T110FP0123]> {1285 let Latency = 6;1286 let ReleaseAtCycles = [2];1287 let NumMicroOps = 3;1288}1289 1290def : InstRW<[THX3T110XWriteFMul], (instregex "^FMUL", "^FNMUL")>;1291def : InstRW<[THX3T110XWriteFMulAcc],1292 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;1293 1294// FP round to integral1295def : InstRW<[THX3T110Write_7Cyc_F01],1296 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;1297 1298// FP select1299def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123], (instregex "^FCSEL")>;1300 1301//---1302// 3.9 FP Miscellaneous Instructions1303//---1304 1305// FP convert, from vec to vec reg1306// FP convert, from gen to vec reg1307// FP convert, from vec to gen reg1308def : WriteRes<WriteFCvt, [THX3T110FP0123]> {1309 let Latency = 7;1310 let NumMicroOps = 3;1311}1312 1313// FP move, immed1314// FP move, register1315def : WriteRes<WriteFImm, [THX3T110FP0123]> {1316 let Latency = 4;1317 let NumMicroOps = 2;1318}1319 1320// FP transfer, from gen to vec reg1321// FP transfer, from vec to gen reg1322def : WriteRes<WriteFCopy, [THX3T110FP0123]> {1323 let Latency = 4;1324 let NumMicroOps = 2;1325}1326 1327def : InstRW<[THX3T110Write_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;1328 1329//---1330// 3.12 ASIMD Integer Instructions1331//---1332 1333// ASIMD absolute diff, D-form1334// ASIMD absolute diff, Q-form1335// ASIMD absolute diff accum, D-form1336// ASIMD absolute diff accum, Q-form1337// ASIMD absolute diff accum long1338// ASIMD absolute diff long1339// ASIMD arith, basic1340// ASIMD arith, complex1341// ASIMD compare1342// ASIMD logical (AND, BIC, EOR)1343// ASIMD max/min, basic1344// ASIMD max/min, reduce, 4H/4S1345// ASIMD max/min, reduce, 8B/8H1346// ASIMD max/min, reduce, 16B1347// ASIMD multiply, D-form1348// ASIMD multiply, Q-form1349// ASIMD multiply accumulate long1350// ASIMD multiply accumulate saturating long1351// ASIMD multiply long1352// ASIMD pairwise add and accumulate1353// ASIMD shift accumulate1354// ASIMD shift by immed, basic1355// ASIMD shift by immed and insert, basic, D-form1356// ASIMD shift by immed and insert, basic, Q-form1357// ASIMD shift by immed, complex1358// ASIMD shift by register, basic, D-form1359// ASIMD shift by register, basic, Q-form1360// ASIMD shift by register, complex, D-form1361// ASIMD shift by register, complex, Q-form1362def : WriteRes<WriteVd, [THX3T110FP0123]> {1363 let Latency = 5;1364 let NumMicroOps = 4;1365 let ReleaseAtCycles = [4];1366}1367def : WriteRes<WriteVq, [THX3T110FP0123]> {1368 let Latency = 5;1369 let NumMicroOps = 4;1370 let ReleaseAtCycles = [4];1371}1372 1373// ASIMD arith, reduce, 4H/4S1374// ASIMD arith, reduce, 8B/8H1375// ASIMD arith, reduce, 16B1376 1377// ASIMD logical (MVN (alias for NOT), ORN, ORR)1378def : InstRW<[THX3T110Write_5Cyc_F0123],1379 (instregex "^ANDv", "^BICv", "^EORv", "^ORRv", "^ORNv", "^NOTv")>;1380 1381// ASIMD arith, reduce1382def : InstRW<[THX3T110Write_5Cyc_F0123],1383 (instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>;1384 1385// ASIMD polynomial (8x8) multiply long1386def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^(S|U|SQD)MULL")>;1387def : InstRW<[THX3T110Write_5Cyc_F0123],1388 (instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>;1389def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^PMULL(v8i8|v16i8)")>;1390def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^PMULL(v1i64|v2i64)")>;1391 1392// ASIMD absolute diff accum, D-form1393def : InstRW<[THX3T110Write_5Cyc_F0123],1394 (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;1395// ASIMD absolute diff accum, Q-form1396def : InstRW<[THX3T110Write_5Cyc_F0123],1397 (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>;1398// ASIMD absolute diff accum long1399def : InstRW<[THX3T110Write_5Cyc_F0123],1400 (instregex "^[SU]ABAL")>;1401// ASIMD arith, reduce, 4H/4S1402def : InstRW<[THX3T110Write_5Cyc_F0123],1403 (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;1404// ASIMD arith, reduce, 8B1405def : InstRW<[THX3T110Write_5Cyc_F0123],1406 (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;1407// ASIMD arith, reduce, 16B/16H1408def : InstRW<[THX3T110Write_10Cyc_F0123],1409 (instregex "^[SU]?ADDL?Vv16i8v$")>;1410// ASIMD max/min, reduce, 4H/4S1411def : InstRW<[THX3T110Write_5Cyc_F0123],1412 (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;1413// ASIMD max/min, reduce, 8B/8H1414def : InstRW<[THX3T110Write_5Cyc_F0123],1415 (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;1416// ASIMD max/min, reduce, 16B/16H1417def : InstRW<[THX3T110Write_5Cyc_F0123],1418 (instregex "^[SU](MIN|MAX)Vv16i8v$")>;1419// ASIMD multiply, D-form1420def : InstRW<[THX3T110Write_5Cyc_F0123],1421 (instregex "^(P?MUL|SQR?DMULH)" #1422 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #1423 "(_indexed)?$")>;1424// ASIMD multiply, Q-form1425def : InstRW<[THX3T110Write_5Cyc_F0123],1426 (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;1427// ASIMD multiply accumulate, D-form1428def : InstRW<[THX3T110Write_5Cyc_F0123],1429 (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;1430// ASIMD multiply accumulate, Q-form1431def : InstRW<[THX3T110Write_5Cyc_F0123],1432 (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>;1433// ASIMD shift accumulate1434def : InstRW<[THX3T110Write_5Cyc_F0123],1435 (instregex "SRSRAv","SSRAv","URSRAv","USRAv")>;1436 1437// ASIMD shift by immed, basic1438def : InstRW<[THX3T110Write_5Cyc_F0123],1439 (instregex "RSHRNv","SHRNv", "SQRSHRNv","SQRSHRUNv",1440 "SQSHRNv","SQSHRUNv", "UQRSHRNv",1441 "UQSHRNv","SQXTNv","SQXTUNv","UQXTNv")>;1442// ASIMD shift by immed, complex1443def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^[SU]?(Q|R){1,2}SHR")>;1444def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SQSHLU")>;1445// ASIMD shift by register, basic, Q-form1446def : InstRW<[THX3T110Write_5Cyc_F01],1447 (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;1448// ASIMD shift by register, complex, D-form1449def : InstRW<[THX3T110Write_5Cyc_F0123],1450 (instregex "^[SU][QR]{1,2}SHL" #1451 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;1452// ASIMD shift by register, complex, Q-form1453def : InstRW<[THX3T110Write_5Cyc_F0123],1454 (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;1455 1456// ASIMD Arithmetic1457def : InstRW<[THX3T110Write_5Cyc_F0123],1458 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;1459def : InstRW<[THX3T110Write_5Cyc_F0123],1460 (instregex "(ADD|SUB)(v16i8|v8i16|v4i32|v2i64)")>;1461def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "(ADD|SUB)HNv.*")>;1462def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "(RADD|RSUB)HNv.*")>;1463def : InstRW<[THX3T110Write_5Cyc_F0123],1464 (instregex "^SQADD", "^SQNEG", "^SQSUB", "^SRHADD",1465 "^SUQADD", "^UQADD", "^UQSUB", "^URHADD", "^USQADD")>;1466def : InstRW<[THX3T110Write_5Cyc_F0123],1467 (instregex "ADDP(v16i8|v8i16|v4i32|v2i64)")>;1468def : InstRW<[THX3T110Write_5Cyc_F0123],1469 (instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|" #1470 "(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>;1471def : InstRW<[THX3T110Write_5Cyc_F0123],1472 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;1473def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SADALP","^UADALP")>;1474def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SADDLPv","^UADDLPv")>;1475def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SADDLV","^UADDLV")>;1476def : InstRW<[THX3T110Write_5Cyc_F0123],1477 (instregex "^ADDVv","^SMAXVv","^UMAXVv","^SMINVv","^UMINVv")>;1478def : InstRW<[THX3T110Write_5Cyc_F0123],1479 (instregex "^SABAv","^UABAv","^SABALv","^UABALv")>;1480def : InstRW<[THX3T110Write_5Cyc_F0123],1481 (instregex "^SQADDv","^SQSUBv","^UQADDv","^UQSUBv")>;1482def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SUQADDv","^USQADDv")>;1483def : InstRW<[THX3T110Write_5Cyc_F0123],1484 (instregex "^ADDHNv","^RADDHNv", "^RSUBHNv",1485 "^SQABS", "^SQADD", "^SQNEG", "^SQSUB",1486 "^SRHADD", "^SUBHNv", "^SUQADD",1487 "^UQADD", "^UQSUB", "^URHADD", "^USQADD")>;1488def : InstRW<[THX3T110Write_5Cyc_F0123],1489 (instregex "^CMEQv","^CMGEv","^CMGTv",1490 "^CMLEv","^CMLTv", "^CMHIv","^CMHSv")>;1491def : InstRW<[THX3T110Write_5Cyc_F0123],1492 (instregex "^SMAXv","^SMINv","^UMAXv","^UMINv",1493 "^SMAXPv","^SMINPv","^UMAXPv","^UMINPv")>;1494def : InstRW<[THX3T110Write_5Cyc_F0123],1495 (instregex "^SABDv","^UABDv", "^SABDLv","^UABDLv")>;1496 1497//---1498// 3.13 ASIMD Floating-point Instructions1499//---1500 1501// ASIMD FP absolute value1502def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^FABSv")>;1503 1504// ASIMD FP arith, normal, D-form1505// ASIMD FP arith, normal, Q-form1506def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123],1507 (instregex "^FABDv", "^FADDv", "^FSUBv")>;1508 1509// ASIMD FP arith,pairwise, D-form1510// ASIMD FP arith, pairwise, Q-form1511def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123], (instregex "^FADDPv")>;1512 1513// ASIMD FP compare, D-form1514// ASIMD FP compare, Q-form1515def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^FACGEv", "^FACGTv")>;1516def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^FCMEQv", "^FCMGEv",1517 "^FCMGTv", "^FCMLEv",1518 "^FCMLTv")>;1519 1520// ASIMD FP round, D-form1521def : InstRW<[THX3T110Write_5Cyc_F0123],1522 (instregex "^FRINT[AIMNPXZ](v2f32)")>;1523// ASIMD FP round, Q-form1524def : InstRW<[THX3T110Write_5Cyc_F0123],1525 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;1526 1527// ASIMD FP convert, long1528// ASIMD FP convert, narrow1529// ASIMD FP convert, other, D-form1530// ASIMD FP convert, other, Q-form1531// NOTE: Handled by WriteV.1532 1533// ASIMD FP convert, long and narrow1534def : InstRW<[THX3T110Write_5Cyc_F01], (instregex "^FCVT(L|N|XN)v")>;1535// ASIMD FP convert, other, D-form1536def : InstRW<[THX3T110Write_5Cyc_F01],1537 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;1538// ASIMD FP convert, other, Q-form1539def : InstRW<[THX3T110Write_5Cyc_F01],1540 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>;1541 1542// ASIMD FP divide, D-form, F321543def : InstRW<[THX3T110Write_16Cyc_F0123], (instrs FDIVv2f32)>;1544def : InstRW<[THX3T110Write_16Cyc_F0123], (instregex "FDIVv2f32")>;1545 1546// ASIMD FP divide, Q-form, F321547def : InstRW<[THX3T110Write_16Cyc_F0123], (instrs FDIVv4f32)>;1548def : InstRW<[THX3T110Write_16Cyc_F0123], (instregex "FDIVv4f32")>;1549 1550// ASIMD FP divide, Q-form, F641551def : InstRW<[THX3T110Write_23Cyc_F0123], (instrs FDIVv2f64)>;1552def : InstRW<[THX3T110Write_23Cyc_F0123], (instregex "FDIVv2f64")>;1553 1554// ASIMD FP max/min, normal, D-form1555// ASIMD FP max/min, normal, Q-form1556def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^FMAXv", "^FMAXNMv",1557 "^FMINv", "^FMINNMv")>;1558 1559// ASIMD FP max/min, pairwise, D-form1560// ASIMD FP max/min, pairwise, Q-form1561def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^FMAXPv", "^FMAXNMPv",1562 "^FMINPv", "^FMINNMPv")>;1563 1564// ASIMD FP max/min, reduce1565def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^FMAXVv", "^FMAXNMVv",1566 "^FMINVv", "^FMINNMVv")>;1567 1568// ASIMD FP multiply, D-form, FZ1569// ASIMD FP multiply, D-form, no FZ1570// ASIMD FP multiply, Q-form, FZ1571// ASIMD FP multiply, Q-form, no FZ1572def : InstRW<[THX3T110Write_5Cyc_F0123],1573 (instregex "^FMULv", "^FMULXv")>;1574def : InstRW<[THX3T110Write_5Cyc_F0123],1575 (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;1576def : InstRW<[THX3T110Write_5Cyc_F0123],1577 (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;1578 1579// ASIMD FP multiply accumulate, Dform, FZ1580// ASIMD FP multiply accumulate, Dform, no FZ1581// ASIMD FP multiply accumulate, Qform, FZ1582// ASIMD FP multiply accumulate, Qform, no FZ1583def : InstRW<[THX3T110Write_5Cyc_F0123],1584 (instregex "^FMLAv", "^FMLSv")>;1585def : InstRW<[THX3T110Write_5Cyc_F0123],1586 (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;1587def : InstRW<[THX3T110Write_5Cyc_F0123],1588 (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;1589 1590// ASIMD FP negate1591def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^FNEGv")>;1592 1593//--1594// 3.14 ASIMD Miscellaneous Instructions1595//--1596 1597// ASIMD bit reverse1598def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^RBITv")>;1599 1600// ASIMD bitwise insert, D-form1601// ASIMD bitwise insert, Q-form1602def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123],1603 (instregex "^BIFv", "^BITv", "^BSLv")>;1604 1605// ASIMD count, D-form1606// ASIMD count, Q-form1607def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123],1608 (instregex "^CLSv", "^CLZv", "^CNTv")>;1609 1610// ASIMD duplicate, gen reg1611// ASIMD duplicate, element1612def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^DUPv")>;1613def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^DUP(i8|i16|i32|i64)$")>;1614def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^DUPv.+gpr")>;1615 1616// ASIMD extract1617def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^EXTv")>;1618 1619// ASIMD extract narrow1620def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^XTNv")>;1621 1622// ASIMD extract narrow, saturating1623def : InstRW<[THX3T110Write_5Cyc_F0123],1624 (instregex "^SQXTNv", "^SQXTUNv", "^UQXTNv")>;1625 1626// ASIMD insert, element to element1627def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^INSv")>;1628 1629// ASIMD transfer, element to gen reg1630def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^[SU]MOVv")>;1631 1632// ASIMD move, integer immed1633def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123], (instregex "^MOVIv")>;1634 1635// ASIMD move, FP immed1636def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123], (instregex "^FMOVv")>;1637 1638// ASIMD transpose1639def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^TRN1", "^TRN2")>;1640 1641// ASIMD unzip/zip1642def : InstRW<[THX3T110Write_5Cyc_F0123],1643 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;1644 1645// ASIMD reciprocal estimate, D-form1646// ASIMD reciprocal estimate, Q-form1647def : InstRW<[THX3T110Write_5Cyc_F0123],1648 (instregex "^FRECPEv", "^FRECPXv", "^URECPEv",1649 "^FRSQRTEv", "^URSQRTEv")>;1650 1651// ASIMD reciprocal step, D-form, FZ1652// ASIMD reciprocal step, D-form, no FZ1653// ASIMD reciprocal step, Q-form, FZ1654// ASIMD reciprocal step, Q-form, no FZ1655def : InstRW<[THX3T110Write_5Cyc_F0123],1656 (instregex "^FRECPSv", "^FRSQRTSv")>;1657 1658// ASIMD reverse1659def : InstRW<[THX3T110Write_5Cyc_F0123],1660 (instregex "^REV16v", "^REV32v", "^REV64v")>;1661 1662// ASIMD table lookup, D-form1663// ASIMD table lookup, Q-form1664def : InstRW<[THX3T110Write_5Cyc_F0123],1665 (instrs TBLv8i8One, TBLv16i8One, TBXv8i8One, TBXv16i8One)>;1666def : InstRW<[THX3T110Write_10Cyc_F0123],1667 (instrs TBLv8i8Two, TBLv16i8Two, TBXv8i8Two, TBXv16i8Two)>;1668def : InstRW<[THX3T110Write_15Cyc_F0123],1669 (instrs TBLv8i8Three, TBLv16i8Three, TBXv8i8Three, TBXv16i8Three)>;1670def : InstRW<[THX3T110Write_20Cyc_F0123],1671 (instrs TBLv8i8Four, TBLv16i8Four, TBXv8i8Four, TBXv16i8Four)>;1672 1673// ASIMD transfer, element to word or word1674def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^[SU]MOVv")>;1675 1676// ASIMD transfer, element to gen reg1677def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "(S|U)MOVv.*")>;1678 1679// ASIMD transfer gen reg to element1680def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^INSv")>;1681 1682// ASIMD transpose1683def : InstRW<[THX3T110Write_5Cyc_F0123],1684 (instregex "^TRN1v", "^TRN2v", "^UZP1v", "^UZP2v")>;1685 1686// ASIMD unzip/zip1687def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^ZIP1v", "^ZIP2v")>;1688 1689//--1690// 3.15 ASIMD Load Instructions1691//--1692 1693// ASIMD load, 1 element, multiple, 1 reg, D-form1694// ASIMD load, 1 element, multiple, 1 reg, Q-form1695def : InstRW<[THX3T110Write_4Cyc_LS01],1696 (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1697def : InstRW<[THX3T110Write_4Cyc_LS01, WriteAdr],1698 (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1699 1700// ASIMD load, 1 element, multiple, 2 reg, D-form1701// ASIMD load, 1 element, multiple, 2 reg, Q-form1702def : InstRW<[THX3T110Write_4Cyc_LS01],1703 (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1704def : InstRW<[THX3T110Write_4Cyc_LS01, WriteAdr],1705 (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1706 1707// ASIMD load, 1 element, multiple, 3 reg, D-form1708// ASIMD load, 1 element, multiple, 3 reg, Q-form1709def : InstRW<[THX3T110Write_5Cyc_LS01],1710 (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1711def : InstRW<[THX3T110Write_5Cyc_LS01, WriteAdr],1712 (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1713 1714// ASIMD load, 1 element, multiple, 4 reg, D-form1715// ASIMD load, 1 element, multiple, 4 reg, Q-form1716def : InstRW<[THX3T110Write_6Cyc_LS01],1717 (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1718def : InstRW<[THX3T110Write_6Cyc_LS01, WriteAdr],1719 (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1720 1721// ASIMD load, 1 element, one lane, B/H/S1722// ASIMD load, 1 element, one lane, D1723def : InstRW<[THX3T110Write_5Cyc_LS01_F0123],1724 (instregex "^LD1i(8|16|32|64)$")>;1725def : InstRW<[THX3T110Write_5Cyc_LS01_F0123, WriteAdr],1726 (instregex "^LD1i(8|16|32|64)_POST$")>;1727 1728// ASIMD load, 1 element, all lanes, D-form, B/H/S1729// ASIMD load, 1 element, all lanes, D-form, D1730// ASIMD load, 1 element, all lanes, Q-form1731def : InstRW<[THX3T110Write_5Cyc_LS01_F0123],1732 (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1733def : InstRW<[THX3T110Write_5Cyc_LS01_F0123, WriteAdr],1734 (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1735 1736// ASIMD load, 2 element, multiple, D-form, B/H/S1737// ASIMD load, 2 element, multiple, Q-form, D1738def : InstRW<[THX3T110Write_5Cyc_LS01_F0123],1739 (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|2d)$")>;1740def : InstRW<[THX3T110Write_5Cyc_LS01_F0123, WriteAdr],1741 (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|2d)_POST$")>;1742 1743// ASIMD load, 2 element, one lane, B/H1744// ASIMD load, 2 element, one lane, S1745// ASIMD load, 2 element, one lane, D1746def : InstRW<[THX3T110Write_5Cyc_LS01_F0123],1747 (instregex "^LD2i(8|16|32|64)$")>;1748def : InstRW<[THX3T110Write_5Cyc_LS01_F0123, WriteAdr],1749 (instregex "^LD2i(8|16|32|64)_POST$")>;1750 1751// ASIMD load, 2 element, all lanes, D-form, B/H/S1752// ASIMD load, 2 element, all lanes, D-form, D1753// ASIMD load, 2 element, all lanes, Q-form1754def : InstRW<[THX3T110Write_5Cyc_LS01_F0123],1755 (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1756def : InstRW<[THX3T110Write_5Cyc_LS01_F0123, WriteAdr],1757 (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1758 1759// ASIMD load, 3 element, multiple, D-form, B/H/S1760// ASIMD load, 3 element, multiple, Q-form, B/H/S1761// ASIMD load, 3 element, multiple, Q-form, D1762def : InstRW<[THX3T110Write_8Cyc_LS01_F0123],1763 (instregex "^LD3Threev(8b|4h|2s|16b|8h|4s|2d)$")>;1764def : InstRW<[THX3T110Write_8Cyc_LS01_F0123, WriteAdr],1765 (instregex "^LD3Threev(8b|4h|2s|16b|8h|4s|2d)_POST$")>;1766 1767// ASIMD load, 3 element, one lone, B/H1768// ASIMD load, 3 element, one lane, S1769// ASIMD load, 3 element, one lane, D1770def : InstRW<[THX3T110Write_7Cyc_LS01_F0123],1771 (instregex "^LD3i(8|16|32|64)$")>;1772def : InstRW<[THX3T110Write_7Cyc_LS01_F0123, WriteAdr],1773 (instregex "^LD3i(8|16|32|64)_POST$")>;1774 1775// ASIMD load, 3 element, all lanes, D-form, B/H/S1776// ASIMD load, 3 element, all lanes, D-form, D1777// ASIMD load, 3 element, all lanes, Q-form, B/H/S1778// ASIMD load, 3 element, all lanes, Q-form, D1779def : InstRW<[THX3T110Write_7Cyc_LS01_F0123],1780 (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1781def : InstRW<[THX3T110Write_7Cyc_LS01_F0123, WriteAdr],1782 (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1783 1784// ASIMD load, 4 element, multiple, D-form, B/H/S1785// ASIMD load, 4 element, multiple, Q-form, B/H/S1786// ASIMD load, 4 element, multiple, Q-form, D1787def : InstRW<[THX3T110Write_8Cyc_LS01_F0123],1788 (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|2d)$")>;1789def : InstRW<[THX3T110Write_8Cyc_LS01_F0123, WriteAdr],1790 (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|2d)_POST$")>;1791 1792// ASIMD load, 4 element, one lane, B/H1793// ASIMD load, 4 element, one lane, S1794// ASIMD load, 4 element, one lane, D1795def : InstRW<[THX3T110Write_6Cyc_LS01_F0123],1796 (instregex "^LD4i(8|16|32|64)$")>;1797def : InstRW<[THX3T110Write_6Cyc_LS01_F0123, WriteAdr],1798 (instregex "^LD4i(8|16|32|64)_POST$")>;1799 1800// ASIMD load, 4 element, all lanes, D-form, B/H/S1801// ASIMD load, 4 element, all lanes, D-form, D1802// ASIMD load, 4 element, all lanes, Q-form, B/H/S1803// ASIMD load, 4 element, all lanes, Q-form, D1804def : InstRW<[THX3T110Write_6Cyc_LS01_F0123],1805 (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1806def : InstRW<[THX3T110Write_6Cyc_LS01_F0123, WriteAdr],1807 (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1808 1809//--1810// 3.16 ASIMD Store Instructions1811//--1812 1813// ASIMD store, 1 element, multiple, 1 reg, D-form1814// ASIMD store, 1 element, multiple, 1 reg, Q-form1815def : InstRW<[THX3T110Write_1Cyc_LS01],1816 (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1817def : InstRW<[THX3T110Write_1Cyc_LS01, WriteAdr],1818 (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1819 1820// ASIMD store, 1 element, multiple, 2 reg, D-form1821// ASIMD store, 1 element, multiple, 2 reg, Q-form1822def : InstRW<[THX3T110Write_1Cyc_LS01],1823 (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1824def : InstRW<[THX3T110Write_1Cyc_LS01, WriteAdr],1825 (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1826 1827// ASIMD store, 1 element, multiple, 3 reg, D-form1828// ASIMD store, 1 element, multiple, 3 reg, Q-form1829def : InstRW<[THX3T110Write_1Cyc_LS01],1830 (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1831def : InstRW<[THX3T110Write_1Cyc_LS01, WriteAdr],1832 (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1833 1834// ASIMD store, 1 element, multiple, 4 reg, D-form1835// ASIMD store, 1 element, multiple, 4 reg, Q-form1836def : InstRW<[THX3T110Write_1Cyc_LS01],1837 (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;1838def : InstRW<[THX3T110Write_1Cyc_LS01, WriteAdr],1839 (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;1840 1841// ASIMD store, 1 element, one lane, B/H/S1842// ASIMD store, 1 element, one lane, D1843def : InstRW<[THX3T110Write_1Cyc_LS01_F0123],1844 (instregex "^ST1i(8|16|32|64)$")>;1845def : InstRW<[THX3T110Write_1Cyc_LS01_F0123, WriteAdr],1846 (instregex "^ST1i(8|16|32|64)_POST$")>;1847 1848// ASIMD store, 2 element, multiple, D-form, B/H/S1849// ASIMD store, 2 element, multiple, Q-form, B/H/S1850// ASIMD store, 2 element, multiple, Q-form, D1851def : InstRW<[THX3T110Write_1Cyc_LS01_F0123],1852 (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|2d)$")>;1853def : InstRW<[THX3T110Write_1Cyc_LS01_F0123, WriteAdr],1854 (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|2d)_POST$")>;1855 1856// ASIMD store, 2 element, one lane, B/H/S1857// ASIMD store, 2 element, one lane, D1858def : InstRW<[THX3T110Write_1Cyc_LS01_F0123],1859 (instregex "^ST2i(8|16|32|64)$")>;1860def : InstRW<[THX3T110Write_1Cyc_LS01_F0123, WriteAdr],1861 (instregex "^ST2i(8|16|32|64)_POST$")>;1862 1863// ASIMD store, 3 element, multiple, D-form, B/H/S1864// ASIMD store, 3 element, multiple, Q-form, B/H/S1865// ASIMD store, 3 element, multiple, Q-form, D1866def : InstRW<[THX3T110Write_1Cyc_LS01_F0123],1867 (instregex "^ST3Threev(8b|4h|2s|16b|8h|4s|2d)$")>;1868def : InstRW<[THX3T110Write_1Cyc_LS01_F0123, WriteAdr],1869 (instregex "^ST3Threev(8b|4h|2s|16b|8h|4s|2d)_POST$")>;1870 1871// ASIMD store, 3 element, one lane, B/H1872// ASIMD store, 3 element, one lane, S1873// ASIMD store, 3 element, one lane, D1874def : InstRW<[THX3T110Write_1Cyc_LS01_F0123],1875 (instregex "^ST3i(8|16|32|64)$")>;1876def : InstRW<[THX3T110Write_1Cyc_LS01_F0123, WriteAdr],1877 (instregex "^ST3i(8|16|32|64)_POST$")>;1878 1879// ASIMD store, 4 element, multiple, D-form, B/H/S1880// ASIMD store, 4 element, multiple, Q-form, B/H/S1881// ASIMD store, 4 element, multiple, Q-form, D1882def : InstRW<[THX3T110Write_1Cyc_LS01_F0123],1883 (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|2d)$")>;1884def : InstRW<[THX3T110Write_1Cyc_LS01_F0123, WriteAdr],1885 (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|2d)_POST$")>;1886 1887// ASIMD store, 4 element, one lane, B/H1888// ASIMD store, 4 element, one lane, S1889// ASIMD store, 4 element, one lane, D1890def : InstRW<[THX3T110Write_1Cyc_LS01_F0123],1891 (instregex "^ST4i(8|16|32|64)$")>;1892def : InstRW<[THX3T110Write_1Cyc_LS01_F0123, WriteAdr],1893 (instregex "^ST4i(8|16|32|64)_POST$")>;1894 1895// V8.1a Atomics (LSE)1896def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1897 (instrs CASB, CASH, CASW, CASX)>;1898 1899def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1900 (instrs CASAB, CASAH, CASAW, CASAX)>;1901 1902def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1903 (instrs CASLB, CASLH, CASLW, CASLX)>;1904 1905def : InstRW<[THX3T110Write_8Cyc_I0123, WriteAtomic],1906 (instrs CASALB, CASALH, CASALW, CASALX)>;1907 1908def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1909 (instrs LDLARB, LDLARH, LDLARW, LDLARX)>;1910 1911def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1912 (instrs LDADDB, LDADDH, LDADDW, LDADDX)>;1913 1914def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1915 (instrs LDADDAB, LDADDAH, LDADDAW, LDADDAX)>;1916 1917def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1918 (instrs LDADDLB, LDADDLH, LDADDLW, LDADDLX)>;1919 1920def : InstRW<[THX3T110Write_8Cyc_I0123, WriteAtomic],1921 (instrs LDADDALB, LDADDALH, LDADDALW, LDADDALX)>;1922 1923def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1924 (instrs LDCLRB, LDCLRH, LDCLRW, LDCLRX)>;1925 1926def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1927 (instrs LDCLRAB, LDCLRAH, LDCLRAW, LDCLRAX)>;1928 1929def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1930 (instrs LDCLRLB, LDCLRLH, LDCLRLW, LDCLRLX)>;1931 1932def : InstRW<[THX3T110Write_8Cyc_I0123, WriteAtomic],1933 (instrs LDCLRALB, LDCLRALH, LDCLRALW, LDCLRALX)>;1934 1935def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1936 (instrs LDEORB, LDEORH, LDEORW, LDEORX)>;1937 1938def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1939 (instrs LDEORAB, LDEORAH, LDEORAW, LDEORAX)>;1940 1941def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1942 (instrs LDEORLB, LDEORLH, LDEORLW, LDEORLX)>;1943 1944def : InstRW<[THX3T110Write_8Cyc_I0123, WriteAtomic],1945 (instrs LDEORALB, LDEORALH, LDEORALW, LDEORALX)>;1946 1947def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1948 (instrs LDSETB, LDSETH, LDSETW, LDSETX)>;1949 1950def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1951 (instrs LDSETAB, LDSETAH, LDSETAW, LDSETAX)>;1952 1953def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1954 (instrs LDSETLB, LDSETLH, LDSETLW, LDSETLX)>;1955 1956def : InstRW<[THX3T110Write_8Cyc_I0123, WriteAtomic],1957 (instrs LDSETALB, LDSETALH, LDSETALW, LDSETALX)>;1958 1959def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1960 (instrs LDSMAXB, LDSMAXH, LDSMAXW, LDSMAXX,1961 LDSMAXAB, LDSMAXAH, LDSMAXAW, LDSMAXAX,1962 LDSMAXLB, LDSMAXLH, LDSMAXLW, LDSMAXLX,1963 LDSMAXALB, LDSMAXALH, LDSMAXALW, LDSMAXALX)>;1964 1965def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1966 (instrs LDSMINB, LDSMINH, LDSMINW, LDSMINX,1967 LDSMINAB, LDSMINAH, LDSMINAW, LDSMINAX,1968 LDSMINLB, LDSMINLH, LDSMINLW, LDSMINLX,1969 LDSMINALB, LDSMINALH, LDSMINALW, LDSMINALX)>;1970 1971def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1972 (instrs LDUMAXB, LDUMAXH, LDUMAXW, LDUMAXX,1973 LDUMAXAB, LDUMAXAH, LDUMAXAW, LDUMAXAX,1974 LDUMAXLB, LDUMAXLH, LDUMAXLW, LDUMAXLX,1975 LDUMAXALB, LDUMAXALH, LDUMAXALW, LDUMAXALX)>;1976 1977def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1978 (instrs LDUMINB, LDUMINH, LDUMINW, LDUMINX,1979 LDUMINAB, LDUMINAH, LDUMINAW, LDUMINAX,1980 LDUMINLB, LDUMINLH, LDUMINLW, LDUMINLX,1981 LDUMINALB, LDUMINALH, LDUMINALW, LDUMINALX)>;1982 1983def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1984 (instrs SWPB, SWPH, SWPW, SWPX)>;1985 1986def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1987 (instrs SWPAB, SWPAH, SWPAW, SWPAX)>;1988 1989def : InstRW<[THX3T110Write_6Cyc_I0123, WriteAtomic],1990 (instrs SWPLB, SWPLH, SWPLW, SWPLX)>;1991 1992def : InstRW<[THX3T110Write_8Cyc_I0123, WriteAtomic],1993 (instrs SWPALB, SWPALH, SWPALW, SWPALX)>;1994 1995def : InstRW<[THX3T110Write_4Cyc_I0123, WriteAtomic],1996 (instrs STLLRB, STLLRH, STLLRW, STLLRX)>;1997 1998// V8.3a PAC1999def : InstRW<[THX3T110Write_11Cyc_LS01_I1], (instregex "^LDRAA", "^LDRAB")>;2000def : InstRW<[THX3T110Write_8Cyc_I123],2001 (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ,2002 BRAA, BRAAZ, BRAB, BRABZ)>;2003def : InstRW<[THX3T110Write_8Cyc_I123], (instrs RETAA, RETAB)>;2004 2005} // SchedModel = ThunderX3T110Model2006