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1//==-- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9// Define TII for use in SchedVariant Predicates.10// const MachineInstr *MI and const TargetSchedModel *SchedModel11// are defined by default.12def : PredicateProlog<[{13 const AArch64InstrInfo *TII =14 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo());15 (void)TII;16}]>;17 18// AArch64 Scheduler Definitions19 20def WriteImm : SchedWrite; // MOVN, MOVZ21// TODO: Provide variants for MOV32/64imm Pseudos that dynamically22// select the correct sequence of WriteImms.23 24def WriteI : SchedWrite; // ALU25def WriteISReg : SchedWrite; // ALU of Shifted-Reg26def WriteIEReg : SchedWrite; // ALU of Extended-Reg27def ReadI : SchedRead; // ALU28def ReadISReg : SchedRead; // ALU of Shifted-Reg29def ReadIEReg : SchedRead; // ALU of Extended-Reg30def WriteExtr : SchedWrite; // EXTR shifts a reg pair31def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair32def WriteIS : SchedWrite; // Shift/Scale33def WriteID32 : SchedWrite; // 32-bit Divide34def WriteID64 : SchedWrite; // 64-bit Divide35def ReadID : SchedRead; // 32/64-bit Divide36def WriteIM32 : SchedWrite; // 32-bit Multiply37def WriteIM64 : SchedWrite; // 64-bit Multiply38def ReadIM : SchedRead; // 32/64-bit Multiply39def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate40def WriteBr : SchedWrite; // Branch41def WriteBrReg : SchedWrite; // Indirect Branch42 43def WriteLD : SchedWrite; // Load from base addr plus immediate offset44def WriteST : SchedWrite; // Store to base addr plus immediate offset45def WriteSTP : SchedWrite; // Store a register pair.46def WriteAdr : SchedWrite; // Address pre/post increment.47 48def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled).49def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).50def ReadST : SchedRead; // Read the stored value.51def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.52 53// Serialized two-level address load.54// EXAMPLE: LOADGot55def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;56 57// Serialized two-level address lookup.58// EXAMPLE: MOVaddr...59def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>;60 61// The second register of a load-pair.62// LDP,LDPSW,LDNP,LDXP,LDAXP63def WriteLDHi : SchedWrite;64 65// Store-exclusive is a store followed by a dependent load.66def WriteSTX : WriteSequence<[WriteST, WriteLD]>;67 68def WriteSys : SchedWrite; // Long, variable latency system ops.69def WriteBarrier : SchedWrite; // Memory barrier.70def WriteHint : SchedWrite; // Hint instruction.71 72def WriteF : SchedWrite; // General floating-point ops.73def WriteFCmp : SchedWrite; // Floating-point compare.74def WriteFCvt : SchedWrite; // Float conversion.75def WriteFCopy : SchedWrite; // Float-int register copy.76def WriteFImm : SchedWrite; // Floating-point immediate.77def WriteFMul : SchedWrite; // Floating-point multiply.78def WriteFDiv : SchedWrite; // Floating-point division.79 80def WriteVd : SchedWrite; // 64bit Vector D ops.81def WriteVq : SchedWrite; // 128bit Vector Q ops.82def WriteVLD : SchedWrite; // Vector loads.83def WriteVST : SchedWrite; // Vector stores.84 85def WriteAtomic : SchedWrite; // Atomic memory operations (CAS, Swap, LDOP)86 87// Read the unwritten lanes of the VLD's destination registers.88def ReadVLD : SchedRead;89 90// Sequential vector load and shuffle.91def WriteVLDShuffle : WriteSequence<[WriteVLD, WriteVq]>;92def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteVq, WriteVq]>;93 94// Store a shuffled vector.95def WriteVSTShuffle : WriteSequence<[WriteVq, WriteVST]>;96def WriteVSTPairShuffle : WriteSequence<[WriteVq, WriteVq, WriteVST]>;97