664 lines · cpp
1//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file implements the AArch64 specific subclass of TargetSubtarget.10//11//===----------------------------------------------------------------------===//12 13#include "AArch64Subtarget.h"14 15#include "AArch64.h"16#include "AArch64InstrInfo.h"17#include "AArch64PBQPRegAlloc.h"18#include "AArch64TargetMachine.h"19#include "GISel/AArch64CallLowering.h"20#include "GISel/AArch64LegalizerInfo.h"21#include "GISel/AArch64RegisterBankInfo.h"22#include "MCTargetDesc/AArch64AddressingModes.h"23#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"24#include "llvm/CodeGen/MachineFrameInfo.h"25#include "llvm/CodeGen/MachineScheduler.h"26#include "llvm/IR/GlobalValue.h"27#include "llvm/Support/SipHash.h"28#include "llvm/TargetParser/AArch64TargetParser.h"29 30using namespace llvm;31 32#define DEBUG_TYPE "aarch64-subtarget"33 34#define GET_SUBTARGETINFO_CTOR35#define GET_SUBTARGETINFO_TARGET_DESC36#include "AArch64GenSubtargetInfo.inc"37 38static cl::opt<bool>39EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "40 "converter pass"), cl::init(true), cl::Hidden);41 42// If OS supports TBI, use this flag to enable it.43static cl::opt<bool>44UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "45 "an address is ignored"), cl::init(false), cl::Hidden);46 47static cl::opt<bool> MachOUseNonLazyBind(48 "aarch64-macho-enable-nonlazybind",49 cl::desc("Call nonlazybind functions via direct GOT load for Mach-O"),50 cl::Hidden);51 52static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),53 cl::desc("Enable the use of AA during codegen."));54 55static cl::opt<unsigned> OverrideVectorInsertExtractBaseCost(56 "aarch64-insert-extract-base-cost",57 cl::desc("Base cost of vector insert/extract element"), cl::Hidden);58 59// Reserve a list of X# registers, so they are unavailable for register60// allocator, but can still be used as ABI requests, such as passing arguments61// to function call.62static cl::list<std::string>63ReservedRegsForRA("reserve-regs-for-regalloc", cl::desc("Reserve physical "64 "registers, so they can't be used by register allocator. "65 "Should only be used for testing register allocator."),66 cl::CommaSeparated, cl::Hidden);67 68static cl::opt<AArch64PAuth::AuthCheckMethod>69 AuthenticatedLRCheckMethod("aarch64-authenticated-lr-check-method",70 cl::Hidden,71 cl::desc("Override the variant of check applied "72 "to authenticated LR during tail call"),73 cl::values(AUTH_CHECK_METHOD_CL_VALUES_LR));74 75static cl::opt<unsigned> AArch64MinimumJumpTableEntries(76 "aarch64-min-jump-table-entries", cl::init(10), cl::Hidden,77 cl::desc("Set minimum number of entries to use a jump table on AArch64"));78 79static cl::opt<unsigned> AArch64StreamingHazardSize(80 "aarch64-streaming-hazard-size",81 cl::desc("Hazard size for streaming mode memory accesses. 0 = disabled."),82 cl::init(0), cl::Hidden);83 84static cl::alias AArch64StreamingStackHazardSize(85 "aarch64-stack-hazard-size",86 cl::desc("alias for -aarch64-streaming-hazard-size"),87 cl::aliasopt(AArch64StreamingHazardSize));88 89static cl::opt<unsigned>90 VScaleForTuningOpt("sve-vscale-for-tuning", cl::Hidden,91 cl::desc("Force a vscale for tuning factor for SVE"));92 93// Subreg liveness tracking is disabled by default for now until all issues94// are ironed out. This option allows the feature to be used in tests.95static cl::opt<bool>96 EnableSubregLivenessTracking("aarch64-enable-subreg-liveness-tracking",97 cl::init(false), cl::Hidden,98 cl::desc("Enable subreg liveness tracking"));99 100static cl::opt<bool>101 UseScalarIncVL("sve-use-scalar-inc-vl", cl::init(false), cl::Hidden,102 cl::desc("Prefer add+cnt over addvl/inc/dec"));103 104unsigned AArch64Subtarget::getVectorInsertExtractBaseCost() const {105 if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)106 return OverrideVectorInsertExtractBaseCost;107 return VectorInsertExtractBaseCost;108}109 110AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(111 StringRef FS, StringRef CPUString, StringRef TuneCPUString,112 bool HasMinSize) {113 // Determine default and user-specified characteristics114 115 if (CPUString.empty())116 CPUString = "generic";117 118 if (TuneCPUString.empty())119 TuneCPUString = CPUString;120 121 ParseSubtargetFeatures(CPUString, TuneCPUString, FS);122 initializeProperties(HasMinSize);123 124 return *this;125}126 127void AArch64Subtarget::initializeProperties(bool HasMinSize) {128 // Initialize CPU specific properties. We should add a tablegen feature for129 // this in the future so we can specify it together with the subtarget130 // features.131 switch (ARMProcFamily) {132 case Generic:133 // Using TuneCPU=generic we avoid ldapur instructions to line up with the134 // cpus that use the AvoidLDAPUR feature. We don't want this to be on135 // forever, so it is enabled between armv8.4 and armv8.7/armv9.2.136 if (hasV8_4aOps() && !hasV8_8aOps())137 AvoidLDAPUR = true;138 break;139 case Carmel:140 CacheLineSize = 64;141 break;142 case CortexA35:143 case CortexA53:144 case CortexA55:145 case CortexR82:146 case CortexR82AE:147 PrefFunctionAlignment = Align(16);148 PrefLoopAlignment = Align(16);149 MaxBytesForLoopAlignment = 8;150 break;151 case CortexA57:152 MaxInterleaveFactor = 4;153 PrefFunctionAlignment = Align(16);154 PrefLoopAlignment = Align(16);155 MaxBytesForLoopAlignment = 8;156 break;157 case CortexA65:158 PrefFunctionAlignment = Align(8);159 break;160 case CortexA72:161 case CortexA73:162 case CortexA75:163 PrefFunctionAlignment = Align(16);164 PrefLoopAlignment = Align(16);165 MaxBytesForLoopAlignment = 8;166 break;167 case CortexA76:168 case CortexA77:169 case CortexA78:170 case CortexA78AE:171 case CortexA78C:172 case CortexX1:173 PrefFunctionAlignment = Align(16);174 PrefLoopAlignment = Align(32);175 MaxBytesForLoopAlignment = 16;176 break;177 case CortexA320:178 case CortexA510:179 case CortexA520:180 PrefFunctionAlignment = Align(16);181 VScaleForTuning = 1;182 PrefLoopAlignment = Align(16);183 MaxBytesForLoopAlignment = 8;184 break;185 case CortexA710:186 case CortexA715:187 case CortexA720:188 case CortexA725:189 case CortexX2:190 case CortexX3:191 case CortexX4:192 case CortexX925:193 PrefFunctionAlignment = Align(16);194 VScaleForTuning = 1;195 PrefLoopAlignment = Align(32);196 MaxBytesForLoopAlignment = 16;197 break;198 case A64FX:199 CacheLineSize = 256;200 PrefFunctionAlignment = Align(8);201 PrefLoopAlignment = Align(4);202 MaxInterleaveFactor = 4;203 PrefetchDistance = 128;204 MinPrefetchStride = 1024;205 MaxPrefetchIterationsAhead = 4;206 VScaleForTuning = 4;207 break;208 case MONAKA:209 VScaleForTuning = 2;210 break;211 case AppleA7:212 case AppleA10:213 case AppleA11:214 case AppleA12:215 case AppleA13:216 case AppleA14:217 case AppleA15:218 case AppleA16:219 case AppleA17:220 case AppleM4:221 CacheLineSize = 64;222 PrefetchDistance = 280;223 MinPrefetchStride = 2048;224 MaxPrefetchIterationsAhead = 3;225 switch (ARMProcFamily) {226 case AppleA14:227 case AppleA15:228 case AppleA16:229 case AppleA17:230 case AppleM4:231 MaxInterleaveFactor = 4;232 break;233 default:234 break;235 }236 break;237 case ExynosM3:238 MaxInterleaveFactor = 4;239 MaxJumpTableSize = 20;240 PrefFunctionAlignment = Align(32);241 PrefLoopAlignment = Align(16);242 break;243 case Falkor:244 MaxInterleaveFactor = 4;245 // FIXME: remove this to enable 64-bit SLP if performance looks good.246 MinVectorRegisterBitWidth = 128;247 CacheLineSize = 128;248 PrefetchDistance = 820;249 MinPrefetchStride = 2048;250 MaxPrefetchIterationsAhead = 8;251 break;252 case Kryo:253 MaxInterleaveFactor = 4;254 VectorInsertExtractBaseCost = 2;255 CacheLineSize = 128;256 PrefetchDistance = 740;257 MinPrefetchStride = 1024;258 MaxPrefetchIterationsAhead = 11;259 // FIXME: remove this to enable 64-bit SLP if performance looks good.260 MinVectorRegisterBitWidth = 128;261 break;262 case NeoverseE1:263 PrefFunctionAlignment = Align(8);264 break;265 case NeoverseN1:266 PrefFunctionAlignment = Align(16);267 PrefLoopAlignment = Align(32);268 MaxBytesForLoopAlignment = 16;269 break;270 case NeoverseV2:271 case NeoverseV3:272 CacheLineSize = 64;273 EpilogueVectorizationMinVF = 8;274 MaxInterleaveFactor = 4;275 ScatterOverhead = 13;276 [[fallthrough]];277 case NeoverseN2:278 case NeoverseN3:279 PrefFunctionAlignment = Align(16);280 PrefLoopAlignment = Align(32);281 MaxBytesForLoopAlignment = 16;282 VScaleForTuning = 1;283 break;284 case NeoverseV1:285 PrefFunctionAlignment = Align(16);286 PrefLoopAlignment = Align(32);287 MaxBytesForLoopAlignment = 16;288 VScaleForTuning = 2;289 DefaultSVETFOpts = TailFoldingOpts::Simple;290 break;291 case Neoverse512TVB:292 PrefFunctionAlignment = Align(16);293 VScaleForTuning = 1;294 MaxInterleaveFactor = 4;295 break;296 case Saphira:297 MaxInterleaveFactor = 4;298 // FIXME: remove this to enable 64-bit SLP if performance looks good.299 MinVectorRegisterBitWidth = 128;300 break;301 case ThunderX2T99:302 CacheLineSize = 64;303 PrefFunctionAlignment = Align(8);304 PrefLoopAlignment = Align(4);305 MaxInterleaveFactor = 4;306 PrefetchDistance = 128;307 MinPrefetchStride = 1024;308 MaxPrefetchIterationsAhead = 4;309 // FIXME: remove this to enable 64-bit SLP if performance looks good.310 MinVectorRegisterBitWidth = 128;311 break;312 case ThunderX:313 case ThunderXT88:314 case ThunderXT81:315 case ThunderXT83:316 CacheLineSize = 128;317 PrefFunctionAlignment = Align(8);318 PrefLoopAlignment = Align(4);319 // FIXME: remove this to enable 64-bit SLP if performance looks good.320 MinVectorRegisterBitWidth = 128;321 break;322 case TSV110:323 CacheLineSize = 64;324 PrefFunctionAlignment = Align(16);325 PrefLoopAlignment = Align(4);326 break;327 case ThunderX3T110:328 CacheLineSize = 64;329 PrefFunctionAlignment = Align(16);330 PrefLoopAlignment = Align(4);331 MaxInterleaveFactor = 4;332 PrefetchDistance = 128;333 MinPrefetchStride = 1024;334 MaxPrefetchIterationsAhead = 4;335 // FIXME: remove this to enable 64-bit SLP if performance looks good.336 MinVectorRegisterBitWidth = 128;337 break;338 case Ampere1:339 case Ampere1A:340 case Ampere1B:341 CacheLineSize = 64;342 PrefFunctionAlignment = Align(64);343 PrefLoopAlignment = Align(64);344 MaxInterleaveFactor = 4;345 break;346 case Oryon:347 CacheLineSize = 64;348 PrefFunctionAlignment = Align(16);349 MaxInterleaveFactor = 4;350 PrefetchDistance = 128;351 MinPrefetchStride = 1024;352 break;353 case Olympus:354 EpilogueVectorizationMinVF = 8;355 MaxInterleaveFactor = 4;356 ScatterOverhead = 13;357 PrefFunctionAlignment = Align(16);358 PrefLoopAlignment = Align(32);359 MaxBytesForLoopAlignment = 16;360 VScaleForTuning = 1;361 break;362 }363 364 if (AArch64MinimumJumpTableEntries.getNumOccurrences() > 0 || !HasMinSize)365 MinimumJumpTableEntries = AArch64MinimumJumpTableEntries;366 if (VScaleForTuningOpt.getNumOccurrences() > 0)367 VScaleForTuning = VScaleForTuningOpt;368}369 370AArch64Subtarget::AArch64Subtarget(const Triple &TT, StringRef CPU,371 StringRef TuneCPU, StringRef FS,372 const TargetMachine &TM, bool LittleEndian,373 unsigned MinSVEVectorSizeInBitsOverride,374 unsigned MaxSVEVectorSizeInBitsOverride,375 bool IsStreaming, bool IsStreamingCompatible,376 bool HasMinSize)377 : AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),378 ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),379 ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()),380 CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),381 IsLittle(LittleEndian), IsStreaming(IsStreaming),382 IsStreamingCompatible(IsStreamingCompatible),383 StreamingHazardSize(384 AArch64StreamingHazardSize.getNumOccurrences() > 0385 ? std::optional<unsigned>(AArch64StreamingHazardSize)386 : std::nullopt),387 MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),388 MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),389 InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU, HasMinSize)),390 TLInfo(TM, *this) {391 if (AArch64::isX18ReservedByDefault(TT))392 ReserveXRegister.set(18);393 394 CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));395 InlineAsmLoweringInfo.reset(new InlineAsmLowering(getTargetLowering()));396 Legalizer.reset(new AArch64LegalizerInfo(*this));397 398 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());399 400 // FIXME: At this point, we can't rely on Subtarget having RBI.401 // It's awkward to mix passing RBI and the Subtarget; should we pass402 // TII/TRI as well?403 InstSelector.reset(createAArch64InstructionSelector(404 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));405 406 RegBankInfo.reset(RBI);407 408 auto TRI = getRegisterInfo();409 StringSet<> ReservedRegNames(llvm::from_range, ReservedRegsForRA);410 for (unsigned i = 0; i < 29; ++i) {411 if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i)))412 ReserveXRegisterForRA.set(i);413 }414 // X30 is named LR, so we can't use TRI->getName to check X30.415 if (ReservedRegNames.count("X30") || ReservedRegNames.count("LR"))416 ReserveXRegisterForRA.set(30);417 // X29 is named FP, so we can't use TRI->getName to check X29.418 if (ReservedRegNames.count("X29") || ReservedRegNames.count("FP"))419 ReserveXRegisterForRA.set(29);420 421 EnableSubregLiveness = EnableSubregLivenessTracking.getValue();422}423 424const CallLowering *AArch64Subtarget::getCallLowering() const {425 return CallLoweringInfo.get();426}427 428const InlineAsmLowering *AArch64Subtarget::getInlineAsmLowering() const {429 return InlineAsmLoweringInfo.get();430}431 432InstructionSelector *AArch64Subtarget::getInstructionSelector() const {433 return InstSelector.get();434}435 436const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {437 return Legalizer.get();438}439 440const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {441 return RegBankInfo.get();442}443 444/// Find the target operand flags that describe how a global value should be445/// referenced for the current subtarget.446unsigned447AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,448 const TargetMachine &TM) const {449 // MachO large model always goes via a GOT, simply to get a single 8-byte450 // absolute relocation on all global addresses.451 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())452 return AArch64II::MO_GOT;453 454 // All globals dynamically protected by MTE must have their address tags455 // synthesized. This is done by having the loader stash the tag in the GOT456 // entry. Force all tagged globals (even ones with internal linkage) through457 // the GOT.458 if (GV->isTagged())459 return AArch64II::MO_GOT;460 461 if (!TM.shouldAssumeDSOLocal(GV)) {462 if (GV->hasDLLImportStorageClass()) {463 return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;464 }465 if (getTargetTriple().isOSWindows())466 return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;467 return AArch64II::MO_GOT;468 }469 470 // The small code model's direct accesses use ADRP, which cannot471 // necessarily produce the value 0 (if the code is above 4GB).472 // Same for the tiny code model, where we have a pc relative LDR.473 if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&474 GV->hasExternalWeakLinkage())475 return AArch64II::MO_GOT;476 477 // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate478 // that their nominal addresses are tagged and outside of the code model. In479 // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the480 // tag if necessary based on MO_TAGGED.481 if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))482 return AArch64II::MO_NC | AArch64II::MO_TAGGED;483 484 return AArch64II::MO_NO_FLAG;485}486 487unsigned AArch64Subtarget::classifyGlobalFunctionReference(488 const GlobalValue *GV, const TargetMachine &TM) const {489 // MachO large model always goes via a GOT, because we don't have the490 // relocations available to do anything else..491 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&492 !GV->hasInternalLinkage())493 return AArch64II::MO_GOT;494 495 // NonLazyBind goes via GOT unless we know it's available locally.496 auto *F = dyn_cast<Function>(GV);497 if ((!isTargetMachO() || MachOUseNonLazyBind) && F &&498 F->hasFnAttribute(Attribute::NonLazyBind) && !TM.shouldAssumeDSOLocal(GV))499 return AArch64II::MO_GOT;500 501 if (getTargetTriple().isOSWindows()) {502 if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy()) {503 if (GV->hasDLLImportStorageClass()) {504 // On Arm64EC, if we're calling a symbol from the import table505 // directly, use MO_ARM64EC_CALLMANGLE.506 return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT |507 AArch64II::MO_ARM64EC_CALLMANGLE;508 }509 if (GV->hasExternalLinkage()) {510 // If we're calling a symbol directly, use the mangled form in the511 // call instruction.512 return AArch64II::MO_ARM64EC_CALLMANGLE;513 }514 }515 516 // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB.517 return ClassifyGlobalReference(GV, TM);518 }519 520 return AArch64II::MO_NO_FLAG;521}522 523void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,524 const SchedRegion &Region) const {525 // LNT run (at least on Cyclone) showed reasonably significant gains for526 // bi-directional scheduling. 253.perlbmk.527 Policy.OnlyTopDown = false;528 Policy.OnlyBottomUp = false;529 // Enabling or Disabling the latency heuristic is a close call: It seems to530 // help nearly no benchmark on out-of-order architectures, on the other hand531 // it regresses register pressure on a few benchmarking.532 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;533}534 535void AArch64Subtarget::adjustSchedDependency(536 SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep,537 const TargetSchedModel *SchedModel) const {538 if (!SchedModel || Dep.getKind() != SDep::Kind::Data || !Dep.getReg() ||539 !Def->isInstr() || !Use->isInstr() ||540 (Def->getInstr()->getOpcode() != TargetOpcode::BUNDLE &&541 Use->getInstr()->getOpcode() != TargetOpcode::BUNDLE))542 return;543 544 // If the Def is a BUNDLE, find the last instruction in the bundle that defs545 // the register.546 const MachineInstr *DefMI = Def->getInstr();547 if (DefMI->getOpcode() == TargetOpcode::BUNDLE) {548 Register Reg = DefMI->getOperand(DefOpIdx).getReg();549 for (const auto &Op : const_mi_bundle_ops(*DefMI)) {550 if (Op.isReg() && Op.isDef() && Op.getReg() == Reg) {551 DefMI = Op.getParent();552 DefOpIdx = Op.getOperandNo();553 }554 }555 }556 557 // If the Use is a BUNDLE, find the first instruction that uses the Reg.558 const MachineInstr *UseMI = Use->getInstr();559 if (UseMI->getOpcode() == TargetOpcode::BUNDLE) {560 Register Reg = UseMI->getOperand(UseOpIdx).getReg();561 for (const auto &Op : const_mi_bundle_ops(*UseMI)) {562 if (Op.isReg() && Op.isUse() && Op.getReg() == Reg) {563 UseMI = Op.getParent();564 UseOpIdx = Op.getOperandNo();565 break;566 }567 }568 }569 570 Dep.setLatency(571 SchedModel->computeOperandLatency(DefMI, DefOpIdx, UseMI, UseOpIdx));572}573 574bool AArch64Subtarget::enableEarlyIfConversion() const {575 return EnableEarlyIfConvert;576}577 578bool AArch64Subtarget::supportsAddressTopByteIgnored() const {579 if (!UseAddressTopByteIgnored)580 return false;581 582 if (TargetTriple.isDriverKit())583 return true;584 if (TargetTriple.isiOS()) {585 return TargetTriple.getiOSVersion() >= VersionTuple(8);586 }587 588 return false;589}590 591std::unique_ptr<PBQPRAConstraint>592AArch64Subtarget::getCustomPBQPConstraints() const {593 return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;594}595 596void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {597 // We usually compute max call frame size after ISel. Do the computation now598 // if the .mir file didn't specify it. Note that this will probably give you599 // bogus values after PEI has eliminated the callframe setup/destroy pseudo600 // instructions, specify explicitly if you need it to be correct.601 MachineFrameInfo &MFI = MF.getFrameInfo();602 if (!MFI.isMaxCallFrameSizeComputed())603 MFI.computeMaxCallFrameSize(MF);604}605 606bool AArch64Subtarget::useAA() const { return UseAA; }607 608bool AArch64Subtarget::useScalarIncVL() const {609 // If SVE2 or SME is present (we are not SVE-1 only) and UseScalarIncVL610 // is not otherwise set, enable it by default.611 if (UseScalarIncVL.getNumOccurrences())612 return UseScalarIncVL;613 return hasSVE2() || hasSME();614}615 616// If return address signing is enabled, tail calls are emitted as follows:617//618// ```619// <authenticate LR>620// <check LR>621// TCRETURN ; the callee may sign and spill the LR in its prologue622// ```623//624// LR may require explicit checking because if FEAT_FPAC is not implemented625// and LR was tampered with, then `<authenticate LR>` will not generate an626// exception on its own. Later, if the callee spills the signed LR value and627// neither FEAT_PAuth2 nor FEAT_EPAC are implemented, the valid PAC replaces628// the higher bits of LR thus hiding the authentication failure.629AArch64PAuth::AuthCheckMethod AArch64Subtarget::getAuthenticatedLRCheckMethod(630 const MachineFunction &MF) const {631 // TODO: Check subtarget for the scheme. Present variant is a default for632 // pauthtest ABI.633 if (MF.getFunction().hasFnAttribute("ptrauth-returns") &&634 MF.getFunction().hasFnAttribute("ptrauth-auth-traps"))635 return AArch64PAuth::AuthCheckMethod::HighBitsNoTBI;636 if (AuthenticatedLRCheckMethod.getNumOccurrences())637 return AuthenticatedLRCheckMethod;638 639 // At now, use None by default because checks may introduce an unexpected640 // performance regression or incompatibility with execute-only mappings.641 return AArch64PAuth::AuthCheckMethod::None;642}643 644std::optional<uint16_t>645AArch64Subtarget::getPtrAuthBlockAddressDiscriminatorIfEnabled(646 const Function &ParentFn) const {647 if (!ParentFn.hasFnAttribute("ptrauth-indirect-gotos"))648 return std::nullopt;649 // We currently have one simple mechanism for all targets.650 // This isn't ABI, so we can always do better in the future.651 return getPointerAuthStableSipHash(652 (Twine(ParentFn.getName()) + " blockaddress").str());653}654 655bool AArch64Subtarget::isX16X17Safer() const {656 // The Darwin kernel implements special protections for x16 and x17 so we657 // should prefer to use those registers on that platform.658 return isTargetDarwin();659}660 661bool AArch64Subtarget::enableMachinePipeliner() const {662 return getSchedModel().hasInstrSchedModel();663}664