2873 lines · plain
1//===- AArch64SystemOperands.td ----------------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the symbolic operands permitted for various kinds of10// AArch64 system instruction.11//12//===----------------------------------------------------------------------===//13 14include "llvm/TableGen/SearchableTable.td"15 16//===----------------------------------------------------------------------===//17// Features that, for the compiler, only enable system operands and PStates18//===----------------------------------------------------------------------===//19 20def HasCCPP : Predicate<"Subtarget->hasCCPP()">,21 AssemblerPredicateWithAll<(all_of FeatureCCPP), "ccpp">;22 23def HasPAN : Predicate<"Subtarget->hasPAN()">,24 AssemblerPredicateWithAll<(all_of FeaturePAN),25 "ARM v8.1 Privileged Access-Never extension">;26 27def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">,28 AssemblerPredicateWithAll<(all_of FeaturePsUAO),29 "ARM v8.2 UAO PState extension (psuao)">;30 31def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">,32 AssemblerPredicateWithAll<(all_of FeaturePAN_RWV),33 "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">;34 35def HasCONTEXTIDREL236 : Predicate<"Subtarget->hasCONTEXTIDREL2()">,37 AssemblerPredicateWithAll<(all_of FeatureCONTEXTIDREL2),38 "Target contains CONTEXTIDR_EL2 RW operand">;39 40//===----------------------------------------------------------------------===//41// AT (address translate) instruction options.42//===----------------------------------------------------------------------===//43 44class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm,45 bits<3> op2> {46 string Name = name;47 bits<14> Encoding;48 let Encoding{13-11} = op1;49 let Encoding{10-7} = crn;50 let Encoding{6-3} = crm;51 let Encoding{2-0} = op2;52 code Requires = [{ {} }];53}54 55def ATValues : GenericEnum {56 let FilterClass = "AT";57 let NameField = "Name";58 let ValueField = "Encoding";59}60 61def ATsList : GenericTable {62 let FilterClass = "AT";63 let Fields = ["Name", "Encoding", "Requires"];64 65 let PrimaryKey = ["Encoding"];66 let PrimaryKeyName = "lookupATByEncoding";67}68 69def lookupATByName : SearchIndex {70 let Table = ATsList;71 let Key = ["Name"];72}73 74def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>;75def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>;76def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>;77def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>;78def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>;79def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>;80def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;81def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>;82def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>;83def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>;84def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>;85def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>;86 87let Requires = [{ {AArch64::FeaturePAN_RWV} }] in {88def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;89def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;90}91 92// v8.9a/v9.4a FEAT_ATS1A93def : AT<"S1E1A", 0b000, 0b0111, 0b1001, 0b010>;94def : AT<"S1E2A", 0b100, 0b0111, 0b1001, 0b010>;95def : AT<"S1E3A", 0b110, 0b0111, 0b1001, 0b010>;96 97//===----------------------------------------------------------------------===//98// DMB/DSB (data barrier) instruction options.99//===----------------------------------------------------------------------===//100 101class DB<string name, bits<4> encoding> {102 string Name = name;103 bits<4> Encoding = encoding;104}105 106def DBValues : GenericEnum {107 let FilterClass = "DB";108 let NameField = "Name";109 let ValueField = "Encoding";110}111 112def DBsList : GenericTable {113 let FilterClass = "DB";114 let Fields = ["Name", "Encoding"];115 116 let PrimaryKey = ["Encoding"];117 let PrimaryKeyName = "lookupDBByEncoding";118}119 120def lookupDBByName : SearchIndex {121 let Table = DBsList;122 let Key = ["Name"];123}124 125def : DB<"oshld", 0x1>;126def : DB<"oshst", 0x2>;127def : DB<"osh", 0x3>;128def : DB<"nshld", 0x5>;129def : DB<"nshst", 0x6>;130def : DB<"nsh", 0x7>;131def : DB<"ishld", 0x9>;132def : DB<"ishst", 0xa>;133def : DB<"ish", 0xb>;134def : DB<"ld", 0xd>;135def : DB<"st", 0xe>;136def : DB<"sy", 0xf>;137 138class DBnXS<string name, bits<4> encoding, bits<5> immValue> {139 string Name = name;140 bits<4> Encoding = encoding;141 bits<5> ImmValue = immValue;142 code Requires = [{ {AArch64::FeatureXS} }];143}144 145def DBnXSValues : GenericEnum {146 let FilterClass = "DBnXS";147 let NameField = "Name";148 let ValueField = "Encoding";149}150 151def DBnXSsList : GenericTable {152 let FilterClass = "DBnXS";153 let Fields = ["Name", "Encoding", "ImmValue", "Requires"];154 155 let PrimaryKey = ["Encoding"];156 let PrimaryKeyName = "lookupDBnXSByEncoding";157}158 159def lookupDBnXSByName : SearchIndex {160 let Table = DBnXSsList;161 let Key = ["Name"];162}163 164def lookupDBnXSByImmValue : SearchIndex {165 let Table = DBnXSsList;166 let Key = ["ImmValue"];167}168 169def : DBnXS<"oshnxs", 0x3, 0x10>;170def : DBnXS<"nshnxs", 0x7, 0x14>;171def : DBnXS<"ishnxs", 0xb, 0x18>;172def : DBnXS<"synxs", 0xf, 0x1c>;173 174//===----------------------------------------------------------------------===//175// DC (data cache maintenance) instruction options.176//===----------------------------------------------------------------------===//177 178class DC<string name, bits<3> op1, bits<4> crn, bits<4> crm,179 bits<3> op2> {180 string Name = name;181 bits<14> Encoding;182 let Encoding{13-11} = op1;183 let Encoding{10-7} = crn;184 let Encoding{6-3} = crm;185 let Encoding{2-0} = op2;186 code Requires = [{ {} }];187}188 189def DCValues : GenericEnum {190 let FilterClass = "DC";191 let NameField = "Name";192 let ValueField = "Encoding";193}194 195def DCsList : GenericTable {196 let FilterClass = "DC";197 let Fields = ["Name", "Encoding", "Requires"];198 199 let PrimaryKey = ["Encoding"];200 let PrimaryKeyName = "lookupDCByEncoding";201}202 203def lookupDCByName : SearchIndex {204 let Table = DCsList;205 let Key = ["Name"];206}207 208// Op1 CRn CRm Op2209def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>;210def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>;211def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;212def : DC<"CVAC", 0b011, 0b0111, 0b1010, 0b001>;213def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>;214def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>;215def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>;216def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>;217 218let Requires = [{ {AArch64::FeatureCCPP} }] in219def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>;220 221let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in222def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>;223 224let Requires = [{ {AArch64::FeatureMTE} }] in {225def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>;226def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>;227def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>;228def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>;229def : DC<"CGVAC", 0b011, 0b0111, 0b1010, 0b011>;230def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>;231def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>;232def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>;233def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>;234def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>;235def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>;236def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>;237def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>;238def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>;239def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>;240def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>;241def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>;242def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>;243}244 245let Requires = [{ {AArch64::FeatureMTETC} }] in {246def : DC<"ZGBVA", 0b011, 0b0111, 0b0100, 0b101>;247def : DC<"GBVA", 0b011, 0b0111, 0b0100, 0b111>;248}249 250let Requires = [{ {AArch64::FeatureMEC} }] in {251def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b000>;252def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>;253}254 255let Requires = [{ {AArch64::FeatureRME} }] in {256def : DC<"CIGDPAPA", 0b110, 0b0111, 0b1110, 0b101>;257def : DC<"CIPAPA", 0b110, 0b0111, 0b1110, 0b001>;258}259 260let Requires = [{ {AArch64::FeatureOCCMO} }] in {261// Outer cacheable CMO (FEAT_OCCMO)262def : DC<"CIVAOC", 0b011, 0b0111, 0b1111, 0b000>;263def : DC<"CVAOC", 0b011, 0b0111, 0b1011, 0b000>;264}265 266let Requires = [{ {AArch64::FeatureOCCMO, AArch64::FeatureMTE} }] in {267def : DC<"CIGDVAOC", 0b011, 0b0111, 0b1111, 0b111>;268def : DC<"CGDVAOC", 0b011, 0b0111, 0b1011, 0b111>;269}270 271//===----------------------------------------------------------------------===//272// IC (instruction cache maintenance) instruction options.273//===----------------------------------------------------------------------===//274 275class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2,276 bit needsreg> {277 string Name = name;278 bits<14> Encoding;279 let Encoding{13-11} = op1;280 let Encoding{10-7} = crn;281 let Encoding{6-3} = crm;282 let Encoding{2-0} = op2;283 bit NeedsReg = needsreg;284}285 286def ICValues : GenericEnum {287 let FilterClass = "IC";288 let NameField = "Name";289 let ValueField = "Encoding";290}291 292def ICsList : GenericTable {293 let FilterClass = "IC";294 let Fields = ["Name", "Encoding", "NeedsReg"];295 296 let PrimaryKey = ["Encoding"];297 let PrimaryKeyName = "lookupICByEncoding";298}299 300def lookupICByName : SearchIndex {301 let Table = ICsList;302 let Key = ["Name"];303}304 305def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>;306def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>;307def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>;308 309//===----------------------------------------------------------------------===//310// ISB (instruction-fetch barrier) instruction options.311//===----------------------------------------------------------------------===//312 313class ISB<string name, bits<4> encoding> {314 string Name = name;315 bits<4> Encoding;316 let Encoding = encoding;317}318 319def ISBValues : GenericEnum {320 let FilterClass = "ISB";321 let NameField = "Name";322 let ValueField = "Encoding";323}324 325def ISBsList : GenericTable {326 let FilterClass = "ISB";327 let Fields = ["Name", "Encoding"];328 329 let PrimaryKey = ["Encoding"];330 let PrimaryKeyName = "lookupISBByEncoding";331}332 333def lookupISBByName : SearchIndex {334 let Table = ISBsList;335 let Key = ["Name"];336}337 338def : ISB<"sy", 0xf>;339 340//===----------------------------------------------------------------------===//341// TSB (Trace synchronization barrier) instruction options.342//===----------------------------------------------------------------------===//343 344class TSB<string name, bits<4> encoding> {345 string Name = name;346 bits<4> Encoding;347 let Encoding = encoding;348 349 code Requires = [{ {AArch64::FeatureTRACEV8_4} }];350}351 352def TSBValues : GenericEnum {353 let FilterClass = "TSB";354 let NameField = "Name";355 let ValueField = "Encoding";356}357 358def TSBsList : GenericTable {359 let FilterClass = "TSB";360 let Fields = ["Name", "Encoding", "Requires"];361 362 let PrimaryKey = ["Encoding"];363 let PrimaryKeyName = "lookupTSBByEncoding";364}365 366def lookupTSBByName : SearchIndex {367 let Table = TSBsList;368 let Key = ["Name"];369}370 371def : TSB<"csync", 2>;372 373//===----------------------------------------------------------------------===//374// PRFM (prefetch) instruction options.375//===----------------------------------------------------------------------===//376 377class PRFM<string type, bits<2> type_encoding,378 string target, bits<2> target_encoding,379 string policy, bits<1> policy_encoding> {380 string Name = type # target # policy;381 bits<5> Encoding;382 let Encoding{4-3} = type_encoding;383 let Encoding{2-1} = target_encoding;384 let Encoding{0} = policy_encoding;385 386 code Requires = [{ {} }];387}388 389def PRFMValues : GenericEnum {390 let FilterClass = "PRFM";391 let NameField = "Name";392 let ValueField = "Encoding";393}394 395def PRFMsList : GenericTable {396 let FilterClass = "PRFM";397 let Fields = ["Name", "Encoding", "Requires"];398 399 let PrimaryKey = ["Encoding"];400 let PrimaryKeyName = "lookupPRFMByEncoding";401}402 403def lookupPRFMByName : SearchIndex {404 let Table = PRFMsList;405 let Key = ["Name"];406}407 408def : PRFM<"pld", 0b00, "l1", 0b00, "keep", 0b0>;409def : PRFM<"pld", 0b00, "l1", 0b00, "strm", 0b1>;410def : PRFM<"pld", 0b00, "l2", 0b01, "keep", 0b0>;411def : PRFM<"pld", 0b00, "l2", 0b01, "strm", 0b1>;412def : PRFM<"pld", 0b00, "l3", 0b10, "keep", 0b0>;413def : PRFM<"pld", 0b00, "l3", 0b10, "strm", 0b1>;414let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in {415def : PRFM<"pld", 0b00, "slc", 0b11, "keep", 0b0>;416def : PRFM<"pld", 0b00, "slc", 0b11, "strm", 0b1>;417}418def : PRFM<"pli", 0b01, "l1", 0b00, "keep", 0b0>;419def : PRFM<"pli", 0b01, "l1", 0b00, "strm", 0b1>;420def : PRFM<"pli", 0b01, "l2", 0b01, "keep", 0b0>;421def : PRFM<"pli", 0b01, "l2", 0b01, "strm", 0b1>;422def : PRFM<"pli", 0b01, "l3", 0b10, "keep", 0b0>;423def : PRFM<"pli", 0b01, "l3", 0b10, "strm", 0b1>;424let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in {425def : PRFM<"pli", 0b01, "slc", 0b11, "keep", 0b0>;426def : PRFM<"pli", 0b01, "slc", 0b11, "strm", 0b1>;427}428def : PRFM<"pst", 0b10, "l1", 0b00, "keep", 0b0>;429def : PRFM<"pst", 0b10, "l1", 0b00, "strm", 0b1>;430def : PRFM<"pst", 0b10, "l2", 0b01, "keep", 0b0>;431def : PRFM<"pst", 0b10, "l2", 0b01, "strm", 0b1>;432def : PRFM<"pst", 0b10, "l3", 0b10, "keep", 0b0>;433def : PRFM<"pst", 0b10, "l3", 0b10, "strm", 0b1>;434let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in {435def : PRFM<"pst", 0b10, "slc", 0b11, "keep", 0b0>;436def : PRFM<"pst", 0b10, "slc", 0b11, "strm", 0b1>;437}438 439//===----------------------------------------------------------------------===//440// SVE Prefetch instruction options.441//===----------------------------------------------------------------------===//442 443class SVEPRFM<string name, bits<4> encoding> {444 string Name = name;445 bits<4> Encoding;446 let Encoding = encoding;447 code Requires = [{ {} }];448}449 450def SVEPRFMValues : GenericEnum {451 let FilterClass = "SVEPRFM";452 let NameField = "Name";453 let ValueField = "Encoding";454}455 456def SVEPRFMsList : GenericTable {457 let FilterClass = "SVEPRFM";458 let Fields = ["Name", "Encoding", "Requires"];459 460 let PrimaryKey = ["Encoding"];461 let PrimaryKeyName = "lookupSVEPRFMByEncoding";462}463 464def lookupSVEPRFMByName : SearchIndex {465 let Table = SVEPRFMsList;466 let Key = ["Name"];467}468 469let Requires = [{ {AArch64::FeatureSVE} }] in {470def : SVEPRFM<"pldl1keep", 0x00>;471def : SVEPRFM<"pldl1strm", 0x01>;472def : SVEPRFM<"pldl2keep", 0x02>;473def : SVEPRFM<"pldl2strm", 0x03>;474def : SVEPRFM<"pldl3keep", 0x04>;475def : SVEPRFM<"pldl3strm", 0x05>;476def : SVEPRFM<"pstl1keep", 0x08>;477def : SVEPRFM<"pstl1strm", 0x09>;478def : SVEPRFM<"pstl2keep", 0x0a>;479def : SVEPRFM<"pstl2strm", 0x0b>;480def : SVEPRFM<"pstl3keep", 0x0c>;481def : SVEPRFM<"pstl3strm", 0x0d>;482}483 484//===----------------------------------------------------------------------===//485// RPRFM (prefetch) instruction options.486//===----------------------------------------------------------------------===//487 488class RPRFM<string name, bits<1> type_encoding, bits<5> policy_encoding> {489 string Name = name;490 bits<6> Encoding;491 let Encoding{0} = type_encoding;492 let Encoding{5-1} = policy_encoding;493 code Requires = [{ {} }];494}495 496def RPRFMValues : GenericEnum {497 let FilterClass = "RPRFM";498 let NameField = "Name";499 let ValueField = "Encoding";500}501 502def RPRFMsList : GenericTable {503 let FilterClass = "RPRFM";504 let Fields = ["Name", "Encoding", "Requires"];505}506 507def lookupRPRFMByName : SearchIndex {508 let Table = RPRFMsList;509 let Key = ["Name"];510}511 512def lookupRPRFMByEncoding : SearchIndex {513 let Table = RPRFMsList;514 let Key = ["Encoding"];515}516 517def : RPRFM<"pldkeep", 0b0, 0b00000>;518def : RPRFM<"pstkeep", 0b1, 0b00000>;519def : RPRFM<"pldstrm", 0b0, 0b00010>;520def : RPRFM<"pststrm", 0b1, 0b00010>;521 522//===----------------------------------------------------------------------===//523// SVE Predicate patterns524//===----------------------------------------------------------------------===//525 526class SVEPREDPAT<string name, bits<5> encoding> {527 string Name = name;528 bits<5> Encoding;529 let Encoding = encoding;530}531 532def SVEPREDPATValues : GenericEnum {533 let FilterClass = "SVEPREDPAT";534 let NameField = "Name";535 let ValueField = "Encoding";536}537 538def SVEPREDPATsList : GenericTable {539 let FilterClass = "SVEPREDPAT";540 let Fields = ["Name", "Encoding"];541 542 let PrimaryKey = ["Encoding"];543 let PrimaryKeyName = "lookupSVEPREDPATByEncoding";544}545 546def lookupSVEPREDPATByName : SearchIndex {547 let Table = SVEPREDPATsList;548 let Key = ["Name"];549}550 551def : SVEPREDPAT<"pow2", 0x00>;552def : SVEPREDPAT<"vl1", 0x01>;553def : SVEPREDPAT<"vl2", 0x02>;554def : SVEPREDPAT<"vl3", 0x03>;555def : SVEPREDPAT<"vl4", 0x04>;556def : SVEPREDPAT<"vl5", 0x05>;557def : SVEPREDPAT<"vl6", 0x06>;558def : SVEPREDPAT<"vl7", 0x07>;559def : SVEPREDPAT<"vl8", 0x08>;560def : SVEPREDPAT<"vl16", 0x09>;561def : SVEPREDPAT<"vl32", 0x0a>;562def : SVEPREDPAT<"vl64", 0x0b>;563def : SVEPREDPAT<"vl128", 0x0c>;564def : SVEPREDPAT<"vl256", 0x0d>;565def : SVEPREDPAT<"mul4", 0x1d>;566def : SVEPREDPAT<"mul3", 0x1e>;567def : SVEPREDPAT<"all", 0x1f>;568 569//===----------------------------------------------------------------------===//570// SVE Predicate-as-counter patterns571//===----------------------------------------------------------------------===//572 573class SVEVECLENSPECIFIER<string name, bits<1> encoding> {574 string Name = name;575 bits<1> Encoding;576 let Encoding = encoding;577}578 579def SVEVECLENSPECIFIERValues : GenericEnum {580 let FilterClass = "SVEVECLENSPECIFIER";581 let NameField = "Name";582 let ValueField = "Encoding";583}584 585def SVEVECLENSPECIFIERsList : GenericTable {586 let FilterClass = "SVEVECLENSPECIFIER";587 let Fields = ["Name", "Encoding"];588 589 let PrimaryKey = ["Encoding"];590 let PrimaryKeyName = "lookupSVEVECLENSPECIFIERByEncoding";591}592 593def lookupSVEVECLENSPECIFIERByName : SearchIndex {594 let Table = SVEVECLENSPECIFIERsList;595 let Key = ["Name"];596}597 598def : SVEVECLENSPECIFIER<"vlx2", 0x0>;599def : SVEVECLENSPECIFIER<"vlx4", 0x1>;600 601//===----------------------------------------------------------------------===//602// Exact FP Immediates.603//604// These definitions are used to create a lookup table with FP Immediates that605// is used for a few instructions that only accept a limited set of exact FP606// immediates values.607//===----------------------------------------------------------------------===//608class ExactFPImm<string name, string repr, bits<4> enum > {609 string Name = name;610 bits<4> Enum = enum;611 string Repr = repr;612}613 614def ExactFPImmValues : GenericEnum {615 let FilterClass = "ExactFPImm";616 let NameField = "Name";617 let ValueField = "Enum";618}619 620def ExactFPImmsList : GenericTable {621 let FilterClass = "ExactFPImm";622 let Fields = ["Enum", "Repr"];623}624 625def lookupExactFPImmByEnum : SearchIndex {626 let Table = ExactFPImmsList;627 let Key = ["Enum"];628}629 630def : ExactFPImm<"zero", "0.0", 0x0>;631def : ExactFPImm<"half", "0.5", 0x1>;632def : ExactFPImm<"one", "1.0", 0x2>;633def : ExactFPImm<"two", "2.0", 0x3>;634 635//===----------------------------------------------------------------------===//636// PState instruction options.637//===----------------------------------------------------------------------===//638 639class PStateImm0_15<string name, bits<3> op1, bits<3> op2> {640 string Name = name;641 bits<6> Encoding;642 let Encoding{5-3} = op1;643 let Encoding{2-0} = op2;644 code Requires = [{ {} }];645}646 647def PStateImm0_15Values : GenericEnum {648 let FilterClass = "PStateImm0_15";649 let NameField = "Name";650 let ValueField = "Encoding";651}652 653def PStateImm0_15sList : GenericTable {654 let FilterClass = "PStateImm0_15";655 let Fields = ["Name", "Encoding", "Requires"];656 657 let PrimaryKey = ["Encoding"];658 let PrimaryKeyName = "lookupPStateImm0_15ByEncoding";659}660 661def lookupPStateImm0_15ByName : SearchIndex {662 let Table = PStateImm0_15sList;663 let Key = ["Name"];664}665 666class PStateImm0_1<string name, bits<3> op1, bits<3> op2, bits<3> crm_high> {667 string Name = name;668 bits<9> Encoding;669 let Encoding{8-6} = crm_high;670 let Encoding{5-3} = op1;671 let Encoding{2-0} = op2;672 code Requires = [{ {} }];673}674 675def PStateImm0_1Values : GenericEnum {676 let FilterClass = "PStateImm0_1";677 let NameField = "Name";678 let ValueField = "Encoding";679}680 681def PStateImm0_1sList : GenericTable {682 let FilterClass = "PStateImm0_1";683 let Fields = ["Name", "Encoding", "Requires"];684 685 let PrimaryKey = ["Encoding"];686 let PrimaryKeyName = "lookupPStateImm0_1ByEncoding";687}688 689def lookupPStateImm0_1ByName : SearchIndex {690 let Table = PStateImm0_1sList;691 let Key = ["Name"];692}693 694// Name, Op1, Op2695def : PStateImm0_15<"SPSel", 0b000, 0b101>;696def : PStateImm0_15<"DAIFSet", 0b011, 0b110>;697def : PStateImm0_15<"DAIFClr", 0b011, 0b111>;698// v8.1a "Privileged Access Never" extension-specific PStates699let Requires = [{ {AArch64::FeaturePAN} }] in700def : PStateImm0_15<"PAN", 0b000, 0b100>;701 702// v8.2a "User Access Override" extension-specific PStates703let Requires = [{ {AArch64::FeaturePsUAO} }] in704def : PStateImm0_15<"UAO", 0b000, 0b011>;705// v8.4a timing insensitivity of data processing instructions706let Requires = [{ {AArch64::FeatureDIT} }] in707def : PStateImm0_15<"DIT", 0b011, 0b010>;708// v8.5a Spectre Mitigation709let Requires = [{ {AArch64::FeatureSSBS} }] in710def : PStateImm0_15<"SSBS", 0b011, 0b001>;711// v8.5a Memory Tagging Extension712let Requires = [{ {AArch64::FeatureMTE} }] in713def : PStateImm0_15<"TCO", 0b011, 0b100>;714// v8.8a Non-Maskable Interrupts715let Requires = [{ {AArch64::FeatureNMI} }] in716def : PStateImm0_1<"ALLINT", 0b001, 0b000, 0b000>;717// v9.4a Exception-based event profiling718// Name, Op1, Op2, Crm_high719def : PStateImm0_1<"PM", 0b001, 0b000, 0b001>;720 721//===----------------------------------------------------------------------===//722// SVCR instruction options.723//===----------------------------------------------------------------------===//724 725class SVCR<string name, bits<3> encoding> {726 string Name = name;727 bits<3> Encoding;728 let Encoding = encoding;729 code Requires = [{ {} }];730}731 732def SVCRValues : GenericEnum {733 let FilterClass = "SVCR";734 let NameField = "Name";735 let ValueField = "Encoding";736}737 738def SVCRsList : GenericTable {739 let FilterClass = "SVCR";740 let Fields = ["Name", "Encoding", "Requires"];741 742 let PrimaryKey = ["Encoding"];743 let PrimaryKeyName = "lookupSVCRByEncoding";744}745 746def lookupSVCRByName : SearchIndex {747 let Table = SVCRsList;748 let Key = ["Name"];749}750 751let Requires = [{ {AArch64::FeatureSME} }] in {752def : SVCR<"SVCRSM", 0b001>;753def : SVCR<"SVCRZA", 0b010>;754def : SVCR<"SVCRSMZA", 0b011>;755}756 757//===----------------------------------------------------------------------===//758// PSB instruction options.759//===----------------------------------------------------------------------===//760 761class PSB<string name, bits<5> encoding> {762 string Name = name;763 bits<5> Encoding;764 let Encoding = encoding;765}766 767def PSBValues : GenericEnum {768 let FilterClass = "PSB";769 let NameField = "Name";770 let ValueField = "Encoding";771}772 773def PSBsList : GenericTable {774 let FilterClass = "PSB";775 let Fields = ["Name", "Encoding"];776 777 let PrimaryKey = ["Encoding"];778 let PrimaryKeyName = "lookupPSBByEncoding";779}780 781def lookupPSBByName : SearchIndex {782 let Table = PSBsList;783 let Key = ["Name"];784}785 786def : PSB<"csync", 0x11>;787 788//===----------------------------------------------------------------------===//789// BTI instruction options.790//===----------------------------------------------------------------------===//791 792class BTI<string name, bits<3> encoding> {793 string Name = name;794 bits<3> Encoding;795 let Encoding = encoding;796}797 798def BTIValues : GenericEnum {799 let FilterClass = "BTI";800 let NameField = "Name";801 let ValueField = "Encoding";802}803 804def BTIsList : GenericTable {805 let FilterClass = "BTI";806 let Fields = ["Name", "Encoding"];807 808 let PrimaryKey = ["Encoding"];809 let PrimaryKeyName = "lookupBTIByEncoding";810}811 812def lookupBTIByName : SearchIndex {813 let Table = BTIsList;814 let Key = ["Name"];815}816 817def : BTI<"r", 0b000>;818def : BTI<"c", 0b010>;819def : BTI<"j", 0b100>;820def : BTI<"jc", 0b110>;821 822//===----------------------------------------------------------------------===//823// CMHPriority instruction options.824//===----------------------------------------------------------------------===//825 826class CMHPriorityHint<string name, bits<1> encoding> : SearchableTable {827 let SearchableFields = ["Name", "Encoding"];828 let EnumValueField = "Encoding";829 830 string Name = name;831 bits<1> Encoding;832 let Encoding = encoding;833}834 835def : CMHPriorityHint<"ph", 0b1>;836 837 838//===----------------------------------------------------------------------===//839// TIndex instruction options.840//===----------------------------------------------------------------------===//841 842class TIndex<string name, bits<1> encoding> : SearchableTable {843 let SearchableFields = ["Name", "Encoding"];844 let EnumValueField = "Encoding";845 846 string Name = name;847 bits<1> Encoding;848 let Encoding = encoding;849}850 851def : TIndex<"nb", 0b1>;852 853 854//===----------------------------------------------------------------------===//855// TLBI (translation lookaside buffer invalidate) instruction options.856//===----------------------------------------------------------------------===//857 858class TLBICommon<string name, bits<3> op1, bits<4> crn, bits<4> crm,859 bits<3> op2, bit needsreg, bit optionalreg> {860 string Name = name;861 bits<14> Encoding;862 let Encoding{13-11} = op1;863 let Encoding{10-7} = crn;864 let Encoding{6-3} = crm;865 let Encoding{2-0} = op2;866 bit NeedsReg = needsreg;867 bit OptionalReg = optionalreg;868 list<string> Requires = [];869 list<string> ExtraRequires = [];870 code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }];871}872 873class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,874 bits<3> op2, bit needsreg, bit optionalreg>875 : TLBICommon<name, op1, crn, crm, op2, needsreg, optionalreg>;876 877class TLBIPEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,878 bits<3> op2, bit needsreg, bit optionalreg>879 : TLBICommon<name, op1, crn, crm, op2, needsreg, optionalreg>;880 881multiclass TLBITableBase {882 def NAME # Table : GenericTable {883 let FilterClass = NAME # "Entry";884 let CppTypeName = NAME;885 let Fields = ["Name", "Encoding", "NeedsReg", "OptionalReg", "RequiresStr"];886 let PrimaryKey = ["Encoding"];887 let PrimaryKeyName = "lookup" # NAME # "ByEncoding";888 }889 def lookup # NAME # ByName : SearchIndex {890 let Table = !cast<GenericTable>(NAME # "Table");891 let Key = ["Name"];892 }893}894 895defm TLBI : TLBITableBase;896defm TLBIP : TLBITableBase;897 898multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm,899 bits<3> op2, bit needsreg = 1, bit optionalreg = 0> {900 def : TLBIEntry<name, op1, crn, crm, op2, needsreg, optionalreg>;901 def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg, optionalreg> {902 let Encoding{7} = 1;903 let ExtraRequires = ["AArch64::FeatureXS"];904 }905 if !eq(hasTLBIP, true) then {906 def : TLBIPEntry<name, op1, crn, crm, op2, needsreg, optionalreg>;907 def : TLBIPEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg, optionalreg> {908 let Encoding{7} = 1;909 let ExtraRequires = ["AArch64::FeatureXS"];910 }911 }912}913 914// hasTLBIP op1 CRn CRm op2 needsreg, optreg915defm : TLBI<"IPAS2E1IS", 1, 0b100, 0b1000, 0b0000, 0b001>;916defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b0000, 0b101>;917defm : TLBI<"VMALLE1IS", 0, 0b000, 0b1000, 0b0011, 0b000, 0, 1>;918defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, 0, 1>;919defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, 0, 1>;920defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001>;921defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001>;922defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001>;923defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010>;924defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011>;925defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, 0, 1>;926defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101>;927defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101>;928defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101>;929defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, 0, 1>;930defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111>;931defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001>;932defm : TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101>;933defm : TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, 0, 0>;934defm : TLBI<"ALLE2", 0, 0b100, 0b1000, 0b0111, 0b000, 0, 0>;935defm : TLBI<"ALLE3", 0, 0b110, 0b1000, 0b0111, 0b000, 0, 0>;936defm : TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001>;937defm : TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001>;938defm : TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001>;939defm : TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010>;940defm : TLBI<"VAAE1", 1, 0b000, 0b1000, 0b0111, 0b011>;941defm : TLBI<"ALLE1", 0, 0b100, 0b1000, 0b0111, 0b100, 0, 0>;942defm : TLBI<"VALE1", 1, 0b000, 0b1000, 0b0111, 0b101>;943defm : TLBI<"VALE2", 1, 0b100, 0b1000, 0b0111, 0b101>;944defm : TLBI<"VALE3", 1, 0b110, 0b1000, 0b0111, 0b101>;945defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, 0, 0>;946defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111>;947 948// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)949let Requires = ["AArch64::FeatureTLB_RMI"] in {950// Armv8.4-A Outer Sharable TLB Maintenance instructions:951// hasTLBIP op1 CRn CRm op2 needsreg, optreg952defm : TLBI<"VMALLE1OS", 0, 0b000, 0b1000, 0b0001, 0b000, 0, 1>;953defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001>;954defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010>;955defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011>;956defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101>;957defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111>;958defm : TLBI<"IPAS2E1OS", 1, 0b100, 0b1000, 0b0100, 0b000>;959defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100>;960defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001>;961defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101>;962defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, 0, 1>;963defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001>;964defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101>;965defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, 0, 1>;966defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, 0, 1>;967defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, 0, 1>;968 969// Armv8.4-A TLB Range Maintenance instructions:970// hasTLBIP op1 CRn CRm op2971defm : TLBI<"RVAE1", 1, 0b000, 0b1000, 0b0110, 0b001>;972defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011>;973defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101>;974defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111>;975defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001>;976defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011>;977defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101>;978defm : TLBI<"RVAALE1IS", 1, 0b000, 0b1000, 0b0010, 0b111>;979defm : TLBI<"RVAE1OS", 1, 0b000, 0b1000, 0b0101, 0b001>;980defm : TLBI<"RVAAE1OS", 1, 0b000, 0b1000, 0b0101, 0b011>;981defm : TLBI<"RVALE1OS", 1, 0b000, 0b1000, 0b0101, 0b101>;982defm : TLBI<"RVAALE1OS", 1, 0b000, 0b1000, 0b0101, 0b111>;983defm : TLBI<"RIPAS2E1IS", 1, 0b100, 0b1000, 0b0000, 0b010>;984defm : TLBI<"RIPAS2LE1IS", 1, 0b100, 0b1000, 0b0000, 0b110>;985defm : TLBI<"RIPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b010>;986defm : TLBI<"RIPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b110>;987defm : TLBI<"RIPAS2E1OS", 1, 0b100, 0b1000, 0b0100, 0b011>;988defm : TLBI<"RIPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b111>;989defm : TLBI<"RVAE2", 1, 0b100, 0b1000, 0b0110, 0b001>;990defm : TLBI<"RVALE2", 1, 0b100, 0b1000, 0b0110, 0b101>;991defm : TLBI<"RVAE2IS", 1, 0b100, 0b1000, 0b0010, 0b001>;992defm : TLBI<"RVALE2IS", 1, 0b100, 0b1000, 0b0010, 0b101>;993defm : TLBI<"RVAE2OS", 1, 0b100, 0b1000, 0b0101, 0b001>;994defm : TLBI<"RVALE2OS", 1, 0b100, 0b1000, 0b0101, 0b101>;995defm : TLBI<"RVAE3", 1, 0b110, 0b1000, 0b0110, 0b001>;996defm : TLBI<"RVALE3", 1, 0b110, 0b1000, 0b0110, 0b101>;997defm : TLBI<"RVAE3IS", 1, 0b110, 0b1000, 0b0010, 0b001>;998defm : TLBI<"RVALE3IS", 1, 0b110, 0b1000, 0b0010, 0b101>;999defm : TLBI<"RVAE3OS", 1, 0b110, 0b1000, 0b0101, 0b001>;1000defm : TLBI<"RVALE3OS", 1, 0b110, 0b1000, 0b0101, 0b101>;1001} //FeatureTLB_RMI1002 1003// Armv9-A Realm Management Extension TLBI Instructions1004let Requires = ["AArch64::FeatureRME"] in {1005// hasTLBIP op1 CRn CRm op2 needsreg1006defm : TLBI<"RPAOS", 0, 0b110, 0b1000, 0b0100, 0b011>;1007defm : TLBI<"RPALOS", 0, 0b110, 0b1000, 0b0100, 0b111>;1008defm : TLBI<"PAALLOS", 0, 0b110, 0b1000, 0b0001, 0b100, 0, 0>;1009defm : TLBI<"PAALL", 0, 0b110, 0b1000, 0b0111, 0b100, 0, 0>;1010}1011 1012// Armv9.5-A TLBI VMALL for Dirty State1013let Requires = ["AArch64::FeatureTLBIW"] in {1014// hasTLBIP op1 CRn CRm op2 needsreg, optreg1015defm : TLBI<"VMALLWS2E1", 0, 0b100, 0b1000, 0b0110, 0b010, 0, 0>;1016defm : TLBI<"VMALLWS2E1IS", 0, 0b100, 0b1000, 0b0010, 0b010, 0, 1>;1017defm : TLBI<"VMALLWS2E1OS", 0, 0b100, 0b1000, 0b0101, 0b010, 0, 1>;1018}1019 1020//===----------------------------------------------------------------------===//1021// MRS/MSR (system register read/write) instruction options.1022//===----------------------------------------------------------------------===//1023 1024class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,1025 bits<3> op2> {1026 string Name = name;1027 bits<16> Encoding;1028 let Encoding{15-14} = op0;1029 let Encoding{13-11} = op1;1030 let Encoding{10-7} = crn;1031 let Encoding{6-3} = crm;1032 let Encoding{2-0} = op2;1033 bit Readable = ?;1034 bit Writeable = ?;1035 code Requires = [{ {} }];1036}1037 1038def SysRegValues : GenericEnum {1039 let FilterClass = "SysReg";1040 let NameField = "Name";1041 let ValueField = "Encoding";1042}1043 1044def SysRegsList : GenericTable {1045 let FilterClass = "SysReg";1046 let Fields = ["Name", "Encoding", "Readable", "Writeable", "Requires"];1047 1048 let PrimaryKey = ["Encoding"];1049 let PrimaryKeyName = "lookupSysRegByEncoding";1050 let PrimaryKeyReturnRange = true;1051}1052 1053def lookupSysRegByName : SearchIndex {1054 let Table = SysRegsList;1055 let Key = ["Name"];1056}1057 1058class RWSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,1059 bits<3> op2>1060 : SysReg<name, op0, op1, crn, crm, op2> {1061 let Readable = 1;1062 let Writeable = 1;1063}1064 1065class ROSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,1066 bits<3> op2>1067 : SysReg<name, op0, op1, crn, crm, op2> {1068 let Readable = 1;1069 let Writeable = 0;1070}1071 1072class WOSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,1073 bits<3> op2>1074 : SysReg<name, op0, op1, crn, crm, op2> {1075 let Readable = 0;1076 let Writeable = 1;1077}1078 1079//===----------------------1080// Read-only regs1081//===----------------------1082 1083// Op0 Op1 CRn CRm Op21084def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;1085def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;1086def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;1087def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>;1088def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>;1089def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;1090def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;1091def : ROSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;1092def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;1093def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;1094 1095//v8.3 CCIDX - extending the CCsIDr number of sets1096def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {1097 let Requires = [{ {AArch64::FeatureCCIDX} }];1098}1099def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;1100def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>;1101def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>;1102def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>;1103def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>;1104def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>;1105def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>;1106def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>;1107def : ROSysReg<"ID_PFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b100> {1108 let Requires = [{ {AArch64::FeatureSpecRestrict} }];1109}1110def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>;1111def : ROSysReg<"ID_DFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b101>;1112def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>;1113def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>;1114def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>;1115def : ROSysReg<"ID_MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b110>;1116def : ROSysReg<"ID_MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b111>;1117def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>;1118def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>;1119def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>;1120def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>;1121def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>;1122def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>;1123def : ROSysReg<"ID_ISAR6_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b111> {1124 let Requires = [{ {AArch64::HasV8_2aOps} }];1125}1126def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>;1127def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>;1128def : ROSysReg<"ID_AA64PFR2_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b010>;1129def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>;1130def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>;1131def : ROSysReg<"ID_AA64DFR2_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b010>;1132def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>;1133def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>;1134def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>;1135def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>;1136def : ROSysReg<"ID_AA64ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b010>;1137def : ROSysReg<"ID_AA64ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b011>;1138def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>;1139def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>;1140def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>;1141def : ROSysReg<"ID_AA64MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b011>;1142def : ROSysReg<"ID_AA64MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b100>;1143def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>;1144def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>;1145def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>;1146def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>;1147def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>;1148def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>;1149def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;1150def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>;1151def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>;1152def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>;1153def : ROSysReg<"ID_MMFR5_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b110>;1154 1155// Trace registers1156// Op0 Op1 CRn CRm Op21157def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>;1158def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>;1159def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>;1160def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>;1161def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>;1162def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>;1163def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>;1164def : ROSysReg<"TRCIDR0", 0b10, 0b001, 0b0000, 0b1000, 0b111>;1165def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>;1166def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>;1167def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>;1168def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>;1169def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>;1170def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>;1171def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>;1172def : ROSysReg<"TRCOSLSR", 0b10, 0b001, 0b0001, 0b0001, 0b100>;1173def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>;1174def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>;1175def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>;1176def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>;1177def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>;1178def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>;1179def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>;1180def : ROSysReg<"TRCDEVTYPE", 0b10, 0b001, 0b0111, 0b0011, 0b111>;1181def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>;1182def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>;1183def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>;1184def : ROSysReg<"TRCPIDR7", 0b10, 0b001, 0b0111, 0b0111, 0b111>;1185def : ROSysReg<"TRCPIDR0", 0b10, 0b001, 0b0111, 0b1000, 0b111>;1186def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>;1187def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>;1188def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>;1189def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>;1190def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>;1191def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>;1192def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>;1193 1194// GICv3 registers1195// Op0 Op1 CRn CRm Op21196def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>;1197def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>;1198def : ROSysReg<"ICC_HPPIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b010>;1199def : ROSysReg<"ICC_HPPIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b010>;1200def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>;1201def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>;1202def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>;1203def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>;1204 1205// SVE control registers1206// Op0 Op1 CRn CRm Op21207let Requires = [{ {AArch64::FeatureSVE} }] in {1208def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>;1209}1210 1211// v8.1a "Limited Ordering Regions" extension-specific system register1212// Op0 Op1 CRn CRm Op21213let Requires = [{ {AArch64::FeatureLOR} }] in1214def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;1215 1216// v8.2a "RAS extension" registers1217// Op0 Op1 CRn CRm Op21218let Requires = [{ {AArch64::FeatureRAS} }] in {1219def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>;1220def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>;1221}1222 1223// v8.5a "random number" registers1224// Op0 Op1 CRn CRm Op21225let Requires = [{ {AArch64::FeatureRandGen} }] in {1226def : ROSysReg<"RNDR", 0b11, 0b011, 0b0010, 0b0100, 0b000>;1227def : ROSysReg<"RNDRRS", 0b11, 0b011, 0b0010, 0b0100, 0b001>;1228}1229 1230// v8.5a Software Context Number registers1231let Requires = [{ {AArch64::FeatureSpecRestrict} }] in {1232def : RWSysReg<"SCXTNUM_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b111>;1233def : RWSysReg<"SCXTNUM_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b111>;1234def : RWSysReg<"SCXTNUM_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b111>;1235def : RWSysReg<"SCXTNUM_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b111>;1236def : RWSysReg<"SCXTNUM_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b111>;1237}1238 1239// v9a Realm Management Extension registers1240let Requires = [{ {AArch64::FeatureRME} }] in {1241def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>;1242def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;1243}1244// MFAR_EL3 is part of both FEAT_RME and FEAT_PFAR (further below). The latter1245// is unconditional so this register has to be too.1246def : RWSysReg<"MFAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b101>;1247 1248// v9a Memory Encryption Contexts Extension registers1249let Requires = [{ {AArch64::FeatureMEC} }] in {1250def : ROSysReg<"MECIDR_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b111>;1251def : RWSysReg<"MECID_P0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b000>;1252def : RWSysReg<"MECID_A0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b001>;1253def : RWSysReg<"MECID_P1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b010>;1254def : RWSysReg<"MECID_A1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b011>;1255def : RWSysReg<"VMECID_P_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b000>;1256def : RWSysReg<"VMECID_A_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b001>;1257def : RWSysReg<"MECID_RL_A_EL3", 0b11, 0b110, 0b1010, 0b1010, 0b001>;1258}1259 1260// v9-a Scalable Matrix Extension (SME) registers1261// Op0 Op1 CRn CRm Op21262let Requires = [{ {AArch64::FeatureSME} }] in {1263def : ROSysReg<"ID_AA64SMFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b101>;1264}1265 1266//===----------------------1267// Write-only regs1268//===----------------------1269 1270// Op0 Op1 CRn CRm Op21271def : WOSysReg<"DBGDTRTX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;1272def : WOSysReg<"OSLAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b100>;1273def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>;1274 1275// Trace Registers1276// Op0 Op1 CRn CRm Op21277def : WOSysReg<"TRCOSLAR", 0b10, 0b001, 0b0001, 0b0000, 0b100>;1278def : WOSysReg<"TRCLAR", 0b10, 0b001, 0b0111, 0b1100, 0b110>;1279 1280// GICv3 registers1281// Op0 Op1 CRn CRm Op21282def : WOSysReg<"ICC_EOIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b001>;1283def : WOSysReg<"ICC_EOIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b001>;1284def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>;1285def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>;1286def : WOSysReg<"ICC_ASGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b110>;1287def : WOSysReg<"ICC_SGI0R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b111>;1288 1289//===----------------------1290// Read-write regs1291//===----------------------1292 1293// Op0 Op1 CRn CRm Op21294def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>;1295def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>;1296def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>;1297def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>;1298def : RWSysReg<"MDSCR_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b010>;1299def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>;1300def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>;1301def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>;1302foreach n = 0-15 in {1303 defvar nb = !cast<bits<4>>(n);1304 // Op0 Op1 CRn CRm Op21305 def : RWSysReg<"DBGBVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b100>;1306 def : RWSysReg<"DBGBCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b101>;1307 def : RWSysReg<"DBGWVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b110>;1308 def : RWSysReg<"DBGWCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b111>;1309}1310// Op0 Op1 CRn CRm Op21311def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>;1312def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>;1313def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>;1314def : RWSysReg<"DBGCLAIMSET_EL1", 0b10, 0b000, 0b0111, 0b1000, 0b110>;1315def : RWSysReg<"DBGCLAIMCLR_EL1", 0b10, 0b000, 0b0111, 0b1001, 0b110>;1316def : RWSysReg<"CSSELR_EL1", 0b11, 0b010, 0b0000, 0b0000, 0b000>;1317def : RWSysReg<"VPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b000>;1318def : RWSysReg<"VMPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b101>;1319def : RWSysReg<"CPACR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b010>;1320def : RWSysReg<"SCTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b000>;1321def : RWSysReg<"SCTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b000>;1322def : RWSysReg<"SCTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b000>;1323def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>;1324def : RWSysReg<"ACTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b001>;1325def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>;1326def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>;1327def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>;1328def : RWSysReg<"HCRX_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b010> {1329 let Requires = [{ {AArch64::FeatureHCX} }];1330}1331def : RWSysReg<"SCR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b000>;1332def : RWSysReg<"MDCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b001>;1333def : RWSysReg<"SDER32_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b001>;1334def : RWSysReg<"CPTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b010>;1335def : RWSysReg<"CPTR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b010>;1336def : RWSysReg<"HSTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b011>;1337def : RWSysReg<"HACR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b111>;1338def : RWSysReg<"MDCR_EL3", 0b11, 0b110, 0b0001, 0b0011, 0b001>;1339def : RWSysReg<"TTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b000>;1340def : RWSysReg<"TTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b000>;1341 1342let Requires = [{ {AArch64::FeatureEL2VMSA} }] in {1343def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000>;1344def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>;1345}1346 1347def : RWSysReg<"TTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b001>;1348def : RWSysReg<"TCR_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b010>;1349def : RWSysReg<"TCR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b010>;1350def : RWSysReg<"TCR_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b010>;1351def : RWSysReg<"VTCR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b010>;1352def : RWSysReg<"DACR32_EL2", 0b11, 0b100, 0b0011, 0b0000, 0b000>;1353def : RWSysReg<"SPSR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b000>;1354def : RWSysReg<"SPSR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b000>;1355def : RWSysReg<"SPSR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b000>;1356def : RWSysReg<"ELR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b001>;1357def : RWSysReg<"ELR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b001>;1358def : RWSysReg<"ELR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b001>;1359def : RWSysReg<"SP_EL0", 0b11, 0b000, 0b0100, 0b0001, 0b000>;1360def : RWSysReg<"SP_EL1", 0b11, 0b100, 0b0100, 0b0001, 0b000>;1361def : RWSysReg<"SP_EL2", 0b11, 0b110, 0b0100, 0b0001, 0b000>;1362def : RWSysReg<"SPSel", 0b11, 0b000, 0b0100, 0b0010, 0b000>;1363def : RWSysReg<"NZCV", 0b11, 0b011, 0b0100, 0b0010, 0b000>;1364def : RWSysReg<"DAIF", 0b11, 0b011, 0b0100, 0b0010, 0b001>;1365def : ROSysReg<"CurrentEL", 0b11, 0b000, 0b0100, 0b0010, 0b010>;1366def : RWSysReg<"SPSR_irq", 0b11, 0b100, 0b0100, 0b0011, 0b000>;1367def : RWSysReg<"SPSR_abt", 0b11, 0b100, 0b0100, 0b0011, 0b001>;1368def : RWSysReg<"SPSR_und", 0b11, 0b100, 0b0100, 0b0011, 0b010>;1369def : RWSysReg<"SPSR_fiq", 0b11, 0b100, 0b0100, 0b0011, 0b011>;1370let Requires = [{ {AArch64::FeatureFPARMv8} }] in {1371def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;1372def : RWSysReg<"FPSR", 0b11, 0b011, 0b0100, 0b0100, 0b001>;1373}1374def : RWSysReg<"DSPSR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b000>;1375def : RWSysReg<"DLR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b001>;1376def : RWSysReg<"IFSR32_EL2", 0b11, 0b100, 0b0101, 0b0000, 0b001>;1377def : RWSysReg<"AFSR0_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b000>;1378def : RWSysReg<"AFSR0_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b000>;1379def : RWSysReg<"AFSR0_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b000>;1380def : RWSysReg<"AFSR1_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b001>;1381def : RWSysReg<"AFSR1_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b001>;1382def : RWSysReg<"AFSR1_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b001>;1383def : RWSysReg<"ESR_EL1", 0b11, 0b000, 0b0101, 0b0010, 0b000>;1384def : RWSysReg<"ESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b000>;1385def : RWSysReg<"ESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b000>;1386def : RWSysReg<"FPEXC32_EL2", 0b11, 0b100, 0b0101, 0b0011, 0b000>;1387def : RWSysReg<"FAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b000>;1388def : RWSysReg<"FAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b000>;1389def : RWSysReg<"FAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b000>;1390def : RWSysReg<"HPFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b100>;1391def : RWSysReg<"PAR_EL1", 0b11, 0b000, 0b0111, 0b0100, 0b000>;1392def : RWSysReg<"PMCR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b000>;1393def : RWSysReg<"PMCNTENSET_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b001>;1394def : RWSysReg<"PMCNTENCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b010>;1395def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>;1396def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>;1397def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>;1398def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>;1399def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>;1400def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>;1401def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>;1402def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>;1403def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>;1404def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>;1405def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>;1406def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>;1407def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>;1408def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>;1409def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>;1410def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>;1411def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>;1412def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>;1413def : RWSysReg<"RMR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b010>;1414def : RWSysReg<"RMR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b010>;1415def : RWSysReg<"RMR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b010>;1416def : RWSysReg<"CONTEXTIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b001>;1417def : RWSysReg<"TPIDR_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b010>;1418def : RWSysReg<"TPIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b010>;1419def : RWSysReg<"TPIDR_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b010>;1420def : RWSysReg<"TPIDRRO_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b011>;1421def : RWSysReg<"TPIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b100>;1422def : RWSysReg<"CNTFRQ_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b000>;1423def : RWSysReg<"CNTVOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b011>;1424def : RWSysReg<"CNTKCTL_EL1", 0b11, 0b000, 0b1110, 0b0001, 0b000>;1425def : RWSysReg<"CNTHCTL_EL2", 0b11, 0b100, 0b1110, 0b0001, 0b000>;1426def : RWSysReg<"CNTP_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b000>;1427def : RWSysReg<"CNTHP_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b000>;1428def : RWSysReg<"CNTPS_TVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b000>;1429def : RWSysReg<"CNTP_CTL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b001>;1430def : RWSysReg<"CNTHP_CTL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b001>;1431def : RWSysReg<"CNTPS_CTL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b001>;1432def : RWSysReg<"CNTP_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b010>;1433def : RWSysReg<"CNTHP_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b010>;1434def : RWSysReg<"CNTPS_CVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b010>;1435def : RWSysReg<"CNTV_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b000>;1436def : RWSysReg<"CNTV_CTL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b001>;1437def : RWSysReg<"CNTV_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b010>;1438def : RWSysReg<"PMEVCNTR0_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b000>;1439def : RWSysReg<"PMEVCNTR1_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b001>;1440def : RWSysReg<"PMEVCNTR2_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b010>;1441def : RWSysReg<"PMEVCNTR3_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b011>;1442def : RWSysReg<"PMEVCNTR4_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b100>;1443def : RWSysReg<"PMEVCNTR5_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b101>;1444def : RWSysReg<"PMEVCNTR6_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b110>;1445def : RWSysReg<"PMEVCNTR7_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b111>;1446def : RWSysReg<"PMEVCNTR8_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b000>;1447def : RWSysReg<"PMEVCNTR9_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b001>;1448def : RWSysReg<"PMEVCNTR10_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b010>;1449def : RWSysReg<"PMEVCNTR11_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b011>;1450def : RWSysReg<"PMEVCNTR12_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b100>;1451def : RWSysReg<"PMEVCNTR13_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b101>;1452def : RWSysReg<"PMEVCNTR14_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b110>;1453def : RWSysReg<"PMEVCNTR15_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b111>;1454def : RWSysReg<"PMEVCNTR16_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b000>;1455def : RWSysReg<"PMEVCNTR17_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b001>;1456def : RWSysReg<"PMEVCNTR18_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b010>;1457def : RWSysReg<"PMEVCNTR19_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b011>;1458def : RWSysReg<"PMEVCNTR20_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b100>;1459def : RWSysReg<"PMEVCNTR21_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b101>;1460def : RWSysReg<"PMEVCNTR22_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b110>;1461def : RWSysReg<"PMEVCNTR23_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b111>;1462def : RWSysReg<"PMEVCNTR24_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b000>;1463def : RWSysReg<"PMEVCNTR25_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b001>;1464def : RWSysReg<"PMEVCNTR26_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b010>;1465def : RWSysReg<"PMEVCNTR27_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b011>;1466def : RWSysReg<"PMEVCNTR28_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b100>;1467def : RWSysReg<"PMEVCNTR29_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b101>;1468def : RWSysReg<"PMEVCNTR30_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b110>;1469def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>;1470def : RWSysReg<"PMEVTYPER0_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b000>;1471def : RWSysReg<"PMEVTYPER1_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b001>;1472def : RWSysReg<"PMEVTYPER2_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b010>;1473def : RWSysReg<"PMEVTYPER3_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b011>;1474def : RWSysReg<"PMEVTYPER4_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b100>;1475def : RWSysReg<"PMEVTYPER5_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b101>;1476def : RWSysReg<"PMEVTYPER6_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b110>;1477def : RWSysReg<"PMEVTYPER7_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b111>;1478def : RWSysReg<"PMEVTYPER8_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b000>;1479def : RWSysReg<"PMEVTYPER9_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b001>;1480def : RWSysReg<"PMEVTYPER10_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b010>;1481def : RWSysReg<"PMEVTYPER11_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b011>;1482def : RWSysReg<"PMEVTYPER12_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b100>;1483def : RWSysReg<"PMEVTYPER13_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b101>;1484def : RWSysReg<"PMEVTYPER14_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b110>;1485def : RWSysReg<"PMEVTYPER15_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b111>;1486def : RWSysReg<"PMEVTYPER16_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b000>;1487def : RWSysReg<"PMEVTYPER17_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b001>;1488def : RWSysReg<"PMEVTYPER18_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b010>;1489def : RWSysReg<"PMEVTYPER19_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b011>;1490def : RWSysReg<"PMEVTYPER20_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b100>;1491def : RWSysReg<"PMEVTYPER21_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b101>;1492def : RWSysReg<"PMEVTYPER22_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b110>;1493def : RWSysReg<"PMEVTYPER23_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b111>;1494def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>;1495def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>;1496def : RWSysReg<"PMEVTYPER26_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b010>;1497def : RWSysReg<"PMEVTYPER27_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b011>;1498def : RWSysReg<"PMEVTYPER28_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b100>;1499def : RWSysReg<"PMEVTYPER29_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b101>;1500def : RWSysReg<"PMEVTYPER30_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b110>;1501 1502// Trace registers1503// Op0 Op1 CRn CRm Op21504def : RWSysReg<"TRCPRGCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b000>;1505def : RWSysReg<"TRCPROCSELR", 0b10, 0b001, 0b0000, 0b0010, 0b000>;1506def : RWSysReg<"TRCCONFIGR", 0b10, 0b001, 0b0000, 0b0100, 0b000>;1507def : RWSysReg<"TRCAUXCTLR", 0b10, 0b001, 0b0000, 0b0110, 0b000>;1508def : RWSysReg<"TRCEVENTCTL0R", 0b10, 0b001, 0b0000, 0b1000, 0b000>;1509def : RWSysReg<"TRCEVENTCTL1R", 0b10, 0b001, 0b0000, 0b1001, 0b000>;1510def : RWSysReg<"TRCSTALLCTLR", 0b10, 0b001, 0b0000, 0b1011, 0b000>;1511def : RWSysReg<"TRCTSCTLR", 0b10, 0b001, 0b0000, 0b1100, 0b000>;1512def : RWSysReg<"TRCSYNCPR", 0b10, 0b001, 0b0000, 0b1101, 0b000>;1513def : RWSysReg<"TRCCCCTLR", 0b10, 0b001, 0b0000, 0b1110, 0b000>;1514def : RWSysReg<"TRCBBCTLR", 0b10, 0b001, 0b0000, 0b1111, 0b000>;1515def : RWSysReg<"TRCTRACEIDR", 0b10, 0b001, 0b0000, 0b0000, 0b001>;1516def : RWSysReg<"TRCQCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b001>;1517def : RWSysReg<"TRCVICTLR", 0b10, 0b001, 0b0000, 0b0000, 0b010>;1518def : RWSysReg<"TRCVIIECTLR", 0b10, 0b001, 0b0000, 0b0001, 0b010>;1519def : RWSysReg<"TRCVISSCTLR", 0b10, 0b001, 0b0000, 0b0010, 0b010>;1520def : RWSysReg<"TRCVIPCSSCTLR", 0b10, 0b001, 0b0000, 0b0011, 0b010>;1521def : RWSysReg<"TRCVDCTLR", 0b10, 0b001, 0b0000, 0b1000, 0b010>;1522def : RWSysReg<"TRCVDSACCTLR", 0b10, 0b001, 0b0000, 0b1001, 0b010>;1523def : RWSysReg<"TRCVDARCCTLR", 0b10, 0b001, 0b0000, 0b1010, 0b010>;1524def : RWSysReg<"TRCSEQEVR0", 0b10, 0b001, 0b0000, 0b0000, 0b100>;1525def : RWSysReg<"TRCSEQEVR1", 0b10, 0b001, 0b0000, 0b0001, 0b100>;1526def : RWSysReg<"TRCSEQEVR2", 0b10, 0b001, 0b0000, 0b0010, 0b100>;1527def : RWSysReg<"TRCSEQRSTEVR", 0b10, 0b001, 0b0000, 0b0110, 0b100>;1528def : RWSysReg<"TRCSEQSTR", 0b10, 0b001, 0b0000, 0b0111, 0b100>;1529def : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>;1530def : RWSysReg<"TRCCNTRLDVR0", 0b10, 0b001, 0b0000, 0b0000, 0b101>;1531def : RWSysReg<"TRCCNTRLDVR1", 0b10, 0b001, 0b0000, 0b0001, 0b101>;1532def : RWSysReg<"TRCCNTRLDVR2", 0b10, 0b001, 0b0000, 0b0010, 0b101>;1533def : RWSysReg<"TRCCNTRLDVR3", 0b10, 0b001, 0b0000, 0b0011, 0b101>;1534def : RWSysReg<"TRCCNTCTLR0", 0b10, 0b001, 0b0000, 0b0100, 0b101>;1535def : RWSysReg<"TRCCNTCTLR1", 0b10, 0b001, 0b0000, 0b0101, 0b101>;1536def : RWSysReg<"TRCCNTCTLR2", 0b10, 0b001, 0b0000, 0b0110, 0b101>;1537def : RWSysReg<"TRCCNTCTLR3", 0b10, 0b001, 0b0000, 0b0111, 0b101>;1538def : RWSysReg<"TRCCNTVR0", 0b10, 0b001, 0b0000, 0b1000, 0b101>;1539def : RWSysReg<"TRCCNTVR1", 0b10, 0b001, 0b0000, 0b1001, 0b101>;1540def : RWSysReg<"TRCCNTVR2", 0b10, 0b001, 0b0000, 0b1010, 0b101>;1541def : RWSysReg<"TRCCNTVR3", 0b10, 0b001, 0b0000, 0b1011, 0b101>;1542def : RWSysReg<"TRCIMSPEC0", 0b10, 0b001, 0b0000, 0b0000, 0b111>;1543def : RWSysReg<"TRCIMSPEC1", 0b10, 0b001, 0b0000, 0b0001, 0b111>;1544def : RWSysReg<"TRCIMSPEC2", 0b10, 0b001, 0b0000, 0b0010, 0b111>;1545def : RWSysReg<"TRCIMSPEC3", 0b10, 0b001, 0b0000, 0b0011, 0b111>;1546def : RWSysReg<"TRCIMSPEC4", 0b10, 0b001, 0b0000, 0b0100, 0b111>;1547def : RWSysReg<"TRCIMSPEC5", 0b10, 0b001, 0b0000, 0b0101, 0b111>;1548def : RWSysReg<"TRCIMSPEC6", 0b10, 0b001, 0b0000, 0b0110, 0b111>;1549def : RWSysReg<"TRCIMSPEC7", 0b10, 0b001, 0b0000, 0b0111, 0b111>;1550def : RWSysReg<"TRCRSCTLR2", 0b10, 0b001, 0b0001, 0b0010, 0b000>;1551def : RWSysReg<"TRCRSCTLR3", 0b10, 0b001, 0b0001, 0b0011, 0b000>;1552def : RWSysReg<"TRCRSCTLR4", 0b10, 0b001, 0b0001, 0b0100, 0b000>;1553def : RWSysReg<"TRCRSCTLR5", 0b10, 0b001, 0b0001, 0b0101, 0b000>;1554def : RWSysReg<"TRCRSCTLR6", 0b10, 0b001, 0b0001, 0b0110, 0b000>;1555def : RWSysReg<"TRCRSCTLR7", 0b10, 0b001, 0b0001, 0b0111, 0b000>;1556def : RWSysReg<"TRCRSCTLR8", 0b10, 0b001, 0b0001, 0b1000, 0b000>;1557def : RWSysReg<"TRCRSCTLR9", 0b10, 0b001, 0b0001, 0b1001, 0b000>;1558def : RWSysReg<"TRCRSCTLR10", 0b10, 0b001, 0b0001, 0b1010, 0b000>;1559def : RWSysReg<"TRCRSCTLR11", 0b10, 0b001, 0b0001, 0b1011, 0b000>;1560def : RWSysReg<"TRCRSCTLR12", 0b10, 0b001, 0b0001, 0b1100, 0b000>;1561def : RWSysReg<"TRCRSCTLR13", 0b10, 0b001, 0b0001, 0b1101, 0b000>;1562def : RWSysReg<"TRCRSCTLR14", 0b10, 0b001, 0b0001, 0b1110, 0b000>;1563def : RWSysReg<"TRCRSCTLR15", 0b10, 0b001, 0b0001, 0b1111, 0b000>;1564def : RWSysReg<"TRCRSCTLR16", 0b10, 0b001, 0b0001, 0b0000, 0b001>;1565def : RWSysReg<"TRCRSCTLR17", 0b10, 0b001, 0b0001, 0b0001, 0b001>;1566def : RWSysReg<"TRCRSCTLR18", 0b10, 0b001, 0b0001, 0b0010, 0b001>;1567def : RWSysReg<"TRCRSCTLR19", 0b10, 0b001, 0b0001, 0b0011, 0b001>;1568def : RWSysReg<"TRCRSCTLR20", 0b10, 0b001, 0b0001, 0b0100, 0b001>;1569def : RWSysReg<"TRCRSCTLR21", 0b10, 0b001, 0b0001, 0b0101, 0b001>;1570def : RWSysReg<"TRCRSCTLR22", 0b10, 0b001, 0b0001, 0b0110, 0b001>;1571def : RWSysReg<"TRCRSCTLR23", 0b10, 0b001, 0b0001, 0b0111, 0b001>;1572def : RWSysReg<"TRCRSCTLR24", 0b10, 0b001, 0b0001, 0b1000, 0b001>;1573def : RWSysReg<"TRCRSCTLR25", 0b10, 0b001, 0b0001, 0b1001, 0b001>;1574def : RWSysReg<"TRCRSCTLR26", 0b10, 0b001, 0b0001, 0b1010, 0b001>;1575def : RWSysReg<"TRCRSCTLR27", 0b10, 0b001, 0b0001, 0b1011, 0b001>;1576def : RWSysReg<"TRCRSCTLR28", 0b10, 0b001, 0b0001, 0b1100, 0b001>;1577def : RWSysReg<"TRCRSCTLR29", 0b10, 0b001, 0b0001, 0b1101, 0b001>;1578def : RWSysReg<"TRCRSCTLR30", 0b10, 0b001, 0b0001, 0b1110, 0b001>;1579def : RWSysReg<"TRCRSCTLR31", 0b10, 0b001, 0b0001, 0b1111, 0b001>;1580def : RWSysReg<"TRCSSCCR0", 0b10, 0b001, 0b0001, 0b0000, 0b010>;1581def : RWSysReg<"TRCSSCCR1", 0b10, 0b001, 0b0001, 0b0001, 0b010>;1582def : RWSysReg<"TRCSSCCR2", 0b10, 0b001, 0b0001, 0b0010, 0b010>;1583def : RWSysReg<"TRCSSCCR3", 0b10, 0b001, 0b0001, 0b0011, 0b010>;1584def : RWSysReg<"TRCSSCCR4", 0b10, 0b001, 0b0001, 0b0100, 0b010>;1585def : RWSysReg<"TRCSSCCR5", 0b10, 0b001, 0b0001, 0b0101, 0b010>;1586def : RWSysReg<"TRCSSCCR6", 0b10, 0b001, 0b0001, 0b0110, 0b010>;1587def : RWSysReg<"TRCSSCCR7", 0b10, 0b001, 0b0001, 0b0111, 0b010>;1588def : RWSysReg<"TRCSSCSR0", 0b10, 0b001, 0b0001, 0b1000, 0b010>;1589def : RWSysReg<"TRCSSCSR1", 0b10, 0b001, 0b0001, 0b1001, 0b010>;1590def : RWSysReg<"TRCSSCSR2", 0b10, 0b001, 0b0001, 0b1010, 0b010>;1591def : RWSysReg<"TRCSSCSR3", 0b10, 0b001, 0b0001, 0b1011, 0b010>;1592def : RWSysReg<"TRCSSCSR4", 0b10, 0b001, 0b0001, 0b1100, 0b010>;1593def : RWSysReg<"TRCSSCSR5", 0b10, 0b001, 0b0001, 0b1101, 0b010>;1594def : RWSysReg<"TRCSSCSR6", 0b10, 0b001, 0b0001, 0b1110, 0b010>;1595def : RWSysReg<"TRCSSCSR7", 0b10, 0b001, 0b0001, 0b1111, 0b010>;1596def : RWSysReg<"TRCSSPCICR0", 0b10, 0b001, 0b0001, 0b0000, 0b011>;1597def : RWSysReg<"TRCSSPCICR1", 0b10, 0b001, 0b0001, 0b0001, 0b011>;1598def : RWSysReg<"TRCSSPCICR2", 0b10, 0b001, 0b0001, 0b0010, 0b011>;1599def : RWSysReg<"TRCSSPCICR3", 0b10, 0b001, 0b0001, 0b0011, 0b011>;1600def : RWSysReg<"TRCSSPCICR4", 0b10, 0b001, 0b0001, 0b0100, 0b011>;1601def : RWSysReg<"TRCSSPCICR5", 0b10, 0b001, 0b0001, 0b0101, 0b011>;1602def : RWSysReg<"TRCSSPCICR6", 0b10, 0b001, 0b0001, 0b0110, 0b011>;1603def : RWSysReg<"TRCSSPCICR7", 0b10, 0b001, 0b0001, 0b0111, 0b011>;1604def : RWSysReg<"TRCPDCR", 0b10, 0b001, 0b0001, 0b0100, 0b100>;1605def : RWSysReg<"TRCACVR0", 0b10, 0b001, 0b0010, 0b0000, 0b000>;1606def : RWSysReg<"TRCACVR1", 0b10, 0b001, 0b0010, 0b0010, 0b000>;1607def : RWSysReg<"TRCACVR2", 0b10, 0b001, 0b0010, 0b0100, 0b000>;1608def : RWSysReg<"TRCACVR3", 0b10, 0b001, 0b0010, 0b0110, 0b000>;1609def : RWSysReg<"TRCACVR4", 0b10, 0b001, 0b0010, 0b1000, 0b000>;1610def : RWSysReg<"TRCACVR5", 0b10, 0b001, 0b0010, 0b1010, 0b000>;1611def : RWSysReg<"TRCACVR6", 0b10, 0b001, 0b0010, 0b1100, 0b000>;1612def : RWSysReg<"TRCACVR7", 0b10, 0b001, 0b0010, 0b1110, 0b000>;1613def : RWSysReg<"TRCACVR8", 0b10, 0b001, 0b0010, 0b0000, 0b001>;1614def : RWSysReg<"TRCACVR9", 0b10, 0b001, 0b0010, 0b0010, 0b001>;1615def : RWSysReg<"TRCACVR10", 0b10, 0b001, 0b0010, 0b0100, 0b001>;1616def : RWSysReg<"TRCACVR11", 0b10, 0b001, 0b0010, 0b0110, 0b001>;1617def : RWSysReg<"TRCACVR12", 0b10, 0b001, 0b0010, 0b1000, 0b001>;1618def : RWSysReg<"TRCACVR13", 0b10, 0b001, 0b0010, 0b1010, 0b001>;1619def : RWSysReg<"TRCACVR14", 0b10, 0b001, 0b0010, 0b1100, 0b001>;1620def : RWSysReg<"TRCACVR15", 0b10, 0b001, 0b0010, 0b1110, 0b001>;1621def : RWSysReg<"TRCACATR0", 0b10, 0b001, 0b0010, 0b0000, 0b010>;1622def : RWSysReg<"TRCACATR1", 0b10, 0b001, 0b0010, 0b0010, 0b010>;1623def : RWSysReg<"TRCACATR2", 0b10, 0b001, 0b0010, 0b0100, 0b010>;1624def : RWSysReg<"TRCACATR3", 0b10, 0b001, 0b0010, 0b0110, 0b010>;1625def : RWSysReg<"TRCACATR4", 0b10, 0b001, 0b0010, 0b1000, 0b010>;1626def : RWSysReg<"TRCACATR5", 0b10, 0b001, 0b0010, 0b1010, 0b010>;1627def : RWSysReg<"TRCACATR6", 0b10, 0b001, 0b0010, 0b1100, 0b010>;1628def : RWSysReg<"TRCACATR7", 0b10, 0b001, 0b0010, 0b1110, 0b010>;1629def : RWSysReg<"TRCACATR8", 0b10, 0b001, 0b0010, 0b0000, 0b011>;1630def : RWSysReg<"TRCACATR9", 0b10, 0b001, 0b0010, 0b0010, 0b011>;1631def : RWSysReg<"TRCACATR10", 0b10, 0b001, 0b0010, 0b0100, 0b011>;1632def : RWSysReg<"TRCACATR11", 0b10, 0b001, 0b0010, 0b0110, 0b011>;1633def : RWSysReg<"TRCACATR12", 0b10, 0b001, 0b0010, 0b1000, 0b011>;1634def : RWSysReg<"TRCACATR13", 0b10, 0b001, 0b0010, 0b1010, 0b011>;1635def : RWSysReg<"TRCACATR14", 0b10, 0b001, 0b0010, 0b1100, 0b011>;1636def : RWSysReg<"TRCACATR15", 0b10, 0b001, 0b0010, 0b1110, 0b011>;1637def : RWSysReg<"TRCDVCVR0", 0b10, 0b001, 0b0010, 0b0000, 0b100>;1638def : RWSysReg<"TRCDVCVR1", 0b10, 0b001, 0b0010, 0b0100, 0b100>;1639def : RWSysReg<"TRCDVCVR2", 0b10, 0b001, 0b0010, 0b1000, 0b100>;1640def : RWSysReg<"TRCDVCVR3", 0b10, 0b001, 0b0010, 0b1100, 0b100>;1641def : RWSysReg<"TRCDVCVR4", 0b10, 0b001, 0b0010, 0b0000, 0b101>;1642def : RWSysReg<"TRCDVCVR5", 0b10, 0b001, 0b0010, 0b0100, 0b101>;1643def : RWSysReg<"TRCDVCVR6", 0b10, 0b001, 0b0010, 0b1000, 0b101>;1644def : RWSysReg<"TRCDVCVR7", 0b10, 0b001, 0b0010, 0b1100, 0b101>;1645def : RWSysReg<"TRCDVCMR0", 0b10, 0b001, 0b0010, 0b0000, 0b110>;1646def : RWSysReg<"TRCDVCMR1", 0b10, 0b001, 0b0010, 0b0100, 0b110>;1647def : RWSysReg<"TRCDVCMR2", 0b10, 0b001, 0b0010, 0b1000, 0b110>;1648def : RWSysReg<"TRCDVCMR3", 0b10, 0b001, 0b0010, 0b1100, 0b110>;1649def : RWSysReg<"TRCDVCMR4", 0b10, 0b001, 0b0010, 0b0000, 0b111>;1650def : RWSysReg<"TRCDVCMR5", 0b10, 0b001, 0b0010, 0b0100, 0b111>;1651def : RWSysReg<"TRCDVCMR6", 0b10, 0b001, 0b0010, 0b1000, 0b111>;1652def : RWSysReg<"TRCDVCMR7", 0b10, 0b001, 0b0010, 0b1100, 0b111>;1653def : RWSysReg<"TRCCIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b000>;1654def : RWSysReg<"TRCCIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b000>;1655def : RWSysReg<"TRCCIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b000>;1656def : RWSysReg<"TRCCIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b000>;1657def : RWSysReg<"TRCCIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b000>;1658def : RWSysReg<"TRCCIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b000>;1659def : RWSysReg<"TRCCIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b000>;1660def : RWSysReg<"TRCCIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b000>;1661def : RWSysReg<"TRCVMIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b001>;1662def : RWSysReg<"TRCVMIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b001>;1663def : RWSysReg<"TRCVMIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b001>;1664def : RWSysReg<"TRCVMIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b001>;1665def : RWSysReg<"TRCVMIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b001>;1666def : RWSysReg<"TRCVMIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b001>;1667def : RWSysReg<"TRCVMIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b001>;1668def : RWSysReg<"TRCVMIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b001>;1669def : RWSysReg<"TRCCIDCCTLR0", 0b10, 0b001, 0b0011, 0b0000, 0b010>;1670def : RWSysReg<"TRCCIDCCTLR1", 0b10, 0b001, 0b0011, 0b0001, 0b010>;1671def : RWSysReg<"TRCVMIDCCTLR0", 0b10, 0b001, 0b0011, 0b0010, 0b010>;1672def : RWSysReg<"TRCVMIDCCTLR1", 0b10, 0b001, 0b0011, 0b0011, 0b010>;1673def : RWSysReg<"TRCITCTRL", 0b10, 0b001, 0b0111, 0b0000, 0b100>;1674def : RWSysReg<"TRCCLAIMSET", 0b10, 0b001, 0b0111, 0b1000, 0b110>;1675def : RWSysReg<"TRCCLAIMCLR", 0b10, 0b001, 0b0111, 0b1001, 0b110>;1676 1677// GICv3 registers1678// Op0 Op1 CRn CRm Op21679def : RWSysReg<"ICC_BPR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b011>;1680def : RWSysReg<"ICC_BPR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b011>;1681def : RWSysReg<"ICC_PMR_EL1", 0b11, 0b000, 0b0100, 0b0110, 0b000>;1682def : RWSysReg<"ICC_CTLR_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b100>;1683def : RWSysReg<"ICC_CTLR_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b100>;1684def : RWSysReg<"ICC_SRE_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b101>;1685def : RWSysReg<"ICC_SRE_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b101>;1686def : RWSysReg<"ICC_SRE_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b101>;1687def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>;1688def : RWSysReg<"ICC_IGRPEN1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b111>;1689def : RWSysReg<"ICC_IGRPEN1_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b111>;1690def : RWSysReg<"ICC_AP0R0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b100>;1691def : RWSysReg<"ICC_AP0R1_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b101>;1692def : RWSysReg<"ICC_AP0R2_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b110>;1693def : RWSysReg<"ICC_AP0R3_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b111>;1694def : RWSysReg<"ICC_AP1R0_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b000>;1695def : RWSysReg<"ICC_AP1R1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b001>;1696def : RWSysReg<"ICC_AP1R2_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b010>;1697def : RWSysReg<"ICC_AP1R3_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b011>;1698def : RWSysReg<"ICH_AP0R0_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b000>;1699def : RWSysReg<"ICH_AP0R1_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b001>;1700def : RWSysReg<"ICH_AP0R2_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b010>;1701def : RWSysReg<"ICH_AP0R3_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b011>;1702def : RWSysReg<"ICH_AP1R0_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b000>;1703def : RWSysReg<"ICH_AP1R1_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b001>;1704def : RWSysReg<"ICH_AP1R2_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b010>;1705def : RWSysReg<"ICH_AP1R3_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b011>;1706def : RWSysReg<"ICH_HCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b000>;1707def : ROSysReg<"ICH_MISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b010>;1708def : RWSysReg<"ICH_VMCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b111>;1709def : RWSysReg<"ICH_LR0_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b000>;1710def : RWSysReg<"ICH_LR1_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b001>;1711def : RWSysReg<"ICH_LR2_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b010>;1712def : RWSysReg<"ICH_LR3_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b011>;1713def : RWSysReg<"ICH_LR4_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b100>;1714def : RWSysReg<"ICH_LR5_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b101>;1715def : RWSysReg<"ICH_LR6_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b110>;1716def : RWSysReg<"ICH_LR7_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b111>;1717def : RWSysReg<"ICH_LR8_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b000>;1718def : RWSysReg<"ICH_LR9_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b001>;1719def : RWSysReg<"ICH_LR10_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b010>;1720def : RWSysReg<"ICH_LR11_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b011>;1721def : RWSysReg<"ICH_LR12_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b100>;1722def : RWSysReg<"ICH_LR13_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b101>;1723def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>;1724def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>;1725 1726// v8r system registers1727let Requires = [{ {AArch64::HasV8_0rOps} }] in {1728//Virtualization System Control Register1729// Op0 Op1 CRn CRm Op21730def : RWSysReg<"VSCTLR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000>;1731 1732//MPU Type Register1733// Op0 Op1 CRn CRm Op21734def : RWSysReg<"MPUIR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b100>;1735def : RWSysReg<"MPUIR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b100>;1736 1737//Protection Region Enable Register1738// Op0 Op1 CRn CRm Op21739def : RWSysReg<"PRENR_EL1", 0b11, 0b000, 0b0110, 0b0001, 0b001>;1740def : RWSysReg<"PRENR_EL2", 0b11, 0b100, 0b0110, 0b0001, 0b001>;1741 1742//Protection Region Selection Register1743// Op0 Op1 CRn CRm Op21744def : RWSysReg<"PRSELR_EL1", 0b11, 0b000, 0b0110, 0b0010, 0b001>;1745def : RWSysReg<"PRSELR_EL2", 0b11, 0b100, 0b0110, 0b0010, 0b001>;1746 1747//Protection Region Base Address Register1748// Op0 Op1 CRn CRm Op21749def : RWSysReg<"PRBAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b000>;1750def : RWSysReg<"PRBAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b000>;1751 1752//Protection Region Limit Address Register1753// Op0 Op1 CRn CRm Op21754def : RWSysReg<"PRLAR_EL1", 0b11, 0b000, 0b0110, 0b1000, 0b001>;1755def : RWSysReg<"PRLAR_EL2", 0b11, 0b100, 0b0110, 0b1000, 0b001>;1756 1757foreach n = 1-15 in {1758foreach x = 1-2 in {1759//Direct access to Protection Region Base Address Register for n th MPU region1760 def : RWSysReg<!strconcat("PRBAR"#n, "_EL"#x),1761 0b11, 0b000, 0b0110, 0b1000, 0b000>{1762 let Encoding{5-2} = n;1763 let Encoding{13} = !add(x,-1);1764 }1765 1766 def : RWSysReg<!strconcat("PRLAR"#n, "_EL"#x),1767 0b11, 0b000, 0b0110, 0b1000, 0b001>{1768 let Encoding{5-2} = n;1769 let Encoding{13} = !add(x,-1);1770 }1771} //foreach x = 1-2 in1772} //foreach n = 1-15 in1773} //let Requires = [{ {AArch64::HasV8_0rOps} }] in1774 1775// v8.1a "Privileged Access Never" extension-specific system registers1776let Requires = [{ {AArch64::FeaturePAN} }] in1777def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>;1778 1779// v8.1a "Limited Ordering Regions" extension-specific system registers1780// Op0 Op1 CRn CRm Op21781let Requires = [{ {AArch64::FeatureLOR} }] in {1782def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>;1783def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>;1784def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>;1785def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>;1786}1787 1788// v8.1a "Virtualization Host extensions" system registers1789// Op0 Op1 CRn CRm Op21790let Requires = [{ {AArch64::FeatureVH} }] in {1791def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>;1792def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>;1793def : RWSysReg<"CNTHV_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b010>;1794def : RWSysReg<"CNTHV_CTL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b001>;1795def : RWSysReg<"SCTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b000>;1796def : RWSysReg<"CPACR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b010>;1797def : RWSysReg<"TTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b000>;1798def : RWSysReg<"TTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b001>;1799def : RWSysReg<"TCR_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b010>;1800def : RWSysReg<"AFSR0_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b000>;1801def : RWSysReg<"AFSR1_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b001>;1802def : RWSysReg<"ESR_EL12", 0b11, 0b101, 0b0101, 0b0010, 0b000>;1803def : RWSysReg<"FAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b000>;1804def : RWSysReg<"MAIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b000>;1805def : RWSysReg<"AMAIR_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b000>;1806def : RWSysReg<"VBAR_EL12", 0b11, 0b101, 0b1100, 0b0000, 0b000>;1807def : RWSysReg<"CONTEXTIDR_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b001>;1808def : RWSysReg<"CNTKCTL_EL12", 0b11, 0b101, 0b1110, 0b0001, 0b000>;1809def : RWSysReg<"CNTP_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b000>;1810def : RWSysReg<"CNTP_CTL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b001>;1811def : RWSysReg<"CNTP_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b010>;1812def : RWSysReg<"CNTV_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b000>;1813def : RWSysReg<"CNTV_CTL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b001>;1814def : RWSysReg<"CNTV_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b010>;1815def : RWSysReg<"SPSR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b000>;1816def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>;1817let Requires = [{ {AArch64::FeatureCONTEXTIDREL2} }] in {1818 def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>;1819}1820}1821// v8.2a registers1822// Op0 Op1 CRn CRm Op21823let Requires = [{ {AArch64::FeaturePsUAO} }] in1824def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>;1825 1826// v8.2a "Statistical Profiling extension" registers1827// Op0 Op1 CRn CRm Op21828let Requires = [{ {AArch64::FeatureSPE} }] in {1829def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>;1830def : RWSysReg<"PMBPTR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b001>;1831def : RWSysReg<"PMBSR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b011>;1832def : ROSysReg<"PMBIDR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b111>;1833def : RWSysReg<"PMSCR_EL2", 0b11, 0b100, 0b1001, 0b1001, 0b000>;1834def : RWSysReg<"PMSCR_EL12", 0b11, 0b101, 0b1001, 0b1001, 0b000>;1835def : RWSysReg<"PMSCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b000>;1836def : RWSysReg<"PMSICR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b010>;1837def : RWSysReg<"PMSIRR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b011>;1838def : RWSysReg<"PMSFCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b100>;1839def : RWSysReg<"PMSEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b101>;1840def : RWSysReg<"PMSLATFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b110>;1841def : ROSysReg<"PMSIDR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b111>;1842}1843 1844// v8.2a "RAS extension" registers1845// Op0 Op1 CRn CRm Op21846let Requires = [{ {AArch64::FeatureRAS} }] in {1847def : RWSysReg<"ERRSELR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b001>;1848def : RWSysReg<"ERXCTLR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b001>;1849def : RWSysReg<"ERXSTATUS_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b010>;1850def : RWSysReg<"ERXADDR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b011>;1851def : RWSysReg<"ERXMISC0_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b000>;1852def : RWSysReg<"ERXMISC1_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b001>;1853def : RWSysReg<"DISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b001>;1854def : RWSysReg<"VDISR_EL2", 0b11, 0b100, 0b1100, 0b0001, 0b001>;1855def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>;1856}1857 1858// v8.3a "Pointer authentication extension" registers1859// Op0 Op1 CRn CRm Op21860let Requires = [{ {AArch64::FeaturePAuth} }] in {1861def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>;1862def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>;1863def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>;1864def : RWSysReg<"APIBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b011>;1865def : RWSysReg<"APDAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b000>;1866def : RWSysReg<"APDAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b001>;1867def : RWSysReg<"APDBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b010>;1868def : RWSysReg<"APDBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b011>;1869def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>;1870def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>;1871}1872 1873// v8.4 "Secure Exception Level 2 extension"1874let Requires = [{ {AArch64::FeatureSEL2} }] in {1875// v8.4a "Virtualization secure second stage translation" registers1876// Op0 Op1 CRn CRm Op21877def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>;1878def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000> {1879 let Requires = [{ {AArch64::HasV8_0aOps} }];1880}1881 1882// v8.4a "Virtualization timer" registers1883// Op0 Op1 CRn CRm Op21884def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>;1885def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>;1886def : RWSysReg<"CNTHVS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b001>;1887def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>;1888def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>;1889def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>;1890 1891// v8.4a "Virtualization debug state" registers1892// Op0 Op1 CRn CRm Op21893def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>;1894} // FeatureSEL21895 1896// v8.4a RAS registers1897// Op0 Op1 CRn CRm Op21898def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;1899def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;1900def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>;1901def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>;1902def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>;1903 1904// v8.4a MPAM registers1905// Op0 Op1 CRn CRm Op21906def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>;1907def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>;1908def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>;1909def : RWSysReg<"MPAMVPM2_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b010>;1910def : RWSysReg<"MPAMVPM3_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b011>;1911def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>;1912def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>;1913def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>;1914def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>;1915 1916// v8.4a Activity Monitor registers1917// Op0 Op1 CRn CRm Op21918let Requires = [{ {AArch64::FeatureAM} }] in {1919def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>;1920def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>;1921def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>;1922def : RWSysReg<"AMUSERENR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b011>;1923def : RWSysReg<"AMCNTENCLR0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b100>;1924def : RWSysReg<"AMCNTENSET0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b101>;1925def : RWSysReg<"AMEVCNTR00_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b000>;1926def : RWSysReg<"AMEVCNTR01_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b001>;1927def : RWSysReg<"AMEVCNTR02_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b010>;1928def : RWSysReg<"AMEVCNTR03_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b011>;1929def : ROSysReg<"AMEVTYPER00_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b000>;1930def : ROSysReg<"AMEVTYPER01_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b001>;1931def : ROSysReg<"AMEVTYPER02_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b010>;1932def : ROSysReg<"AMEVTYPER03_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b011>;1933def : RWSysReg<"AMCNTENCLR1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b000>;1934def : RWSysReg<"AMCNTENSET1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b001>;1935def : RWSysReg<"AMEVCNTR10_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b000>;1936def : RWSysReg<"AMEVCNTR11_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b001>;1937def : RWSysReg<"AMEVCNTR12_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b010>;1938def : RWSysReg<"AMEVCNTR13_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b011>;1939def : RWSysReg<"AMEVCNTR14_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b100>;1940def : RWSysReg<"AMEVCNTR15_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b101>;1941def : RWSysReg<"AMEVCNTR16_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b110>;1942def : RWSysReg<"AMEVCNTR17_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b111>;1943def : RWSysReg<"AMEVCNTR18_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b000>;1944def : RWSysReg<"AMEVCNTR19_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b001>;1945def : RWSysReg<"AMEVCNTR110_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b010>;1946def : RWSysReg<"AMEVCNTR111_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b011>;1947def : RWSysReg<"AMEVCNTR112_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b100>;1948def : RWSysReg<"AMEVCNTR113_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b101>;1949def : RWSysReg<"AMEVCNTR114_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b110>;1950def : RWSysReg<"AMEVCNTR115_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b111>;1951def : RWSysReg<"AMEVTYPER10_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b000>;1952def : RWSysReg<"AMEVTYPER11_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b001>;1953def : RWSysReg<"AMEVTYPER12_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b010>;1954def : RWSysReg<"AMEVTYPER13_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b011>;1955def : RWSysReg<"AMEVTYPER14_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b100>;1956def : RWSysReg<"AMEVTYPER15_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b101>;1957def : RWSysReg<"AMEVTYPER16_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b110>;1958def : RWSysReg<"AMEVTYPER17_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b111>;1959def : RWSysReg<"AMEVTYPER18_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b000>;1960def : RWSysReg<"AMEVTYPER19_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b001>;1961def : RWSysReg<"AMEVTYPER110_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b010>;1962def : RWSysReg<"AMEVTYPER111_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b011>;1963def : RWSysReg<"AMEVTYPER112_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b100>;1964def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>;1965def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>;1966def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>;1967} //FeatureAM1968 1969// v8.4a Trace Extension registers1970//1971// Please note that the 8.4 spec also defines these registers:1972// TRCIDR1, ID_DFR0_EL1, ID_AA64DFR0_EL1, MDSCR_EL1, MDCR_EL2, and MDCR_EL3,1973// but they are already defined above.1974//1975// Op0 Op1 CRn CRm Op21976let Requires = [{ {AArch64::FeatureTRACEV8_4} }] in {1977def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>;1978def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>;1979def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>;1980} //FeatureTRACEV8_41981 1982// v8.4a Timing insensitivity of data processing instructions1983// DIT: Data Independent Timing instructions1984// Op0 Op1 CRn CRm Op21985let Requires = [{ {AArch64::FeatureDIT} }] in {1986def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>;1987} //FeatureDIT1988 1989// v8.4a Enhanced Support for Nested Virtualization1990// Op0 Op1 CRn CRm Op21991let Requires = [{ {AArch64::FeatureNV} }] in {1992def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>;1993} //FeatureNV1994 1995// SVE control registers1996// Op0 Op1 CRn CRm Op21997let Requires = [{ {AArch64::FeatureSVE} }] in {1998def : RWSysReg<"ZCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b000>;1999def : RWSysReg<"ZCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b000>;2000def : RWSysReg<"ZCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b000>;2001def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>;2002}2003 2004// V8.5a Spectre mitigation SSBS register2005// Op0 Op1 CRn CRm Op22006let Requires = [{ {AArch64::FeatureSSBS} }] in2007def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>;2008 2009// v8.5a Memory Tagging Extension2010// Op0 Op1 CRn CRm Op22011let Requires = [{ {AArch64::FeatureMTE} }] in {2012def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>;2013def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>;2014def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>;2015def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b000>;2016def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0101, 0b0110, 0b000>;2017def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0101, 0b0110, 0b000>;2018def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0101, 0b0110, 0b000>;2019def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b001>;2020def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>;2021} // HasMTE2022 2023// Embedded Trace Extension R/W System registers2024let Requires = [{ {AArch64::FeatureETE} }] in {2025// Name Op0 Op1 CRn CRm Op22026def : RWSysReg<"TRCRSR", 0b10, 0b001, 0b0000, 0b1010, 0b000>;2027// TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR2028def : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>;2029def : RWSysReg<"TRCEXTINSELR1", 0b10, 0b001, 0b0000, 0b1001, 0b100>;2030def : RWSysReg<"TRCEXTINSELR2", 0b10, 0b001, 0b0000, 0b1010, 0b100>;2031def : RWSysReg<"TRCEXTINSELR3", 0b10, 0b001, 0b0000, 0b1011, 0b100>;2032} // FeatureETE2033 2034// Trace Buffer Extension System registers2035let Requires = [{ {AArch64::FeatureTRBE} }] in {2036// Name Op0 Op1 CRn CRm Op22037def : RWSysReg<"TRBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b000>;2038def : RWSysReg<"TRBPTR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b001>;2039def : RWSysReg<"TRBBASER_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b010>;2040def : RWSysReg<"TRBSR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b011>;2041def : RWSysReg<"TRBMAR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b100>;2042def : RWSysReg<"TRBMPAM_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b101>;2043def : RWSysReg<"TRBTRG_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b110>;2044def : ROSysReg<"TRBIDR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b111>;2045} // FeatureTRBE2046 2047 2048// v8.6a Activity Monitors Virtualization Support2049let Requires = [{ {AArch64::FeatureAMVS} }] in {2050// Name Op0 Op1 CRn CRm Op22051def : ROSysReg<"AMCG1IDR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b110>;2052foreach n = 0-15 in {2053 foreach x = 0-1 in {2054 def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2",2055 0b11, 0b100, 0b1101, 0b1000, 0b000>{2056 let Encoding{4} = x;2057 let Encoding{3-0} = n;2058 }2059 }2060}2061}2062 2063// v8.6a Fine Grained Virtualization Traps2064// Op0 Op1 CRn CRm Op22065let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in {2066def : RWSysReg<"HFGRTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b100>;2067def : RWSysReg<"HFGWTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b101>;2068def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>;2069def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>;2070def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>;2071def : RWSysReg<"HAFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b110>;2072 2073// v8.9a/v9.4a additions to Fine Grained Traps (FEAT_FGT2)2074// Op0 Op1 CRn CRm Op22075def : RWSysReg<"HDFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b000>;2076def : RWSysReg<"HDFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b001>;2077def : RWSysReg<"HFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b010>;2078def : RWSysReg<"HFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b011>;2079def : RWSysReg<"HFGITR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b111>;2080}2081 2082// v8.6a Enhanced Counter Virtualization2083// Op0 Op1 CRn CRm Op22084let Requires = [{ {AArch64::FeatureEnhancedCounterVirtualization} }] in {2085def : RWSysReg<"CNTSCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b100>;2086def : RWSysReg<"CNTISCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b101>;2087def : RWSysReg<"CNTPOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b110>;2088def : RWSysReg<"CNTVFRQ_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b111>;2089def : ROSysReg<"CNTPCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b101>;2090def : ROSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>;2091}2092 2093// v8.7a LD64B/ST64B Accelerator Extension system register2094let Requires = [{ {AArch64::FeatureLS64} }] in2095def : RWSysReg<"ACCDATA_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b101>;2096 2097// Branch Record Buffer system registers2098let Requires = [{ {AArch64::FeatureBRBE} }] in {2099def : RWSysReg<"BRBCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b000>;2100def : RWSysReg<"BRBCR_EL12", 0b10, 0b101, 0b1001, 0b0000, 0b000>;2101def : RWSysReg<"BRBCR_EL2", 0b10, 0b100, 0b1001, 0b0000, 0b000>;2102def : RWSysReg<"BRBFCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b001>;2103def : ROSysReg<"BRBIDR0_EL1", 0b10, 0b001, 0b1001, 0b0010, 0b000>;2104def : RWSysReg<"BRBINFINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b000>;2105def : RWSysReg<"BRBSRCINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b001>;2106def : RWSysReg<"BRBTGTINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b010>;2107def : RWSysReg<"BRBTS_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b010>;2108foreach n = 0-31 in {2109 defvar nb = !cast<bits<5>>(n);2110 def : ROSysReg<"BRBINF"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b00}>;2111 def : ROSysReg<"BRBSRC"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b01}>;2112 def : ROSysReg<"BRBTGT"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b10}>;2113}2114}2115 2116// Statistical Profiling Extension system register2117let Requires = [{ {AArch64::FeatureSPE_EEF} }] in2118def : RWSysReg<"PMSNEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b001>;2119 2120// Scalable Matrix Extension (SME)2121// Op0 Op1 CRn CRm Op22122let Requires = [{ {AArch64::FeatureSME} }] in {2123def : RWSysReg<"SMCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b110>;2124def : RWSysReg<"SMCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b110>;2125def : RWSysReg<"SMCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b110>;2126def : RWSysReg<"SMCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b110>;2127def : RWSysReg<"SVCR", 0b11, 0b011, 0b0100, 0b0010, 0b010>;2128def : RWSysReg<"SMPRI_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b100>;2129def : RWSysReg<"SMPRIMAP_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b101>;2130def : ROSysReg<"SMIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b110>;2131def : RWSysReg<"TPIDR2_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b101>;2132} // HasSME2133 2134// v8.4a MPAM and SME registers2135// Op0 Op1 CRn CRm Op22136let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in {2137def : RWSysReg<"MPAMSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b011>;2138} // HasMPAM, HasSME2139 2140// v8.8a Non-Maskable Interrupts2141let Requires = [{ {AArch64::FeatureNMI} }] in {2142 // Op0 Op1 CRn CRm Op22143 def : RWSysReg<"ALLINT", 0b11, 0b000, 0b0100, 0b0011, 0b000>;2144 def : ROSysReg<"ICC_NMIAR1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b101>; // FEAT_GICv3_NMI2145}2146 2147// v9.4a Guarded Control Stack Extension (GCS)2148// Op0 Op1 CRn CRm Op22149def : RWSysReg<"GCSCR_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b000>;2150def : RWSysReg<"GCSPR_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b001>;2151def : RWSysReg<"GCSCRE0_EL1", 0b11, 0b000, 0b0010, 0b0101, 0b010>;2152def : RWSysReg<"GCSPR_EL0", 0b11, 0b011, 0b0010, 0b0101, 0b001>;2153def : RWSysReg<"GCSCR_EL2", 0b11, 0b100, 0b0010, 0b0101, 0b000>;2154def : RWSysReg<"GCSPR_EL2", 0b11, 0b100, 0b0010, 0b0101, 0b001>;2155def : RWSysReg<"GCSCR_EL12", 0b11, 0b101, 0b0010, 0b0101, 0b000>;2156def : RWSysReg<"GCSPR_EL12", 0b11, 0b101, 0b0010, 0b0101, 0b001>;2157def : RWSysReg<"GCSCR_EL3", 0b11, 0b110, 0b0010, 0b0101, 0b000>;2158def : RWSysReg<"GCSPR_EL3", 0b11, 0b110, 0b0010, 0b0101, 0b001>;2159 2160// v8.9a/v9.4a Memory Attribute Index Enhancement (FEAT_AIE)2161// Op0 Op1 CRn CRm Op22162def : RWSysReg<"AMAIR2_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b001>;2163def : RWSysReg<"AMAIR2_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b001>;2164def : RWSysReg<"AMAIR2_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b001>;2165def : RWSysReg<"AMAIR2_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b001>;2166def : RWSysReg<"MAIR2_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b001>;2167def : RWSysReg<"MAIR2_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b001>;2168def : RWSysReg<"MAIR2_EL2", 0b11, 0b100, 0b1010, 0b0001, 0b001>;2169def : RWSysReg<"MAIR2_EL3", 0b11, 0b110, 0b1010, 0b0001, 0b001>;2170 2171// v8.9a/9.4a Stage 1 Permission Indirection Extension (FEAT_S1PIE)2172// Op0 Op1 CRn CRm Op22173def : RWSysReg<"PIRE0_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b010>;2174def : RWSysReg<"PIRE0_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b010>;2175def : RWSysReg<"PIRE0_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b010>;2176def : RWSysReg<"PIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b011>;2177def : RWSysReg<"PIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b011>;2178def : RWSysReg<"PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b011>;2179def : RWSysReg<"PIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b011>;2180 2181// v8.9a/v9.4a Stage 2 Permission Indirection Extension (FEAT_S2PIE)2182// Op0 Op1 CRn CRm Op22183def : RWSysReg<"S2PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b101>;2184 2185// v8.9a/v9.4a Stage 1 Permission Overlay Extension (FEAT_S1POE)2186// Op0 Op1 CRn CRm Op22187def : RWSysReg<"POR_EL0", 0b11, 0b011, 0b1010, 0b0010, 0b100>;2188def : RWSysReg<"POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b100>;2189def : RWSysReg<"POR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b100>;2190def : RWSysReg<"POR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b100>;2191def : RWSysReg<"POR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b100>;2192 2193// v8.9a/v9.4a Stage 2 Permission Overlay Extension (FEAT_S2POE)2194// Op0 Op1 CRn CRm Op22195def : RWSysReg<"S2POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b101>;2196 2197// v8.9a/v9.4a Extension to System Control Registers (FEAT_SCTLR2)2198// Op0 Op1 CRn CRm Op22199def : RWSysReg<"SCTLR2_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b011>;2200def : RWSysReg<"SCTLR2_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b011>;2201def : RWSysReg<"SCTLR2_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b011>;2202def : RWSysReg<"SCTLR2_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b011>;2203 2204// v8.9a/v9.4a Extension to Translation Control Registers (FEAT_TCR2)2205// Op0 Op1 CRn CRm Op22206def : RWSysReg<"TCR2_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b011>;2207def : RWSysReg<"TCR2_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b011>;2208def : RWSysReg<"TCR2_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b011>;2209 2210// v8.9a/9.4a Translation Hardening Extension (FEAT_THE)2211// Op0 Op1 CRn CRm Op22212let Requires = [{ {AArch64::FeatureTHE} }] in {2213def : RWSysReg<"RCWMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b110>;2214def : RWSysReg<"RCWSMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b011>;2215}2216 2217// v8.9a/9.4a new Debug feature (FEAT_DEBUGv8p9)2218// Op0 Op1 CRn CRm Op22219def : RWSysReg<"MDSELR_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b010>;2220 2221// v8.9a/9.4a new Performance Monitors Extension (FEAT_PMUv3p9)2222// Op0 Op1 CRn CRm Op22223def : RWSysReg<"PMUACR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b100>;2224 2225// v8.9a/9.4a PMU Snapshot Extension (FEAT_PMUv3_SS)2226// Op0 Op1 CRn CRm Op22227def : ROSysReg<"PMCCNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1011, 0b111>;2228def : ROSysReg<"PMICNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1100, 0b000>;2229def : RWSysReg<"PMSSCR_EL1", 0b11, 0b000, 0b1001, 0b1101, 0b011>;2230foreach n = 0-30 in {2231 defvar nb = !cast<bits<5>>(n);2232 def : ROSysReg<"PMEVCNTSVR"#n#"_EL1", 0b10, 0b000, 0b1110, {0b10,nb{4-3}}, nb{2-0}>;2233}2234 2235// v8.9a/v9.4a PMUv3 Fixed-function instruction counter (FEAT_PMUv3_ICNTR)2236// Op0 Op1 CRn CRm Op22237def : RWSysReg<"PMICNTR_EL0", 0b11, 0b011, 0b1001, 0b0100, 0b000>;2238def : RWSysReg<"PMICFILTR_EL0", 0b11, 0b011, 0b1001, 0b0110, 0b000>;2239 2240// v8.9a/v9.4a PMUv3 Performance Monitors Zero with Mask (FEAT_PMUv3p9/FEAT_PMUv3_ICNTR)2241// Op0 Op1 CRn CRm Op22242def : WOSysReg<"PMZR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b100>;2243 2244// v8.9a/9.4a Synchronous-Exception-Based Event Profiling extension (FEAT_SEBEP)2245// Op0 Op1 CRn CRm Op22246def : RWSysReg<"PMECR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b101>;2247def : RWSysReg<"PMIAR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b111>;2248 2249// v8.9a/9.4a System Performance Monitors Extension (FEAT_SPMU)2250// Op0 Op1 CRn CRm Op22251def : RWSysReg<"SPMACCESSR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b011>;2252def : RWSysReg<"SPMACCESSR_EL12", 0b10, 0b101, 0b1001, 0b1101, 0b011>;2253def : RWSysReg<"SPMACCESSR_EL2", 0b10, 0b100, 0b1001, 0b1101, 0b011>;2254def : RWSysReg<"SPMACCESSR_EL3", 0b10, 0b110, 0b1001, 0b1101, 0b011>;2255def : RWSysReg<"SPMCNTENCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b010>;2256def : RWSysReg<"SPMCNTENSET_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b001>;2257def : RWSysReg<"SPMCR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b000>;2258def : ROSysReg<"SPMDEVAFF_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b110>;2259def : ROSysReg<"SPMDEVARCH_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b101>;2260foreach n = 0-15 in {2261 defvar nb = !cast<bits<4>>(n);2262 // Op0 Op1 CRn CRm Op22263 def : RWSysReg<"SPMEVCNTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b000,nb{3}}, nb{2-0}>;2264 def : RWSysReg<"SPMEVFILT2R"#n#"_EL0", 0b10, 0b011, 0b1110, {0b011,nb{3}}, nb{2-0}>;2265 def : RWSysReg<"SPMEVFILTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b010,nb{3}}, nb{2-0}>;2266 def : RWSysReg<"SPMEVTYPER"#n#"_EL0", 0b10, 0b011, 0b1110, {0b001,nb{3}}, nb{2-0}>;2267}2268// Op0 Op1 CRn CRm Op22269def : ROSysReg<"SPMIIDR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b100>;2270def : RWSysReg<"SPMINTENCLR_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b010>;2271def : RWSysReg<"SPMINTENSET_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b001>;2272def : RWSysReg<"SPMOVSCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b011>;2273def : RWSysReg<"SPMOVSSET_EL0", 0b10, 0b011, 0b1001, 0b1110, 0b011>;2274def : RWSysReg<"SPMSELR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b101>;2275def : ROSysReg<"SPMCGCR0_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b000>;2276def : ROSysReg<"SPMCGCR1_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b001>;2277def : ROSysReg<"SPMCFGR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b111>;2278def : RWSysReg<"SPMROOTCR_EL3", 0b10, 0b110, 0b1001, 0b1110, 0b111>;2279def : RWSysReg<"SPMSCR_EL1", 0b10, 0b111, 0b1001, 0b1110, 0b111>;2280 2281// v8.9a/9.4a Instrumentation Extension (FEAT_ITE)2282// Op0 Op1 CRn CRm Op22283let Requires = [{ {AArch64::FeatureITE} }] in {2284def : RWSysReg<"TRCITEEDCR", 0b10, 0b001, 0b0000, 0b0010, 0b001>;2285def : RWSysReg<"TRCITECR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b011>;2286def : RWSysReg<"TRCITECR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b011>;2287def : RWSysReg<"TRCITECR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b011>;2288}2289 2290// v8.9a/9.4a SPE Data Source Filtering (FEAT_SPE_FDS)2291// Op0 Op1 CRn CRm Op22292def : RWSysReg<"PMSDSFR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b100>;2293 2294// v8.9a/9.4a RASv2 (FEAT_RASv2)2295// Op0 Op1 CRn CRm Op22296let Requires = [{ {AArch64::FeatureRASv2} }] in2297def : ROSysReg<"ERXGSR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b010>;2298 2299// v8.9a/9.4a Physical Fault Address (FEAT_PFAR)2300// Op0 Op1 CRn CRm Op22301def : RWSysReg<"PFAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b101>;2302def : RWSysReg<"PFAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b101>;2303def : RWSysReg<"PFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b101>;2304 2305// v9.4a Exception-based event profiling (FEAT_EBEP)2306// Op0 Op1 CRn CRm Op22307def : RWSysReg<"PM", 0b11, 0b000, 0b0100, 0b0011, 0b001>;2308 2309// 2023 ISA Extension2310// AArch64 Floating-point Mode Register controls behaviors of the FP82311// instructions (FEAT_FPMR)2312// Op0 Op1 CRn CRm Op22313def : ROSysReg<"ID_AA64FPFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b111>;2314def : RWSysReg<"FPMR", 0b11, 0b011, 0b0100, 0b0100, 0b010>;2315 2316// v9.5a Software Stepping Enhancements (FEAT_STEP2)2317// Op0 Op1 CRn CRm Op22318def : RWSysReg<"MDSTEPOP_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b010>;2319 2320// v9.5a System PMU zero register (FEAT_SPMU2)2321// Op0 Op1 CRn CRm Op22322def : WOSysReg<"SPMZR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b100>;2323 2324// v9.5a Delegated SError exceptions for EL3 (FEAT_E3DSE)2325// Op0 Op1 CRn CRm Op22326def : RWSysReg<"VDISR_EL3", 0b11, 0b110, 0b1100, 0b0001, 0b001>;2327def : RWSysReg<"VSESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b011>;2328 2329// v9.5a Hardware Dirty State Tracking Structure (FEAT_HDBSS)2330// Op0 Op1 CRn CRm Op22331def : RWSysReg<"HDBSSBR_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b010>;2332def : RWSysReg<"HDBSSPROD_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b011>;2333 2334// v9.5a Hardware Accelerator for Cleaning Dirty State (FEAT_HACDBS)2335// Op0 Op1 CRn CRm Op22336def : RWSysReg<"HACDBSBR_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b100>;2337def : RWSysReg<"HACDBSCONS_EL2", 0b11, 0b100, 0b0010, 0b0011, 0b101>;2338 2339// v9.5a Fine Grained Write Trap EL3 (FEAT_FGWTE3)2340// Op0 Op1 CRn CRm Op22341def : RWSysReg<"FGWTE3_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b101>;2342 2343// v9.6a Memory partitioning and monitoring (FEAT_MPAM) registers2344// Op0 Op1 CRn CRm Op22345def : ROSysReg<"MPAMBWIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b101>;2346def : RWSysReg<"MPAMBW3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b100>;2347def : RWSysReg<"MPAMBW2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b100>;2348def : RWSysReg<"MPAMBW1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b100>;2349def : RWSysReg<"MPAMBW1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b100>;2350def : RWSysReg<"MPAMBW0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b101>;2351def : RWSysReg<"MPAMBWCAP_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b110>;2352def : RWSysReg<"MPAMBWSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b111>;2353 2354// v9.7a Memory partitioning and monitoring version 22355// (FEAT_MPAMv2) registers2356// Op0 Op1 CRn CRm Op22357// MPAM system registers that are also available for MPAMv22358def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>;2359def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>;2360def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>;2361def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>;2362def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>;2363def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>;2364def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>;2365// Only MPAMv2 registers2366def : RWSysReg<"MPAMCTL_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b010>;2367def : RWSysReg<"MPAMCTL_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b010>;2368def : RWSysReg<"MPAMCTL_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b010>;2369def : RWSysReg<"MPAMCTL_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b010>;2370def : RWSysReg<"MPAMVIDCR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b000>;2371def : RWSysReg<"MPAMVIDSR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b001>;2372def : RWSysReg<"MPAMVIDSR_EL3", 0b11, 0b110, 0b1010, 0b0111, 0b001>;2373 2374//===----------------------------------------------------------------------===//2375// FEAT_SRMASK v9.6a registers2376//===----------------------------------------------------------------------===//2377def : RWSysReg<"SCTLRMASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b000>;2378def : RWSysReg<"SCTLRMASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b000>;2379def : RWSysReg<"SCTLRMASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b000>;2380def : RWSysReg<"CPACRMASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b010>;2381def : RWSysReg<"CPTRMASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b010>;2382def : RWSysReg<"CPACRMASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b010>;2383def : RWSysReg<"SCTLR2MASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b011>;2384def : RWSysReg<"SCTLR2MASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b011>;2385def : RWSysReg<"SCTLR2MASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b011>;2386def : RWSysReg<"CPACRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b100>;2387def : RWSysReg<"SCTLRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b110>;2388def : RWSysReg<"SCTLR2ALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b111>;2389def : RWSysReg<"TCRMASK_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b010>;2390def : RWSysReg<"TCRMASK_EL2", 0b11, 0b100, 0b0010, 0b0111, 0b010>;2391def : RWSysReg<"TCRMASK_EL12", 0b11, 0b101, 0b0010, 0b0111, 0b010>;2392def : RWSysReg<"TCR2MASK_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b011>;2393def : RWSysReg<"TCR2MASK_EL2", 0b11, 0b100, 0b0010, 0b0111, 0b011>;2394def : RWSysReg<"TCR2MASK_EL12", 0b11, 0b101, 0b0010, 0b0111, 0b011>;2395def : RWSysReg<"TCRALIAS_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b110>;2396def : RWSysReg<"TCR2ALIAS_EL1", 0b11, 0b000, 0b0010, 0b0111, 0b111>;2397def : RWSysReg<"ACTLRMASK_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b001>;2398def : RWSysReg<"ACTLRMASK_EL2", 0b11, 0b100, 0b0001, 0b0100, 0b001>;2399def : RWSysReg<"ACTLRMASK_EL12", 0b11, 0b101, 0b0001, 0b0100, 0b001>;2400def : RWSysReg<"ACTLRALIAS_EL1", 0b11, 0b000, 0b0001, 0b0100, 0b101>;2401 2402//===----------------------------------------------------------------------===//2403// v9.6a PCDPHINT instruction options.2404//===----------------------------------------------------------------------===//2405 2406class PHint<bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,2407 bits<3> op2, string name> {2408 string Name = name;2409 bits<16> Encoding;2410 let Encoding{15-14} = op0;2411 let Encoding{13-11} = op1;2412 let Encoding{10-7} = crn;2413 let Encoding{6-3} = crm;2414 let Encoding{2-0} = op2;2415 code Requires = [{ {} }];2416}2417 2418def PHintValues : GenericEnum {2419 let FilterClass = "PHint";2420 let NameField = "Name";2421 let ValueField = "Encoding";2422}2423 2424def PHintsList : GenericTable {2425 let FilterClass = "PHint";2426 let Fields = ["Name", "Encoding", "Requires"];2427 2428 let PrimaryKey = ["Encoding"];2429 let PrimaryKeyName = "lookupPHintByEncoding";2430}2431 2432def lookupPHintByName : SearchIndex {2433 let Table = PHintsList;2434 let Key = ["Name"];2435}2436 2437let Requires = [{ {AArch64::FeaturePCDPHINT} }] in {2438 def KEEP : PHint<0b00, 0b000, 0b0000, 0b0000, 0b000, "keep">;2439 def STRM : PHint<0b00, 0b000, 0b0000, 0b0000, 0b001, "strm">;2440}2441 2442// v9.6a Realm management extension enhancements2443def : RWSysReg<"GPCBW_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b101>;2444 2445// v9.6a Statistical Profiling Extension exception registers (FEAT_SPE_EXC)2446// Op0 Op1 CRn CRm Op22447def : RWSysReg<"PMBMAR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b101>;2448def : RWSysReg<"PMBSR_EL12", 0b11, 0b101, 0b1001, 0b1010, 0b011>;2449def : RWSysReg<"PMBSR_EL2", 0b11, 0b100, 0b1001, 0b1010, 0b011>;2450def : RWSysReg<"PMBSR_EL3", 0b11, 0b110, 0b1001, 0b1010, 0b011>;2451 2452// v9.6a Trace Buffer Management Events exception registers (FEAT_TRBE_EXC)2453// Op0 Op1 CRn CRm Op22454def : RWSysReg<"TRBSR_EL12", 0b11, 0b101, 0b1001, 0b1011, 0b011>;2455def : RWSysReg<"TRBSR_EL2", 0b11, 0b100, 0b1001, 0b1011, 0b011>;2456def : RWSysReg<"TRBSR_EL3", 0b11, 0b110, 0b1001, 0b1011, 0b011>;2457 2458// v9.6 FEAT_PoPS2459//2460let Requires = [{ {AArch64::FeaturePoPS} }] in {2461def : DC<"CIVAPS", 0b000, 0b0111, 0b1111, 0b001>;2462}2463 2464let Requires = [{ {AArch64::FeaturePoPS, AArch64::FeatureMTE} }] in {2465def : DC<"CIGDVAPS", 0b000, 0b0111, 0b1111, 0b101>;2466}2467 2468// v9.7a TLBI domains system registers (MemSys)2469foreach n = 0-3 in {2470 defvar nb = !cast<bits<3>>(n);2471 def : RWSysReg<"VTLBID"#n#"_EL2", 0b11, 0b100, 0b0010, 0b1000, nb>;2472}2473 2474foreach n = 0-3 in {2475 defvar nb = !cast<bits<3>>(n);2476 def : RWSysReg<"VTLBIDOS"#n#"_EL2", 0b11, 0b100, 0b0010, 0b1001, nb>;2477}2478 2479def : ROSysReg<"TLBIDIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b110>;2480 2481// MPAM Lookaside Buffer Invalidate (MLBI) instructions2482class MLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg> {2483 string Name = name;2484 bits<14> Encoding;2485 let Encoding{13-11} = op1;2486 let Encoding{10-7} = crn;2487 let Encoding{6-3} = crm;2488 let Encoding{2-0} = op2;2489 bit NeedsReg = needsreg;2490 string RequiresStr = [{ {AArch64::FeatureMPAMv2} }];2491}2492 2493def MLBITable : GenericTable {2494 let FilterClass = "MLBI";2495 let CppTypeName = "MLBI";2496 let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];2497 2498 let PrimaryKey = ["Encoding"];2499 let PrimaryKeyName = "lookupMLBIByEncoding";2500}2501 2502def lookupMLBIByName : SearchIndex {2503 let Table = MLBITable;2504 let Key = ["Name"];2505}2506 2507// Op1 CRn CRm Op2 needsReg2508def : MLBI<"ALLE1", 0b100, 0b0111, 0b0000, 0b100, 0>;2509def : MLBI<"VMALLE1", 0b100, 0b0111, 0b0000, 0b101, 0>;2510def : MLBI<"VPIDE1", 0b100, 0b0111, 0b0000, 0b110, 1>;2511def : MLBI<"VPMGE1", 0b100, 0b0111, 0b0000, 0b111, 1>;2512 2513 2514// v9.7-A GICv5 (FEAT_GCIE)2515// CPU Interface Registers2516// Op0 Op1 CRn CRm Op22517def : RWSysReg<"ICC_APR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b000>;2518def : RWSysReg<"ICC_APR_EL3", 0b11, 0b110, 0b1100, 0b1000, 0b000>;2519def : RWSysReg<"ICC_CR0_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b001>;2520def : RWSysReg<"ICC_CR0_EL3", 0b11, 0b110, 0b1100, 0b1001, 0b000>;2521def : ROSysReg<"ICC_DOMHPPIR_EL3", 0b11, 0b110, 0b1100, 0b1000, 0b010>;2522def : ROSysReg<"ICC_HAPR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b011>;2523def : ROSysReg<"ICC_HPPIR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b011>;2524def : ROSysReg<"ICC_HPPIR_EL3", 0b11, 0b110, 0b1100, 0b1001, 0b001>;2525def : ROSysReg<"ICC_IAFFIDR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b101>;2526def : RWSysReg<"ICC_ICSR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b100>;2527def : ROSysReg<"ICC_IDR0_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b010>;2528def : RWSysReg<"ICC_PCR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b010>;2529def : RWSysReg<"ICC_PCR_EL3", 0b11, 0b110, 0b1100, 0b1000, 0b001>;2530 2531// Virtual CPU Interface Registers2532// Op0 Op1 CRn CRm Op22533def : RWSysReg<"ICV_APR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b000>;2534def : RWSysReg<"ICV_CR0_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b001>;2535def : RWSysReg<"ICV_HAPR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b011>;2536def : RWSysReg<"ICV_HPPIR_EL1", 0b11, 0b000, 0b1100, 0b1010, 0b011>;2537def : RWSysReg<"ICV_PCR_EL1", 0b11, 0b001, 0b1100, 0b0000, 0b010>;2538 2539foreach n=0-3 in {2540 defvar nb = !cast<bits<2>>(n);2541// Op0 Op1 CRn CRm Op22542 def : RWSysReg<"ICC_PPI_DOMAINR"#n#"_EL3", 0b11, 0b110, 0b1100, 0b1000, {0b1,nb{1-0}}>;2543 2544}2545 2546foreach n=0-15 in{2547 defvar nb = !cast<bits<4>>(n);2548// Op0 Op1 CRn CRm Op22549 def : RWSysReg<"ICC_PPI_PRIORITYR"#n#"_EL1", 0b11, 0b000, 0b1100, {0b111,nb{3}}, nb{2-0}>;2550}2551 2552// PPI and Virtual PPI Registers2553multiclass PPIRegisters<string prefix> {2554 foreach n=0-1 in {2555 defvar nb = !cast<bit>(n);2556// Op0 Op1 CRn CRm Op22557 def : RWSysReg<prefix#"_PPI_CACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b00,nb}>;2558 def : RWSysReg<prefix#"_PPI_CPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b10,nb}>;2559 def : RWSysReg<prefix#"_PPI_ENABLER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b11,nb}>;2560 def : RWSysReg<prefix#"_PPI_SACTIVER"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b01,nb}>;2561 def : RWSysReg<prefix#"_PPI_SPENDR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1101, {0b11,nb}>;2562 def : RWSysReg<prefix#"_PPI_HMR"#n#"_EL1", 0b11, 0b000, 0b1100, 0b1010, {0b00,nb}>;2563 }2564}2565 2566defm : PPIRegisters<"ICC">; // PPI Registers2567defm : PPIRegisters<"ICV">; // Virtual PPI Registers2568 2569foreach n=0-15 in {2570 defvar nb = !cast<bits<4>>(n);2571// Op0 Op1 CRn CRm Op22572 def : RWSysReg<"ICV_PPI_PRIORITYR"#n#"_EL1", 0b11, 0b000, 0b1100, {0b111,nb{3}}, nb{2-0}>;2573}2574 2575// Hypervisor Control Registers2576// Op0 Op1 CRn CRm Op22577def : RWSysReg<"ICH_APR_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b100>;2578def : RWSysReg<"ICH_CONTEXTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b110>;2579def : RWSysReg<"ICH_HFGITR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b111>;2580def : RWSysReg<"ICH_HFGRTR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b100>;2581def : RWSysReg<"ICH_HFGWTR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b110>;2582def : ROSysReg<"ICH_HPPIR_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b101>;2583def : RWSysReg<"ICH_VCTLR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b100>;2584 2585foreach n=0-1 in {2586 defvar nb = !cast<bit>(n);2587// Op0 Op1 CRn CRm Op22588def : RWSysReg<"ICH_PPI_ACTIVER"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b11,nb}>;2589def : RWSysReg<"ICH_PPI_DVIR"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b00,nb}>;2590def : RWSysReg<"ICH_PPI_ENABLER"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b01,nb}>;2591def : RWSysReg<"ICH_PPI_PENDR"#n#"_EL2", 0b11, 0b100, 0b1100, 0b1010, {0b10,nb}>;2592}2593 2594foreach n=0-15 in {2595 defvar nb = !cast<bits<4>>(n);2596// Op0 Op1 CRn CRm Op22597 def : RWSysReg<"ICH_PPI_PRIORITYR"#n#"_EL2", 0b11, 0b100, 0b1100, {0b111,nb{3}}, nb{2-0}>;2598}2599 2600//===----------------------------------------------------------------------===//2601// GICv5 instruction options.2602//===----------------------------------------------------------------------===//2603 2604// GIC2605class GIC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg = 1> {2606 string Name = name;2607 bits<14> Encoding;2608 let Encoding{13-11} = op1;2609 let Encoding{10-7} = crn;2610 let Encoding{6-3} = crm;2611 let Encoding{2-0} = op2;2612 bit NeedsReg = needsreg;2613 string RequiresStr = [{ {AArch64::FeatureGCIE} }];2614}2615 2616// GSB2617class GSB<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> {2618 string Name = name;2619 bits<14> Encoding;2620 let Encoding{13-11} = op1;2621 let Encoding{10-7} = crn;2622 let Encoding{6-3} = crm;2623 let Encoding{2-0} = op2;2624 string RequiresStr = [{ {AArch64::FeatureGCIE} }];2625}2626 2627// GICR2628class GICR<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> {2629 string Name = name;2630 bits<14> Encoding;2631 let Encoding{13-11} = op1;2632 let Encoding{10-7} = crn;2633 let Encoding{6-3} = crm;2634 let Encoding{2-0} = op2;2635 bit NeedsReg = 1;2636 string RequiresStr = [{ {AArch64::FeatureGCIE} }];2637}2638 2639def GICTable : GenericTable {2640 let FilterClass = "GIC";2641 let CppTypeName = "GIC";2642 let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];2643 2644 let PrimaryKey = ["Encoding"];2645 let PrimaryKeyName = "lookupGICByEncoding";2646}2647 2648def GSBTable : GenericTable {2649 let FilterClass = "GSB";2650 let CppTypeName = "GSB";2651 let Fields = ["Name", "Encoding", "RequiresStr"];2652 2653 let PrimaryKey = ["Encoding"];2654 let PrimaryKeyName = "lookupGSBByEncoding";2655}2656 2657def GICRTable : GenericTable {2658 let FilterClass = "GICR";2659 let CppTypeName = "GICR";2660 let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];2661 2662 let PrimaryKey = ["Encoding"];2663 let PrimaryKeyName = "lookupGICRByEncoding";2664}2665 2666def lookupGICByName : SearchIndex {2667 let Table = GICTable;2668 let Key = ["Name"];2669}2670 2671def lookupGSBByName : SearchIndex {2672 let Table = GSBTable;2673 let Key = ["Name"];2674}2675 2676def lookupGICRByName : SearchIndex {2677 let Table = GICRTable;2678 let Key = ["Name"];2679}2680 2681// Op1 CRn CRm Op22682def : GSB<"sys", 0b000, 0b1100, 0b0000, 0b000>;2683def : GSB<"ack", 0b000, 0b1100, 0b0000, 0b001>;2684 2685// Op1 CRn CRm Op22686def : GICR<"cdia", 0b000, 0b1100, 0b0011, 0b000>;2687def : GICR<"cdnmia", 0b000, 0b1100, 0b0011, 0b001>;2688 2689// Op1 CRn CRm Op2, needsreg2690def : GIC<"cdaff", 0b000, 0b1100, 0b0001, 0b011>;2691def : GIC<"cddi", 0b000, 0b1100, 0b0010, 0b000>;2692def : GIC<"cddis", 0b000, 0b1100, 0b0001, 0b000>;2693def : GIC<"cden", 0b000, 0b1100, 0b0001, 0b001>;2694def : GIC<"cdeoi", 0b000, 0b1100, 0b0001, 0b111, 0>;2695def : GIC<"cdhm", 0b000, 0b1100, 0b0010, 0b001>;2696def : GIC<"cdpend", 0b000, 0b1100, 0b0001, 0b100>;2697def : GIC<"cdpri", 0b000, 0b1100, 0b0001, 0b010>;2698def : GIC<"cdrcfg", 0b000, 0b1100, 0b0001, 0b101>;2699def : GIC<"vdaff", 0b100, 0b1100, 0b0001, 0b011>;2700def : GIC<"vddi", 0b100, 0b1100, 0b0010, 0b000>;2701def : GIC<"vddis", 0b100, 0b1100, 0b0001, 0b000>;2702def : GIC<"vden", 0b100, 0b1100, 0b0001, 0b001>;2703def : GIC<"vdhm", 0b100, 0b1100, 0b0010, 0b001>;2704def : GIC<"vdpend", 0b100, 0b1100, 0b0001, 0b100>;2705def : GIC<"vdpri", 0b100, 0b1100, 0b0001, 0b010>;2706def : GIC<"vdrcfg", 0b100, 0b1100, 0b0001, 0b101>;2707def : GIC<"ldaff", 0b110, 0b1100, 0b0001, 0b011>;2708def : GIC<"lddi", 0b110, 0b1100, 0b0010, 0b000>;2709def : GIC<"lddis", 0b110, 0b1100, 0b0001, 0b000>;2710def : GIC<"lden", 0b110, 0b1100, 0b0001, 0b001>;2711def : GIC<"ldhm", 0b110, 0b1100, 0b0010, 0b001>;2712def : GIC<"ldpend", 0b110, 0b1100, 0b0001, 0b100>;2713def : GIC<"ldpri", 0b110, 0b1100, 0b0001, 0b010>;2714def : GIC<"ldrcfg", 0b110, 0b1100, 0b0001, 0b101>;2715 2716 2717// Stage 1 Permission Overlays Extension 2 (FEAT_S1POE2).2718// Op0 Op1 CRn CRm Op22719def : RWSysReg<"DPOTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b110>;2720def : RWSysReg<"DPOTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b110>;2721def : RWSysReg<"DPOTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b111>;2722def : RWSysReg<"DPOTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b111>;2723def : RWSysReg<"DPOTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b110>;2724def : RWSysReg<"DPOTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b111>;2725def : RWSysReg<"DPOTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b110>;2726 2727// Op0 Op1 CRn CRm Op22728def : RWSysReg<"IRTBRU_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b100>;2729def : RWSysReg<"IRTBRU_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b100>;2730def : RWSysReg<"IRTBRP_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b101>;2731def : RWSysReg<"IRTBRP_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b101>;2732def : RWSysReg<"IRTBRU_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b100>;2733def : RWSysReg<"IRTBRP_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b101>;2734def : RWSysReg<"IRTBRP_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b101>;2735 2736// Op0 Op1 CRn CRm Op22737def : RWSysReg<"TTTBRU_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b110>;2738def : RWSysReg<"TTTBRU_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b110>;2739def : RWSysReg<"TTTBRP_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b111>;2740def : RWSysReg<"TTTBRP_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b111>;2741def : RWSysReg<"TTTBRU_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b110>;2742def : RWSysReg<"TTTBRP_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b111>;2743def : RWSysReg<"TTTBRP_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b111>;2744 2745foreach n = 0-15 in {2746 defvar nb = !cast<bits<4>>(n);2747 // Op0 Op1 CRn CRm Op22748 def : RWSysReg<"FGDTP"#n#"_EL1", 0b11, 0b000, 0b0011, {0b001,nb{3}}, nb{2-0}>;2749 def : RWSysReg<"FGDTP"#n#"_EL2", 0b11, 0b100, 0b0011, {0b001,nb{3}}, nb{2-0}>;2750 def : RWSysReg<"FGDTP"#n#"_EL12", 0b11, 0b101, 0b0011, {0b001,nb{3}}, nb{2-0}>;2751 def : RWSysReg<"FGDTP"#n#"_EL3", 0b11, 0b110, 0b0011, {0b001,nb{3}}, nb{2-0}>;2752 2753 def : RWSysReg<"FGDTU"#n#"_EL1", 0b11, 0b000, 0b0011, {0b010,nb{3}}, nb{2-0}>;2754 def : RWSysReg<"FGDTU"#n#"_EL2", 0b11, 0b100, 0b0011, {0b010,nb{3}}, nb{2-0}>;2755 def : RWSysReg<"FGDTU"#n#"_EL12", 0b11, 0b101, 0b0011, {0b010,nb{3}}, nb{2-0}>;2756}2757 2758// Op0 Op1 CRn CRm Op22759def : RWSysReg<"LDSTT_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b111>;2760def : RWSysReg<"LDSTT_EL12", 0b11, 0b101, 0b0010, 0b0001, 0b111>;2761def : RWSysReg<"LDSTT_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b111>;2762 2763// Op0 Op1 CRn CRm Op22764def : RWSysReg<"TINDEX_EL0", 0b11, 0b011, 0b0100, 0b0000, 0b011>;2765def : RWSysReg<"TINDEX_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b011>;2766def : RWSysReg<"TINDEX_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b011>;2767def : RWSysReg<"TINDEX_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b011>;2768def : RWSysReg<"TINDEX_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b011>;2769 2770// Op0 Op1 CRn CRm Op22771def : RWSysReg<"STINDEX_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b010>;2772def : RWSysReg<"STINDEX_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b010>;2773def : RWSysReg<"STINDEX_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b010>;2774def : RWSysReg<"STINDEX_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b010>;2775 2776// Op0 Op1 CRn CRm Op22777def : RWSysReg<"TPIDR3_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b000>;2778def : RWSysReg<"TPIDR3_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b000>;2779def : RWSysReg<"TPIDR3_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b000>;2780def : RWSysReg<"TPIDR3_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b000>;2781def : RWSysReg<"TPIDR3_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b000>;2782 2783// Op0 Op1 CRn CRm Op22784def : RWSysReg<"VNCCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b001>;2785 2786// Op0 Op1 CRn CRm Op22787def : RWSysReg<"DPOCR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b010>;2788 2789foreach n = 0-15 in {2790 defvar nb = !cast<bits<4>>(n);2791 // Op0 Op1 CRn CRm Op22792 def : RWSysReg<"AFGDTP"#n#"_EL1", 0b11, 0b000, 0b0011, {0b011,nb{3}}, nb{2-0}>;2793 def : RWSysReg<"AFGDTU"#n#"_EL1", 0b11, 0b000, 0b0011, {0b100,nb{3}}, nb{2-0}>;2794 def : RWSysReg<"AFGDTP"#n#"_EL2", 0b11, 0b100, 0b0011, {0b011,nb{3}}, nb{2-0}>;2795 def : RWSysReg<"AFGDTU"#n#"_EL2", 0b11, 0b100, 0b0011, {0b100,nb{3}}, nb{2-0}>;2796 def : RWSysReg<"AFGDTP"#n#"_EL12", 0b11, 0b101, 0b0011, {0b011,nb{3}}, nb{2-0}>;2797 def : RWSysReg<"AFGDTU"#n#"_EL12", 0b11, 0b101, 0b0011, {0b100,nb{3}}, nb{2-0}>;2798 def : RWSysReg<"AFGDTP"#n#"_EL3", 0b11, 0b110, 0b0011, {0b011,nb{3}}, nb{2-0}>;2799}2800 2801// Extra S1POE2 Hypervisor Configuration Registers2802// Op0 Op1 CRn CRm Op22803def : RWSysReg<"HCRMASK_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b110>;2804def : RWSysReg<"HCRXMASK_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b111>;2805def : RWSysReg<"NVHCR_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b000>;2806def : RWSysReg<"NVHCRX_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b001>;2807def : RWSysReg<"NVHCRMASK_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b100>;2808def : RWSysReg<"NVHCRXMASK_EL2", 0b11, 0b100, 0b0001, 0b0101, 0b101>;2809 2810// S1POE2 Thread private state extension (FEAT_TPS/TPSP).2811foreach n = 0-1 in {2812 defvar nb = !cast<bits<1>>(n);2813 // Op0 Op1 CRn CRm Op22814 def : RWSysReg<"TPMIN"#n#"_EL0", 0b11, 0b011, 0b0010, 0b0010, {0b1,nb,0}>;2815 def : RWSysReg<"TPMAX"#n#"_EL0", 0b11, 0b011, 0b0010, 0b0010, {0b1,nb,1}>;2816 def : RWSysReg<"TPMIN"#n#"_EL1", 0b11, 0b000, 0b0010, 0b0010, {0b1,nb,0}>;2817 def : RWSysReg<"TPMAX"#n#"_EL1", 0b11, 0b000, 0b0010, 0b0010, {0b1,nb,1}>;2818 def : RWSysReg<"TPMIN"#n#"_EL2", 0b11, 0b100, 0b0010, 0b0010, {0b1,nb,0}>;2819 def : RWSysReg<"TPMAX"#n#"_EL2", 0b11, 0b100, 0b0010, 0b0010, {0b1,nb,1}>;2820 def : RWSysReg<"TPMIN"#n#"_EL12", 0b11, 0b101, 0b0010, 0b0010, {0b1,nb,0}>;2821 def : RWSysReg<"TPMAX"#n#"_EL12", 0b11, 0b101, 0b0010, 0b0010, {0b1,nb,1}>;2822}2823 2824class PLBIEntry<bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, string name,2825 bit needsreg, bit optionalreg> {2826 string Name = name;2827 bits<14> Encoding;2828 let Encoding{13-11} = op1;2829 let Encoding{10-7} = crn;2830 let Encoding{6-3} = crm;2831 let Encoding{2-0} = op2;2832 bit NeedsReg = needsreg;2833 bit OptionalReg = optionalreg;2834 string RequiresStr = [{ {AArch64::FeatureS1POE2} }];2835}2836 2837def PLBITable : GenericTable {2838 let FilterClass = "PLBIEntry";2839 let CppTypeName = "PLBI";2840 let Fields = ["Name", "Encoding", "NeedsReg", "OptionalReg", "RequiresStr"];2841 2842 let PrimaryKey = ["Encoding"];2843 let PrimaryKeyName = "lookupPLBIByEncoding";2844}2845 2846def lookupPLBIByName : SearchIndex {2847 let Table = PLBITable;2848 let Key = ["Name"];2849}2850 2851multiclass PLBI<string name, bits<3> op1, bits<4> crn, bits<3> op2,2852 bit needsreg, bit optreg> {2853 // Entries containing "IS" or "OS" allow optional regs when +tlbid enabled2854 def : PLBIEntry<op1, crn, 0b0111, op2, name, needsreg, 0>;2855 def : PLBIEntry<op1, crn, 0b0011, op2, name#"IS", needsreg, optreg>;2856 def : PLBIEntry<op1, crn, 0b0001, op2, name#"OS", needsreg, optreg>;2857 def : PLBIEntry<op1, crn, 0b1111, op2, name#"NXS", needsreg, 0>;2858 def : PLBIEntry<op1, crn, 0b1011, op2, name#"ISNXS", needsreg, optreg>;2859 def : PLBIEntry<op1, crn, 0b1001, op2, name#"OSNXS", needsreg, optreg>;2860}2861 2862// CRm defines above six variants of each instruction. It is omitted here.2863// Op1 CRn Op2 nr optreg2864defm : PLBI<"ALLE3", 0b110, 0b1010, 0b000, 0, 0>;2865defm : PLBI<"ALLE2", 0b100, 0b1010, 0b000, 0, 1>;2866defm : PLBI<"ALLE1", 0b100, 0b1010, 0b100, 0, 1>;2867defm : PLBI<"VMALLE1", 0b000, 0b1010, 0b000, 0, 1>;2868defm : PLBI<"ASIDE1", 0b000, 0b1010, 0b010, 1, 0>;2869defm : PLBI<"PERME3", 0b110, 0b1010, 0b001, 1, 0>;2870defm : PLBI<"PERME2", 0b100, 0b1010, 0b001, 1, 0>;2871defm : PLBI<"PERME1", 0b000, 0b1010, 0b001, 1, 0>;2872defm : PLBI<"PERMAE1", 0b000, 0b1010, 0b011, 1, 0>;2873