931 lines · cpp
1//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9//10//===----------------------------------------------------------------------===//11 12#include "AArch64TargetMachine.h"13#include "AArch64.h"14#include "AArch64MachineFunctionInfo.h"15#include "AArch64MachineScheduler.h"16#include "AArch64MacroFusion.h"17#include "AArch64Subtarget.h"18#include "AArch64TargetObjectFile.h"19#include "AArch64TargetTransformInfo.h"20#include "MCTargetDesc/AArch64MCTargetDesc.h"21#include "TargetInfo/AArch64TargetInfo.h"22#include "llvm/Analysis/TargetTransformInfo.h"23#include "llvm/Analysis/ValueTracking.h"24#include "llvm/CodeGen/CSEConfigBase.h"25#include "llvm/CodeGen/GlobalISel/CSEInfo.h"26#include "llvm/CodeGen/GlobalISel/IRTranslator.h"27#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"28#include "llvm/CodeGen/GlobalISel/Legalizer.h"29#include "llvm/CodeGen/GlobalISel/LoadStoreOpt.h"30#include "llvm/CodeGen/GlobalISel/Localizer.h"31#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"32#include "llvm/CodeGen/MIRParser/MIParser.h"33#include "llvm/CodeGen/MachineScheduler.h"34#include "llvm/CodeGen/Passes.h"35#include "llvm/CodeGen/TargetInstrInfo.h"36#include "llvm/CodeGen/TargetPassConfig.h"37#include "llvm/IR/Attributes.h"38#include "llvm/IR/Function.h"39#include "llvm/InitializePasses.h"40#include "llvm/MC/MCAsmInfo.h"41#include "llvm/MC/MCTargetOptions.h"42#include "llvm/MC/TargetRegistry.h"43#include "llvm/Pass.h"44#include "llvm/Passes/PassBuilder.h"45#include "llvm/Support/CodeGen.h"46#include "llvm/Support/CommandLine.h"47#include "llvm/Support/Compiler.h"48#include "llvm/Target/TargetLoweringObjectFile.h"49#include "llvm/Target/TargetOptions.h"50#include "llvm/TargetParser/Triple.h"51#include "llvm/Transforms/CFGuard.h"52#include "llvm/Transforms/Scalar.h"53#include "llvm/Transforms/Utils/LowerIFunc.h"54#include "llvm/Transforms/Vectorize/LoopIdiomVectorize.h"55#include <memory>56 57using namespace llvm;58 59static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",60 cl::desc("Enable the CCMP formation pass"),61 cl::init(true), cl::Hidden);62 63static cl::opt<bool>64 EnableCondBrTuning("aarch64-enable-cond-br-tune",65 cl::desc("Enable the conditional branch tuning pass"),66 cl::init(true), cl::Hidden);67 68static cl::opt<bool> EnableAArch64CopyPropagation(69 "aarch64-enable-copy-propagation",70 cl::desc("Enable the copy propagation with AArch64 copy instr"),71 cl::init(true), cl::Hidden);72 73static cl::opt<bool> EnableMCR("aarch64-enable-mcr",74 cl::desc("Enable the machine combiner pass"),75 cl::init(true), cl::Hidden);76 77static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",78 cl::desc("Suppress STP for AArch64"),79 cl::init(true), cl::Hidden);80 81static cl::opt<bool> EnableAdvSIMDScalar(82 "aarch64-enable-simd-scalar",83 cl::desc("Enable use of AdvSIMD scalar integer instructions"),84 cl::init(false), cl::Hidden);85 86static cl::opt<bool>87 EnablePromoteConstant("aarch64-enable-promote-const",88 cl::desc("Enable the promote constant pass"),89 cl::init(true), cl::Hidden);90 91static cl::opt<bool> EnableCollectLOH(92 "aarch64-enable-collect-loh",93 cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),94 cl::init(true), cl::Hidden);95 96static cl::opt<bool>97 EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,98 cl::desc("Enable the pass that removes dead"99 " definitions and replaces stores to"100 " them with stores to the zero"101 " register"),102 cl::init(true));103 104static cl::opt<bool> EnableRedundantCopyElimination(105 "aarch64-enable-copyelim",106 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),107 cl::Hidden);108 109static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",110 cl::desc("Enable the load/store pair"111 " optimization pass"),112 cl::init(true), cl::Hidden);113 114static cl::opt<bool> EnableAtomicTidy(115 "aarch64-enable-atomic-cfg-tidy", cl::Hidden,116 cl::desc("Run SimplifyCFG after expanding atomic operations"117 " to make use of cmpxchg flow-based information"),118 cl::init(true));119 120static cl::opt<bool>121EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,122 cl::desc("Run early if-conversion"),123 cl::init(true));124 125static cl::opt<bool>126 EnableCondOpt("aarch64-enable-condopt",127 cl::desc("Enable the condition optimizer pass"),128 cl::init(true), cl::Hidden);129 130static cl::opt<bool>131 EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,132 cl::desc("Enable optimizations on complex GEPs"),133 cl::init(false));134 135static cl::opt<bool>136 EnableSelectOpt("aarch64-select-opt", cl::Hidden,137 cl::desc("Enable select to branch optimizations"),138 cl::init(true));139 140static cl::opt<bool>141 BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),142 cl::desc("Relax out of range conditional branches"));143 144static cl::opt<bool> EnableCompressJumpTables(145 "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),146 cl::desc("Use smallest entry possible for jump tables"));147 148// FIXME: Unify control over GlobalMerge.149static cl::opt<cl::boolOrDefault>150 EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,151 cl::desc("Enable the global merge pass"));152 153static cl::opt<bool>154 EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,155 cl::desc("Enable the loop data prefetch pass"),156 cl::init(true));157 158static cl::opt<int> EnableGlobalISelAtO(159 "aarch64-enable-global-isel-at-O", cl::Hidden,160 cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),161 cl::init(0));162 163static cl::opt<bool>164 EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,165 cl::desc("Enable SVE intrinsic opts"),166 cl::init(true));167 168static cl::opt<bool>169 EnableSMEPeepholeOpt("enable-aarch64-sme-peephole-opt", cl::init(true),170 cl::Hidden,171 cl::desc("Perform SME peephole optimization"));172 173static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",174 cl::init(true), cl::Hidden);175 176static cl::opt<bool>177 EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,178 cl::desc("Enable the AArch64 branch target pass"),179 cl::init(true));180 181static cl::opt<unsigned> SVEVectorBitsMaxOpt(182 "aarch64-sve-vector-bits-max",183 cl::desc("Assume SVE vector registers are at most this big, "184 "with zero meaning no maximum size is assumed."),185 cl::init(0), cl::Hidden);186 187static cl::opt<unsigned> SVEVectorBitsMinOpt(188 "aarch64-sve-vector-bits-min",189 cl::desc("Assume SVE vector registers are at least this big, "190 "with zero meaning no minimum size is assumed."),191 cl::init(0), cl::Hidden);192 193static cl::opt<bool> ForceStreaming(194 "force-streaming",195 cl::desc("Force the use of streaming code for all functions"),196 cl::init(false), cl::Hidden);197 198static cl::opt<bool> ForceStreamingCompatible(199 "force-streaming-compatible",200 cl::desc("Force the use of streaming-compatible code for all functions"),201 cl::init(false), cl::Hidden);202 203extern cl::opt<bool> EnableHomogeneousPrologEpilog;204 205static cl::opt<bool> EnableGISelLoadStoreOptPreLegal(206 "aarch64-enable-gisel-ldst-prelegal",207 cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"),208 cl::init(true), cl::Hidden);209 210static cl::opt<bool> EnableGISelLoadStoreOptPostLegal(211 "aarch64-enable-gisel-ldst-postlegal",212 cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"),213 cl::init(false), cl::Hidden);214 215static cl::opt<bool>216 EnableSinkFold("aarch64-enable-sink-fold",217 cl::desc("Enable sinking and folding of instruction copies"),218 cl::init(true), cl::Hidden);219 220static cl::opt<bool>221 EnableMachinePipeliner("aarch64-enable-pipeliner",222 cl::desc("Enable Machine Pipeliner for AArch64"),223 cl::init(false), cl::Hidden);224 225static cl::opt<bool>226 EnableNewSMEABILowering("aarch64-new-sme-abi",227 cl::desc("Enable new lowering for the SME ABI"),228 cl::init(false), cl::Hidden);229 230extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void231LLVMInitializeAArch64Target() {232 // Register the target.233 RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());234 RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());235 RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());236 RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());237 RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());238 auto &PR = *PassRegistry::getPassRegistry();239 initializeGlobalISel(PR);240 initializeAArch64A53Fix835769Pass(PR);241 initializeAArch64A57FPLoadBalancingPass(PR);242 initializeAArch64AdvSIMDScalarPass(PR);243 initializeAArch64AsmPrinterPass(PR);244 initializeAArch64BranchTargetsPass(PR);245 initializeAArch64CollectLOHPass(PR);246 initializeAArch64CompressJumpTablesPass(PR);247 initializeAArch64ConditionalComparesPass(PR);248 initializeAArch64ConditionOptimizerPass(PR);249 initializeAArch64DeadRegisterDefinitionsPass(PR);250 initializeAArch64ExpandPseudoPass(PR);251 initializeAArch64LoadStoreOptPass(PR);252 initializeAArch64MIPeepholeOptPass(PR);253 initializeAArch64SIMDInstrOptPass(PR);254 initializeAArch64O0PreLegalizerCombinerPass(PR);255 initializeAArch64PreLegalizerCombinerPass(PR);256 initializeAArch64PointerAuthPass(PR);257 initializeAArch64PostCoalescerPass(PR);258 initializeAArch64PostLegalizerCombinerPass(PR);259 initializeAArch64PostLegalizerLoweringPass(PR);260 initializeAArch64PostSelectOptimizePass(PR);261 initializeAArch64PromoteConstantPass(PR);262 initializeAArch64RedundantCopyEliminationPass(PR);263 initializeAArch64StorePairSuppressPass(PR);264 initializeFalkorHWPFFixPass(PR);265 initializeFalkorMarkStridedAccessesLegacyPass(PR);266 initializeLDTLSCleanupPass(PR);267 initializeKCFIPass(PR);268 initializeSMEABIPass(PR);269 initializeMachineSMEABIPass(PR);270 initializeSMEPeepholeOptPass(PR);271 initializeSVEIntrinsicOptsPass(PR);272 initializeAArch64SpeculationHardeningPass(PR);273 initializeAArch64SLSHardeningPass(PR);274 initializeAArch64StackTaggingPass(PR);275 initializeAArch64StackTaggingPreRAPass(PR);276 initializeAArch64LowerHomogeneousPrologEpilogPass(PR);277 initializeAArch64DAGToDAGISelLegacyPass(PR);278 initializeAArch64CondBrTuningPass(PR);279 initializeAArch64Arm64ECCallLoweringPass(PR);280}281 282void AArch64TargetMachine::reset() { SubtargetMap.clear(); }283 284//===----------------------------------------------------------------------===//285// AArch64 Lowering public interface.286//===----------------------------------------------------------------------===//287static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {288 if (TT.isOSBinFormatMachO())289 return std::make_unique<AArch64_MachoTargetObjectFile>();290 if (TT.isOSBinFormatCOFF())291 return std::make_unique<AArch64_COFFTargetObjectFile>();292 293 return std::make_unique<AArch64_ELFTargetObjectFile>();294}295 296static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {297 if (CPU.empty() && TT.isArm64e())298 return "apple-a12";299 return CPU;300}301 302static Reloc::Model getEffectiveRelocModel(const Triple &TT,303 std::optional<Reloc::Model> RM) {304 // AArch64 Darwin and Windows are always PIC.305 if (TT.isOSDarwin() || TT.isOSWindows())306 return Reloc::PIC_;307 // On ELF platforms the default static relocation model has a smart enough308 // linker to cope with referencing external symbols defined in a shared309 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.310 if (!RM || *RM == Reloc::DynamicNoPIC)311 return Reloc::Static;312 return *RM;313}314 315static CodeModel::Model316getEffectiveAArch64CodeModel(const Triple &TT,317 std::optional<CodeModel::Model> CM, bool JIT) {318 if (CM) {319 if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&320 *CM != CodeModel::Large) {321 report_fatal_error(322 "Only small, tiny and large code models are allowed on AArch64");323 } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF()) {324 report_fatal_error("tiny code model is only supported on ELF");325 }326 return *CM;327 }328 // The default MCJIT memory managers make no guarantees about where they can329 // find an executable page; JITed code needs to be able to refer to globals330 // no matter how far away they are.331 // We should set the CodeModel::Small for Windows ARM64 in JIT mode,332 // since with large code model LLVM generating 4 MOV instructions, and333 // Windows doesn't support relocating these long branch (4 MOVs).334 if (JIT && !TT.isOSWindows())335 return CodeModel::Large;336 return CodeModel::Small;337}338 339/// Create an AArch64 architecture model.340///341AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,342 StringRef CPU, StringRef FS,343 const TargetOptions &Options,344 std::optional<Reloc::Model> RM,345 std::optional<CodeModel::Model> CM,346 CodeGenOptLevel OL, bool JIT,347 bool LittleEndian)348 : CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT,349 computeDefaultCPU(TT, CPU), FS, Options,350 getEffectiveRelocModel(TT, RM),351 getEffectiveAArch64CodeModel(TT, CM, JIT), OL),352 TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian),353 UseNewSMEABILowering(EnableNewSMEABILowering) {354 initAsmInfo();355 356 if (TT.isOSBinFormatMachO()) {357 this->Options.TrapUnreachable = true;358 this->Options.NoTrapAfterNoreturn = true;359 }360 361 if (getMCAsmInfo()->usesWindowsCFI()) {362 // Unwinding can get confused if the last instruction in an363 // exception-handling region (function, funclet, try block, etc.)364 // is a call.365 //366 // FIXME: We could elide the trap if the next instruction would be in367 // the same region anyway.368 this->Options.TrapUnreachable = true;369 }370 371 if (this->Options.TLSSize == 0) // default372 this->Options.TLSSize = 24;373 if ((getCodeModel() == CodeModel::Small ||374 getCodeModel() == CodeModel::Kernel) &&375 this->Options.TLSSize > 32)376 // for the small (and kernel) code model, the maximum TLS size is 4GiB377 this->Options.TLSSize = 32;378 else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)379 // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)380 this->Options.TLSSize = 24;381 382 // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is383 // MachO/CodeModel::Large, which GlobalISel does not support.384 if (static_cast<int>(getOptLevel()) <= EnableGlobalISelAtO &&385 TT.getArch() != Triple::aarch64_32 &&386 TT.getEnvironment() != Triple::GNUILP32 &&387 !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {388 setGlobalISel(true);389 setGlobalISelAbort(GlobalISelAbortMode::Disable);390 }391 392 // AArch64 supports the MachineOutliner.393 setMachineOutliner(true);394 395 // AArch64 supports default outlining behaviour.396 setSupportsDefaultOutlining(true);397 398 // AArch64 supports the debug entry values.399 setSupportsDebugEntryValues(true);400 401 // AArch64 supports fixing up the DWARF unwind information.402 if (!getMCAsmInfo()->usesWindowsCFI())403 setCFIFixup(true);404}405 406AArch64TargetMachine::~AArch64TargetMachine() = default;407 408const AArch64Subtarget *409AArch64TargetMachine::getSubtargetImpl(const Function &F) const {410 Attribute CPUAttr = F.getFnAttribute("target-cpu");411 Attribute TuneAttr = F.getFnAttribute("tune-cpu");412 Attribute FSAttr = F.getFnAttribute("target-features");413 414 StringRef CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString() : TargetCPU;415 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString() : CPU;416 StringRef FS = FSAttr.isValid() ? FSAttr.getValueAsString() : TargetFS;417 bool HasMinSize = F.hasMinSize();418 419 bool IsStreaming = ForceStreaming ||420 F.hasFnAttribute("aarch64_pstate_sm_enabled") ||421 F.hasFnAttribute("aarch64_pstate_sm_body");422 bool IsStreamingCompatible = ForceStreamingCompatible ||423 F.hasFnAttribute("aarch64_pstate_sm_compatible");424 425 unsigned MinSVEVectorSize = 0;426 unsigned MaxSVEVectorSize = 0;427 if (F.hasFnAttribute(Attribute::VScaleRange)) {428 ConstantRange CR = getVScaleRange(&F, 64);429 MinSVEVectorSize = CR.getUnsignedMin().getZExtValue() * 128;430 MaxSVEVectorSize = CR.getUnsignedMax().getZExtValue() * 128;431 } else {432 MinSVEVectorSize = SVEVectorBitsMinOpt;433 MaxSVEVectorSize = SVEVectorBitsMaxOpt;434 }435 436 assert(MinSVEVectorSize % 128 == 0 &&437 "SVE requires vector length in multiples of 128!");438 assert(MaxSVEVectorSize % 128 == 0 &&439 "SVE requires vector length in multiples of 128!");440 assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&441 "Minimum SVE vector size should not be larger than its maximum!");442 443 // Sanitize user input in case of no asserts444 if (MaxSVEVectorSize != 0) {445 MinSVEVectorSize = std::min(MinSVEVectorSize, MaxSVEVectorSize);446 MaxSVEVectorSize = std::max(MinSVEVectorSize, MaxSVEVectorSize);447 }448 449 SmallString<512> Key;450 raw_svector_ostream(Key) << "SVEMin" << MinSVEVectorSize << "SVEMax"451 << MaxSVEVectorSize << "IsStreaming=" << IsStreaming452 << "IsStreamingCompatible=" << IsStreamingCompatible453 << CPU << TuneCPU << FS454 << "HasMinSize=" << HasMinSize;455 456 auto &I = SubtargetMap[Key];457 if (!I) {458 // This needs to be done before we create a new subtarget since any459 // creation will depend on the TM and the code generation flags on the460 // function that reside in TargetOptions.461 resetTargetOptions(F);462 I = std::make_unique<AArch64Subtarget>(463 TargetTriple, CPU, TuneCPU, FS, *this, isLittle, MinSVEVectorSize,464 MaxSVEVectorSize, IsStreaming, IsStreamingCompatible, HasMinSize);465 }466 467 if (IsStreaming && !I->hasSME())468 reportFatalUsageError("streaming SVE functions require SME");469 470 return I.get();471}472 473ScheduleDAGInstrs *474AArch64TargetMachine::createMachineScheduler(MachineSchedContext *C) const {475 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();476 ScheduleDAGMILive *DAG = createSchedLive(C);477 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));478 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));479 if (ST.hasFusion())480 DAG->addMutation(createAArch64MacroFusionDAGMutation());481 return DAG;482}483 484ScheduleDAGInstrs *485AArch64TargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {486 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();487 ScheduleDAGMI *DAG = createSchedPostRA<AArch64PostRASchedStrategy>(C);488 if (ST.hasFusion()) {489 // Run the Macro Fusion after RA again since literals are expanded from490 // pseudos then (v. addPreSched2()).491 DAG->addMutation(createAArch64MacroFusionDAGMutation());492 return DAG;493 }494 495 return DAG;496}497 498size_t AArch64TargetMachine::clearLinkerOptimizationHints(499 const SmallPtrSetImpl<MachineInstr *> &MIs) const {500 if (MIs.empty())501 return 0;502 auto *MI = *MIs.begin();503 auto *FuncInfo = MI->getMF()->getInfo<AArch64FunctionInfo>();504 return FuncInfo->clearLinkerOptimizationHints(MIs);505}506 507void AArch64leTargetMachine::anchor() { }508 509AArch64leTargetMachine::AArch64leTargetMachine(510 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,511 const TargetOptions &Options, std::optional<Reloc::Model> RM,512 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)513 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}514 515void AArch64beTargetMachine::anchor() { }516 517AArch64beTargetMachine::AArch64beTargetMachine(518 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,519 const TargetOptions &Options, std::optional<Reloc::Model> RM,520 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, bool JIT)521 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}522 523namespace {524 525/// AArch64 Code Generator Pass Configuration Options.526class AArch64PassConfig : public TargetPassConfig {527public:528 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)529 : TargetPassConfig(TM, PM) {530 if (TM.getOptLevel() != CodeGenOptLevel::None)531 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);532 setEnableSinkAndFold(EnableSinkFold);533 }534 535 AArch64TargetMachine &getAArch64TargetMachine() const {536 return getTM<AArch64TargetMachine>();537 }538 539 void addIRPasses() override;540 bool addPreISel() override;541 void addCodeGenPrepare() override;542 bool addInstSelector() override;543 bool addIRTranslator() override;544 void addPreLegalizeMachineIR() override;545 bool addLegalizeMachineIR() override;546 void addPreRegBankSelect() override;547 bool addRegBankSelect() override;548 bool addGlobalInstructionSelect() override;549 void addMachineSSAOptimization() override;550 bool addILPOpts() override;551 void addPreRegAlloc() override;552 void addPostRegAlloc() override;553 void addPreSched2() override;554 void addPreEmitPass() override;555 void addPostBBSections() override;556 void addPreEmitPass2() override;557 bool addRegAssignAndRewriteOptimized() override;558 559 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;560};561 562} // end anonymous namespace563 564void AArch64TargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {565 566 PB.registerLateLoopOptimizationsEPCallback(567 [=](LoopPassManager &LPM, OptimizationLevel Level) {568 if (Level != OptimizationLevel::O0)569 LPM.addPass(LoopIdiomVectorizePass());570 });571 if (getTargetTriple().isOSWindows())572 PB.registerPipelineEarlySimplificationEPCallback(573 [](ModulePassManager &PM, OptimizationLevel, ThinOrFullLTOPhase) {574 PM.addPass(LowerIFuncPass());575 });576}577 578TargetTransformInfo579AArch64TargetMachine::getTargetTransformInfo(const Function &F) const {580 return TargetTransformInfo(std::make_unique<AArch64TTIImpl>(this, F));581}582 583TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {584 return new AArch64PassConfig(*this, PM);585}586 587std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {588 return getStandardCSEConfigForOpt(TM->getOptLevel());589}590 591void AArch64PassConfig::addIRPasses() {592 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg593 // ourselves.594 addPass(createAtomicExpandLegacyPass());595 596 // Expand any SVE vector library calls that we can't code generate directly.597 if (EnableSVEIntrinsicOpts &&598 TM->getOptLevel() != CodeGenOptLevel::None)599 addPass(createSVEIntrinsicOptsPass());600 601 // Cmpxchg instructions are often used with a subsequent comparison to602 // determine whether it succeeded. We can exploit existing control-flow in603 // ldrex/strex loops to simplify this, but it needs tidying up.604 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)605 addPass(createCFGSimplificationPass(SimplifyCFGOptions()606 .forwardSwitchCondToPhi(true)607 .convertSwitchRangeToICmp(true)608 .convertSwitchToLookupTable(true)609 .needCanonicalLoops(false)610 .hoistCommonInsts(true)611 .sinkCommonInsts(true)));612 613 // Run LoopDataPrefetch614 //615 // Run this before LSR to remove the multiplies involved in computing the616 // pointer values N iterations ahead.617 if (TM->getOptLevel() != CodeGenOptLevel::None) {618 if (EnableLoopDataPrefetch)619 addPass(createLoopDataPrefetchPass());620 if (EnableFalkorHWPFFix)621 addPass(createFalkorMarkStridedAccessesPass());622 }623 624 if (EnableGEPOpt) {625 // Call SeparateConstOffsetFromGEP pass to extract constants within indices626 // and lower a GEP with multiple indices to either arithmetic operations or627 // multiple GEPs with single index.628 addPass(createSeparateConstOffsetFromGEPPass(true));629 // Call EarlyCSE pass to find and remove subexpressions in the lowered630 // result.631 addPass(createEarlyCSEPass());632 // Do loop invariant code motion in case part of the lowered result is633 // invariant.634 addPass(createLICMPass());635 }636 637 TargetPassConfig::addIRPasses();638 639 if (getOptLevel() == CodeGenOptLevel::Aggressive && EnableSelectOpt)640 addPass(createSelectOptimizePass());641 642 addPass(createAArch64StackTaggingPass(643 /*IsOptNone=*/TM->getOptLevel() == CodeGenOptLevel::None));644 645 // Match complex arithmetic patterns646 if (TM->getOptLevel() >= CodeGenOptLevel::Default)647 addPass(createComplexDeinterleavingPass(TM));648 649 // Match interleaved memory accesses to ldN/stN intrinsics.650 if (TM->getOptLevel() != CodeGenOptLevel::None) {651 addPass(createInterleavedLoadCombinePass());652 addPass(createInterleavedAccessPass());653 }654 655 if (!EnableNewSMEABILowering) {656 // Expand any functions marked with SME attributes which require special657 // changes for the calling convention or that require the lazy-saving658 // mechanism specified in the SME ABI.659 addPass(createSMEABIPass());660 }661 662 // Add Control Flow Guard checks.663 if (TM->getTargetTriple().isOSWindows()) {664 if (TM->getTargetTriple().isWindowsArm64EC())665 addPass(createAArch64Arm64ECCallLoweringPass());666 else667 addPass(createCFGuardCheckPass());668 }669 670 if (TM->Options.JMCInstrument)671 addPass(createJMCInstrumenterPass());672}673 674// Pass Pipeline Configuration675bool AArch64PassConfig::addPreISel() {676 // Run promote constant before global merge, so that the promoted constants677 // get a chance to be merged678 if (TM->getOptLevel() != CodeGenOptLevel::None && EnablePromoteConstant)679 addPass(createAArch64PromoteConstantPass());680 // FIXME: On AArch64, this depends on the type.681 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().682 // and the offset has to be a multiple of the related size in bytes.683 if ((TM->getOptLevel() != CodeGenOptLevel::None &&684 EnableGlobalMerge == cl::BOU_UNSET) ||685 EnableGlobalMerge == cl::BOU_TRUE) {686 bool OnlyOptimizeForSize =687 (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&688 (EnableGlobalMerge == cl::BOU_UNSET);689 690 // Merging of extern globals is enabled by default on non-Mach-O as we691 // expect it to be generally either beneficial or harmless. On Mach-O it692 // is disabled as we emit the .subsections_via_symbols directive which693 // means that merging extern globals is not safe.694 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();695 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,696 MergeExternalByDefault));697 }698 699 return false;700}701 702void AArch64PassConfig::addCodeGenPrepare() {703 if (getOptLevel() != CodeGenOptLevel::None)704 addPass(createTypePromotionLegacyPass());705 TargetPassConfig::addCodeGenPrepare();706}707 708bool AArch64PassConfig::addInstSelector() {709 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));710 711 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many712 // references to _TLS_MODULE_BASE_ as possible.713 if (TM->getTargetTriple().isOSBinFormatELF() &&714 getOptLevel() != CodeGenOptLevel::None)715 addPass(createAArch64CleanupLocalDynamicTLSPass());716 717 return false;718}719 720bool AArch64PassConfig::addIRTranslator() {721 addPass(new IRTranslator(getOptLevel()));722 return false;723}724 725void AArch64PassConfig::addPreLegalizeMachineIR() {726 if (getOptLevel() == CodeGenOptLevel::None) {727 addPass(createAArch64O0PreLegalizerCombiner());728 addPass(new Localizer());729 } else {730 addPass(createAArch64PreLegalizerCombiner());731 addPass(new Localizer());732 if (EnableGISelLoadStoreOptPreLegal)733 addPass(new LoadStoreOpt());734 }735}736 737bool AArch64PassConfig::addLegalizeMachineIR() {738 addPass(new Legalizer());739 return false;740}741 742void AArch64PassConfig::addPreRegBankSelect() {743 bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;744 if (!IsOptNone) {745 addPass(createAArch64PostLegalizerCombiner(IsOptNone));746 if (EnableGISelLoadStoreOptPostLegal)747 addPass(new LoadStoreOpt());748 }749 addPass(createAArch64PostLegalizerLowering());750}751 752bool AArch64PassConfig::addRegBankSelect() {753 addPass(new RegBankSelect());754 return false;755}756 757bool AArch64PassConfig::addGlobalInstructionSelect() {758 addPass(new InstructionSelect(getOptLevel()));759 if (getOptLevel() != CodeGenOptLevel::None)760 addPass(createAArch64PostSelectOptimize());761 return false;762}763 764void AArch64PassConfig::addMachineSSAOptimization() {765 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableNewSMEABILowering)766 addPass(createMachineSMEABIPass(TM->getOptLevel()));767 768 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableSMEPeepholeOpt)769 addPass(createSMEPeepholeOptPass());770 771 // Run default MachineSSAOptimization first.772 TargetPassConfig::addMachineSSAOptimization();773 774 if (TM->getOptLevel() != CodeGenOptLevel::None)775 addPass(createAArch64MIPeepholeOptPass());776}777 778bool AArch64PassConfig::addILPOpts() {779 if (EnableCondOpt)780 addPass(createAArch64ConditionOptimizerPass());781 if (EnableCCMP)782 addPass(createAArch64ConditionalCompares());783 if (EnableMCR)784 addPass(&MachineCombinerID);785 if (EnableCondBrTuning)786 addPass(createAArch64CondBrTuning());787 if (EnableEarlyIfConversion)788 addPass(&EarlyIfConverterLegacyID);789 if (EnableStPairSuppress)790 addPass(createAArch64StorePairSuppressPass());791 addPass(createAArch64SIMDInstrOptPass());792 if (TM->getOptLevel() != CodeGenOptLevel::None)793 addPass(createAArch64StackTaggingPreRAPass());794 return true;795}796 797void AArch64PassConfig::addPreRegAlloc() {798 if (TM->getOptLevel() == CodeGenOptLevel::None && EnableNewSMEABILowering)799 addPass(createMachineSMEABIPass(CodeGenOptLevel::None));800 801 // Change dead register definitions to refer to the zero register.802 if (TM->getOptLevel() != CodeGenOptLevel::None &&803 EnableDeadRegisterElimination)804 addPass(createAArch64DeadRegisterDefinitions());805 806 // Use AdvSIMD scalar instructions whenever profitable.807 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAdvSIMDScalar) {808 addPass(createAArch64AdvSIMDScalar());809 // The AdvSIMD pass may produce copies that can be rewritten to810 // be register coalescer friendly.811 addPass(&PeepholeOptimizerLegacyID);812 }813 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableMachinePipeliner)814 addPass(&MachinePipelinerID);815}816 817void AArch64PassConfig::addPostRegAlloc() {818 // Remove redundant copy instructions.819 if (TM->getOptLevel() != CodeGenOptLevel::None &&820 EnableRedundantCopyElimination)821 addPass(createAArch64RedundantCopyEliminationPass());822 823 if (TM->getOptLevel() != CodeGenOptLevel::None && usingDefaultRegAlloc())824 // Improve performance for some FP/SIMD code for A57.825 addPass(createAArch64A57FPLoadBalancing());826}827 828void AArch64PassConfig::addPreSched2() {829 // Lower homogeneous frame instructions830 if (EnableHomogeneousPrologEpilog)831 addPass(createAArch64LowerHomogeneousPrologEpilogPass());832 // Expand some pseudo instructions to allow proper scheduling.833 addPass(createAArch64ExpandPseudoPass());834 // Use load/store pair instructions when possible.835 if (TM->getOptLevel() != CodeGenOptLevel::None) {836 if (EnableLoadStoreOpt)837 addPass(createAArch64LoadStoreOptimizationPass());838 }839 // Emit KCFI checks for indirect calls.840 addPass(createKCFIPass());841 842 // The AArch64SpeculationHardeningPass destroys dominator tree and natural843 // loop info, which is needed for the FalkorHWPFFixPass and also later on.844 // Therefore, run the AArch64SpeculationHardeningPass before the845 // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop846 // info.847 addPass(createAArch64SpeculationHardeningPass());848 849 if (TM->getOptLevel() != CodeGenOptLevel::None) {850 if (EnableFalkorHWPFFix)851 addPass(createFalkorHWPFFixPass());852 }853}854 855void AArch64PassConfig::addPreEmitPass() {856 // Machine Block Placement might have created new opportunities when run857 // at O3, where the Tail Duplication Threshold is set to 4 instructions.858 // Run the load/store optimizer once more.859 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive && EnableLoadStoreOpt)860 addPass(createAArch64LoadStoreOptimizationPass());861 862 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive &&863 EnableAArch64CopyPropagation)864 addPass(createMachineCopyPropagationPass(true));865 866 addPass(createAArch64A53Fix835769());867 868 if (TM->getTargetTriple().isOSWindows()) {869 // Identify valid longjmp targets for Windows Control Flow Guard.870 addPass(createCFGuardLongjmpPass());871 // Identify valid eh continuation targets for Windows EHCont Guard.872 addPass(createEHContGuardTargetsPass());873 }874 875 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableCollectLOH &&876 TM->getTargetTriple().isOSBinFormatMachO())877 addPass(createAArch64CollectLOHPass());878}879 880void AArch64PassConfig::addPostBBSections() {881 addPass(createAArch64SLSHardeningPass());882 addPass(createAArch64PointerAuthPass());883 if (EnableBranchTargets)884 addPass(createAArch64BranchTargetsPass());885 // Relax conditional branch instructions if they're otherwise out of886 // range of their destination.887 if (BranchRelaxation)888 addPass(&BranchRelaxationPassID);889 890 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableCompressJumpTables)891 addPass(createAArch64CompressJumpTablesPass());892}893 894void AArch64PassConfig::addPreEmitPass2() {895 // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo896 // instructions are lowered to bundles as well.897 addPass(createUnpackMachineBundles(nullptr));898}899 900bool AArch64PassConfig::addRegAssignAndRewriteOptimized() {901 addPass(createAArch64PostCoalescerPass());902 return TargetPassConfig::addRegAssignAndRewriteOptimized();903}904 905MachineFunctionInfo *AArch64TargetMachine::createMachineFunctionInfo(906 BumpPtrAllocator &Allocator, const Function &F,907 const TargetSubtargetInfo *STI) const {908 return AArch64FunctionInfo::create<AArch64FunctionInfo>(909 Allocator, F, static_cast<const AArch64Subtarget *>(STI));910}911 912yaml::MachineFunctionInfo *913AArch64TargetMachine::createDefaultFuncInfoYAML() const {914 return new yaml::AArch64FunctionInfo();915}916 917yaml::MachineFunctionInfo *918AArch64TargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {919 const auto *MFI = MF.getInfo<AArch64FunctionInfo>();920 return new yaml::AArch64FunctionInfo(*MFI);921}922 923bool AArch64TargetMachine::parseMachineFunctionInfo(924 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,925 SMDiagnostic &Error, SMRange &SourceRange) const {926 const auto &YamlMFI = static_cast<const yaml::AArch64FunctionInfo &>(MFI);927 MachineFunction &MF = PFS.MF;928 MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);929 return false;930}931