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1add_llvm_component_group(AArch64 HAS_JIT)2 3set(LLVM_TARGET_DEFINITIONS AArch64.td)4 5tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)6tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)7tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)8tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)9tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)10tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)11tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)12tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)13tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner14 -combiners="AArch64O0PreLegalizerCombiner")15tablegen(LLVM AArch64GenPreLegalizeGICombiner.inc -gen-global-isel-combiner16 -combiners="AArch64PreLegalizerCombiner")17tablegen(LLVM AArch64GenPostLegalizeGICombiner.inc -gen-global-isel-combiner18 -combiners="AArch64PostLegalizerCombiner")19tablegen(LLVM AArch64GenPostLegalizeGILowering.inc -gen-global-isel-combiner20 -combiners="AArch64PostLegalizerLowering")21tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)22tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter)23tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)24tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)25tablegen(LLVM AArch64GenRegisterInfo.inc -gen-register-info)26tablegen(LLVM AArch64GenSDNodeInfo.inc -gen-sd-node-info)27tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)28tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)29tablegen(LLVM AArch64GenExegesis.inc -gen-exegesis)30 31add_public_tablegen_target(AArch64CommonTableGen)32 33add_llvm_target(AArch64CodeGen34 GISel/AArch64CallLowering.cpp35 GISel/AArch64GlobalISelUtils.cpp36 GISel/AArch64InstructionSelector.cpp37 GISel/AArch64LegalizerInfo.cpp38 GISel/AArch64O0PreLegalizerCombiner.cpp39 GISel/AArch64PreLegalizerCombiner.cpp40 GISel/AArch64PostLegalizerCombiner.cpp41 GISel/AArch64PostLegalizerLowering.cpp42 GISel/AArch64PostSelectOptimize.cpp43 GISel/AArch64RegisterBankInfo.cpp44 AArch64A57FPLoadBalancing.cpp45 AArch64AdvSIMDScalarPass.cpp46 AArch64Arm64ECCallLowering.cpp47 AArch64AsmPrinter.cpp48 AArch64BranchTargets.cpp49 AArch64CallingConvention.cpp50 AArch64CleanupLocalDynamicTLSPass.cpp51 AArch64CollectLOH.cpp52 AArch64CondBrTuning.cpp53 AArch64ConditionalCompares.cpp54 AArch64DeadRegisterDefinitionsPass.cpp55 AArch64ExpandImm.cpp56 AArch64ExpandPseudoInsts.cpp57 AArch64FalkorHWPFFix.cpp58 AArch64FastISel.cpp59 AArch64A53Fix835769.cpp60 AArch64FrameLowering.cpp61 AArch64CompressJumpTables.cpp62 AArch64ConditionOptimizer.cpp63 AArch64RedundantCopyElimination.cpp64 AArch64ISelDAGToDAG.cpp65 AArch64ISelLowering.cpp66 AArch64InstrInfo.cpp67 AArch64LoadStoreOptimizer.cpp68 AArch64LowerHomogeneousPrologEpilog.cpp69 AArch64MachineFunctionInfo.cpp70 AArch64MachineScheduler.cpp71 AArch64MacroFusion.cpp72 AArch64MIPeepholeOpt.cpp73 AArch64MCInstLower.cpp74 AArch64PointerAuth.cpp75 AArch64PostCoalescerPass.cpp76 AArch64PromoteConstant.cpp77 AArch64PBQPRegAlloc.cpp78 AArch64RegisterInfo.cpp79 AArch64SMEAttributes.cpp80 AArch64SLSHardening.cpp81 AArch64SelectionDAGInfo.cpp82 AArch64SpeculationHardening.cpp83 AArch64StackTagging.cpp84 AArch64StackTaggingPreRA.cpp85 AArch64StorePairSuppress.cpp86 AArch64Subtarget.cpp87 AArch64TargetMachine.cpp88 AArch64TargetObjectFile.cpp89 AArch64TargetTransformInfo.cpp90 SMEABIPass.cpp91 SMEPeepholeOpt.cpp92 SVEIntrinsicOpts.cpp93 MachineSMEABIPass.cpp94 AArch64SIMDInstrOpt.cpp95 AArch64PrologueEpilogue.cpp96 97 DEPENDS98 intrinsics_gen99 100 LINK_COMPONENTS101 AArch64Desc102 AArch64Info103 AArch64Utils104 Analysis105 AsmPrinter106 CFGuard107 CodeGen108 CodeGenTypes109 Core110 GlobalISel111 MC112 Passes113 Scalar114 SelectionDAG115 Support116 Target117 TargetParser118 TransformUtils119 Vectorize120 121 ADD_TO_COMPONENT122 AArch64123 )124 125add_subdirectory(AsmParser)126add_subdirectory(Disassembler)127add_subdirectory(MCTargetDesc)128add_subdirectory(TargetInfo)129add_subdirectory(Utils)130