810 lines · cpp
1//===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "MCTargetDesc/AArch64FixupKinds.h"10#include "MCTargetDesc/AArch64MCAsmInfo.h"11#include "MCTargetDesc/AArch64MCTargetDesc.h"12#include "Utils/AArch64BaseInfo.h"13#include "llvm/BinaryFormat/MachO.h"14#include "llvm/MC/MCAsmBackend.h"15#include "llvm/MC/MCAssembler.h"16#include "llvm/MC/MCContext.h"17#include "llvm/MC/MCELFObjectWriter.h"18#include "llvm/MC/MCObjectWriter.h"19#include "llvm/MC/MCRegisterInfo.h"20#include "llvm/MC/MCSubtargetInfo.h"21#include "llvm/MC/MCTargetOptions.h"22#include "llvm/MC/MCValue.h"23#include "llvm/MC/TargetRegistry.h"24#include "llvm/Support/ErrorHandling.h"25#include "llvm/Support/MathExtras.h"26#include "llvm/TargetParser/Triple.h"27using namespace llvm;28 29namespace {30 31class AArch64AsmBackend : public MCAsmBackend {32protected:33 Triple TheTriple;34 35public:36 AArch64AsmBackend(const Target &T, const Triple &TT, bool IsLittleEndian)37 : MCAsmBackend(IsLittleEndian ? llvm::endianness::little38 : llvm::endianness::big),39 TheTriple(TT) {}40 41 42 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;43 44 MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override {45 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {46 // This table *must* be in the order that the fixup_* kinds are defined47 // in AArch64FixupKinds.h.48 //49 // Name Offset (bits) Size (bits) Flags50 {"fixup_aarch64_pcrel_adr_imm21", 0, 32, 0},51 {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, 0},52 {"fixup_aarch64_add_imm12", 10, 12, 0},53 {"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0},54 {"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0},55 {"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0},56 {"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0},57 {"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0},58 {"fixup_aarch64_ldr_pcrel_imm19", 5, 19, 0},59 {"fixup_aarch64_movw", 5, 16, 0},60 {"fixup_aarch64_pcrel_branch9", 5, 9, 0},61 {"fixup_aarch64_pcrel_branch14", 5, 14, 0},62 {"fixup_aarch64_pcrel_branch16", 5, 16, 0},63 {"fixup_aarch64_pcrel_branch19", 5, 19, 0},64 {"fixup_aarch64_pcrel_branch26", 0, 26, 0},65 {"fixup_aarch64_pcrel_call26", 0, 26, 0}};66 67 // Fixup kinds from raw relocation types and .reloc directives force68 // relocations and do not need these fields.69 if (mc::isRelocation(Kind))70 return {};71 72 if (Kind < FirstTargetFixupKind)73 return MCAsmBackend::getFixupKindInfo(Kind);74 75 assert(unsigned(Kind - FirstTargetFixupKind) <76 AArch64::NumTargetFixupKinds &&77 "Invalid kind!");78 return Infos[Kind - FirstTargetFixupKind];79 }80 81 void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,82 uint8_t *Data, uint64_t Value, bool IsResolved) override;83 84 bool fixupNeedsRelaxation(const MCFixup &Fixup,85 uint64_t Value) const override;86 bool writeNopData(raw_ostream &OS, uint64_t Count,87 const MCSubtargetInfo *STI) const override;88 89 unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;90};91 92} // end anonymous namespace93 94/// The number of bytes the fixup may change.95static unsigned getFixupKindNumBytes(unsigned Kind) {96 switch (Kind) {97 default:98 llvm_unreachable("Unknown fixup kind!");99 100 case FK_Data_1:101 return 1;102 103 case FK_Data_2:104 case FK_SecRel_2:105 return 2;106 107 case AArch64::fixup_aarch64_movw:108 case AArch64::fixup_aarch64_pcrel_branch9:109 case AArch64::fixup_aarch64_pcrel_branch14:110 case AArch64::fixup_aarch64_pcrel_branch16:111 case AArch64::fixup_aarch64_add_imm12:112 case AArch64::fixup_aarch64_ldst_imm12_scale1:113 case AArch64::fixup_aarch64_ldst_imm12_scale2:114 case AArch64::fixup_aarch64_ldst_imm12_scale4:115 case AArch64::fixup_aarch64_ldst_imm12_scale8:116 case AArch64::fixup_aarch64_ldst_imm12_scale16:117 case AArch64::fixup_aarch64_ldr_pcrel_imm19:118 case AArch64::fixup_aarch64_pcrel_branch19:119 return 3;120 121 case AArch64::fixup_aarch64_pcrel_adr_imm21:122 case AArch64::fixup_aarch64_pcrel_adrp_imm21:123 case AArch64::fixup_aarch64_pcrel_branch26:124 case AArch64::fixup_aarch64_pcrel_call26:125 case FK_Data_4:126 case FK_SecRel_4:127 return 4;128 129 case FK_Data_8:130 return 8;131 }132}133 134static unsigned AdrImmBits(unsigned Value) {135 unsigned lo2 = Value & 0x3;136 unsigned hi19 = (Value & 0x1ffffc) >> 2;137 return (hi19 << 5) | (lo2 << 29);138}139 140static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,141 uint64_t Value, MCContext &Ctx,142 const Triple &TheTriple, bool IsResolved) {143 int64_t SignedValue = static_cast<int64_t>(Value);144 switch (Fixup.getKind()) {145 default:146 llvm_unreachable("Unknown fixup kind!");147 case AArch64::fixup_aarch64_pcrel_adr_imm21:148 if (!isInt<21>(SignedValue))149 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");150 return AdrImmBits(Value & 0x1fffffULL);151 case AArch64::fixup_aarch64_pcrel_adrp_imm21:152 assert(!IsResolved);153 if (TheTriple.isOSBinFormatCOFF()) {154 if (!isInt<21>(SignedValue))155 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");156 return AdrImmBits(Value & 0x1fffffULL);157 }158 return AdrImmBits((Value & 0x1fffff000ULL) >> 12);159 case AArch64::fixup_aarch64_ldr_pcrel_imm19:160 case AArch64::fixup_aarch64_pcrel_branch19:161 // Signed 19-bit immediate which gets multiplied by 4162 if (!isInt<21>(SignedValue))163 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");164 if (Value & 0x3)165 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");166 // Low two bits are not encoded.167 return (Value >> 2) & 0x7ffff;168 case AArch64::fixup_aarch64_add_imm12:169 case AArch64::fixup_aarch64_ldst_imm12_scale1:170 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)171 Value &= 0xfff;172 // Unsigned 12-bit immediate173 if (!isUInt<12>(Value))174 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");175 return Value;176 case AArch64::fixup_aarch64_ldst_imm12_scale2:177 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)178 Value &= 0xfff;179 // Unsigned 12-bit immediate which gets multiplied by 2180 if (!isUInt<13>(Value))181 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");182 if (Value & 0x1)183 Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");184 return Value >> 1;185 case AArch64::fixup_aarch64_ldst_imm12_scale4:186 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)187 Value &= 0xfff;188 // Unsigned 12-bit immediate which gets multiplied by 4189 if (!isUInt<14>(Value))190 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");191 if (Value & 0x3)192 Ctx.reportError(Fixup.getLoc(), "fixup must be 4-byte aligned");193 return Value >> 2;194 case AArch64::fixup_aarch64_ldst_imm12_scale8:195 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)196 Value &= 0xfff;197 // Unsigned 12-bit immediate which gets multiplied by 8198 if (!isUInt<15>(Value))199 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");200 if (Value & 0x7)201 Ctx.reportError(Fixup.getLoc(), "fixup must be 8-byte aligned");202 return Value >> 3;203 case AArch64::fixup_aarch64_ldst_imm12_scale16:204 if (TheTriple.isOSBinFormatCOFF() && !IsResolved)205 Value &= 0xfff;206 // Unsigned 12-bit immediate which gets multiplied by 16207 if (!isUInt<16>(Value))208 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");209 if (Value & 0xf)210 Ctx.reportError(Fixup.getLoc(), "fixup must be 16-byte aligned");211 return Value >> 4;212 case AArch64::fixup_aarch64_movw: {213 AArch64::Specifier RefKind =214 static_cast<AArch64::Specifier>(Target.getSpecifier());215 if (AArch64::getSymbolLoc(RefKind) != AArch64::S_ABS &&216 AArch64::getSymbolLoc(RefKind) != AArch64::S_SABS) {217 if (!RefKind) {218 // The fixup is an expression219 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)220 Ctx.reportError(Fixup.getLoc(),221 "fixup value out of range [-0xFFFF, 0xFFFF]");222 223 // Invert the negative immediate because it will feed into a MOVN.224 if (SignedValue < 0)225 SignedValue = ~SignedValue;226 Value = static_cast<uint64_t>(SignedValue);227 } else228 // VK_GOTTPREL, VK_TPREL, VK_DTPREL are movw fixups, but they can't229 // ever be resolved in the assembler.230 Ctx.reportError(Fixup.getLoc(),231 "relocation for a thread-local variable points to an "232 "absolute symbol");233 return Value;234 }235 236 if (!IsResolved) {237 // FIXME: Figure out when this can actually happen, and verify our238 // behavior.239 Ctx.reportError(Fixup.getLoc(), "unresolved movw fixup not yet "240 "implemented");241 return Value;242 }243 244 if (AArch64::getSymbolLoc(RefKind) == AArch64::S_SABS) {245 switch (AArch64::getAddressFrag(RefKind)) {246 case AArch64::S_G0:247 break;248 case AArch64::S_G1:249 SignedValue = SignedValue >> 16;250 break;251 case AArch64::S_G2:252 SignedValue = SignedValue >> 32;253 break;254 case AArch64::S_G3:255 SignedValue = SignedValue >> 48;256 break;257 default:258 llvm_unreachable("Variant kind doesn't correspond to fixup");259 }260 261 } else {262 switch (AArch64::getAddressFrag(RefKind)) {263 case AArch64::S_G0:264 break;265 case AArch64::S_G1:266 Value = Value >> 16;267 break;268 case AArch64::S_G2:269 Value = Value >> 32;270 break;271 case AArch64::S_G3:272 Value = Value >> 48;273 break;274 default:275 llvm_unreachable("Variant kind doesn't correspond to fixup");276 }277 }278 279 if (RefKind & AArch64::S_NC) {280 Value &= 0xFFFF;281 } else if (AArch64::getSymbolLoc(RefKind) == AArch64::S_SABS) {282 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)283 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");284 285 // Invert the negative immediate because it will feed into a MOVN.286 if (SignedValue < 0)287 SignedValue = ~SignedValue;288 Value = static_cast<uint64_t>(SignedValue);289 } else if (Value > 0xFFFF) {290 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");291 }292 return Value;293 }294 case AArch64::fixup_aarch64_pcrel_branch9:295 // Signed 11-bit(9bits + 2 shifts) label296 if (!isInt<11>(SignedValue))297 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");298 // Low two bits are not encoded (4-byte alignment assumed).299 if (Value & 0b11)300 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");301 return (Value >> 2) & 0x1ff;302 case AArch64::fixup_aarch64_pcrel_branch14:303 // Signed 16-bit immediate304 if (!isInt<16>(SignedValue))305 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");306 // Low two bits are not encoded (4-byte alignment assumed).307 if (Value & 0x3)308 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");309 return (Value >> 2) & 0x3fff;310 case AArch64::fixup_aarch64_pcrel_branch16:311 // Unsigned PC-relative offset, so invert the negative immediate.312 SignedValue = -SignedValue;313 Value = static_cast<uint64_t>(SignedValue);314 // Check valid 18-bit unsigned range.315 if (SignedValue < 0 || SignedValue > ((1 << 18) - 1))316 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");317 // Low two bits are not encoded (4-byte alignment assumed).318 if (Value & 0b11)319 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");320 return (Value >> 2) & 0xffff;321 case AArch64::fixup_aarch64_pcrel_branch26:322 case AArch64::fixup_aarch64_pcrel_call26:323 if (TheTriple.isOSBinFormatCOFF() && !IsResolved && SignedValue != 0) {324 // MSVC link.exe and lld do not support this relocation type325 // with a non-zero offset326 Ctx.reportError(Fixup.getLoc(),327 "cannot perform a PC-relative fixup with a non-zero "328 "symbol offset");329 }330 // Signed 28-bit immediate331 if (!isInt<28>(SignedValue))332 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");333 // Low two bits are not encoded (4-byte alignment assumed).334 if (Value & 0x3)335 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");336 return (Value >> 2) & 0x3ffffff;337 case FK_Data_1:338 case FK_Data_2:339 case FK_Data_4:340 case FK_Data_8:341 case FK_SecRel_2:342 case FK_SecRel_4:343 return Value;344 }345}346 347std::optional<MCFixupKind>348AArch64AsmBackend::getFixupKind(StringRef Name) const {349 if (!TheTriple.isOSBinFormatELF())350 return std::nullopt;351 352 unsigned Type = llvm::StringSwitch<unsigned>(Name)353#define ELF_RELOC(X, Y) .Case(#X, Y)354#include "llvm/BinaryFormat/ELFRelocs/AArch64.def"355#undef ELF_RELOC356 .Case("BFD_RELOC_NONE", ELF::R_AARCH64_NONE)357 .Case("BFD_RELOC_16", ELF::R_AARCH64_ABS16)358 .Case("BFD_RELOC_32", ELF::R_AARCH64_ABS32)359 .Case("BFD_RELOC_64", ELF::R_AARCH64_ABS64)360 .Default(-1u);361 if (Type == -1u)362 return std::nullopt;363 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);364}365 366/// getFixupKindContainereSizeInBytes - The number of bytes of the367/// container involved in big endian or 0 if the item is little endian368unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {369 if (Endian == llvm::endianness::little)370 return 0;371 372 switch (Kind) {373 default:374 llvm_unreachable("Unknown fixup kind!");375 376 case FK_Data_1:377 return 1;378 case FK_Data_2:379 return 2;380 case FK_Data_4:381 return 4;382 case FK_Data_8:383 return 8;384 385 case AArch64::fixup_aarch64_movw:386 case AArch64::fixup_aarch64_pcrel_branch9:387 case AArch64::fixup_aarch64_pcrel_branch14:388 case AArch64::fixup_aarch64_pcrel_branch16:389 case AArch64::fixup_aarch64_add_imm12:390 case AArch64::fixup_aarch64_ldst_imm12_scale1:391 case AArch64::fixup_aarch64_ldst_imm12_scale2:392 case AArch64::fixup_aarch64_ldst_imm12_scale4:393 case AArch64::fixup_aarch64_ldst_imm12_scale8:394 case AArch64::fixup_aarch64_ldst_imm12_scale16:395 case AArch64::fixup_aarch64_ldr_pcrel_imm19:396 case AArch64::fixup_aarch64_pcrel_branch19:397 case AArch64::fixup_aarch64_pcrel_adr_imm21:398 case AArch64::fixup_aarch64_pcrel_adrp_imm21:399 case AArch64::fixup_aarch64_pcrel_branch26:400 case AArch64::fixup_aarch64_pcrel_call26:401 // Instructions are always little endian402 return 0;403 }404}405 406static bool shouldForceRelocation(const MCFixup &Fixup) {407 // The ADRP instruction adds some multiple of 0x1000 to the current PC &408 // ~0xfff. This means that the required offset to reach a symbol can vary by409 // up to one step depending on where the ADRP is in memory. For example:410 //411 // ADRP x0, there412 // there:413 //414 // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and415 // we'll need that as an offset. At any other address "there" will be in the416 // same page as the ADRP and the instruction should encode 0x0. Assuming the417 // section isn't 0x1000-aligned, we therefore need to delegate this decision418 // to the linker -- a relocation!419 return Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21;420}421 422void AArch64AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,423 const MCValue &Target, uint8_t *Data,424 uint64_t Value, bool IsResolved) {425 if (shouldForceRelocation(Fixup))426 IsResolved = false;427 maybeAddReloc(F, Fixup, Target, Value, IsResolved);428 MCFixupKind Kind = Fixup.getKind();429 if (mc::isRelocation(Kind))430 return;431 432 if (Fixup.getKind() == FK_Data_8 && TheTriple.isOSBinFormatELF()) {433 auto RefKind = static_cast<AArch64::Specifier>(Target.getSpecifier());434 AArch64::Specifier SymLoc = AArch64::getSymbolLoc(RefKind);435 if (SymLoc == AArch64::S_AUTH || SymLoc == AArch64::S_AUTHADDR) {436 const auto *Expr = dyn_cast<AArch64AuthMCExpr>(Fixup.getValue());437 if (!Expr) {438 getContext().reportError(Fixup.getValue()->getLoc(),439 "expected relocatable expression");440 return;441 }442 assert(Value == 0);443 Value = (uint64_t(Expr->getDiscriminator()) << 32) |444 (uint64_t(Expr->getKey()) << 60) |445 (uint64_t(Expr->hasAddressDiversity()) << 63);446 }447 }448 449 if (!Value)450 return; // Doesn't change encoding.451 unsigned NumBytes = getFixupKindNumBytes(Kind);452 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());453 MCContext &Ctx = getContext();454 int64_t SignedValue = static_cast<int64_t>(Value);455 // Apply any target-specific value adjustments.456 Value = adjustFixupValue(Fixup, Target, Value, Ctx, TheTriple, IsResolved);457 458 // Shift the value into position.459 Value <<= Info.TargetOffset;460 461 assert(Fixup.getOffset() + NumBytes <= F.getSize() &&462 "Invalid fixup offset!");463 464 // Used to point to big endian bytes.465 unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind());466 467 // For each byte of the fragment that the fixup touches, mask in the468 // bits from the fixup value.469 if (FulleSizeInBytes == 0) {470 // Handle as little-endian471 for (unsigned i = 0; i != NumBytes; ++i) {472 Data[i] |= uint8_t((Value >> (i * 8)) & 0xff);473 }474 } else {475 // Handle as big-endian476 assert(Fixup.getOffset() + FulleSizeInBytes <= F.getSize() &&477 "Invalid fixup size!");478 assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!");479 for (unsigned i = 0; i != NumBytes; ++i) {480 unsigned Idx = FulleSizeInBytes - 1 - i;481 Data[Idx] |= uint8_t((Value >> (i * 8)) & 0xff);482 }483 }484 485 // FIXME: getFixupKindInfo() and getFixupKindNumBytes() could be fixed to486 // handle this more cleanly. This may affect the output of -show-mc-encoding.487 AArch64::Specifier RefKind =488 static_cast<AArch64::Specifier>(Target.getSpecifier());489 if (AArch64::getSymbolLoc(RefKind) == AArch64::S_SABS ||490 (!RefKind && Fixup.getKind() == AArch64::fixup_aarch64_movw)) {491 // If the immediate is negative, generate MOVN else MOVZ.492 // (Bit 30 = 0) ==> MOVN, (Bit 30 = 1) ==> MOVZ.493 if (SignedValue < 0)494 Data[3] &= ~(1 << 6);495 else496 Data[3] |= (1 << 6);497 }498}499 500bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,501 uint64_t Value) const {502 // FIXME: This isn't correct for AArch64. Just moving the "generic" logic503 // into the targets for now.504 //505 // Relax if the value is too big for a (signed) i8.506 return int64_t(Value) != int64_t(int8_t(Value));507}508 509bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,510 const MCSubtargetInfo *STI) const {511 // If the count is not 4-byte aligned, we must be writing data into the text512 // section (otherwise we have unaligned instructions, and thus have far513 // bigger problems), so just write zeros instead.514 OS.write_zeros(Count % 4);515 516 // We are properly aligned, so write NOPs as requested.517 Count /= 4;518 for (uint64_t i = 0; i != Count; ++i)519 OS.write("\x1f\x20\x03\xd5", 4);520 return true;521}522 523namespace {524 525namespace CU {526 527/// Compact unwind encoding values.528enum CompactUnwindEncodings {529 /// A "frameless" leaf function, where no non-volatile registers are530 /// saved. The return remains in LR throughout the function.531 UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,532 533 /// No compact unwind encoding available. Instead the low 23-bits of534 /// the compact unwind encoding is the offset of the DWARF FDE in the535 /// __eh_frame section. This mode is never used in object files. It is only536 /// generated by the linker in final linked images, which have only DWARF info537 /// for a function.538 UNWIND_ARM64_MODE_DWARF = 0x03000000,539 540 /// This is a standard arm64 prologue where FP/LR are immediately541 /// pushed on the stack, then SP is copied to FP. If there are any542 /// non-volatile register saved, they are copied into the stack fame in pairs543 /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the544 /// five X pairs and four D pairs can be saved, but the memory layout must be545 /// in register number order.546 UNWIND_ARM64_MODE_FRAME = 0x04000000,547 548 /// Frame register pair encodings.549 UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,550 UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,551 UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,552 UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,553 UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,554 UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,555 UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,556 UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,557 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800558};559 560} // end CU namespace561 562// FIXME: This should be in a separate file.563class DarwinAArch64AsmBackend : public AArch64AsmBackend {564 const MCRegisterInfo &MRI;565 566 /// Encode compact unwind stack adjustment for frameless functions.567 /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.568 /// The stack size always needs to be 16 byte aligned.569 uint32_t encodeStackAdjustment(uint32_t StackSize) const {570 return (StackSize / 16) << 12;571 }572 573public:574 DarwinAArch64AsmBackend(const Target &T, const Triple &TT,575 const MCRegisterInfo &MRI)576 : AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MRI(MRI) {}577 578 std::unique_ptr<MCObjectTargetWriter>579 createObjectTargetWriter() const override {580 uint32_t CPUType = cantFail(MachO::getCPUType(TheTriple));581 uint32_t CPUSubType = cantFail(MachO::getCPUSubType(TheTriple));582 return createAArch64MachObjectWriter(CPUType, CPUSubType,583 TheTriple.isArch32Bit());584 }585 586 /// Generate the compact unwind encoding from the CFI directives.587 uint64_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,588 const MCContext *Ctxt) const override {589 ArrayRef<MCCFIInstruction> Instrs = FI->Instructions;590 if (Instrs.empty())591 return CU::UNWIND_ARM64_MODE_FRAMELESS;592 if (!isDarwinCanonicalPersonality(FI->Personality) &&593 !Ctxt->emitCompactUnwindNonCanonical())594 return CU::UNWIND_ARM64_MODE_DWARF;595 596 bool HasFP = false;597 uint64_t StackSize = 0;598 599 uint64_t CompactUnwindEncoding = 0;600 int64_t CurOffset = 0;601 for (size_t i = 0, e = Instrs.size(); i != e; ++i) {602 const MCCFIInstruction &Inst = Instrs[i];603 604 switch (Inst.getOperation()) {605 default:606 // Cannot handle this directive: bail out.607 return CU::UNWIND_ARM64_MODE_DWARF;608 case MCCFIInstruction::OpDefCfa: {609 // Defines a frame pointer.610 MCRegister XReg =611 getXRegFromWReg(*MRI.getLLVMRegNum(Inst.getRegister(), true));612 613 // Other CFA registers than FP are not supported by compact unwind.614 // Fallback on DWARF.615 // FIXME: When opt-remarks are supported in MC, add a remark to notify616 // the user.617 if (XReg != AArch64::FP)618 return CU::UNWIND_ARM64_MODE_DWARF;619 620 if (i + 2 >= e)621 return CU::UNWIND_ARM64_MODE_DWARF;622 623 const MCCFIInstruction &LRPush = Instrs[++i];624 if (LRPush.getOperation() != MCCFIInstruction::OpOffset)625 return CU::UNWIND_ARM64_MODE_DWARF;626 const MCCFIInstruction &FPPush = Instrs[++i];627 if (FPPush.getOperation() != MCCFIInstruction::OpOffset)628 return CU::UNWIND_ARM64_MODE_DWARF;629 630 if (FPPush.getOffset() + 8 != LRPush.getOffset())631 return CU::UNWIND_ARM64_MODE_DWARF;632 CurOffset = FPPush.getOffset();633 634 MCRegister LRReg = *MRI.getLLVMRegNum(LRPush.getRegister(), true);635 MCRegister FPReg = *MRI.getLLVMRegNum(FPPush.getRegister(), true);636 637 LRReg = getXRegFromWReg(LRReg);638 FPReg = getXRegFromWReg(FPReg);639 640 if (LRReg != AArch64::LR || FPReg != AArch64::FP)641 return CU::UNWIND_ARM64_MODE_DWARF;642 643 // Indicate that the function has a frame.644 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;645 HasFP = true;646 break;647 }648 case MCCFIInstruction::OpDefCfaOffset: {649 if (StackSize != 0)650 return CU::UNWIND_ARM64_MODE_DWARF;651 StackSize = std::abs(Inst.getOffset());652 break;653 }654 case MCCFIInstruction::OpOffset: {655 // Registers are saved in pairs. We expect there to be two consecutive656 // `.cfi_offset' instructions with the appropriate registers specified.657 MCRegister Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true);658 if (i + 1 == e)659 return CU::UNWIND_ARM64_MODE_DWARF;660 661 if (CurOffset != 0 && Inst.getOffset() != CurOffset - 8)662 return CU::UNWIND_ARM64_MODE_DWARF;663 CurOffset = Inst.getOffset();664 665 const MCCFIInstruction &Inst2 = Instrs[++i];666 if (Inst2.getOperation() != MCCFIInstruction::OpOffset)667 return CU::UNWIND_ARM64_MODE_DWARF;668 MCRegister Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true);669 670 if (Inst2.getOffset() != CurOffset - 8)671 return CU::UNWIND_ARM64_MODE_DWARF;672 CurOffset = Inst2.getOffset();673 674 // N.B. The encodings must be in register number order, and the X675 // registers before the D registers.676 677 // X19/X20 pair = 0x00000001,678 // X21/X22 pair = 0x00000002,679 // X23/X24 pair = 0x00000004,680 // X25/X26 pair = 0x00000008,681 // X27/X28 pair = 0x00000010682 Reg1 = getXRegFromWReg(Reg1);683 Reg2 = getXRegFromWReg(Reg2);684 685 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&686 (CompactUnwindEncoding & 0xF1E) == 0)687 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;688 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&689 (CompactUnwindEncoding & 0xF1C) == 0)690 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;691 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&692 (CompactUnwindEncoding & 0xF18) == 0)693 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;694 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&695 (CompactUnwindEncoding & 0xF10) == 0)696 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;697 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&698 (CompactUnwindEncoding & 0xF00) == 0)699 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;700 else {701 Reg1 = getDRegFromBReg(Reg1);702 Reg2 = getDRegFromBReg(Reg2);703 704 // D8/D9 pair = 0x00000100,705 // D10/D11 pair = 0x00000200,706 // D12/D13 pair = 0x00000400,707 // D14/D15 pair = 0x00000800708 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&709 (CompactUnwindEncoding & 0xE00) == 0)710 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;711 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&712 (CompactUnwindEncoding & 0xC00) == 0)713 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;714 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 &&715 (CompactUnwindEncoding & 0x800) == 0)716 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;717 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)718 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;719 else720 // A pair was pushed which we cannot handle.721 return CU::UNWIND_ARM64_MODE_DWARF;722 }723 724 break;725 }726 }727 }728 729 if (!HasFP) {730 // With compact unwind info we can only represent stack adjustments of up731 // to 65520 bytes.732 if (StackSize > 65520)733 return CU::UNWIND_ARM64_MODE_DWARF;734 735 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;736 CompactUnwindEncoding |= encodeStackAdjustment(StackSize);737 }738 739 return CompactUnwindEncoding;740 }741};742 743} // end anonymous namespace744 745namespace {746 747class ELFAArch64AsmBackend : public AArch64AsmBackend {748public:749 uint8_t OSABI;750 bool IsILP32;751 752 ELFAArch64AsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,753 bool IsLittleEndian, bool IsILP32)754 : AArch64AsmBackend(T, TT, IsLittleEndian), OSABI(OSABI),755 IsILP32(IsILP32) {}756 757 std::unique_ptr<MCObjectTargetWriter>758 createObjectTargetWriter() const override {759 return createAArch64ELFObjectWriter(OSABI, IsILP32);760 }761};762 763}764 765namespace {766class COFFAArch64AsmBackend : public AArch64AsmBackend {767public:768 COFFAArch64AsmBackend(const Target &T, const Triple &TheTriple)769 : AArch64AsmBackend(T, TheTriple, /*IsLittleEndian*/ true) {}770 771 std::unique_ptr<MCObjectTargetWriter>772 createObjectTargetWriter() const override {773 return createAArch64WinCOFFObjectWriter(TheTriple);774 }775};776}777 778MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,779 const MCSubtargetInfo &STI,780 const MCRegisterInfo &MRI,781 const MCTargetOptions &Options) {782 const Triple &TheTriple = STI.getTargetTriple();783 if (TheTriple.isOSBinFormatMachO()) {784 return new DarwinAArch64AsmBackend(T, TheTriple, MRI);785 }786 787 if (TheTriple.isOSBinFormatCOFF())788 return new COFFAArch64AsmBackend(T, TheTriple);789 790 assert(TheTriple.isOSBinFormatELF() && "Invalid target");791 792 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());793 bool IsILP32 = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32;794 return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/true,795 IsILP32);796}797 798MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,799 const MCSubtargetInfo &STI,800 const MCRegisterInfo &MRI,801 const MCTargetOptions &Options) {802 const Triple &TheTriple = STI.getTargetTriple();803 assert(TheTriple.isOSBinFormatELF() &&804 "Big endian is only supported for ELF targets!");805 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());806 bool IsILP32 = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32;807 return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/false,808 IsILP32);809}810