557 lines · cpp
1//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides AArch64 specific target descriptions.10//11//===----------------------------------------------------------------------===//12 13#include "AArch64MCTargetDesc.h"14#include "AArch64ELFStreamer.h"15#include "AArch64MCAsmInfo.h"16#include "AArch64WinCOFFStreamer.h"17#include "MCTargetDesc/AArch64AddressingModes.h"18#include "MCTargetDesc/AArch64InstPrinter.h"19#include "TargetInfo/AArch64TargetInfo.h"20#include "llvm/DebugInfo/CodeView/CodeView.h"21#include "llvm/MC/MCAsmBackend.h"22#include "llvm/MC/MCCodeEmitter.h"23#include "llvm/MC/MCInstrAnalysis.h"24#include "llvm/MC/MCInstrInfo.h"25#include "llvm/MC/MCObjectWriter.h"26#include "llvm/MC/MCRegisterInfo.h"27#include "llvm/MC/MCStreamer.h"28#include "llvm/MC/MCSubtargetInfo.h"29#include "llvm/MC/TargetRegistry.h"30#include "llvm/Support/Compiler.h"31#include "llvm/Support/Endian.h"32#include "llvm/Support/ErrorHandling.h"33#include "llvm/TargetParser/AArch64TargetParser.h"34 35using namespace llvm;36 37#define GET_INSTRINFO_MC_DESC38#define GET_INSTRINFO_MC_HELPERS39#define ENABLE_INSTR_PREDICATE_VERIFIER40#include "AArch64GenInstrInfo.inc"41 42#define GET_SUBTARGETINFO_MC_DESC43#include "AArch64GenSubtargetInfo.inc"44 45#define GET_REGINFO_MC_DESC46#include "AArch64GenRegisterInfo.inc"47 48static MCInstrInfo *createAArch64MCInstrInfo() {49 MCInstrInfo *X = new MCInstrInfo();50 InitAArch64MCInstrInfo(X);51 return X;52}53 54static MCSubtargetInfo *55createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {56 CPU = AArch64::resolveCPUAlias(CPU);57 58 if (CPU.empty()) {59 CPU = "generic";60 if (FS.empty())61 FS = "+v8a";62 63 if (TT.isArm64e())64 CPU = "apple-a12";65 }66 67 return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);68}69 70void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {71 // Mapping from CodeView to MC register id.72 static const struct {73 codeview::RegisterId CVReg;74 MCPhysReg Reg;75 } RegMap[] = {76 {codeview::RegisterId::ARM64_W0, AArch64::W0},77 {codeview::RegisterId::ARM64_W1, AArch64::W1},78 {codeview::RegisterId::ARM64_W2, AArch64::W2},79 {codeview::RegisterId::ARM64_W3, AArch64::W3},80 {codeview::RegisterId::ARM64_W4, AArch64::W4},81 {codeview::RegisterId::ARM64_W5, AArch64::W5},82 {codeview::RegisterId::ARM64_W6, AArch64::W6},83 {codeview::RegisterId::ARM64_W7, AArch64::W7},84 {codeview::RegisterId::ARM64_W8, AArch64::W8},85 {codeview::RegisterId::ARM64_W9, AArch64::W9},86 {codeview::RegisterId::ARM64_W10, AArch64::W10},87 {codeview::RegisterId::ARM64_W11, AArch64::W11},88 {codeview::RegisterId::ARM64_W12, AArch64::W12},89 {codeview::RegisterId::ARM64_W13, AArch64::W13},90 {codeview::RegisterId::ARM64_W14, AArch64::W14},91 {codeview::RegisterId::ARM64_W15, AArch64::W15},92 {codeview::RegisterId::ARM64_W16, AArch64::W16},93 {codeview::RegisterId::ARM64_W17, AArch64::W17},94 {codeview::RegisterId::ARM64_W18, AArch64::W18},95 {codeview::RegisterId::ARM64_W19, AArch64::W19},96 {codeview::RegisterId::ARM64_W20, AArch64::W20},97 {codeview::RegisterId::ARM64_W21, AArch64::W21},98 {codeview::RegisterId::ARM64_W22, AArch64::W22},99 {codeview::RegisterId::ARM64_W23, AArch64::W23},100 {codeview::RegisterId::ARM64_W24, AArch64::W24},101 {codeview::RegisterId::ARM64_W25, AArch64::W25},102 {codeview::RegisterId::ARM64_W26, AArch64::W26},103 {codeview::RegisterId::ARM64_W27, AArch64::W27},104 {codeview::RegisterId::ARM64_W28, AArch64::W28},105 {codeview::RegisterId::ARM64_W29, AArch64::W29},106 {codeview::RegisterId::ARM64_W30, AArch64::W30},107 {codeview::RegisterId::ARM64_WZR, AArch64::WZR},108 {codeview::RegisterId::ARM64_X0, AArch64::X0},109 {codeview::RegisterId::ARM64_X1, AArch64::X1},110 {codeview::RegisterId::ARM64_X2, AArch64::X2},111 {codeview::RegisterId::ARM64_X3, AArch64::X3},112 {codeview::RegisterId::ARM64_X4, AArch64::X4},113 {codeview::RegisterId::ARM64_X5, AArch64::X5},114 {codeview::RegisterId::ARM64_X6, AArch64::X6},115 {codeview::RegisterId::ARM64_X7, AArch64::X7},116 {codeview::RegisterId::ARM64_X8, AArch64::X8},117 {codeview::RegisterId::ARM64_X9, AArch64::X9},118 {codeview::RegisterId::ARM64_X10, AArch64::X10},119 {codeview::RegisterId::ARM64_X11, AArch64::X11},120 {codeview::RegisterId::ARM64_X12, AArch64::X12},121 {codeview::RegisterId::ARM64_X13, AArch64::X13},122 {codeview::RegisterId::ARM64_X14, AArch64::X14},123 {codeview::RegisterId::ARM64_X15, AArch64::X15},124 {codeview::RegisterId::ARM64_X16, AArch64::X16},125 {codeview::RegisterId::ARM64_X17, AArch64::X17},126 {codeview::RegisterId::ARM64_X18, AArch64::X18},127 {codeview::RegisterId::ARM64_X19, AArch64::X19},128 {codeview::RegisterId::ARM64_X20, AArch64::X20},129 {codeview::RegisterId::ARM64_X21, AArch64::X21},130 {codeview::RegisterId::ARM64_X22, AArch64::X22},131 {codeview::RegisterId::ARM64_X23, AArch64::X23},132 {codeview::RegisterId::ARM64_X24, AArch64::X24},133 {codeview::RegisterId::ARM64_X25, AArch64::X25},134 {codeview::RegisterId::ARM64_X26, AArch64::X26},135 {codeview::RegisterId::ARM64_X27, AArch64::X27},136 {codeview::RegisterId::ARM64_X28, AArch64::X28},137 {codeview::RegisterId::ARM64_FP, AArch64::FP},138 {codeview::RegisterId::ARM64_LR, AArch64::LR},139 {codeview::RegisterId::ARM64_SP, AArch64::SP},140 {codeview::RegisterId::ARM64_ZR, AArch64::XZR},141 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},142 {codeview::RegisterId::ARM64_S0, AArch64::S0},143 {codeview::RegisterId::ARM64_S1, AArch64::S1},144 {codeview::RegisterId::ARM64_S2, AArch64::S2},145 {codeview::RegisterId::ARM64_S3, AArch64::S3},146 {codeview::RegisterId::ARM64_S4, AArch64::S4},147 {codeview::RegisterId::ARM64_S5, AArch64::S5},148 {codeview::RegisterId::ARM64_S6, AArch64::S6},149 {codeview::RegisterId::ARM64_S7, AArch64::S7},150 {codeview::RegisterId::ARM64_S8, AArch64::S8},151 {codeview::RegisterId::ARM64_S9, AArch64::S9},152 {codeview::RegisterId::ARM64_S10, AArch64::S10},153 {codeview::RegisterId::ARM64_S11, AArch64::S11},154 {codeview::RegisterId::ARM64_S12, AArch64::S12},155 {codeview::RegisterId::ARM64_S13, AArch64::S13},156 {codeview::RegisterId::ARM64_S14, AArch64::S14},157 {codeview::RegisterId::ARM64_S15, AArch64::S15},158 {codeview::RegisterId::ARM64_S16, AArch64::S16},159 {codeview::RegisterId::ARM64_S17, AArch64::S17},160 {codeview::RegisterId::ARM64_S18, AArch64::S18},161 {codeview::RegisterId::ARM64_S19, AArch64::S19},162 {codeview::RegisterId::ARM64_S20, AArch64::S20},163 {codeview::RegisterId::ARM64_S21, AArch64::S21},164 {codeview::RegisterId::ARM64_S22, AArch64::S22},165 {codeview::RegisterId::ARM64_S23, AArch64::S23},166 {codeview::RegisterId::ARM64_S24, AArch64::S24},167 {codeview::RegisterId::ARM64_S25, AArch64::S25},168 {codeview::RegisterId::ARM64_S26, AArch64::S26},169 {codeview::RegisterId::ARM64_S27, AArch64::S27},170 {codeview::RegisterId::ARM64_S28, AArch64::S28},171 {codeview::RegisterId::ARM64_S29, AArch64::S29},172 {codeview::RegisterId::ARM64_S30, AArch64::S30},173 {codeview::RegisterId::ARM64_S31, AArch64::S31},174 {codeview::RegisterId::ARM64_D0, AArch64::D0},175 {codeview::RegisterId::ARM64_D1, AArch64::D1},176 {codeview::RegisterId::ARM64_D2, AArch64::D2},177 {codeview::RegisterId::ARM64_D3, AArch64::D3},178 {codeview::RegisterId::ARM64_D4, AArch64::D4},179 {codeview::RegisterId::ARM64_D5, AArch64::D5},180 {codeview::RegisterId::ARM64_D6, AArch64::D6},181 {codeview::RegisterId::ARM64_D7, AArch64::D7},182 {codeview::RegisterId::ARM64_D8, AArch64::D8},183 {codeview::RegisterId::ARM64_D9, AArch64::D9},184 {codeview::RegisterId::ARM64_D10, AArch64::D10},185 {codeview::RegisterId::ARM64_D11, AArch64::D11},186 {codeview::RegisterId::ARM64_D12, AArch64::D12},187 {codeview::RegisterId::ARM64_D13, AArch64::D13},188 {codeview::RegisterId::ARM64_D14, AArch64::D14},189 {codeview::RegisterId::ARM64_D15, AArch64::D15},190 {codeview::RegisterId::ARM64_D16, AArch64::D16},191 {codeview::RegisterId::ARM64_D17, AArch64::D17},192 {codeview::RegisterId::ARM64_D18, AArch64::D18},193 {codeview::RegisterId::ARM64_D19, AArch64::D19},194 {codeview::RegisterId::ARM64_D20, AArch64::D20},195 {codeview::RegisterId::ARM64_D21, AArch64::D21},196 {codeview::RegisterId::ARM64_D22, AArch64::D22},197 {codeview::RegisterId::ARM64_D23, AArch64::D23},198 {codeview::RegisterId::ARM64_D24, AArch64::D24},199 {codeview::RegisterId::ARM64_D25, AArch64::D25},200 {codeview::RegisterId::ARM64_D26, AArch64::D26},201 {codeview::RegisterId::ARM64_D27, AArch64::D27},202 {codeview::RegisterId::ARM64_D28, AArch64::D28},203 {codeview::RegisterId::ARM64_D29, AArch64::D29},204 {codeview::RegisterId::ARM64_D30, AArch64::D30},205 {codeview::RegisterId::ARM64_D31, AArch64::D31},206 {codeview::RegisterId::ARM64_Q0, AArch64::Q0},207 {codeview::RegisterId::ARM64_Q1, AArch64::Q1},208 {codeview::RegisterId::ARM64_Q2, AArch64::Q2},209 {codeview::RegisterId::ARM64_Q3, AArch64::Q3},210 {codeview::RegisterId::ARM64_Q4, AArch64::Q4},211 {codeview::RegisterId::ARM64_Q5, AArch64::Q5},212 {codeview::RegisterId::ARM64_Q6, AArch64::Q6},213 {codeview::RegisterId::ARM64_Q7, AArch64::Q7},214 {codeview::RegisterId::ARM64_Q8, AArch64::Q8},215 {codeview::RegisterId::ARM64_Q9, AArch64::Q9},216 {codeview::RegisterId::ARM64_Q10, AArch64::Q10},217 {codeview::RegisterId::ARM64_Q11, AArch64::Q11},218 {codeview::RegisterId::ARM64_Q12, AArch64::Q12},219 {codeview::RegisterId::ARM64_Q13, AArch64::Q13},220 {codeview::RegisterId::ARM64_Q14, AArch64::Q14},221 {codeview::RegisterId::ARM64_Q15, AArch64::Q15},222 {codeview::RegisterId::ARM64_Q16, AArch64::Q16},223 {codeview::RegisterId::ARM64_Q17, AArch64::Q17},224 {codeview::RegisterId::ARM64_Q18, AArch64::Q18},225 {codeview::RegisterId::ARM64_Q19, AArch64::Q19},226 {codeview::RegisterId::ARM64_Q20, AArch64::Q20},227 {codeview::RegisterId::ARM64_Q21, AArch64::Q21},228 {codeview::RegisterId::ARM64_Q22, AArch64::Q22},229 {codeview::RegisterId::ARM64_Q23, AArch64::Q23},230 {codeview::RegisterId::ARM64_Q24, AArch64::Q24},231 {codeview::RegisterId::ARM64_Q25, AArch64::Q25},232 {codeview::RegisterId::ARM64_Q26, AArch64::Q26},233 {codeview::RegisterId::ARM64_Q27, AArch64::Q27},234 {codeview::RegisterId::ARM64_Q28, AArch64::Q28},235 {codeview::RegisterId::ARM64_Q29, AArch64::Q29},236 {codeview::RegisterId::ARM64_Q30, AArch64::Q30},237 {codeview::RegisterId::ARM64_Q31, AArch64::Q31},238 {codeview::RegisterId::ARM64_B0, AArch64::B0},239 {codeview::RegisterId::ARM64_B1, AArch64::B1},240 {codeview::RegisterId::ARM64_B2, AArch64::B2},241 {codeview::RegisterId::ARM64_B3, AArch64::B3},242 {codeview::RegisterId::ARM64_B4, AArch64::B4},243 {codeview::RegisterId::ARM64_B5, AArch64::B5},244 {codeview::RegisterId::ARM64_B6, AArch64::B6},245 {codeview::RegisterId::ARM64_B7, AArch64::B7},246 {codeview::RegisterId::ARM64_B8, AArch64::B8},247 {codeview::RegisterId::ARM64_B9, AArch64::B9},248 {codeview::RegisterId::ARM64_B10, AArch64::B10},249 {codeview::RegisterId::ARM64_B11, AArch64::B11},250 {codeview::RegisterId::ARM64_B12, AArch64::B12},251 {codeview::RegisterId::ARM64_B13, AArch64::B13},252 {codeview::RegisterId::ARM64_B14, AArch64::B14},253 {codeview::RegisterId::ARM64_B15, AArch64::B15},254 {codeview::RegisterId::ARM64_B16, AArch64::B16},255 {codeview::RegisterId::ARM64_B17, AArch64::B17},256 {codeview::RegisterId::ARM64_B18, AArch64::B18},257 {codeview::RegisterId::ARM64_B19, AArch64::B19},258 {codeview::RegisterId::ARM64_B20, AArch64::B20},259 {codeview::RegisterId::ARM64_B21, AArch64::B21},260 {codeview::RegisterId::ARM64_B22, AArch64::B22},261 {codeview::RegisterId::ARM64_B23, AArch64::B23},262 {codeview::RegisterId::ARM64_B24, AArch64::B24},263 {codeview::RegisterId::ARM64_B25, AArch64::B25},264 {codeview::RegisterId::ARM64_B26, AArch64::B26},265 {codeview::RegisterId::ARM64_B27, AArch64::B27},266 {codeview::RegisterId::ARM64_B28, AArch64::B28},267 {codeview::RegisterId::ARM64_B29, AArch64::B29},268 {codeview::RegisterId::ARM64_B30, AArch64::B30},269 {codeview::RegisterId::ARM64_B31, AArch64::B31},270 {codeview::RegisterId::ARM64_H0, AArch64::H0},271 {codeview::RegisterId::ARM64_H1, AArch64::H1},272 {codeview::RegisterId::ARM64_H2, AArch64::H2},273 {codeview::RegisterId::ARM64_H3, AArch64::H3},274 {codeview::RegisterId::ARM64_H4, AArch64::H4},275 {codeview::RegisterId::ARM64_H5, AArch64::H5},276 {codeview::RegisterId::ARM64_H6, AArch64::H6},277 {codeview::RegisterId::ARM64_H7, AArch64::H7},278 {codeview::RegisterId::ARM64_H8, AArch64::H8},279 {codeview::RegisterId::ARM64_H9, AArch64::H9},280 {codeview::RegisterId::ARM64_H10, AArch64::H10},281 {codeview::RegisterId::ARM64_H11, AArch64::H11},282 {codeview::RegisterId::ARM64_H12, AArch64::H12},283 {codeview::RegisterId::ARM64_H13, AArch64::H13},284 {codeview::RegisterId::ARM64_H14, AArch64::H14},285 {codeview::RegisterId::ARM64_H15, AArch64::H15},286 {codeview::RegisterId::ARM64_H16, AArch64::H16},287 {codeview::RegisterId::ARM64_H17, AArch64::H17},288 {codeview::RegisterId::ARM64_H18, AArch64::H18},289 {codeview::RegisterId::ARM64_H19, AArch64::H19},290 {codeview::RegisterId::ARM64_H20, AArch64::H20},291 {codeview::RegisterId::ARM64_H21, AArch64::H21},292 {codeview::RegisterId::ARM64_H22, AArch64::H22},293 {codeview::RegisterId::ARM64_H23, AArch64::H23},294 {codeview::RegisterId::ARM64_H24, AArch64::H24},295 {codeview::RegisterId::ARM64_H25, AArch64::H25},296 {codeview::RegisterId::ARM64_H26, AArch64::H26},297 {codeview::RegisterId::ARM64_H27, AArch64::H27},298 {codeview::RegisterId::ARM64_H28, AArch64::H28},299 {codeview::RegisterId::ARM64_H29, AArch64::H29},300 {codeview::RegisterId::ARM64_H30, AArch64::H30},301 {codeview::RegisterId::ARM64_H31, AArch64::H31},302 };303 for (const auto &I : RegMap)304 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));305}306 307bool AArch64_MC::isHForm(const MCInst &MI, const MCInstrInfo *MCII) {308 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];309 return llvm::any_of(MI, [&](const MCOperand &Op) {310 return Op.isReg() && FPR16.contains(Op.getReg());311 });312}313 314bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) {315 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];316 return llvm::any_of(MI, [&](const MCOperand &Op) {317 return Op.isReg() && FPR128.contains(Op.getReg());318 });319}320 321bool AArch64_MC::isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII) {322 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];323 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID];324 const auto &FPR32 = AArch64MCRegisterClasses[AArch64::FPR32RegClassID];325 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];326 const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID];327 328 auto IsFPR = [&](const MCOperand &Op) {329 if (!Op.isReg())330 return false;331 auto Reg = Op.getReg();332 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) ||333 FPR16.contains(Reg) || FPR8.contains(Reg);334 };335 336 return llvm::any_of(MI, IsFPR);337}338 339static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {340 MCRegisterInfo *X = new MCRegisterInfo();341 InitAArch64MCRegisterInfo(X, AArch64::LR);342 AArch64_MC::initLLVMToCVRegMapping(X);343 return X;344}345 346static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,347 const Triple &TheTriple,348 const MCTargetOptions &Options) {349 MCAsmInfo *MAI;350 if (TheTriple.isOSBinFormatMachO())351 MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32);352 else if (TheTriple.isOSBinFormatELF())353 MAI = new AArch64MCAsmInfoELF(TheTriple);354 else if (TheTriple.isWindowsMSVCEnvironment())355 MAI = new AArch64MCAsmInfoMicrosoftCOFF();356 else if (TheTriple.isOSBinFormatCOFF())357 MAI = new AArch64MCAsmInfoGNUCOFF();358 else359 reportFatalUsageError("unsupported object format");360 361 // Initial state of the frame pointer is SP.362 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);363 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);364 MAI->addInitialFrameState(Inst);365 366 return MAI;367}368 369static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,370 unsigned SyntaxVariant,371 const MCAsmInfo &MAI,372 const MCInstrInfo &MII,373 const MCRegisterInfo &MRI) {374 if (SyntaxVariant == 0)375 return new AArch64InstPrinter(MAI, MII, MRI);376 if (SyntaxVariant == 1)377 return new AArch64AppleInstPrinter(MAI, MII, MRI);378 379 return nullptr;380}381 382static MCStreamer *383createMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,384 std::unique_ptr<MCObjectWriter> &&OW,385 std::unique_ptr<MCCodeEmitter> &&Emitter) {386 return createMachOStreamer(Ctx, std::move(TAB), std::move(OW),387 std::move(Emitter), /*ignore=*/false,388 /*LabelSections*/ true);389}390 391namespace {392 393class AArch64MCInstrAnalysis : public MCInstrAnalysis {394public:395 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}396 397 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,398 uint64_t &Target) const override {399 // Search for a PC-relative argument.400 // This will handle instructions like bcc (where the first argument is the401 // condition code) and cbz (where it is a register).402 const auto &Desc = Info->get(Inst.getOpcode());403 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {404 if (Desc.operands()[i].OperandType == MCOI::OPERAND_PCREL) {405 int64_t Imm = Inst.getOperand(i).getImm();406 if (Inst.getOpcode() == AArch64::ADR)407 Target = Addr + Imm;408 else if (Inst.getOpcode() == AArch64::ADRP)409 Target = (Addr & -4096) + Imm * 4096;410 else411 Target = Addr + Imm * 4;412 return true;413 }414 }415 return false;416 }417 418 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,419 APInt &Mask) const override {420 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());421 unsigned NumDefs = Desc.getNumDefs();422 unsigned NumImplicitDefs = Desc.implicit_defs().size();423 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&424 "Unexpected number of bits in the mask!");425 // 32-bit General Purpose Register class.426 const MCRegisterClass &GPR32RC = MRI.getRegClass(AArch64::GPR32RegClassID);427 // Floating Point Register classes.428 const MCRegisterClass &FPR8RC = MRI.getRegClass(AArch64::FPR8RegClassID);429 const MCRegisterClass &FPR16RC = MRI.getRegClass(AArch64::FPR16RegClassID);430 const MCRegisterClass &FPR32RC = MRI.getRegClass(AArch64::FPR32RegClassID);431 const MCRegisterClass &FPR64RC = MRI.getRegClass(AArch64::FPR64RegClassID);432 const MCRegisterClass &FPR128RC =433 MRI.getRegClass(AArch64::FPR128RegClassID);434 435 auto ClearsSuperReg = [=](MCRegister Reg) {436 // An update to the lower 32 bits of a 64 bit integer register is437 // architecturally defined to zero extend the upper 32 bits on a write.438 if (GPR32RC.contains(Reg))439 return true;440 // SIMD&FP instructions operating on scalar data only access the lower441 // bits of a register, the upper bits are zero extended on a write. For442 // SIMD vector registers smaller than 128-bits, the upper 64-bits of the443 // register are zero extended on a write.444 // When VL is higher than 128 bits, any write to a SIMD&FP register sets445 // bits higher than 128 to zero.446 return FPR8RC.contains(Reg) || FPR16RC.contains(Reg) ||447 FPR32RC.contains(Reg) || FPR64RC.contains(Reg) ||448 FPR128RC.contains(Reg);449 };450 451 Mask.clearAllBits();452 for (unsigned I = 0, E = NumDefs; I < E; ++I) {453 const MCOperand &Op = Inst.getOperand(I);454 if (ClearsSuperReg(Op.getReg()))455 Mask.setBit(I);456 }457 458 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {459 const MCPhysReg Reg = Desc.implicit_defs()[I];460 if (ClearsSuperReg(Reg))461 Mask.setBit(NumDefs + I);462 }463 464 return Mask.getBoolValue();465 }466 467 std::vector<std::pair<uint64_t, uint64_t>>468 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,469 const MCSubtargetInfo &STI) const override {470 // Do a lightweight parsing of PLT entries.471 std::vector<std::pair<uint64_t, uint64_t>> Result;472 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;473 Byte += 4) {474 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);475 uint64_t Off = 0;476 // Check for optional bti c that prefixes adrp in BTI enabled entries477 if (Insn == 0xd503245f) {478 Off = 4;479 Insn = support::endian::read32le(PltContents.data() + Byte + Off);480 }481 // Check for adrp.482 if ((Insn & 0x9f000000) != 0x90000000)483 continue;484 Off += 4;485 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +486 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);487 uint32_t Insn2 =488 support::endian::read32le(PltContents.data() + Byte + Off);489 // Check for: ldr Xt, [Xn, #pimm].490 if (Insn2 >> 22 == 0x3e5) {491 Imm += ((Insn2 >> 10) & 0xfff) << 3;492 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));493 Byte += 4;494 }495 }496 return Result;497 }498};499 500} // end anonymous namespace501 502static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {503 return new AArch64MCInstrAnalysis(Info);504}505 506// Force static initialization.507extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void508LLVMInitializeAArch64TargetMC() {509 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),510 &getTheAArch64_32Target(), &getTheARM64Target(),511 &getTheARM64_32Target()}) {512 // Register the MC asm info.513 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);514 515 // Register the MC instruction info.516 TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);517 518 // Register the MC register info.519 TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);520 521 // Register the MC subtarget info.522 TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);523 524 // Register the MC instruction analyzer.525 TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis);526 527 // Register the MC Code Emitter528 TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);529 530 // Register the obj streamers.531 TargetRegistry::RegisterELFStreamer(*T, createAArch64ELFStreamer);532 TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);533 TargetRegistry::RegisterCOFFStreamer(*T, createAArch64WinCOFFStreamer);534 535 // Register the obj target streamer.536 TargetRegistry::RegisterObjectTargetStreamer(537 *T, createAArch64ObjectTargetStreamer);538 539 // Register the asm streamer.540 TargetRegistry::RegisterAsmTargetStreamer(*T,541 createAArch64AsmTargetStreamer);542 // Register the null streamer.543 TargetRegistry::RegisterNullTargetStreamer(*T,544 createAArch64NullTargetStreamer);545 546 // Register the MCInstPrinter.547 TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);548 }549 550 // Register the asm backend.551 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(),552 &getTheARM64Target(), &getTheARM64_32Target()})553 TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);554 TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(),555 createAArch64beAsmBackend);556}557