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1//===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides AArch64 specific target descriptions.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H14#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H15 16#include "llvm/MC/MCInstrDesc.h"17#include "llvm/Support/DataTypes.h"18 19#include <memory>20 21namespace llvm {22class formatted_raw_ostream;23class MCAsmBackend;24class MCCodeEmitter;25class MCContext;26class MCInst;27class MCInstrInfo;28class MCInstPrinter;29class MCRegisterInfo;30class MCObjectTargetWriter;31class MCStreamer;32class MCSubtargetInfo;33class MCTargetOptions;34class MCTargetStreamer;35class Target;36class Triple;37 38MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,39 MCContext &Ctx);40MCAsmBackend *createAArch64leAsmBackend(const Target &T,41 const MCSubtargetInfo &STI,42 const MCRegisterInfo &MRI,43 const MCTargetOptions &Options);44MCAsmBackend *createAArch64beAsmBackend(const Target &T,45 const MCSubtargetInfo &STI,46 const MCRegisterInfo &MRI,47 const MCTargetOptions &Options);48 49std::unique_ptr<MCObjectTargetWriter>50createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);51 52std::unique_ptr<MCObjectTargetWriter>53createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype,54 bool IsILP32);55 56std::unique_ptr<MCObjectTargetWriter>57createAArch64WinCOFFObjectWriter(const Triple &TheTriple);58 59MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,60 formatted_raw_ostream &OS,61 MCInstPrinter *InstPrint);62 63namespace AArch64_MC {64void initLLVMToCVRegMapping(MCRegisterInfo *MRI);65bool isHForm(const MCInst &MI, const MCInstrInfo *MCII);66bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);67bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);68} // namespace AArch64_MC69 70namespace AArch64 {71enum OperandType {72 OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET,73 OPERAND_SHIFT_MSL,74};75} // namespace AArch6476 77} // namespace llvm78 79// Defines symbolic names for AArch64 registers. This defines a mapping from80// register name to register number.81//82#define GET_REGINFO_ENUM83#include "AArch64GenRegisterInfo.inc"84 85// Defines symbolic names for the AArch64 instructions.86//87#define GET_INSTRINFO_ENUM88#define GET_INSTRINFO_MC_HELPER_DECLS89#include "AArch64GenInstrInfo.inc"90 91#define GET_SUBTARGETINFO_ENUM92#include "AArch64GenSubtargetInfo.inc"93 94#endif95