248 lines · cpp
1//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides basic encoding and assembly information for AArch64.10//11//===----------------------------------------------------------------------===//12#include "AArch64BaseInfo.h"13#include "llvm/ADT/SmallVector.h"14#include "llvm/ADT/StringExtras.h"15#include "llvm/Support/Regex.h"16 17using namespace llvm;18 19namespace llvm {20 namespace AArch64AT {21#define GET_ATsList_IMPL22#include "AArch64GenSystemOperands.inc"23 }24}25 26 27namespace llvm {28 namespace AArch64DBnXS {29#define GET_DBnXSsList_IMPL30#include "AArch64GenSystemOperands.inc"31 }32}33 34namespace llvm {35 namespace AArch64DB {36#define GET_DBsList_IMPL37#include "AArch64GenSystemOperands.inc"38 }39}40 41namespace llvm {42 namespace AArch64DC {43#define GET_DCsList_IMPL44#include "AArch64GenSystemOperands.inc"45 }46}47 48namespace llvm {49 namespace AArch64IC {50#define GET_ICsList_IMPL51#include "AArch64GenSystemOperands.inc"52 }53}54 55namespace llvm {56 namespace AArch64ISB {57#define GET_ISBsList_IMPL58#include "AArch64GenSystemOperands.inc"59 }60}61 62namespace llvm {63 namespace AArch64TSB {64#define GET_TSBsList_IMPL65#include "AArch64GenSystemOperands.inc"66 }67}68 69namespace llvm {70 namespace AArch64PRFM {71#define GET_PRFMsList_IMPL72#include "AArch64GenSystemOperands.inc"73 }74}75 76namespace llvm {77 namespace AArch64SVEPRFM {78#define GET_SVEPRFMsList_IMPL79#include "AArch64GenSystemOperands.inc"80 }81}82 83namespace llvm {84 namespace AArch64RPRFM {85#define GET_RPRFMsList_IMPL86#include "AArch64GenSystemOperands.inc"87 } // namespace AArch64RPRFM88} // namespace llvm89 90namespace llvm {91 namespace AArch64SVEPredPattern {92#define GET_SVEPREDPATsList_IMPL93#include "AArch64GenSystemOperands.inc"94 }95}96 97namespace llvm {98namespace AArch64SVEVecLenSpecifier {99#define GET_SVEVECLENSPECIFIERsList_IMPL100#include "AArch64GenSystemOperands.inc"101} // namespace AArch64SVEVecLenSpecifier102} // namespace llvm103 104namespace llvm {105 namespace AArch64ExactFPImm {106#define GET_ExactFPImmsList_IMPL107#include "AArch64GenSystemOperands.inc"108 }109}110 111namespace llvm {112 namespace AArch64PState {113#define GET_PStateImm0_15sList_IMPL114#include "AArch64GenSystemOperands.inc"115#define GET_PStateImm0_1sList_IMPL116#include "AArch64GenSystemOperands.inc"117 }118}119 120namespace llvm {121 namespace AArch64PSBHint {122#define GET_PSBsList_IMPL123#include "AArch64GenSystemOperands.inc"124 }125}126 127namespace llvm {128namespace AArch64PHint {129#define GET_PHintsList_IMPL130#include "AArch64GenSystemOperands.inc"131} // namespace AArch64PHint132} // namespace llvm133 134namespace llvm {135 namespace AArch64BTIHint {136#define GET_BTIsList_IMPL137#include "AArch64GenSystemOperands.inc"138 }139}140 141namespace llvm {142namespace AArch64CMHPriorityHint {143#define GET_CMHPRIORITYHINT_IMPL144#include "AArch64GenSystemOperands.inc"145} // namespace AArch64CMHPriorityHint146} // namespace llvm147 148namespace llvm {149namespace AArch64TIndexHint {150#define GET_TINDEX_IMPL151#include "AArch64GenSystemOperands.inc"152} // namespace AArch64TIndexHint153} // namespace llvm154 155namespace llvm {156 namespace AArch64SysReg {157#define GET_SysRegsList_IMPL158#include "AArch64GenSystemOperands.inc"159 }160}161 162uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {163 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name164 static const Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");165 166 std::string UpperName = Name.upper();167 SmallVector<StringRef, 5> Ops;168 if (!GenericRegPattern.match(UpperName, &Ops))169 return -1;170 171 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;172 uint32_t Bits;173 Ops[1].getAsInteger(10, Op0);174 Ops[2].getAsInteger(10, Op1);175 Ops[3].getAsInteger(10, CRn);176 Ops[4].getAsInteger(10, CRm);177 Ops[5].getAsInteger(10, Op2);178 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;179 180 return Bits;181}182 183std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {184 assert(Bits < 0x10000);185 uint32_t Op0 = (Bits >> 14) & 0x3;186 uint32_t Op1 = (Bits >> 11) & 0x7;187 uint32_t CRn = (Bits >> 7) & 0xf;188 uint32_t CRm = (Bits >> 3) & 0xf;189 uint32_t Op2 = Bits & 0x7;190 191 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +192 utostr(CRm) + "_" + utostr(Op2);193}194 195namespace llvm {196namespace AArch64TLBI {197#define GET_TLBITable_IMPL198#include "AArch64GenSystemOperands.inc"199} // namespace AArch64TLBI200} // namespace llvm201 202namespace llvm {203namespace AArch64PLBI {204#define GET_PLBITable_IMPL205#include "AArch64GenSystemOperands.inc"206} // namespace AArch64PLBI207} // namespace llvm208 209namespace llvm {210namespace AArch64TLBIP {211#define GET_TLBIPTable_IMPL212#include "AArch64GenSystemOperands.inc"213} // namespace AArch64TLBIP214 215namespace AArch64MLBI {216#define GET_MLBITable_IMPL217#include "AArch64GenSystemOperands.inc"218} // namespace AArch64MLBI219} // namespace llvm220 221namespace llvm {222namespace AArch64GIC {223#define GET_GICTable_IMPL224#include "AArch64GenSystemOperands.inc"225} // namespace AArch64GIC226} // namespace llvm227 228namespace llvm {229namespace AArch64GICR {230#define GET_GICRTable_IMPL231#include "AArch64GenSystemOperands.inc"232} // namespace AArch64GICR233} // namespace llvm234 235namespace llvm {236namespace AArch64GSB {237#define GET_GSBTable_IMPL238#include "AArch64GenSystemOperands.inc"239} // namespace AArch64GSB240} // namespace llvm241 242namespace llvm {243 namespace AArch64SVCR {244#define GET_SVCRsList_IMPL245#include "AArch64GenSystemOperands.inc"246 }247}248