194 lines · cpp
1//===----------------------------------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "AMDGPUArgumentUsageInfo.h"10#include "AMDGPU.h"11#include "MCTargetDesc/AMDGPUMCTargetDesc.h"12#include "SIRegisterInfo.h"13#include "llvm/CodeGen/TargetRegisterInfo.h"14#include "llvm/IR/Function.h"15#include "llvm/Support/NativeFormatting.h"16#include "llvm/Support/raw_ostream.h"17 18using namespace llvm;19 20#define DEBUG_TYPE "amdgpu-argument-reg-usage-info"21 22INITIALIZE_PASS(AMDGPUArgumentUsageInfo, DEBUG_TYPE,23 "Argument Register Usage Information Storage", false, true)24 25void ArgDescriptor::print(raw_ostream &OS,26 const TargetRegisterInfo *TRI) const {27 if (!isSet()) {28 OS << "<not set>\n";29 return;30 }31 32 if (isRegister())33 OS << "Reg " << printReg(getRegister(), TRI);34 else35 OS << "Stack offset " << getStackOffset();36 37 if (isMasked()) {38 OS << " & ";39 llvm::write_hex(OS, Mask, llvm::HexPrintStyle::PrefixLower);40 }41 42 OS << '\n';43}44 45char AMDGPUArgumentUsageInfo::ID = 0;46 47const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{};48 49// Hardcoded registers from fixed function ABI50const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::FixedABIFunctionInfo51 = AMDGPUFunctionArgInfo::fixedABILayout();52 53bool AMDGPUArgumentUsageInfo::doInitialization(Module &M) {54 return false;55}56 57bool AMDGPUArgumentUsageInfo::doFinalization(Module &M) {58 ArgInfoMap.clear();59 return false;60}61 62// TODO: Print preload kernargs?63void AMDGPUArgumentUsageInfo::print(raw_ostream &OS, const Module *M) const {64 for (const auto &FI : ArgInfoMap) {65 OS << "Arguments for " << FI.first->getName() << '\n'66 << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer67 << " DispatchPtr: " << FI.second.DispatchPtr68 << " QueuePtr: " << FI.second.QueuePtr69 << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr70 << " DispatchID: " << FI.second.DispatchID71 << " FlatScratchInit: " << FI.second.FlatScratchInit72 << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize73 << " WorkGroupIDX: " << FI.second.WorkGroupIDX74 << " WorkGroupIDY: " << FI.second.WorkGroupIDY75 << " WorkGroupIDZ: " << FI.second.WorkGroupIDZ76 << " WorkGroupInfo: " << FI.second.WorkGroupInfo77 << " LDSKernelId: " << FI.second.LDSKernelId78 << " PrivateSegmentWaveByteOffset: "79 << FI.second.PrivateSegmentWaveByteOffset80 << " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr81 << " ImplicitArgPtr: " << FI.second.ImplicitArgPtr82 << " WorkItemIDX " << FI.second.WorkItemIDX83 << " WorkItemIDY " << FI.second.WorkItemIDY84 << " WorkItemIDZ " << FI.second.WorkItemIDZ85 << '\n';86 }87}88 89std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>90AMDGPUFunctionArgInfo::getPreloadedValue(91 AMDGPUFunctionArgInfo::PreloadedValue Value) const {92 switch (Value) {93 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: {94 return std::tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,95 &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32));96 }97 case AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR:98 return std::tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,99 &AMDGPU::SGPR_64RegClass,100 LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));101 case AMDGPUFunctionArgInfo::WORKGROUP_ID_X:102 return std::tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,103 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));104 case AMDGPUFunctionArgInfo::WORKGROUP_ID_Y:105 return std::tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,106 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));107 case AMDGPUFunctionArgInfo::WORKGROUP_ID_Z:108 return std::tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,109 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));110 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_X:111 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_Y:112 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_ID_Z:113 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_X:114 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_Y:115 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_ID_Z:116 case AMDGPUFunctionArgInfo::CLUSTER_WORKGROUP_MAX_FLAT_ID:117 return std::tuple(nullptr, &AMDGPU::SGPR_32RegClass, LLT::scalar(32));118 case AMDGPUFunctionArgInfo::LDS_KERNEL_ID:119 return std::tuple(LDSKernelId ? &LDSKernelId : nullptr,120 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));121 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET:122 return std::tuple(123 PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,124 &AMDGPU::SGPR_32RegClass, LLT::scalar(32));125 case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_SIZE:126 return {PrivateSegmentSize ? &PrivateSegmentSize : nullptr,127 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)};128 case AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR:129 return std::tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,130 &AMDGPU::SGPR_64RegClass,131 LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));132 case AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR:133 return std::tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,134 &AMDGPU::SGPR_64RegClass,135 LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));136 case AMDGPUFunctionArgInfo::DISPATCH_ID:137 return std::tuple(DispatchID ? &DispatchID : nullptr,138 &AMDGPU::SGPR_64RegClass, LLT::scalar(64));139 case AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT:140 return std::tuple(FlatScratchInit ? &FlatScratchInit : nullptr,141 &AMDGPU::SGPR_64RegClass, LLT::scalar(64));142 case AMDGPUFunctionArgInfo::DISPATCH_PTR:143 return std::tuple(DispatchPtr ? &DispatchPtr : nullptr,144 &AMDGPU::SGPR_64RegClass,145 LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));146 case AMDGPUFunctionArgInfo::QUEUE_PTR:147 return std::tuple(QueuePtr ? &QueuePtr : nullptr, &AMDGPU::SGPR_64RegClass,148 LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));149 case AMDGPUFunctionArgInfo::WORKITEM_ID_X:150 return std::tuple(WorkItemIDX ? &WorkItemIDX : nullptr,151 &AMDGPU::VGPR_32RegClass, LLT::scalar(32));152 case AMDGPUFunctionArgInfo::WORKITEM_ID_Y:153 return std::tuple(WorkItemIDY ? &WorkItemIDY : nullptr,154 &AMDGPU::VGPR_32RegClass, LLT::scalar(32));155 case AMDGPUFunctionArgInfo::WORKITEM_ID_Z:156 return std::tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,157 &AMDGPU::VGPR_32RegClass, LLT::scalar(32));158 }159 llvm_unreachable("unexpected preloaded value type");160}161 162AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::fixedABILayout() {163 AMDGPUFunctionArgInfo AI;164 AI.PrivateSegmentBuffer165 = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);166 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5);167 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7);168 169 // Do not pass kernarg segment pointer, only pass increment version in its170 // place.171 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9);172 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11);173 174 // Skip FlatScratchInit/PrivateSegmentSize175 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12);176 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13);177 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14);178 AI.LDSKernelId = ArgDescriptor::createRegister(AMDGPU::SGPR15);179 180 const unsigned Mask = 0x3ff;181 AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask);182 AI.WorkItemIDY = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 10);183 AI.WorkItemIDZ = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 20);184 return AI;185}186 187const AMDGPUFunctionArgInfo &188AMDGPUArgumentUsageInfo::lookupFuncArgInfo(const Function &F) const {189 auto I = ArgInfoMap.find(&F);190 if (I == ArgInfoMap.end())191 return FixedABIFunctionInfo;192 return I->second;193}194