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1//===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H10#define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H11 12#include "llvm/ADT/DenseSet.h"13#include "llvm/CodeGen/Register.h"14#include <utility>15 16namespace llvm {17 18class MachineRegisterInfo;19class GCNSubtarget;20class GISelValueTracking;21class LLT;22class MachineFunction;23class MachineIRBuilder;24class RegisterBankInfo;25 26namespace AMDGPU {27 28/// Returns base register and constant offset.29std::pair<Register, unsigned>30getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,31 GISelValueTracking *ValueTracking = nullptr,32 bool CheckNUW = false);33 34// Currently finds S32/S64 lane masks that can be declared as divergent by35// uniformity analysis (all are phis at the moment).36// These are defined as i32/i64 in some IR intrinsics (not as i1).37// Tablegen forces(via telling that lane mask IR intrinsics are uniform) most of38// S32/S64 lane masks to be uniform, as this results in them ending up with sgpr39// reg class after instruction-select, don't search for all of them.40class IntrinsicLaneMaskAnalyzer {41 SmallDenseSet<Register, 8> S32S64LaneMask;42 MachineRegisterInfo &MRI;43 44public:45 IntrinsicLaneMaskAnalyzer(MachineFunction &MF);46 bool isS32S64LaneMask(Register Reg) const;47 48private:49 void initLaneMaskIntrinsics(MachineFunction &MF);50};51 52void buildReadAnyLane(MachineIRBuilder &B, Register SgprDst, Register VgprSrc,53 const RegisterBankInfo &RBI);54void buildReadFirstLane(MachineIRBuilder &B, Register SgprDst, Register VgprSrc,55 const RegisterBankInfo &RBI);56}57}58 59#endif60