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1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains DAG node definitions for the AMDGPU target.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// AMDGPU DAG Profiles15//===----------------------------------------------------------------------===//16 17def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [18 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>19]>;20 21def AMDGPUFPClassOp : SDTypeProfile<1, 2,22 [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]23>;24 25def AMDGPUFPPackOp : SDTypeProfile<1, 2,26 [SDTCisFP<1>, SDTCisSameAs<1, 2>]27>;28 29def AMDGPUIntPackOp : SDTypeProfile<1, 2,30 [SDTCisInt<1>, SDTCisSameAs<1, 2>]31>;32 33def AMDGPUDivScaleOp : SDTypeProfile<2, 3,34 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]35>;36 37// float, float, float, vcc38def AMDGPUFmasOp : SDTypeProfile<1, 4,39 [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]40>;41 42def ImmOp : SDTypeProfile<0, 1, [SDTCisInt<0>]>;43def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;44 45def AMDGPUIfOp : SDTypeProfile<1, 2,46 [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]47>;48 49def AMDGPUElseOp : SDTypeProfile<1, 2,50 [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]51>;52 53def AMDGPULoopOp : SDTypeProfile<0, 2,54 [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]55>;56 57def AMDGPUIfBreakOp : SDTypeProfile<1, 2,58 [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, i1>]59>;60 61//===----------------------------------------------------------------------===//62// AMDGPU DAG Nodes63//64 65// Masked control flow nodes.66def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;67def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;68def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;69 70def callseq_start : SDNode<"ISD::CALLSEQ_START",71 SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,72 [SDNPHasChain, SDNPOutGlue]73>;74 75def callseq_end : SDNode<"ISD::CALLSEQ_END",76 SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,77 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]78>;79 80def AMDGPUcall : SDNode<"AMDGPUISD::CALL",81 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,83 SDNPVariadic]84>;85 86def AMDGPUTCReturnTP : SDTypeProfile<0, 3, [87 SDTCisPtrTy<0>88]>;89 90def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN", AMDGPUTCReturnTP,91[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]92>;93 94def AMDGPUtc_return_gfx: SDNode<"AMDGPUISD::TC_RETURN_GFX", AMDGPUTCReturnTP,95[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]96>;97 98def AMDGPUtc_return_gfx_ww: SDNode<"AMDGPUISD::TC_RETURN_GFX_WholeWave", AMDGPUTCReturnTP,99[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]100>;101 102def AMDGPUtc_return_chain: SDNode<"AMDGPUISD::TC_RETURN_CHAIN",103 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,104 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]105>;106 107// With dynamic VGPRs.108def AMDGPUtc_return_chain_dvgpr: SDNode<"AMDGPUISD::TC_RETURN_CHAIN_DVGPR",109 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,110 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]111>;112 113def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",114 SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>,115 [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPOptInGlue]116>;117 118// Pointer to the start of the shader's constant data.119def AMDGPUconstdata_ptr : SDNode<120 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,121 SDTCisVT<0, iPTR>]>122>;123 124// This argument to this node is a dword address.125def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;126 127// SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.128// Denormals handled on some parts.129def AMDGPUcos_impl : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;130def AMDGPUsin_impl : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;131 132// out = a - floor(a)133def AMDGPUfract_impl : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;134 135// out = 1.0 / a136def AMDGPUrcp_impl : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;137 138// v_log_f32, which is log2, no denormal handling for f32.139def AMDGPUlog_impl : SDNode<"AMDGPUISD::LOG", SDTFPUnaryOp>;140 141// v_exp_f32, which is exp2, no denormal handling for f32.142def AMDGPUexp_impl : SDNode<"AMDGPUISD::EXP", SDTFPUnaryOp>;143 144// out = 1.0 / sqrt(a)145def AMDGPUrsq_impl : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;146 147def AMDGPUrcp_legacy_impl : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;148 149def AMDGPUrcp_iflag : SDNode<"AMDGPUISD::RCP_IFLAG", SDTFPUnaryOp>;150 151// out = 1.0 / sqrt(a) result clamped to +/- max_float.152def AMDGPUrsq_clamp_impl : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;153 154// Convert two float 32 numbers into a single register holding two packed f16155// with round to zero.156def AMDGPUpkrtz_f16_f32_impl : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;157def AMDGPUpknorm_i16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_I16_F32", AMDGPUFPPackOp>;158def AMDGPUpknorm_u16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFPPackOp>;159def AMDGPUpk_i16_i32_impl : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;160def AMDGPUpk_u16_u32_impl : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;161 162// Same as the standard node, except the high bits of the resulting integer163// are known 0.164def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;165 166 167def AMDGPUfp_class_impl : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;168 169// out = max(a, b) a and b are floats, where a nan comparison fails.170// This is not commutative because this gives the second operand:171// x < nan ? x : nan -> nan172// nan < x ? nan : x -> x173def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,174 []175>;176 177def AMDGPUfmul_legacy_impl : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,178 [SDNPCommutative, SDNPAssociative]179>;180 181// out = min(a, b) a and b are floats, where a nan comparison fails.182def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,183 []184>;185 186// FIXME: TableGen doesn't like commutative instructions with more187// than 2 operands.188// out = max(a, b, c) a, b and c are floats189def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,190 [/*SDNPCommutative, SDNPAssociative*/]191>;192 193// out = max(a, b, c) a, b and c are floats. Operation is IEEE2019 compliant.194def AMDGPUfmaximum3 : SDNode<"AMDGPUISD::FMAXIMUM3", SDTFPTernaryOp,195 [/*SDNPCommutative, SDNPAssociative*/]196>;197 198// out = max(a, b, c) a, b, and c are signed ints199def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,200 [/*SDNPCommutative, SDNPAssociative*/]201>;202 203// out = max(a, b, c) a, b and c are unsigned ints204def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,205 [/*SDNPCommutative, SDNPAssociative*/]206>;207 208// out = min(a, b, c) a, b and c are floats209def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,210 [/*SDNPCommutative, SDNPAssociative*/]211>;212 213// out = min(a, b, c) a, b and c are floats. Operation is IEEE2019 compliant.214def AMDGPUfminimum3 : SDNode<"AMDGPUISD::FMINIMUM3", SDTFPTernaryOp,215 [/*SDNPCommutative, SDNPAssociative*/]216>;217 218// out = min(a, b, c) a, b and c are signed ints219def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,220 [/*SDNPCommutative, SDNPAssociative*/]221>;222 223// out = min(a, b) a and b are unsigned ints224def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,225 [/*SDNPCommutative, SDNPAssociative*/]226>;227 228// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0229def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;230 231// out = (src1 > src0) ? 1 : 0232def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;233 234def AMDGPUSetCCOp : SDTypeProfile<1, 3, [ // setcc235 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>236]>;237 238// This is SETCC with the full mask result which is used for a compare with a239// result bit per item in the wavefront.240def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;241 242// FP ops with input and output chain.243def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [244 SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;245 246def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [247 SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;248 249// These cvt_f32_ubyte* nodes need to remain consecutive and in order.250def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",251 SDTIntToFPOp, []>;252def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",253 SDTIntToFPOp, []>;254def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",255 SDTIntToFPOp, []>;256def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",257 SDTIntToFPOp, []>;258 259def AMDGPUcvt_pk_i16_i32 : SDNode<"AMDGPUISD::CVT_PK_I16_I32",260 AMDGPUIntPackOp, []>;261 262// urecip - This operation is a helper for integer division, it returns the263// result of 1 / a as a fractional unsigned integer.264// out = (2^32 / a) + e265// e is rounding error266def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;267 268// Special case divide preop and flags.269def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;270 271// Special case divide FMA with scale and flags (src0 = Quotient,272// src1 = Denominator, src2 = Numerator).273def AMDGPUdiv_fmas_impl : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp,274 [SDNPOptInGlue]>;275 276// Single or double precision division fixup.277// Special case divide fixup and flags(src0 = Quotient, src1 =278// Denominator, src2 = Numerator).279def AMDGPUdiv_fixup_impl : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;280 281// For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is282// treated as an illegal operation.283def AMDGPUfmad_ftz_impl : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;284 285def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",286 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,287 [SDNPHasChain, SDNPMayLoad]>;288 289def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",290 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,291 [SDNPHasChain, SDNPMayStore]>;292 293// MSKOR instructions are atomic memory instructions used mainly for storing294// 8-bit and 16-bit values. The definition is:295//296// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)297//298// src0: vec4(src, 0, 0, mask)299// src1: dst - rat offset (aka pointer) in dwords300def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",301 SDTypeProfile<0, 2, []>,302 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;303 304def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",305 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,306 [SDNPHasChain, SDNPMayStore, SDNPMayLoad,307 SDNPMemOperand]>;308 309// Extract range of bits with zero extension to 32-bits.310def AMDGPUbfe_u32_impl : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;311 312// Extract range of bits with sign extension to 32-bits.313def AMDGPUbfe_i32_impl : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;314 315// (src0 & src1) | (~src0 & src2)316def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;317 318// Insert a range of bits into a 32-bit word.319def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;320 321// ctlz with -1 if input is zero.322def AMDGPUffbh_u32_impl : SDNode<"AMDGPUISD::FFBH_U32", SDTIntBitCountUnaryOp>;323def AMDGPUffbh_i32_impl : SDNode<"AMDGPUISD::FFBH_I32", SDTIntBitCountUnaryOp>;324 325// cttz with -1 if input is zero.326def AMDGPUffbl_b32_impl : SDNode<"AMDGPUISD::FFBL_B32", SDTIntBitCountUnaryOp>;327 328// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore329// when performing the multiply. The result is a 32 or 64 bit value.330def AMDGPUMul24Op : SDTypeProfile<1, 2, [331 SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 2>332]>;333 334def AMDGPUmul_u24_impl : SDNode<"AMDGPUISD::MUL_U24", AMDGPUMul24Op,335 [SDNPCommutative, SDNPAssociative]336>;337def AMDGPUmul_i24_impl : SDNode<"AMDGPUISD::MUL_I24", AMDGPUMul24Op,338 [SDNPCommutative, SDNPAssociative]339>;340 341// mulhi24 yields the high-order 16 bits of the 48-bit result. Here's an example342// that shows mulhi24 is not associative:343//344// Given a = 0x10002, b = c = 0xffffff:345// mulhi24(mulhi24(a, b), c) = mulhi24(0x100, 0xffffff) = 0346// Which is not equal to:347// mulhi24(a, mulhi24(b, c)) = mulhi24(0x10002, 0xffff) = 1348def AMDGPUmulhi_u24_impl : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,349 [SDNPCommutative]350>;351def AMDGPUmulhi_i24_impl : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,352 [SDNPCommutative]353>;354 355def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,356 []357>;358def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,359 []360>;361 362def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,363 []364>;365 366def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,367 []368>;369 370def AMDGPUfmed3_impl : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;371 372def AMDGPUfdot2_impl : SDNode<"AMDGPUISD::FDOT2",373 SDTypeProfile<1, 4, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>,374 SDTCisFP<0>, SDTCisVec<1>,375 SDTCisInt<4>]>,376 []>;377 378def AMDGPUperm_impl : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;379 380// Marks the entry into a whole wave function.381def AMDGPUwhole_wave_setup : SDNode<382 "AMDGPUISD::WHOLE_WAVE_SETUP", SDTypeProfile<1, 0, [SDTCisInt<0>]>,383 [SDNPHasChain, SDNPSideEffect]>;384 385// Marks the return from a whole wave function.386def AMDGPUwhole_wave_return : SDNode<387 "AMDGPUISD::WHOLE_WAVE_RETURN", SDTNone,388 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]389>;390 391// SI+ export392def AMDGPUExportOp : SDTypeProfile<0, 8, [393 SDTCisInt<0>, // i8 tgt394 SDTCisInt<1>, // i8 en395 // i32 or f32 src0396 SDTCisSameAs<3, 2>, // f32 src1397 SDTCisSameAs<4, 2>, // f32 src2398 SDTCisSameAs<5, 2>, // f32 src3399 SDTCisInt<6>, // i1 compr400 // skip done401 SDTCisInt<1> // i1 vm402 403]>;404 405 406//===----------------------------------------------------------------------===//407// Flow Control Profile Types408//===----------------------------------------------------------------------===//409// Branch instruction where second and third are basic blocks410def SDTIL_BRCond : SDTypeProfile<0, 2, [411 SDTCisVT<0, OtherVT>412 ]>;413 414//===----------------------------------------------------------------------===//415// Flow Control DAG Nodes416//===----------------------------------------------------------------------===//417def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;418 419//===----------------------------------------------------------------------===//420// Call/Return DAG Nodes421//===----------------------------------------------------------------------===//422 423// A uniform kernel return that terminates the wavefront.424def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,425 [SDNPHasChain, SDNPOptInGlue]>;426 427// s_endpgm, but we may want to insert it in the middle of the block.428def AMDGPUendpgm_trap : SDNode<"AMDGPUISD::ENDPGM_TRAP", SDTNone,429 [SDNPHasChain]>;430 431// "s_trap 2" equivalent on hardware that does not support it.432def AMDGPUsimulated_trap : SDNode<"AMDGPUISD::SIMULATED_TRAP", SDTNone,433 [SDNPHasChain]>;434 435// Return to a shader part's epilog code.436def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,437 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;438 439// Return with values from a non-entry function.440def AMDGPUret_glue : SDNode<"AMDGPUISD::RET_GLUE", SDTNone,441 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]442>;443 444 445//===----------------------------------------------------------------------===//446// Intrinsic/Custom node compatibility PatFrags447//===----------------------------------------------------------------------===//448 449def AMDGPUrcp : PatFrags<(ops node:$src), [(int_amdgcn_rcp node:$src),450 (AMDGPUrcp_impl node:$src)]>;451def AMDGPUrcp_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rcp_legacy node:$src),452 (AMDGPUrcp_legacy_impl node:$src)]>;453 454def AMDGPUrsq : PatFrags<(ops node:$src), [(int_amdgcn_rsq node:$src),455 (AMDGPUrsq_impl node:$src)]>;456 457def AMDGPUrsq_clamp : PatFrags<(ops node:$src), [(int_amdgcn_rsq_clamp node:$src),458 (AMDGPUrsq_clamp_impl node:$src)]>;459 460def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),461 (AMDGPUsin_impl node:$src)]>;462def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),463 (AMDGPUcos_impl node:$src)]>;464def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),465 (AMDGPUfract_impl node:$src)]>;466def AMDGPUlog : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src),467 (AMDGPUlog_impl node:$src)]>;468def AMDGPUlogf16 : PatFrags<(ops node:$src), [(int_amdgcn_log node:$src),469 (flog2 node:$src)]>;470 471def AMDGPUexp : PatFrags<(ops node:$src), [(int_amdgcn_exp2 node:$src),472 (AMDGPUexp_impl node:$src)]>;473def AMDGPUexpf16 : PatFrags<(ops node:$src), [(int_amdgcn_exp2 node:$src),474 (fexp2 node:$src)]>;475 476def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),477 [(int_amdgcn_class node:$src0, node:$src1),478 (AMDGPUfp_class_impl node:$src0, node:$src1)]>;479 480def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),481 [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),482 (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;483 484def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),485 [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),486 (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;487 488def AMDGPUffbh_i32 : PatFrags<(ops node:$src),489 [(int_amdgcn_sffbh node:$src),490 (AMDGPUffbh_i32_impl node:$src)]>;491 492def AMDGPUffbh_u32 : PatFrags<(ops node:$src),493 [(ctlz_zero_undef node:$src),494 (AMDGPUffbh_u32_impl node:$src)]>;495 496def AMDGPUffbl_b32 : PatFrags<(ops node:$src),497 [(cttz_zero_undef node:$src),498 (AMDGPUffbl_b32_impl node:$src)]>;499 500def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),501 [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),502 (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;503 504def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),505 [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),506 (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;507 508def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),509 [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),510 (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;511 512def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),513 [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),514 (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;515 516def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),517 [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),518 (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;519 520def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),521 [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),522 (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;523 524def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),525 [(int_amdgcn_mul_u24 node:$src0, node:$src1),526 (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;527 528def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),529 [(int_amdgcn_mul_i24 node:$src0, node:$src1),530 (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;531 532def AMDGPUmulhi_u24 : PatFrags<(ops node:$src0, node:$src1),533 [(int_amdgcn_mulhi_u24 node:$src0, node:$src1),534 (AMDGPUmulhi_u24_impl node:$src0, node:$src1)]>;535 536def AMDGPUmulhi_i24 : PatFrags<(ops node:$src0, node:$src1),537 [(int_amdgcn_mulhi_i24 node:$src0, node:$src1),538 (AMDGPUmulhi_i24_impl node:$src0, node:$src1)]>;539 540def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),541 [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),542 (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;543 544def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),545 [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),546 (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;547 548def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),549 [(int_amdgcn_fmul_legacy node:$src0, node:$src1),550 (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;551 552def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),553 [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),554 (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;555 556def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),557 [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),558 (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;559 560def AMDGPUperm : PatFrags<(ops node:$src0, node:$src1, node:$src2),561 [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),562 (AMDGPUperm_impl node:$src0, node:$src1, node:$src2)]>;563