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1//===- AMDGPURegBankLegalizeHelper ------------------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGBANKLEGALIZEHELPER_H10#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGBANKLEGALIZEHELPER_H11 12#include "AMDGPURegBankLegalizeRules.h"13#include "llvm/ADT/SmallSet.h"14#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"15#include "llvm/CodeGen/MachineRegisterInfo.h"16 17namespace llvm {18 19class MachineIRBuilder;20 21namespace AMDGPU {22 23// Receives list of RegBankLLTMappingApplyID and applies register banks on all24// operands. It is user's responsibility to provide RegBankLLTMappingApplyIDs25// for all register operands, there is no need to specify NonReg for trailing26// imm operands. This finishes selection of register banks if there is no need27// to replace instruction. In other case InstApplyMethod will create new28// instruction(s).29class RegBankLegalizeHelper {30 const GCNSubtarget &ST;31 MachineIRBuilder &B;32 MachineRegisterInfo &MRI;33 const MachineUniformityInfo &MUI;34 const RegisterBankInfo &RBI;35 const RegBankLegalizeRules &RBLRules;36 const bool IsWave32;37 const RegisterBank *SgprRB;38 const RegisterBank *VgprRB;39 const RegisterBank *VccRB;40 41 static constexpr LLT S1 = LLT::scalar(1);42 static constexpr LLT S16 = LLT::scalar(16);43 static constexpr LLT S32 = LLT::scalar(32);44 static constexpr LLT S64 = LLT::scalar(64);45 static constexpr LLT S96 = LLT::scalar(96);46 static constexpr LLT S128 = LLT::scalar(128);47 static constexpr LLT S256 = LLT::scalar(256);48 49 static constexpr LLT V2S16 = LLT::fixed_vector(2, 16);50 static constexpr LLT V4S16 = LLT::fixed_vector(4, 16);51 static constexpr LLT V6S16 = LLT::fixed_vector(6, 16);52 static constexpr LLT V8S16 = LLT::fixed_vector(8, 16);53 static constexpr LLT V16S16 = LLT::fixed_vector(16, 16);54 static constexpr LLT V32S16 = LLT::fixed_vector(32, 16);55 56 static constexpr LLT V2S32 = LLT::fixed_vector(2, 32);57 static constexpr LLT V3S32 = LLT::fixed_vector(3, 32);58 static constexpr LLT V4S32 = LLT::fixed_vector(4, 32);59 static constexpr LLT V6S32 = LLT::fixed_vector(6, 32);60 static constexpr LLT V7S32 = LLT::fixed_vector(7, 32);61 static constexpr LLT V8S32 = LLT::fixed_vector(8, 32);62 static constexpr LLT V16S32 = LLT::fixed_vector(16, 32);63 64 static constexpr LLT V2S64 = LLT::fixed_vector(2, 64);65 static constexpr LLT V3S64 = LLT::fixed_vector(3, 64);66 static constexpr LLT V4S64 = LLT::fixed_vector(4, 64);67 static constexpr LLT V8S64 = LLT::fixed_vector(8, 64);68 static constexpr LLT V16S64 = LLT::fixed_vector(16, 64);69 70 static constexpr LLT P1 = LLT::pointer(1, 64);71 static constexpr LLT P4 = LLT::pointer(4, 64);72 static constexpr LLT P6 = LLT::pointer(6, 32);73 74 MachineRegisterInfo::VRegAttrs SgprRB_S32 = {SgprRB, S32};75 MachineRegisterInfo::VRegAttrs SgprRB_S16 = {SgprRB, S16};76 MachineRegisterInfo::VRegAttrs VgprRB_S32 = {VgprRB, S32};77 MachineRegisterInfo::VRegAttrs VccRB_S1 = {VccRB, S1};78 79public:80 RegBankLegalizeHelper(MachineIRBuilder &B, const MachineUniformityInfo &MUI,81 const RegisterBankInfo &RBI,82 const RegBankLegalizeRules &RBLRules);83 84 void findRuleAndApplyMapping(MachineInstr &MI);85 86 // Manual apply helpers.87 void applyMappingPHI(MachineInstr &MI);88 void applyMappingTrivial(MachineInstr &MI);89 90private:91 bool executeInWaterfallLoop(MachineIRBuilder &B,92 iterator_range<MachineBasicBlock::iterator> Range,93 SmallSet<Register, 4> &SgprOperandRegs);94 95 LLT getTyFromID(RegBankLLTMappingApplyID ID);96 LLT getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty);97 98 const RegisterBank *getRegBankFromID(RegBankLLTMappingApplyID ID);99 100 void101 applyMappingDst(MachineInstr &MI, unsigned &OpIdx,102 const SmallVectorImpl<RegBankLLTMappingApplyID> &MethodIDs);103 104 void105 applyMappingSrc(MachineInstr &MI, unsigned &OpIdx,106 const SmallVectorImpl<RegBankLLTMappingApplyID> &MethodIDs,107 SmallSet<Register, 4> &SgprWaterfallOperandRegs);108 109 void splitLoad(MachineInstr &MI, ArrayRef<LLT> LLTBreakdown,110 LLT MergeTy = LLT());111 void widenLoad(MachineInstr &MI, LLT WideTy, LLT MergeTy = LLT());112 void widenMMOToS32(GAnyLoad &MI) const;113 114 void lower(MachineInstr &MI, const RegBankLLTMapping &Mapping,115 SmallSet<Register, 4> &SgprWaterfallOperandRegs);116 117 void lowerVccExtToSel(MachineInstr &MI);118 std::pair<Register, Register> unpackZExt(Register Reg);119 std::pair<Register, Register> unpackSExt(Register Reg);120 std::pair<Register, Register> unpackAExt(Register Reg);121 std::pair<Register, Register> unpackAExtTruncS16(Register Reg);122 void lowerUnpackBitShift(MachineInstr &MI);123 void lowerV_BFE(MachineInstr &MI);124 void lowerS_BFE(MachineInstr &MI);125 void lowerSplitTo32(MachineInstr &MI);126 void lowerSplitTo16(MachineInstr &MI);127 void lowerSplitTo32Select(MachineInstr &MI);128 void lowerSplitTo32SExtInReg(MachineInstr &MI);129 void lowerUnpackMinMax(MachineInstr &MI);130 void lowerUnpackAExt(MachineInstr &MI);131};132 133} // end namespace AMDGPU134} // end namespace llvm135 136#endif137