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1//===----------------------------------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H10#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H11 12#include "llvm/CodeGen/SelectionDAGTargetInfo.h"13 14#define GET_SDNODE_ENUM15#include "AMDGPUGenSDNodeInfo.inc"16 17namespace llvm {18namespace AMDGPUISD {19 20enum NodeType : unsigned {21 // Convert a unswizzled wave uniform stack address to an address compatible22 // with a vector offset for use in stack access.23 WAVE_ADDRESS = GENERATED_OPCODE_END,24 25 DOT4,26 MAD_U64_U32,27 MAD_I64_I32,28 TEXTURE_FETCH,29 R600_EXPORT,30 CONST_ADDRESS,31 32 /// This node is for VLIW targets and it is used to represent a vector33 /// that is stored in consecutive registers with the same channel.34 /// For example:35 /// |X |Y|Z|W|36 /// T0|v.x| | | |37 /// T1|v.y| | | |38 /// T2|v.z| | | |39 /// T3|v.w| | | |40 BUILD_VERTICAL_VECTOR,41 42 DUMMY_CHAIN,43};44 45} // namespace AMDGPUISD46 47class AMDGPUSelectionDAGInfo : public SelectionDAGGenTargetInfo {48public:49 AMDGPUSelectionDAGInfo();50 51 ~AMDGPUSelectionDAGInfo() override;52 53 const char *getTargetNodeName(unsigned Opcode) const override;54 55 void verifyTargetNode(const SelectionDAG &DAG,56 const SDNode *N) const override;57};58 59} // namespace llvm60 61#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H62