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1add_llvm_component_group(AMDGPU)2 3set(LLVM_TARGET_DEFINITIONS AMDGPU.td)4 5tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)6tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)7tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)8tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)9tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler10              --specialize-decoders-per-bitwidth11              -ignore-non-decodable-operands12              -ignore-fully-defined-operands)13tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)14tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)15tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)16tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)17tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)18tablegen(LLVM AMDGPUGenSDNodeInfo.inc -gen-sd-node-info)19tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)20tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)21 22set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)23tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)24tablegen(LLVM AMDGPUGenPreLegalizeGICombiner.inc -gen-global-isel-combiner25              -combiners="AMDGPUPreLegalizerCombiner")26tablegen(LLVM AMDGPUGenPostLegalizeGICombiner.inc -gen-global-isel-combiner27              -combiners="AMDGPUPostLegalizerCombiner")28tablegen(LLVM AMDGPUGenRegBankGICombiner.inc -gen-global-isel-combiner29              -combiners="AMDGPURegBankCombiner")30 31set(LLVM_TARGET_DEFINITIONS R600.td)32tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)33tablegen(LLVM R600GenCallingConv.inc -gen-callingconv)34tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel)35tablegen(LLVM R600GenDFAPacketizer.inc -gen-dfa-packetizer)36tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info)37tablegen(LLVM R600GenMCCodeEmitter.inc -gen-emitter)38tablegen(LLVM R600GenRegisterInfo.inc -gen-register-info)39tablegen(LLVM R600GenSubtargetInfo.inc -gen-subtarget)40 41add_public_tablegen_target(AMDGPUCommonTableGen)42 43set(LLVM_TARGET_DEFINITIONS InstCombineTables.td)44tablegen(LLVM InstCombineTables.inc -gen-searchable-tables)45add_public_tablegen_target(InstCombineTableGen)46 47add_llvm_target(AMDGPUCodeGen48  AMDGPUAliasAnalysis.cpp49  AMDGPUAlwaysInlinePass.cpp50  AMDGPUAnnotateUniformValues.cpp51  AMDGPUArgumentUsageInfo.cpp52  AMDGPUAsanInstrumentation.cpp53  AMDGPUAsmPrinter.cpp54  AMDGPUAtomicOptimizer.cpp55  AMDGPUAttributor.cpp56  AMDGPUBarrierLatency.cpp57  AMDGPUCallLowering.cpp58  AMDGPUCodeGenPrepare.cpp59  AMDGPUCombinerHelper.cpp60  AMDGPUCtorDtorLowering.cpp61  AMDGPUExportClustering.cpp62  AMDGPUExportKernelRuntimeHandles.cpp63  AMDGPUFrameLowering.cpp64  AMDGPUGlobalISelDivergenceLowering.cpp65  AMDGPUGlobalISelUtils.cpp66  AMDGPUHSAMetadataStreamer.cpp67  AMDGPUInsertDelayAlu.cpp68  AMDGPUInstCombineIntrinsic.cpp69  AMDGPUUniformIntrinsicCombine.cpp70  AMDGPUInstrInfo.cpp71  AMDGPUInstructionSelector.cpp72  AMDGPUISelDAGToDAG.cpp73  AMDGPUISelLowering.cpp74  AMDGPULateCodeGenPrepare.cpp75  AMDGPULegalizerInfo.cpp76  AMDGPULibCalls.cpp77  AMDGPUImageIntrinsicOptimizer.cpp78  AMDGPULibFunc.cpp79  AMDGPULowerBufferFatPointers.cpp80  AMDGPULowerIntrinsics.cpp81  AMDGPULowerKernelArguments.cpp82  AMDGPULowerKernelAttributes.cpp83  AMDGPULowerModuleLDSPass.cpp84  AMDGPUPrepareAGPRAlloc.cpp85  AMDGPULowerExecSync.cpp86  AMDGPUSwLowerLDS.cpp87  AMDGPUMachineFunction.cpp88  AMDGPUMachineModuleInfo.cpp89  AMDGPUMacroFusion.cpp90  AMDGPUMCInstLower.cpp91  AMDGPUMemoryUtils.cpp92  AMDGPUIGroupLP.cpp93  AMDGPULowerVGPREncoding.cpp94  AMDGPUMCResourceInfo.cpp95  AMDGPUMarkLastScratchLoad.cpp96  AMDGPUMIRFormatter.cpp97  AMDGPUPerfHintAnalysis.cpp98  AMDGPUPostLegalizerCombiner.cpp99  AMDGPUPreLegalizerCombiner.cpp100  AMDGPUPreloadKernArgProlog.cpp101  AMDGPUPreloadKernelArguments.cpp102  AMDGPUPrintfRuntimeBinding.cpp103  AMDGPUPromoteAlloca.cpp104  AMDGPUPromoteKernelArguments.cpp105  AMDGPURegBankCombiner.cpp106  AMDGPURegBankLegalize.cpp107  AMDGPURegBankLegalizeHelper.cpp108  AMDGPURegBankLegalizeRules.cpp109  AMDGPURegBankSelect.cpp110  AMDGPURegisterBankInfo.cpp111  AMDGPURemoveIncompatibleFunctions.cpp112  AMDGPUReserveWWMRegs.cpp113  AMDGPUResourceUsageAnalysis.cpp114  AMDGPURewriteAGPRCopyMFMA.cpp115  AMDGPURewriteOutArguments.cpp116  AMDGPURewriteUndefForPHI.cpp117  AMDGPUSelectionDAGInfo.cpp118  AMDGPUSetWavePriority.cpp119  AMDGPUSplitModule.cpp120  AMDGPUSubtarget.cpp121  AMDGPUTargetMachine.cpp122  AMDGPUTargetObjectFile.cpp123  AMDGPUTargetTransformInfo.cpp124  AMDGPUWaitSGPRHazards.cpp125  AMDGPUUnifyDivergentExitNodes.cpp126  R600MachineCFGStructurizer.cpp127  GCNCreateVOPD.cpp128  GCNDPPCombine.cpp129  GCNHazardRecognizer.cpp130  GCNILPSched.cpp131  GCNIterativeScheduler.cpp132  GCNMinRegStrategy.cpp133  GCNNSAReassign.cpp134  GCNPreRAOptimizations.cpp135  GCNPreRALongBranchReg.cpp136  GCNRegPressure.cpp137  GCNRewritePartialRegUses.cpp138  GCNSchedStrategy.cpp139  GCNSubtarget.cpp140  GCNVOPDUtils.cpp141  R600AsmPrinter.cpp142  R600ClauseMergePass.cpp143  R600ControlFlowFinalizer.cpp144  R600EmitClauseMarkers.cpp145  R600ExpandSpecialInstrs.cpp146  R600FrameLowering.cpp147  R600InstrInfo.cpp148  R600ISelDAGToDAG.cpp149  R600ISelLowering.cpp150  R600MachineFunctionInfo.cpp151  R600MachineScheduler.cpp152  R600MCInstLower.cpp153  R600OpenCLImageTypeLoweringPass.cpp154  R600OptimizeVectorRegisters.cpp155  R600Packetizer.cpp156  R600RegisterInfo.cpp157  R600Subtarget.cpp158  R600TargetMachine.cpp159  R600TargetTransformInfo.cpp160  SIAnnotateControlFlow.cpp161  SIFixSGPRCopies.cpp162  SIFixVGPRCopies.cpp163  SIFoldOperands.cpp164  SIFormMemoryClauses.cpp165  SIFrameLowering.cpp166  SIInsertHardClauses.cpp167  SIInsertWaitcnts.cpp168  SIInstrInfo.cpp169  SIISelLowering.cpp170  SILateBranchLowering.cpp171  SILoadStoreOptimizer.cpp172  SILowerControlFlow.cpp173  SILowerI1Copies.cpp174  SILowerWWMCopies.cpp175  SILowerSGPRSpills.cpp176  SIMachineFunctionInfo.cpp177  SIMachineScheduler.cpp178  SIMemoryLegalizer.cpp179  SIModeRegister.cpp180  SIModeRegisterDefaults.cpp181  SIOptimizeExecMasking.cpp182  SIOptimizeExecMaskingPreRA.cpp183  SIOptimizeVGPRLiveRange.cpp184  SIPeepholeSDWA.cpp185  SIPostRABundler.cpp186  SIPreAllocateWWMRegs.cpp187  SIPreEmitPeephole.cpp188  SIProgramInfo.cpp189  SIRegisterInfo.cpp190  SIShrinkInstructions.cpp191  SIWholeQuadMode.cpp192 193  LINK_COMPONENTS194  AMDGPUDesc195  AMDGPUInfo196  AMDGPUUtils197  Analysis198  AsmPrinter199  BinaryFormat200  CodeGen201  CodeGenTypes202  Core203  GlobalISel204  HipStdPar205  IPO206  IRPrinter207  Instrumentation208  MC209  MIRParser210  ObjCARC211  Passes212  Scalar213  SelectionDAG214  Support215  Target216  TargetParser217  TransformUtils218  Vectorize219 220  ADD_TO_COMPONENT221  AMDGPU222  )223 224add_subdirectory(AsmParser)225add_subdirectory(Disassembler)226add_subdirectory(MCA)227add_subdirectory(MCTargetDesc)228add_subdirectory(TargetInfo)229add_subdirectory(Utils)230