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1//===-- CaymanInstructions.td - CM Instruction defs -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// TableGen definitions for instructions which are available only on Cayman10// family GPUs.11//12//===----------------------------------------------------------------------===//13 14def isCayman : Predicate<"Subtarget->hasCaymanISA()">;15 16//===----------------------------------------------------------------------===//17// Cayman Instructions18//===----------------------------------------------------------------------===//19 20let SubtargetPredicate = isCayman in {21 22def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24",23 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU24>;25def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",26 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU27>;28 29def : IMad24Pat<MULADD_INT24_cm>;30 31let isVector = 1 in {32 33def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;34 35def MULLO_INT_cm : MULLO_INT_Common<0x8F>;36def MULHI_INT_cm : MULHI_INT_Common<0x90>;37def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;38def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;39def MULHI_INT_cm24 : MULHI_INT24_Common<0x5c>;40def MULHI_UINT_cm24 : MULHI_UINT24_Common<0xb2>;41 42def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;43def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;44def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;45def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;46def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;47def SIN_cm : SIN_Common<0x8D>;48def COS_cm : COS_Common<0x8E>;49} // End isVector = 150 51def : SqrtPat<RECIPSQRT_IEEE_cm, RECIP_IEEE_cm>;52 53def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;54 55defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;56 57// RECIP_UINT emulation for Cayman58// The multiplication scales from [0,1) to the unsigned integer range,59// rounding down a bit to avoid unwanted overflow.60def : R600Pat <61 (AMDGPUurecip i32:$src0),62 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),63 (MOV_IMM_I32 CONST.FP_4294966784)))64>;65 66def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {67 let ADDR = 0;68 let POP_COUNT = 0;69 let COUNT = 0;70 }71 72 73 74class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> :75 CF_MEM_RAT_CACHELESS <0x14, 0, mask,76 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr),77 "STORE_DWORD $rw_gpr, $index_gpr",78 [(store_global vt:$rw_gpr, i32:$index_gpr)]> {79 let eop = 0; // This bit is not used on Cayman.80}81 82def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>;83def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>;84def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>;85 86def RAT_STORE_TYPED_cm: CF_MEM_RAT_STORE_TYPED<0> {87 let eop = 0; // This bit is not used on Cayman.88}89 90class VTX_READ_cm <string name, dag outs>91 : VTX_WORD0_cm, VTX_READ<name, outs, []> {92 93 // Static fields94 let VC_INST = 0;95 let FETCH_TYPE = 2;96 let FETCH_WHOLE_QUAD = 0;97 let SRC_REL = 0;98 // XXX: We can infer this field based on the SRC_GPR. This would allow us99 // to store vertex addresses in any channel, not just X.100 let SRC_SEL_X = 0;101 let SRC_SEL_Y = 0;102 let STRUCTURED_READ = 0;103 let LDS_REQ = 0;104 let COALESCED_READ = 0;105 106 let Inst{31-0} = Word0;107}108 109def VTX_READ_8_cm110 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr",111 (outs R600_TReg32_X:$dst_gpr)> {112 113 let DST_SEL_X = 0;114 let DST_SEL_Y = 7; // Masked115 let DST_SEL_Z = 7; // Masked116 let DST_SEL_W = 7; // Masked117 let DATA_FORMAT = 1; // FMT_8118}119 120def VTX_READ_16_cm121 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr",122 (outs R600_TReg32_X:$dst_gpr)> {123 let DST_SEL_X = 0;124 let DST_SEL_Y = 7; // Masked125 let DST_SEL_Z = 7; // Masked126 let DST_SEL_W = 7; // Masked127 let DATA_FORMAT = 5; // FMT_16128 129}130 131def VTX_READ_32_cm132 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr",133 (outs R600_TReg32_X:$dst_gpr)> {134 135 let DST_SEL_X = 0;136 let DST_SEL_Y = 7; // Masked137 let DST_SEL_Z = 7; // Masked138 let DST_SEL_W = 7; // Masked139 let DATA_FORMAT = 0xD; // COLOR_32140 141 // This is not really necessary, but there were some GPU hangs that appeared142 // to be caused by ALU instructions in the next instruction group that wrote143 // to the $src_gpr registers of the VTX_READ.144 // e.g.145 // %t3_x = VTX_READ_PARAM_32_eg killed %t2_x, 24146 // %t2_x = MOV %zero147 //Adding this constraint prevents this from happening.148 let Constraints = "$src_gpr.ptr = $dst_gpr";149}150 151def VTX_READ_64_cm152 : VTX_READ_cm <"VTX_READ_64 $dst_gpr.XY, $src_gpr",153 (outs R600_Reg64:$dst_gpr)> {154 155 let DST_SEL_X = 0;156 let DST_SEL_Y = 1;157 let DST_SEL_Z = 7;158 let DST_SEL_W = 7;159 let DATA_FORMAT = 0x1D; // COLOR_32_32160}161 162def VTX_READ_128_cm163 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr",164 (outs R600_Reg128:$dst_gpr)> {165 166 let DST_SEL_X = 0;167 let DST_SEL_Y = 1;168 let DST_SEL_Z = 2;169 let DST_SEL_W = 3;170 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32171 172 // XXX: Need to force VTX_READ_128 instructions to write to the same register173 // that holds its buffer address to avoid potential hangs. We can't use174 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst175 // registers are different sizes.176}177 178//===----------------------------------------------------------------------===//179// VTX Read from parameter memory space180//===----------------------------------------------------------------------===//181def : R600Pat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)),182 (VTX_READ_8_cm MEMxi:$src_gpr, 3)>;183def : R600Pat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)),184 (VTX_READ_16_cm MEMxi:$src_gpr, 3)>;185def : R600Pat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),186 (VTX_READ_32_cm MEMxi:$src_gpr, 3)>;187def : R600Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),188 (VTX_READ_64_cm MEMxi:$src_gpr, 3)>;189def : R600Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),190 (VTX_READ_128_cm MEMxi:$src_gpr, 3)>;191 192//===----------------------------------------------------------------------===//193// VTX Read from constant memory space194//===----------------------------------------------------------------------===//195def : R600Pat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)),196 (VTX_READ_8_cm MEMxi:$src_gpr, 2)>;197def : R600Pat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)),198 (VTX_READ_16_cm MEMxi:$src_gpr, 2)>;199def : R600Pat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),200 (VTX_READ_32_cm MEMxi:$src_gpr, 2)>;201def : R600Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),202 (VTX_READ_64_cm MEMxi:$src_gpr, 2)>;203def : R600Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),204 (VTX_READ_128_cm MEMxi:$src_gpr, 2)>;205 206//===----------------------------------------------------------------------===//207// VTX Read from global memory space208//===----------------------------------------------------------------------===//209def : R600Pat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)),210 (VTX_READ_8_cm MEMxi:$src_gpr, 1)>;211def : R600Pat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)),212 (VTX_READ_16_cm MEMxi:$src_gpr, 1)>;213def : R600Pat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),214 (VTX_READ_32_cm MEMxi:$src_gpr, 1)>;215def : R600Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),216 (VTX_READ_64_cm MEMxi:$src_gpr, 1)>;217def : R600Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),218 (VTX_READ_128_cm MEMxi:$src_gpr, 1)>;219 220} // End let SubtargetPredicate = isCayman221