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1//===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// TableGen definitions for instructions which are:10// - Available to Evergreen and newer VLIW4/VLIW5 GPUs11// - Available only on Evergreen family GPUs.12//13//===----------------------------------------------------------------------===//14 15def isEG : Predicate<16 "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && "17 "!Subtarget->hasCaymanISA()"18>;19 20def isEGorCayman : Predicate<21 "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||"22 "Subtarget->getGeneration() == AMDGPUSubtarget::NORTHERN_ISLANDS"23>;24 25class EGPat<dag pattern, dag result> : AMDGPUPat<pattern, result> {26 let SubtargetPredicate = isEG;27}28 29class EGOrCaymanPat<dag pattern, dag result> : AMDGPUPat<pattern, result> {30 let SubtargetPredicate = isEGorCayman;31}32 33def IMMZeroBasedBitfieldMask : ImmLeaf <i32, [{34 return isMask_32(Imm);35}]>;36 37def IMMPopCount : SDNodeXForm<imm, [{38 return CurDAG->getTargetConstant(llvm::popcount(N->getZExtValue()), SDLoc(N),39 MVT::i32);40}]>;41 42//===----------------------------------------------------------------------===//43// Evergreen / Cayman store instructions44//===----------------------------------------------------------------------===//45 46let SubtargetPredicate = isEGorCayman in {47 48class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,49 string name, list<dag> pattern>50 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,51 "MEM_RAT_CACHELESS "#name, pattern>;52 53class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins,54 dag outs, string name, list<dag> pattern>55 : EG_CF_RAT <0x56, rat_inst, rat_id, mask, outs, ins,56 "MEM_RAT "#name, pattern>;57 58class CF_MEM_RAT_STORE_TYPED<bits<1> has_eop>59 : CF_MEM_RAT <0x1, ?, 0xf, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr,60 i32imm:$rat_id, InstFlag:$eop), (outs),61 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr"62 #!if(has_eop, ", $eop", ""),63 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr,64 R600_Reg128:$index_gpr,65 (i32 imm:$rat_id))]>;66 67def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 0xf,68 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), (outs),69 "MSKOR $rw_gpr.XW, $index_gpr",70 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]71> {72 let eop = 0;73}74 75 76multiclass RAT_ATOMIC<bits<6> op_ret, bits<6> op_noret, string name> {77 let Constraints = "$rw_gpr = $out_gpr", eop = 0, mayStore = 1 in {78 def _RTN: CF_MEM_RAT <op_ret, 0, 0xf,79 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),80 (outs R600_Reg128:$out_gpr),81 name # "_RTN $rw_gpr, $index_gpr", [] >;82 def _NORET: CF_MEM_RAT <op_noret, 0, 0xf,83 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),84 (outs R600_Reg128:$out_gpr),85 name # " $rw_gpr, $index_gpr", [] >;86 }87}88 89// Swap no-ret is just store. Raw store to cached target90// can only store on dword, which exactly matches swap_no_ret.91defm RAT_ATOMIC_XCHG_INT : RAT_ATOMIC<1, 34, "ATOMIC_XCHG_INT">;92defm RAT_ATOMIC_CMPXCHG_INT : RAT_ATOMIC<4, 36, "ATOMIC_CMPXCHG_INT">;93defm RAT_ATOMIC_ADD : RAT_ATOMIC<7, 39, "ATOMIC_ADD">;94defm RAT_ATOMIC_SUB : RAT_ATOMIC<8, 40, "ATOMIC_SUB">;95defm RAT_ATOMIC_RSUB : RAT_ATOMIC<9, 41, "ATOMIC_RSUB">;96defm RAT_ATOMIC_MIN_INT : RAT_ATOMIC<10, 42, "ATOMIC_MIN_INT">;97defm RAT_ATOMIC_MIN_UINT : RAT_ATOMIC<11, 43, "ATOMIC_MIN_UINT">;98defm RAT_ATOMIC_MAX_INT : RAT_ATOMIC<12, 44, "ATOMIC_MAX_INT">;99defm RAT_ATOMIC_MAX_UINT : RAT_ATOMIC<13, 45, "ATOMIC_MAX_UINT">;100defm RAT_ATOMIC_AND : RAT_ATOMIC<14, 46, "ATOMIC_AND">;101defm RAT_ATOMIC_OR : RAT_ATOMIC<15, 47, "ATOMIC_OR">;102defm RAT_ATOMIC_XOR : RAT_ATOMIC<16, 48, "ATOMIC_XOR">;103defm RAT_ATOMIC_INC_UINT : RAT_ATOMIC<18, 50, "ATOMIC_INC_UINT">;104defm RAT_ATOMIC_DEC_UINT : RAT_ATOMIC<19, 51, "ATOMIC_DEC_UINT">;105 106} // End SubtargetPredicate = isEGorCayman107 108//===----------------------------------------------------------------------===//109// Evergreen Only instructions110//===----------------------------------------------------------------------===//111 112let SubtargetPredicate = isEG in {113 114def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;115defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;116 117def MULLO_INT_eg : MULLO_INT_Common<0x8F>;118def MULHI_INT_eg : MULHI_INT_Common<0x90>;119def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;120def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;121def MULHI_UINT24_eg : MULHI_UINT24_Common<0xb2>;122 123def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;124def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;125def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;126def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;127def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;128def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;129def : SqrtPat<RECIPSQRT_IEEE_eg, RECIP_IEEE_eg>;130 131def SIN_eg : SIN_Common<0x8D>;132def COS_eg : COS_Common<0x8E>;133 134def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;135} // End SubtargetPredicate = isEG136 137//===----------------------------------------------------------------------===//138// Memory read/write instructions139//===----------------------------------------------------------------------===//140 141let usesCustomInserter = 1 in {142 143// 32-bit store144def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1,145 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),146 "STORE_RAW $rw_gpr, $index_gpr, $eop",147 [(store_global i32:$rw_gpr, i32:$index_gpr)]148>;149 150// 64-bit store151def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3,152 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),153 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop",154 [(store_global v2i32:$rw_gpr, i32:$index_gpr)]155>;156 157//128-bit store158def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf,159 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),160 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop",161 [(store_global v4i32:$rw_gpr, i32:$index_gpr)]162>;163 164def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>;165 166} // End usesCustomInserter = 1167 168class VTX_READ_eg <string name, dag outs>169 : VTX_WORD0_eg, VTX_READ<name, outs, []> {170 171 // Static fields172 let VC_INST = 0;173 let FETCH_TYPE = 2;174 let FETCH_WHOLE_QUAD = 0;175 let SRC_REL = 0;176 // XXX: We can infer this field based on the SRC_GPR. This would allow us177 // to store vertex addresses in any channel, not just X.178 let SRC_SEL_X = 0;179 180 let Inst{31-0} = Word0;181}182 183def VTX_READ_8_eg184 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr",185 (outs R600_TReg32_X:$dst_gpr)> {186 187 let MEGA_FETCH_COUNT = 1;188 let DST_SEL_X = 0;189 let DST_SEL_Y = 7; // Masked190 let DST_SEL_Z = 7; // Masked191 let DST_SEL_W = 7; // Masked192 let DATA_FORMAT = 1; // FMT_8193}194 195def VTX_READ_16_eg196 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr",197 (outs R600_TReg32_X:$dst_gpr)> {198 let MEGA_FETCH_COUNT = 2;199 let DST_SEL_X = 0;200 let DST_SEL_Y = 7; // Masked201 let DST_SEL_Z = 7; // Masked202 let DST_SEL_W = 7; // Masked203 let DATA_FORMAT = 5; // FMT_16204 205}206 207def VTX_READ_32_eg208 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr",209 (outs R600_TReg32_X:$dst_gpr)> {210 211 let MEGA_FETCH_COUNT = 4;212 let DST_SEL_X = 0;213 let DST_SEL_Y = 7; // Masked214 let DST_SEL_Z = 7; // Masked215 let DST_SEL_W = 7; // Masked216 let DATA_FORMAT = 0xD; // COLOR_32217 218 // This is not really necessary, but there were some GPU hangs that appeared219 // to be caused by ALU instructions in the next instruction group that wrote220 // to the $src_gpr registers of the VTX_READ.221 // e.g.222 // %t3_x = VTX_READ_PARAM_32_eg killed %t2_x, 24223 // %t2_x = MOV %zero224 //Adding this constraint prevents this from happening.225 let Constraints = "$src_gpr.ptr = $dst_gpr";226}227 228def VTX_READ_64_eg229 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr",230 (outs R600_Reg64:$dst_gpr)> {231 232 let MEGA_FETCH_COUNT = 8;233 let DST_SEL_X = 0;234 let DST_SEL_Y = 1;235 let DST_SEL_Z = 7;236 let DST_SEL_W = 7;237 let DATA_FORMAT = 0x1D; // COLOR_32_32238}239 240def VTX_READ_128_eg241 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr",242 (outs R600_Reg128:$dst_gpr)> {243 244 let MEGA_FETCH_COUNT = 16;245 let DST_SEL_X = 0;246 let DST_SEL_Y = 1;247 let DST_SEL_Z = 2;248 let DST_SEL_W = 3;249 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32250 251 // XXX: Need to force VTX_READ_128 instructions to write to the same register252 // that holds its buffer address to avoid potential hangs. We can't use253 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst254 // registers are different sizes.255}256 257//===----------------------------------------------------------------------===//258// VTX Read from parameter memory space259//===----------------------------------------------------------------------===//260def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)),261 (VTX_READ_8_eg MEMxi:$src_gpr, 3)>;262def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)),263 (VTX_READ_16_eg MEMxi:$src_gpr, 3)>;264def : EGPat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),265 (VTX_READ_32_eg MEMxi:$src_gpr, 3)>;266def : EGPat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),267 (VTX_READ_64_eg MEMxi:$src_gpr, 3)>;268def : EGPat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),269 (VTX_READ_128_eg MEMxi:$src_gpr, 3)>;270 271//===----------------------------------------------------------------------===//272// VTX Read from constant memory space273//===----------------------------------------------------------------------===//274def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)),275 (VTX_READ_8_eg MEMxi:$src_gpr, 2)>;276def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)),277 (VTX_READ_16_eg MEMxi:$src_gpr, 2)>;278def : EGPat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),279 (VTX_READ_32_eg MEMxi:$src_gpr, 2)>;280def : EGPat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),281 (VTX_READ_64_eg MEMxi:$src_gpr, 2)>;282def : EGPat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),283 (VTX_READ_128_eg MEMxi:$src_gpr, 2)>;284 285//===----------------------------------------------------------------------===//286// VTX Read from global memory space287//===----------------------------------------------------------------------===//288def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)),289 (VTX_READ_8_eg MEMxi:$src_gpr, 1)>;290def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)),291 (VTX_READ_16_eg MEMxi:$src_gpr, 1)>;292def : EGPat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),293 (VTX_READ_32_eg MEMxi:$src_gpr, 1)>;294def : EGPat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),295 (VTX_READ_64_eg MEMxi:$src_gpr, 1)>;296def : EGPat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),297 (VTX_READ_128_eg MEMxi:$src_gpr, 1)>;298 299//===----------------------------------------------------------------------===//300// Evergreen / Cayman Instructions301//===----------------------------------------------------------------------===//302 303let SubtargetPredicate = isEGorCayman in {304 305multiclass AtomicPat<Instruction inst_noret,306 SDPatternOperator node_noret> {307 // FIXME: Add _RTN version. We need per WI scratch location to store the old value308 // EXTRACT_SUBREG here is dummy, we know the node has no uses309 def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, i32:$data)),310 (EXTRACT_SUBREG (inst_noret311 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>;312}313 314// CMPSWAP is pattern is special315// EXTRACT_SUBREG here is dummy, we know the node has no uses316// FIXME: Add _RTN version. We need per WI scratch location to store the old value317def : EGOrCaymanPat<(i32 (atomic_cmp_swap_global_noret i32:$ptr, i32:$cmp, i32:$data)),318 (EXTRACT_SUBREG (RAT_ATOMIC_CMPXCHG_INT_NORET319 (INSERT_SUBREG320 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $cmp, sub3),321 $data, sub0),322 $ptr), sub1)>;323 324defm AtomicSwapPat : AtomicPat <RAT_ATOMIC_XCHG_INT_NORET,325 atomic_swap_global_noret_i32>;326defm AtomicAddPat : AtomicPat <RAT_ATOMIC_ADD_NORET,327 atomic_load_add_global_noret_i32>;328defm AtomicSubPat : AtomicPat <RAT_ATOMIC_SUB_NORET,329 atomic_load_sub_global_noret_i32>;330defm AtomicMinPat : AtomicPat <RAT_ATOMIC_MIN_INT_NORET,331 atomic_load_min_global_noret_i32>;332defm AtomicUMinPat : AtomicPat <RAT_ATOMIC_MIN_UINT_NORET,333 atomic_load_umin_global_noret_i32>;334defm AtomicMaxPat : AtomicPat <RAT_ATOMIC_MAX_INT_NORET,335 atomic_load_max_global_noret_i32>;336defm AtomicUMaxPat : AtomicPat <RAT_ATOMIC_MAX_UINT_NORET,337 atomic_load_umax_global_noret_i32>;338defm AtomicAndPat : AtomicPat <RAT_ATOMIC_AND_NORET,339 atomic_load_and_global_noret_i32>;340defm AtomicOrPat : AtomicPat <RAT_ATOMIC_OR_NORET,341 atomic_load_or_global_noret_i32>;342defm AtomicXorPat : AtomicPat <RAT_ATOMIC_XOR_NORET,343 atomic_load_xor_global_noret_i32>;344 345// Should be predicated on FeatureFP64346// def FMA_64 : R600_3OP <347// 0xA, "FMA_64",348// [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]349// >;350 351// BFE_UINT - bit_extract, an optimization for mask and shift352// Src0 = Input353// Src1 = Offset354// Src2 = Width355//356// bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)357//358// Example Usage:359// (Offset, Width)360//361// (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0362// (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8363// (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16364// (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24365def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",366 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],367 VecALU368>;369 370def BFE_INT_eg : R600_3OP <0x5, "BFE_INT",371 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],372 VecALU373>;374 375// Bitfield extract patterns376 377def : AMDGPUPat <378 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask),379 (BFE_UINT_eg $src, $rshift, (MOV_IMM_I32 (i32 (IMMPopCount $mask))))380>;381 382// x & ((1 << y) - 1)383def : AMDGPUPat <384 (and i32:$src, (add_oneuse (shl_oneuse 1, i32:$width), -1)),385 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width)386>;387 388// x & ~(-1 << y)389def : AMDGPUPat <390 (and i32:$src, (xor_oneuse (shl_oneuse -1, i32:$width), -1)),391 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width)392>;393 394// x & (-1 >> (bitwidth - y))395def : AMDGPUPat <396 (and i32:$src, (srl_oneuse -1, (sub 32, i32:$width))),397 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width)398>;399 400// x << (bitwidth - y) >> (bitwidth - y)401def : AMDGPUPat <402 (srl (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),403 (BFE_UINT_eg $src, (MOV_IMM_I32 (i32 0)), $width)404>;405 406def : AMDGPUPat <407 (sra (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),408 (BFE_INT_eg $src, (MOV_IMM_I32 (i32 0)), $width)409>;410 411def BFI_INT_eg : R600_3OP <0x06, "BFI_INT",412 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],413 VecALU414>;415 416def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i1)),417 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>;418def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i8)),419 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>;420def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i16)),421 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>;422 423// BFI patterns424 425// Definition from ISA doc:426// (y & x) | (z & ~x)427def : AMDGPUPat <428 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),429 (BFI_INT_eg $x, $y, $z)430>;431 432// 64-bit version433def : AMDGPUPat <434 (or (and i64:$y, i64:$x), (and i64:$z, (not i64:$x))),435 (REG_SEQUENCE R600_Reg64,436 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)),437 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0)),438 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0))), sub0,439 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)),440 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)),441 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1)442>;443 444// SHA-256 Ch function445// z ^ (x & (y ^ z))446def : AMDGPUPat <447 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),448 (BFI_INT_eg $x, $y, $z)449>;450 451// 64-bit version452def : AMDGPUPat <453 (xor i64:$z, (and i64:$x, (xor i64:$y, i64:$z))),454 (REG_SEQUENCE R600_Reg64,455 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)),456 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0)),457 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0))), sub0,458 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)),459 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)),460 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1)461>;462 463def : AMDGPUPat <464 (fcopysign f32:$src0, f32:$src1),465 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0, $src1)466>;467 468def : AMDGPUPat <469 (fcopysign f32:$src0, f64:$src1),470 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0,471 (i32 (EXTRACT_SUBREG R600_Reg64:$src1, sub1)))472>;473 474def : AMDGPUPat <475 (fcopysign f64:$src0, f64:$src1),476 (REG_SEQUENCE R600_Reg64,477 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,478 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)),479 (i32 (EXTRACT_SUBREG R600_Reg64:$src0, sub1)),480 (i32 (EXTRACT_SUBREG R600_Reg64:$src1, sub1))), sub1)481>;482 483def : AMDGPUPat <484 (fcopysign f64:$src0, f32:$src1),485 (REG_SEQUENCE R600_Reg64,486 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,487 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)),488 (i32 (EXTRACT_SUBREG R600_Reg64:$src0, sub1)),489 $src1), sub1)490>;491 492def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT",493 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],494 VecALU495>;496 497def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",498 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU499>;500 501def : UMad24Pat<MULADD_UINT24_eg>;502 503def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;504def : AMDGPUPat <505 (fshr i32:$src0, i32:$src1, i32:$src2),506 (BIT_ALIGN_INT_eg $src0, $src1, $src2)507>;508def : ROTRPattern <BIT_ALIGN_INT_eg>;509def MULADD_eg : MULADD_Common<0x14>;510def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;511def FMA_eg : FMA_Common<0x7>;512def ASHR_eg : ASHR_Common<0x15>;513def LSHR_eg : LSHR_Common<0x16>;514def LSHL_eg : LSHL_Common<0x17>;515def CNDE_eg : CNDE_Common<0x19>;516def CNDGT_eg : CNDGT_Common<0x1A>;517def CNDGE_eg : CNDGE_Common<0x1B>;518def MUL_LIT_eg : MUL_LIT_Common<0x1F>;519def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;520def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",521 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU522>;523def DOT4_eg : DOT4_Common<0xBE>;524defm CUBE_eg : CUBE_Common<0xC0>;525 526 527def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>;528def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>;529 530def FLT32_TO_FLT16 : R600_1OP_Helper <0xA2, "FLT32_TO_FLT16", AMDGPUfp_to_f16, VecALU>;531def FLT16_TO_FLT32 : R600_1OP_Helper <0xA3, "FLT16_TO_FLT32", f16_to_fp, VecALU>;532def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>;533def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>;534def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", AMDGPUffbl_b32, VecALU>;535 536let hasSideEffects = 1 in {537 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;538}539 540def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {541 let Pattern = [];542 let Itinerary = AnyALU;543}544 545def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;546 547def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {548 let Pattern = [];549}550 551def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;552 553def GROUP_BARRIER : InstR600 <554 (outs), (ins), " GROUP_BARRIER", [(int_r600_group_barrier)], AnyALU>,555 R600ALU_Word0,556 R600ALU_Word1_OP2 <0x54> {557 558 let dst = 0;559 let dst_rel = 0;560 let src0 = 0;561 let src0_rel = 0;562 let src0_neg = 0;563 let src0_abs = 0;564 let src1 = 0;565 let src1_rel = 0;566 let src1_neg = 0;567 let src1_abs = 0;568 let write = 0;569 let omod = 0;570 let clamp = 0;571 let last = 1;572 let bank_swizzle = 0;573 let pred_sel = 0;574 let update_exec_mask = 0;575 let update_pred = 0;576 577 let Inst{31-0} = Word0;578 let Inst{63-32} = Word1;579 580 let ALUInst = 1;581}582 583//===----------------------------------------------------------------------===//584// LDS Instructions585//===----------------------------------------------------------------------===//586class R600_LDS <bits<6> op, dag outs, dag ins, string asm,587 list<dag> pattern = []> :588 589 InstR600 <outs, ins, asm, pattern, XALU>,590 R600_ALU_LDS_Word0,591 R600LDS_Word1 {592 593 bits<6> offset = 0;594 let lds_op = op;595 596 let Word1{27} = offset{0};597 let Word1{12} = offset{1};598 let Word1{28} = offset{2};599 let Word1{31} = offset{3};600 let Word0{12} = offset{4};601 let Word0{25} = offset{5};602 603 604 let Inst{31-0} = Word0;605 let Inst{63-32} = Word1;606 607 let ALUInst = 1;608 let HasNativeOperands = 1;609 let UseNamedOperandTable = 1;610}611 612class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <613 lds_op,614 (outs R600_Reg32:$dst),615 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,616 LAST:$last, R600_Pred:$pred_sel,617 BANK_SWIZZLE:$bank_swizzle),618 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",619 pattern620 > {621 622 let src1 = 0;623 let src1_rel = 0;624 let src2 = 0;625 let src2_rel = 0;626 627 let usesCustomInserter = 1;628 let LDS_1A = 1;629}630 631class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,632 string dst =""> :633 R600_LDS <634 lds_op, outs,635 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,636 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,637 LAST:$last, R600_Pred:$pred_sel,638 BANK_SWIZZLE:$bank_swizzle),639 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel",640 pattern641 > {642 643 field string BaseOp;644 645 let src2 = 0;646 let src2_rel = 0;647 let LDS_1A1D = 1;648}649 650class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :651 R600_LDS_1A1D <lds_op, (outs), name, pattern> {652 let BaseOp = name;653}654 655class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :656 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name#"_RET", pattern, "OQAP, "> {657 658 let BaseOp = name;659 let usesCustomInserter = 1;660}661 662class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern,663 string dst =""> :664 R600_LDS <665 lds_op, outs,666 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,667 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,668 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,669 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),670 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",671 pattern> {672 673 field string BaseOp;674 675 let LDS_1A1D = 0;676 let LDS_1A2D = 1;677}678 679class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> :680 R600_LDS_1A2D <lds_op, (outs), name, pattern> {681 let BaseOp = name;682}683 684class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> :685 R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> {686 687 let BaseOp = name;688 let usesCustomInserter = 1;689}690 691def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;692def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >;693def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >;694def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >;695def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >;696def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >;697def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >;698def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >;699def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >;700def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >;701def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >;702def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE",703 [(store_local (i32 R600_Reg32:$src1), R600_Reg32:$src0)]704>;705def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE",706 [(truncstorei8_local i32:$src1, i32:$src0)]707>;708def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE",709 [(truncstorei16_local i32:$src1, i32:$src0)]710>;711def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD",712 [(set i32:$dst, (atomic_load_add_local_i32 i32:$src0, i32:$src1))]713>;714def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB",715 [(set i32:$dst, (atomic_load_sub_local_i32 i32:$src0, i32:$src1))]716>;717def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND",718 [(set i32:$dst, (atomic_load_and_local_i32 i32:$src0, i32:$src1))]719>;720def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR",721 [(set i32:$dst, (atomic_load_or_local_i32 i32:$src0, i32:$src1))]722>;723def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR",724 [(set i32:$dst, (atomic_load_xor_local_i32 i32:$src0, i32:$src1))]725>;726def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT",727 [(set i32:$dst, (atomic_load_min_local_i32 i32:$src0, i32:$src1))]728>;729def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT",730 [(set i32:$dst, (atomic_load_max_local_i32 i32:$src0, i32:$src1))]731>;732def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT",733 [(set i32:$dst, (atomic_load_umin_local_i32 i32:$src0, i32:$src1))]734>;735def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT",736 [(set i32:$dst, (atomic_load_umax_local_i32 i32:$src0, i32:$src1))]737>;738def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG",739 [(set i32:$dst, (atomic_swap_local_i32 i32:$src0, i32:$src1))]740>;741def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST",742 [(set i32:$dst, (atomic_cmp_swap_local_i32 i32:$src0, i32:$src1, i32:$src2))]743>;744def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",745 [(set (i32 R600_Reg32:$dst), (load_local R600_Reg32:$src0))]746>;747def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET",748 [(set i32:$dst, (sextloadi8_local i32:$src0))]749>;750def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET",751 [(set i32:$dst, (az_extloadi8_local i32:$src0))]752>;753def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET",754 [(set i32:$dst, (sextloadi16_local i32:$src0))]755>;756def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET",757 [(set i32:$dst, (az_extloadi16_local i32:$src0))]758>;759 760// TRUNC is used for the FLT_TO_INT instructions to work around a761// perceived problem where the rounding modes are applied differently762// depending on the instruction and the slot they are in.763// See:764// https://bugs.freedesktop.org/show_bug.cgi?id=50232765// Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c766//767// XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,768// which do not need to be truncated since the fp values are 0.0f or 1.0f.769// We should look into handling these cases separately.770def : EGOrCaymanPat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;771 772def : EGOrCaymanPat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;773 774// SHA-256 Ma patterns775 776// ((x & z) | (y & (x | z))) -> BFI (XOR x, y), z, y777def : AMDGPUPat <778 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),779 (BFI_INT_eg (XOR_INT i32:$x, i32:$y), i32:$z, i32:$y)780>;781 782def : AMDGPUPat <783 (or (and i64:$x, i64:$z), (and i64:$y, (or i64:$x, i64:$z))),784 (REG_SEQUENCE R600_Reg64,785 (BFI_INT_eg (XOR_INT (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)),786 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0))),787 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0)),788 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0))), sub0,789 (BFI_INT_eg (XOR_INT (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)),790 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1))),791 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1)),792 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1))), sub1)793>;794 795def EG_ExportSwz : ExportSwzInst {796 let Word1{19-16} = 0; // BURST_COUNT797 let Word1{20} = 0; // VALID_PIXEL_MODE798 let Word1{21} = eop;799 let Word1{29-22} = inst;800 let Word1{30} = 0; // MARK801 let Word1{31} = 1; // BARRIER802}803defm : ExportPattern<EG_ExportSwz, 83>;804 805def EG_ExportBuf : ExportBufInst {806 let Word1{19-16} = 0; // BURST_COUNT807 let Word1{20} = 0; // VALID_PIXEL_MODE808 let Word1{21} = eop;809 let Word1{29-22} = inst;810 let Word1{30} = 0; // MARK811 let Word1{31} = 1; // BARRIER812}813defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;814 815def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),816 "TEX $COUNT @$ADDR"> {817 let POP_COUNT = 0;818}819def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),820 "VTX $COUNT @$ADDR"> {821 let POP_COUNT = 0;822}823def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),824 "LOOP_START_DX10 @$ADDR"> {825 let POP_COUNT = 0;826 let COUNT = 0;827}828def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {829 let POP_COUNT = 0;830 let COUNT = 0;831}832def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),833 "LOOP_BREAK @$ADDR"> {834 let POP_COUNT = 0;835 let COUNT = 0;836}837def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),838 "CONTINUE @$ADDR"> {839 let POP_COUNT = 0;840 let COUNT = 0;841}842def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),843 "JUMP @$ADDR POP:$POP_COUNT"> {844 let COUNT = 0;845}846def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT),847 "PUSH @$ADDR POP:$POP_COUNT"> {848 let COUNT = 0;849}850def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),851 "ELSE @$ADDR POP:$POP_COUNT"> {852 let COUNT = 0;853}854def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {855 let ADDR = 0;856 let COUNT = 0;857 let POP_COUNT = 0;858}859def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),860 "POP @$ADDR POP:$POP_COUNT"> {861 let COUNT = 0;862}863def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {864 let COUNT = 0;865 let POP_COUNT = 0;866 let ADDR = 0;867 let END_OF_PROGRAM = 1;868}869 870} // End Predicates = [isEGorCayman]871