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1//===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9/// \file10/// Provides AMDGPU specific target descriptions.11//12//===----------------------------------------------------------------------===//13//14 15#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H16#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H17 18#include "llvm/MC/MCInstrAnalysis.h"19#include <cstdint>20#include <memory>21 22namespace llvm {23class Target;24class MCAsmBackend;25class MCCodeEmitter;26class MCContext;27class MCInstrInfo;28class MCObjectTargetWriter;29class MCRegisterInfo;30class MCSubtargetInfo;31class MCTargetOptions;32 33enum AMDGPUDwarfFlavour : unsigned { Wave64 = 0, Wave32 = 1 };34 35MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour);36 37MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,38 MCContext &Ctx);39 40MCAsmBackend *createAMDGPUAsmBackend(const Target &T,41 const MCSubtargetInfo &STI,42 const MCRegisterInfo &MRI,43 const MCTargetOptions &Options);44 45std::unique_ptr<MCObjectTargetWriter>46createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,47 bool HasRelocationAddend);48 49namespace AMDGPU {50class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {51private:52 unsigned VgprMSBs = 0;53 54public:55 explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)56 : MCInstrAnalysis(Info) {}57 58 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,59 uint64_t &Target) const override;60 61 void resetState() override { VgprMSBs = 0; }62 63 void updateState(const MCInst &Inst, uint64_t Addr) override;64 65 unsigned getVgprMSBs() const { return VgprMSBs; }66};67 68} // namespace AMDGPU69 70} // namespace llvm71 72#define GET_REGINFO_ENUM73#include "AMDGPUGenRegisterInfo.inc"74 75#define GET_INSTRINFO_ENUM76#define GET_INSTRINFO_MC_HELPER_DECLS77#include "AMDGPUGenInstrInfo.inc"78 79#define GET_SUBTARGETINFO_ENUM80#include "AMDGPUGenSubtargetInfo.inc"81 82#endif83