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1//===-- R600.td - R600 Tablegen files ----------------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9include "llvm/Target/Target.td"10 11let Namespace = "R600" in {12 13foreach Index = 0-15 in {14 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;15}16 17include "R600RegisterInfo.td"18 19}20 21defm : RemapAllTargetPseudoPointerOperands<R600_Addr>;22 23def R600InstrInfo : InstrInfo {24 let guessInstructionProperties = 1;25}26 27def R600 : Target {28 let InstructionSet = R600InstrInfo;29 let AllowRegisterRenaming = 1;30}31 32 33def NullALU : InstrItinClass;34def ALU_NULL : FuncUnit;35 36include "AMDGPUFeatures.td"37include "R600Schedule.td"38include "R600Processors.td"39include "R600InstrInfo.td"40include "AMDGPUInstrInfo.td"41include "AMDGPUPredicateControl.td"42include "AMDGPUInstructions.td"43include "R600Instructions.td"44include "R700Instructions.td"45include "EvergreenInstructions.td"46include "CaymanInstructions.td"47 48// Calling convention for R60049def CC_R600 : CallingConv<[50 CCIfInReg<CCIfType<[v4f32, v4i32] , CCAssignToReg<[51 T0_XYZW, T1_XYZW, T2_XYZW, T3_XYZW, T4_XYZW, T5_XYZW, T6_XYZW, T7_XYZW,52 T8_XYZW, T9_XYZW, T10_XYZW, T11_XYZW, T12_XYZW, T13_XYZW, T14_XYZW, T15_XYZW,53 T16_XYZW, T17_XYZW, T18_XYZW, T19_XYZW, T20_XYZW, T21_XYZW, T22_XYZW,54 T23_XYZW, T24_XYZW, T25_XYZW, T26_XYZW, T27_XYZW, T28_XYZW, T29_XYZW,55 T30_XYZW, T31_XYZW, T32_XYZW56 ]>>>57]>;58