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1//===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// R600 Instruction format definitions.10//11//===----------------------------------------------------------------------===//12 13def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">;14 15def isR600toCayman : Predicate<16 "Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;17 18class R600Pat<dag pattern, dag result> : AMDGPUPat<pattern, result> {19 let SubtargetPredicate = isR600toCayman;20}21 22class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,23 InstrItinClass itin = NoItinerary>24 : AMDGPUInst <outs, ins, asm, pattern>, PredicateControl {25 26 field bits<64> Inst;27 bit Trig = 0;28 bit Op3 = 0;29 bit isVector = 0;30 bits<2> FlagOperandIdx = 0;31 bit Op1 = 0;32 bit Op2 = 0;33 bit LDS_1A = 0;34 bit LDS_1A1D = 0;35 bit HasNativeOperands = 0;36 bit VTXInst = 0;37 bit TEXInst = 0;38 bit ALUInst = 0;39 bit IsExport = 0;40 bit LDS_1A2D = 0;41 42 let SubtargetPredicate = isR600toCayman;43 let Namespace = "R600";44 let OutOperandList = outs;45 let InOperandList = ins;46 let AsmString = asm;47 let Pattern = pattern;48 let Itinerary = itin;49 50 // No AsmMatcher support.51 let isCodeGenOnly = 1;52 53 let TSFlags{4} = Trig;54 let TSFlags{5} = Op3;55 56 // Vector instructions are instructions that must fill all slots in an57 // instruction group58 let TSFlags{6} = isVector;59 let TSFlags{8-7} = FlagOperandIdx;60 let TSFlags{9} = HasNativeOperands;61 let TSFlags{10} = Op1;62 let TSFlags{11} = Op2;63 let TSFlags{12} = VTXInst;64 let TSFlags{13} = TEXInst;65 let TSFlags{14} = ALUInst;66 let TSFlags{15} = LDS_1A;67 let TSFlags{16} = LDS_1A1D;68 let TSFlags{17} = IsExport;69 let TSFlags{18} = LDS_1A2D;70}71 72//===----------------------------------------------------------------------===//73// ALU instructions74//===----------------------------------------------------------------------===//75 76class R600_ALU_LDS_Word0 {77 field bits<32> Word0;78 79 bits<11> src0;80 bits<1> src0_rel;81 bits<11> src1;82 bits<1> src1_rel;83 bits<3> index_mode = 0;84 bits<2> pred_sel;85 bits<1> last;86 87 bits<9> src0_sel = src0{8-0};88 bits<2> src0_chan = src0{10-9};89 bits<9> src1_sel = src1{8-0};90 bits<2> src1_chan = src1{10-9};91 92 let Word0{8-0} = src0_sel;93 let Word0{9} = src0_rel;94 let Word0{11-10} = src0_chan;95 let Word0{21-13} = src1_sel;96 let Word0{22} = src1_rel;97 let Word0{24-23} = src1_chan;98 let Word0{28-26} = index_mode;99 let Word0{30-29} = pred_sel;100 let Word0{31} = last;101}102 103class R600ALU_Word0 : R600_ALU_LDS_Word0 {104 105 bits<1> src0_neg;106 bits<1> src1_neg;107 108 let Word0{12} = src0_neg;109 let Word0{25} = src1_neg;110}111 112class R600ALU_Word1 {113 field bits<32> Word1;114 115 bits<11> dst;116 bits<3> bank_swizzle;117 bits<1> dst_rel;118 bits<1> clamp;119 120 bits<7> dst_sel = dst{6-0};121 bits<2> dst_chan = dst{10-9};122 123 let Word1{20-18} = bank_swizzle;124 let Word1{27-21} = dst_sel;125 let Word1{28} = dst_rel;126 let Word1{30-29} = dst_chan;127 let Word1{31} = clamp;128}129 130class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{131 132 bits<1> src0_abs;133 bits<1> src1_abs;134 bits<1> update_exec_mask;135 bits<1> update_pred;136 bits<1> write;137 bits<2> omod;138 139 let Word1{0} = src0_abs;140 let Word1{1} = src1_abs;141 let Word1{2} = update_exec_mask;142 let Word1{3} = update_pred;143 let Word1{4} = write;144 let Word1{6-5} = omod;145 let Word1{17-7} = alu_inst;146}147 148class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{149 150 bits<11> src2;151 bits<1> src2_rel;152 bits<1> src2_neg;153 154 bits<9> src2_sel = src2{8-0};155 bits<2> src2_chan = src2{10-9};156 157 let Word1{8-0} = src2_sel;158 let Word1{9} = src2_rel;159 let Word1{11-10} = src2_chan;160 let Word1{12} = src2_neg;161 let Word1{17-13} = alu_inst;162}163 164class R600LDS_Word1 {165 field bits<32> Word1;166 167 bits<11> src2;168 bits<9> src2_sel = src2{8-0};169 bits<2> src2_chan = src2{10-9};170 bits<1> src2_rel;171 // offset specifies the stride offset to the second set of data to be read172 // from. This is a dword offset.173 bits<5> alu_inst = 17; // OP3_INST_LDS_IDX_OP174 bits<3> bank_swizzle;175 bits<6> lds_op;176 bits<2> dst_chan = 0;177 178 let Word1{8-0} = src2_sel;179 let Word1{9} = src2_rel;180 let Word1{11-10} = src2_chan;181 let Word1{17-13} = alu_inst;182 let Word1{20-18} = bank_swizzle;183 let Word1{26-21} = lds_op;184 let Word1{30-29} = dst_chan;185}186 187 188/*189XXX: R600 subtarget uses a slightly different encoding than the other190subtargets. We currently handle this in R600MCCodeEmitter, but we may191want to use these instruction classes in the future.192 193class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {194 195 bits<1> fog_merge;196 bits<10> alu_inst;197 198 let Inst{37} = fog_merge;199 let Inst{39-38} = omod;200 let Inst{49-40} = alu_inst;201}202 203class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {204 205 bits<11> alu_inst;206 207 let Inst{38-37} = omod;208 let Inst{49-39} = alu_inst;209}210*/211 212//===----------------------------------------------------------------------===//213// Vertex Fetch instructions214//===----------------------------------------------------------------------===//215 216class VTX_WORD0 {217 field bits<32> Word0;218 bits<7> src_gpr;219 bits<5> VC_INST;220 bits<2> FETCH_TYPE;221 bits<1> FETCH_WHOLE_QUAD;222 bits<8> buffer_id;223 bits<1> SRC_REL;224 bits<2> SRC_SEL_X;225 226 let Word0{4-0} = VC_INST;227 let Word0{6-5} = FETCH_TYPE;228 let Word0{7} = FETCH_WHOLE_QUAD;229 let Word0{15-8} = buffer_id;230 let Word0{22-16} = src_gpr;231 let Word0{23} = SRC_REL;232 let Word0{25-24} = SRC_SEL_X;233}234 235class VTX_WORD0_eg : VTX_WORD0 {236 237 bits<6> MEGA_FETCH_COUNT;238 239 let Word0{31-26} = MEGA_FETCH_COUNT;240}241 242class VTX_WORD0_cm : VTX_WORD0 {243 244 bits<2> SRC_SEL_Y;245 bits<2> STRUCTURED_READ;246 bits<1> LDS_REQ;247 bits<1> COALESCED_READ;248 249 let Word0{27-26} = SRC_SEL_Y;250 let Word0{29-28} = STRUCTURED_READ;251 let Word0{30} = LDS_REQ;252 let Word0{31} = COALESCED_READ;253}254 255class VTX_WORD1_GPR {256 field bits<32> Word1;257 bits<7> dst_gpr;258 bits<1> DST_REL;259 bits<3> DST_SEL_X;260 bits<3> DST_SEL_Y;261 bits<3> DST_SEL_Z;262 bits<3> DST_SEL_W;263 bits<1> USE_CONST_FIELDS;264 bits<6> DATA_FORMAT;265 bits<2> NUM_FORMAT_ALL;266 bits<1> FORMAT_COMP_ALL;267 bits<1> SRF_MODE_ALL;268 269 let Word1{6-0} = dst_gpr;270 let Word1{7} = DST_REL;271 let Word1{8} = 0; // Reserved272 let Word1{11-9} = DST_SEL_X;273 let Word1{14-12} = DST_SEL_Y;274 let Word1{17-15} = DST_SEL_Z;275 let Word1{20-18} = DST_SEL_W;276 let Word1{21} = USE_CONST_FIELDS;277 let Word1{27-22} = DATA_FORMAT;278 let Word1{29-28} = NUM_FORMAT_ALL;279 let Word1{30} = FORMAT_COMP_ALL;280 let Word1{31} = SRF_MODE_ALL;281}282 283//===----------------------------------------------------------------------===//284// Texture fetch instructions285//===----------------------------------------------------------------------===//286 287class TEX_WORD0 {288 field bits<32> Word0;289 290 bits<5> TEX_INST;291 bits<2> INST_MOD;292 bits<1> FETCH_WHOLE_QUAD;293 bits<8> RESOURCE_ID;294 bits<7> SRC_GPR;295 bits<1> SRC_REL;296 bits<1> ALT_CONST;297 bits<2> RESOURCE_INDEX_MODE;298 bits<2> SAMPLER_INDEX_MODE;299 300 let Word0{4-0} = TEX_INST;301 let Word0{6-5} = INST_MOD;302 let Word0{7} = FETCH_WHOLE_QUAD;303 let Word0{15-8} = RESOURCE_ID;304 let Word0{22-16} = SRC_GPR;305 let Word0{23} = SRC_REL;306 let Word0{24} = ALT_CONST;307 let Word0{26-25} = RESOURCE_INDEX_MODE;308 let Word0{28-27} = SAMPLER_INDEX_MODE;309}310 311class TEX_WORD1 {312 field bits<32> Word1;313 314 bits<7> DST_GPR;315 bits<1> DST_REL;316 bits<3> DST_SEL_X;317 bits<3> DST_SEL_Y;318 bits<3> DST_SEL_Z;319 bits<3> DST_SEL_W;320 bits<7> LOD_BIAS;321 bits<1> COORD_TYPE_X;322 bits<1> COORD_TYPE_Y;323 bits<1> COORD_TYPE_Z;324 bits<1> COORD_TYPE_W;325 326 let Word1{6-0} = DST_GPR;327 let Word1{7} = DST_REL;328 let Word1{11-9} = DST_SEL_X;329 let Word1{14-12} = DST_SEL_Y;330 let Word1{17-15} = DST_SEL_Z;331 let Word1{20-18} = DST_SEL_W;332 let Word1{27-21} = LOD_BIAS;333 let Word1{28} = COORD_TYPE_X;334 let Word1{29} = COORD_TYPE_Y;335 let Word1{30} = COORD_TYPE_Z;336 let Word1{31} = COORD_TYPE_W;337}338 339class TEX_WORD2 {340 field bits<32> Word2;341 342 bits<5> OFFSET_X;343 bits<5> OFFSET_Y;344 bits<5> OFFSET_Z;345 bits<5> SAMPLER_ID;346 bits<3> SRC_SEL_X;347 bits<3> SRC_SEL_Y;348 bits<3> SRC_SEL_Z;349 bits<3> SRC_SEL_W;350 351 let Word2{4-0} = OFFSET_X;352 let Word2{9-5} = OFFSET_Y;353 let Word2{14-10} = OFFSET_Z;354 let Word2{19-15} = SAMPLER_ID;355 let Word2{22-20} = SRC_SEL_X;356 let Word2{25-23} = SRC_SEL_Y;357 let Word2{28-26} = SRC_SEL_Z;358 let Word2{31-29} = SRC_SEL_W;359}360 361//===----------------------------------------------------------------------===//362// Control Flow Instructions363//===----------------------------------------------------------------------===//364 365class CF_WORD1_R600 {366 field bits<32> Word1;367 368 bits<3> POP_COUNT;369 bits<5> CF_CONST;370 bits<2> COND;371 bits<3> COUNT;372 bits<6> CALL_COUNT;373 bits<1> COUNT_3;374 bits<1> END_OF_PROGRAM;375 bits<1> VALID_PIXEL_MODE;376 bits<7> CF_INST;377 bits<1> WHOLE_QUAD_MODE;378 bits<1> BARRIER;379 380 let Word1{2-0} = POP_COUNT;381 let Word1{7-3} = CF_CONST;382 let Word1{9-8} = COND;383 let Word1{12-10} = COUNT;384 let Word1{18-13} = CALL_COUNT;385 let Word1{19} = COUNT_3;386 let Word1{21} = END_OF_PROGRAM;387 let Word1{22} = VALID_PIXEL_MODE;388 let Word1{29-23} = CF_INST;389 let Word1{30} = WHOLE_QUAD_MODE;390 let Word1{31} = BARRIER;391}392 393class CF_WORD0_EG {394 field bits<32> Word0;395 396 bits<24> ADDR;397 bits<3> JUMPTABLE_SEL;398 399 let Word0{23-0} = ADDR;400 let Word0{26-24} = JUMPTABLE_SEL;401}402 403class CF_WORD1_EG {404 field bits<32> Word1;405 406 bits<3> POP_COUNT;407 bits<5> CF_CONST;408 bits<2> COND;409 bits<6> COUNT;410 bits<1> VALID_PIXEL_MODE;411 bits<1> END_OF_PROGRAM;412 bits<8> CF_INST;413 bits<1> BARRIER;414 415 let Word1{2-0} = POP_COUNT;416 let Word1{7-3} = CF_CONST;417 let Word1{9-8} = COND;418 let Word1{15-10} = COUNT;419 let Word1{20} = VALID_PIXEL_MODE;420 let Word1{21} = END_OF_PROGRAM;421 let Word1{29-22} = CF_INST;422 let Word1{31} = BARRIER;423}424 425class CF_ALU_WORD0 {426 field bits<32> Word0;427 428 bits<22> ADDR;429 bits<4> KCACHE_BANK0;430 bits<4> KCACHE_BANK1;431 bits<2> KCACHE_MODE0;432 433 let Word0{21-0} = ADDR;434 let Word0{25-22} = KCACHE_BANK0;435 let Word0{29-26} = KCACHE_BANK1;436 let Word0{31-30} = KCACHE_MODE0;437}438 439class CF_ALU_WORD1 {440 field bits<32> Word1;441 442 bits<2> KCACHE_MODE1;443 bits<8> KCACHE_ADDR0;444 bits<8> KCACHE_ADDR1;445 bits<7> COUNT;446 bits<1> ALT_CONST;447 bits<4> CF_INST;448 bits<1> WHOLE_QUAD_MODE;449 bits<1> BARRIER;450 451 let Word1{1-0} = KCACHE_MODE1;452 let Word1{9-2} = KCACHE_ADDR0;453 let Word1{17-10} = KCACHE_ADDR1;454 let Word1{24-18} = COUNT;455 let Word1{25} = ALT_CONST;456 let Word1{29-26} = CF_INST;457 let Word1{30} = WHOLE_QUAD_MODE;458 let Word1{31} = BARRIER;459}460 461class CF_ALLOC_EXPORT_WORD0_RAT {462 field bits<32> Word0;463 464 bits<4> rat_id;465 bits<6> rat_inst;466 bits<2> rim;467 bits<2> type;468 bits<7> rw_gpr;469 bits<1> rw_rel;470 bits<7> index_gpr;471 bits<2> elem_size;472 473 let Word0{3-0} = rat_id;474 let Word0{9-4} = rat_inst;475 let Word0{10} = 0; // Reserved476 let Word0{12-11} = rim;477 let Word0{14-13} = type;478 let Word0{21-15} = rw_gpr;479 let Word0{22} = rw_rel;480 let Word0{29-23} = index_gpr;481 let Word0{31-30} = elem_size;482}483 484class CF_ALLOC_EXPORT_WORD1_BUF {485 field bits<32> Word1;486 487 bits<12> array_size;488 bits<4> comp_mask;489 bits<4> burst_count;490 bits<1> vpm;491 bits<1> eop;492 bits<8> cf_inst;493 bits<1> mark;494 bits<1> barrier;495 496 let Word1{11-0} = array_size;497 let Word1{15-12} = comp_mask;498 let Word1{19-16} = burst_count;499 let Word1{20} = vpm;500 let Word1{21} = eop;501 let Word1{29-22} = cf_inst;502 let Word1{30} = mark;503 let Word1{31} = barrier;504}505