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1//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// TableGen definitions for instructions which are available on R600 family10// GPUs.11//12//===----------------------------------------------------------------------===//13 14include "R600InstrFormats.td"15 16// FIXME: Should not be arbitrarily split from other R600 inst classes.17class R600WrapperInst <dag outs, dag ins, string asm = "", list<dag> pattern = []> :18 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {19 let SubtargetPredicate = isR600toCayman;20 let Namespace = "R600";21}22 23 24class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern = []> :25 InstR600 <outs, ins, asm, pattern, NullALU> {26 27}28 29def MEMxi : Operand<iPTR> {30 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);31 let PrintMethod = "printMemOperand";32}33 34def MEMrr : Operand<iPTR> {35 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);36}37 38// Operands for non-registers39 40class InstFlag<string PM = "printOperand", int Default = 0>41 : OperandWithDefaultOps <i32, (ops (i32 Default))> {42 let PrintMethod = PM;43}44 45// src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers46def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))>;47def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {48 let PrintMethod = "printBankSwizzle";49}50 51def LITERAL : InstFlag<"printLiteral">;52 53def WRITE : InstFlag <"printWrite", 1>;54def OMOD : InstFlag <"printOMOD">;55def REL : InstFlag <"printRel">;56def CLAMP : InstFlag <"printClamp">;57def NEG : InstFlag <"printNeg">;58def ABS : InstFlag <"printAbs">;59def UEM : InstFlag <"printUpdateExecMask">;60def UP : InstFlag <"printUpdatePred">;61 62// XXX: The r600g finalizer in Mesa expects last to be one in most cases.63// Once we start using the packetizer in this backend we should have this64// default to 0.65def LAST : InstFlag<"printLast", 1>;66def RSel : Operand<i32> {67 let PrintMethod = "printRSel";68}69def CT: Operand<i32> {70 let PrintMethod = "printCT";71}72 73def FRAMEri : Operand<iPTR> {74 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);75}76 77def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;78def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;79def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;80def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;81 82 83def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),84 (ops PRED_SEL_OFF)>;85 86let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,87 usesCustomInserter = 1, Namespace = "R600" in {88 def RETURN : ILFormat<(outs), (ins variable_ops),89 "RETURN", [(AMDGPUendpgm)]90 >;91}92 93let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {94 95// Class for instructions with only one source register.96// If you add new ins to this instruction, make sure they are listed before97// $literal, because the backend currently assumes that the last operand is98// a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in99// R600Defines.h, R600InstrInfo::buildDefaultInstruction(),100// and R600InstrInfo::getOperandIdx().101class R600_1OP <bits<11> inst, string opName, list<dag> pattern,102 InstrItinClass itin = AnyALU> :103 InstR600 <(outs R600_Reg32:$dst),104 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,105 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,106 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,107 BANK_SWIZZLE:$bank_swizzle),108 !strconcat(" ", opName,109 "$clamp $last $dst$write$dst_rel$omod, "110 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "111 "$pred_sel $bank_swizzle"),112 pattern,113 itin>,114 R600ALU_Word0,115 R600ALU_Word1_OP2 <inst> {116 117 let src1 = 0;118 let src1_rel = 0;119 let src1_neg = 0;120 let src1_abs = 0;121 let update_exec_mask = 0;122 let update_pred = 0;123 let HasNativeOperands = 1;124 let Op1 = 1;125 let ALUInst = 1;126 let UseNamedOperandTable = 1;127 128 let Inst{31-0} = Word0;129 let Inst{63-32} = Word1;130}131 132class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,133 InstrItinClass itin = AnyALU> :134 R600_1OP <inst, opName,135 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin136>;137 138// If you add or change the operands for R600_2OP instructions, you must139// also update the R600Op2OperandIndex::ROI enum in R600Defines.h,140// R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().141class R600_2OP <bits<11> inst, string opName, list<dag> pattern,142 InstrItinClass itin = AnyALU> :143 InstR600 <(outs R600_Reg32:$dst),144 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,145 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,146 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,147 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,148 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,149 BANK_SWIZZLE:$bank_swizzle),150 !strconcat(" ", opName,151 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "152 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "153 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "154 "$pred_sel $bank_swizzle"),155 pattern,156 itin>,157 R600ALU_Word0,158 R600ALU_Word1_OP2 <inst> {159 160 let HasNativeOperands = 1;161 let Op2 = 1;162 let ALUInst = 1;163 let UseNamedOperandTable = 1;164 165 let Inst{31-0} = Word0;166 let Inst{63-32} = Word1;167}168 169class R600_2OP_Helper <bits<11> inst, string opName,170 SDPatternOperator node = null_frag,171 InstrItinClass itin = AnyALU> :172 R600_2OP <inst, opName,173 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,174 R600_Reg32:$src1))], itin175>;176 177// If you add our change the operands for R600_3OP instructions, you must178// also update the R600Op3OperandIndex::ROI enum in R600Defines.h,179// R600InstrInfo::buildDefaultInstruction(), and180// R600InstrInfo::getOperandIdx().181class R600_3OP <bits<5> inst, string opName, list<dag> pattern,182 InstrItinClass itin = AnyALU> :183 InstR600 <(outs R600_Reg32:$dst),184 (ins REL:$dst_rel, CLAMP:$clamp,185 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,186 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,187 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,188 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,189 BANK_SWIZZLE:$bank_swizzle),190 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "191 "$src0_neg$src0$src0_rel, "192 "$src1_neg$src1$src1_rel, "193 "$src2_neg$src2$src2_rel, "194 "$pred_sel"195 "$bank_swizzle"),196 pattern,197 itin>,198 R600ALU_Word0,199 R600ALU_Word1_OP3<inst>{200 201 let HasNativeOperands = 1;202 let Op3 = 1;203 let UseNamedOperandTable = 1;204 let ALUInst = 1;205 206 let Inst{31-0} = Word0;207 let Inst{63-32} = Word1;208}209 210} // End mayLoad = 1, mayStore = 0, hasSideEffects = 0211 212class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask,213 dag outs, dag ins, string asm, list<dag> pattern> :214 InstR600ISA <outs, ins, asm, pattern>,215 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF {216 217 let rat_id = ratid;218 let rat_inst = ratinst;219 let rim = 0;220 // XXX: Have a separate instruction for non-indexed writes.221 let type = 1;222 let rw_rel = 0;223 let elem_size = 0;224 225 let array_size = 0;226 let comp_mask = mask;227 let burst_count = 0;228 let vpm = 0;229 let cf_inst = cfinst;230 let mark = 0;231 let barrier = 1;232 233 let Inst{31-0} = Word0;234 let Inst{63-32} = Word1;235 let IsExport = 1;236 237}238 239class VTX_READ <string name, dag outs, list<dag> pattern>240 : InstR600ISA <outs, (ins MEMxi:$src_gpr, i8imm:$buffer_id), !strconcat(" ", name, ", #$buffer_id"), pattern>,241 VTX_WORD1_GPR {242 243 // Static fields244 let DST_REL = 0;245 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,246 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,247 // however, based on my testing if USE_CONST_FIELDS is set, then all248 // these fields need to be set to 0.249 let USE_CONST_FIELDS = 0;250 let NUM_FORMAT_ALL = 1;251 let FORMAT_COMP_ALL = 0;252 let SRF_MODE_ALL = 0;253 254 let Inst{63-32} = Word1;255 // LLVM can only encode 64-bit instructions, so these fields are manually256 // encoded in R600CodeEmitter257 //258 // bits<16> OFFSET;259 // bits<2> ENDIAN_SWAP = 0;260 // bits<1> CONST_BUF_NO_STRIDE = 0;261 // bits<1> MEGA_FETCH = 0;262 // bits<1> ALT_CONST = 0;263 // bits<2> BUFFER_INDEX_MODE = 0;264 265 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding266 // is done in R600CodeEmitter267 //268 // Inst{79-64} = OFFSET;269 // Inst{81-80} = ENDIAN_SWAP;270 // Inst{82} = CONST_BUF_NO_STRIDE;271 // Inst{83} = MEGA_FETCH;272 // Inst{84} = ALT_CONST;273 // Inst{86-85} = BUFFER_INDEX_MODE;274 // Inst{95-86} = 0; Reserved275 276 // VTX_WORD3 (Padding)277 //278 // Inst{127-96} = 0;279 280 let VTXInst = 1;281}282 283// Legacy.284def atomic_cmp_swap_global_noret : PatFrag<285 (ops node:$ptr, node:$cmp, node:$value),286 (atomic_cmp_swap node:$ptr, node:$cmp, node:$value),287 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (SDValue(N, 0).use_empty());}]>;288 289def atomic_cmp_swap_global_ret : PatFrag<290 (ops node:$ptr, node:$cmp, node:$value),291 (atomic_cmp_swap node:$ptr, node:$cmp, node:$value),292 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (!SDValue(N, 0).use_empty());}]>;293 294def mskor_global : PatFrag<(ops node:$val, node:$ptr),295 (AMDGPUstore_mskor node:$val, node:$ptr), [{296 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;297}]>;298 299// FIXME: These are deprecated300class AZExtLoadBase <SDPatternOperator ld_node>: PatFrag<(ops node:$ptr),301 (ld_node node:$ptr), [{302 LoadSDNode *L = cast<LoadSDNode>(N);303 return L->getExtensionType() == ISD::ZEXTLOAD ||304 L->getExtensionType() == ISD::EXTLOAD;305}]>;306 307def az_extload : AZExtLoadBase <unindexedload>;308 309def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{310 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;311}]>;312 313def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{314 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;315}]>;316 317def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{318 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;319}]>;320 321let AddressSpaces = LoadAddress_local.AddrSpaces in {322def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr)>;323def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr)>;324}325 326class LoadParamFrag <PatFrag load_type> : PatFrag <327 (ops node:$ptr), (load_type node:$ptr),328 [{ return isConstantLoad(cast<LoadSDNode>(N), 0) ||329 (cast<LoadSDNode>(N)->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS); }]330>;331 332def vtx_id3_az_extloadi8 : LoadParamFrag<az_extloadi8>;333def vtx_id3_az_extloadi16 : LoadParamFrag<az_extloadi16>;334def vtx_id3_load : LoadParamFrag<load>;335 336class LoadVtxId1 <PatFrag load> : PatFrag <337 (ops node:$ptr), (load node:$ptr), [{338 const MemSDNode *LD = cast<MemSDNode>(N);339 return LD->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||340 (LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&341 !isa<GlobalValue>(getUnderlyingObject(342 LD->getMemOperand()->getValue())));343}]>;344 345def vtx_id1_az_extloadi8 : LoadVtxId1 <az_extloadi8>;346def vtx_id1_az_extloadi16 : LoadVtxId1 <az_extloadi16>;347def vtx_id1_load : LoadVtxId1 <load>;348 349class LoadVtxId2 <PatFrag load> : PatFrag <350 (ops node:$ptr), (load node:$ptr), [{351 const MemSDNode *LD = cast<MemSDNode>(N);352 return LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&353 isa<GlobalValue>(getUnderlyingObject(354 LD->getMemOperand()->getValue()));355}]>;356 357def vtx_id2_az_extloadi8 : LoadVtxId2 <az_extloadi8>;358def vtx_id2_az_extloadi16 : LoadVtxId2 <az_extloadi16>;359def vtx_id2_load : LoadVtxId2 <load>;360 361//===----------------------------------------------------------------------===//362// R600 SDNodes363//===----------------------------------------------------------------------===//364 365let Namespace = "R600" in {366 367def INTERP_PAIR_XY : AMDGPUShaderInst <368 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),369 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),370 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",371 []>;372 373def INTERP_PAIR_ZW : AMDGPUShaderInst <374 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),375 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),376 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",377 []>;378 379}380 381def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",382 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,383 [SDNPVariadic]384>;385 386def DOT4 : SDNode<"AMDGPUISD::DOT4",387 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,388 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,389 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,390 []391>;392 393def COS_HW : SDNode<"AMDGPUISD::COS_HW",394 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>395>;396 397def SIN_HW : SDNode<"AMDGPUISD::SIN_HW",398 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>399>;400 401def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;402 403def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;404 405multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {406def : R600Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,407 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),408 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),409 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),410 (i32 imm:$DST_SEL_W),411 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),412 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),413 (i32 imm:$COORD_TYPE_W)),414 (inst R600_Reg128:$SRC_GPR,415 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,416 imm:$offsetx, imm:$offsety, imm:$offsetz,417 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,418 imm:$DST_SEL_W,419 imm:$RESOURCE_ID, imm:$SAMPLER_ID,420 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,421 imm:$COORD_TYPE_W)>;422}423 424//===----------------------------------------------------------------------===//425// Interpolation Instructions426//===----------------------------------------------------------------------===//427 428let Namespace = "R600" in {429 430def INTERP_VEC_LOAD : AMDGPUShaderInst <431 (outs R600_Reg128:$dst),432 (ins i32imm:$src0),433 "INTERP_LOAD $src0 : $dst">;434 435}436 437def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {438 let bank_swizzle = 5;439}440 441def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {442 let bank_swizzle = 5;443}444 445def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;446 447//===----------------------------------------------------------------------===//448// Export Instructions449//===----------------------------------------------------------------------===//450 451class ExportWord0 {452 field bits<32> Word0;453 454 bits<13> arraybase;455 bits<2> type;456 bits<7> gpr;457 bits<2> elem_size;458 459 let Word0{12-0} = arraybase;460 let Word0{14-13} = type;461 let Word0{21-15} = gpr;462 let Word0{22} = 0; // RW_REL463 let Word0{29-23} = 0; // INDEX_GPR464 let Word0{31-30} = elem_size;465}466 467class ExportSwzWord1 {468 field bits<32> Word1;469 470 bits<3> sw_x;471 bits<3> sw_y;472 bits<3> sw_z;473 bits<3> sw_w;474 bits<1> eop;475 bits<8> inst;476 477 let Word1{2-0} = sw_x;478 let Word1{5-3} = sw_y;479 let Word1{8-6} = sw_z;480 let Word1{11-9} = sw_w;481}482 483class ExportBufWord1 {484 field bits<32> Word1;485 486 bits<12> arraySize;487 bits<4> compMask;488 bits<1> eop;489 bits<8> inst;490 491 let Word1{11-0} = arraySize;492 let Word1{15-12} = compMask;493}494 495multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {496 def : R600Pat<(R600_EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),497 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),498 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,499 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)500 >;501 502}503 504multiclass SteamOutputExportPattern<Instruction ExportInst,505 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {506// Stream0507 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),508 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),509 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,510 4095, imm:$mask, buf0inst, 0)>;511// Stream1512 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),513 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),514 (ExportInst $src, 0, imm:$arraybase,515 4095, imm:$mask, buf1inst, 0)>;516// Stream2517 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),518 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),519 (ExportInst $src, 0, imm:$arraybase,520 4095, imm:$mask, buf2inst, 0)>;521// Stream3522 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),523 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),524 (ExportInst $src, 0, imm:$arraybase,525 4095, imm:$mask, buf3inst, 0)>;526}527 528// Export Instructions should not be duplicated by TailDuplication pass529// (which assumes that duplicable instruction are affected by exec mask)530let usesCustomInserter = 1, isNotDuplicable = 1 in {531 532class ExportSwzInst : InstR600ISA<(533 outs),534 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,535 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst,536 i32imm:$eop),537 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"),538 []>, ExportWord0, ExportSwzWord1 {539 let elem_size = 3;540 let Inst{31-0} = Word0;541 let Inst{63-32} = Word1;542 let IsExport = 1;543}544 545} // End usesCustomInserter = 1546 547class ExportBufInst : InstR600ISA<(548 outs),549 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,550 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),551 !strconcat("EXPORT", " $gpr"),552 []>, ExportWord0, ExportBufWord1 {553 let elem_size = 0;554 let Inst{31-0} = Word0;555 let Inst{63-32} = Word1;556 let IsExport = 1;557}558 559//===----------------------------------------------------------------------===//560// Control Flow Instructions561//===----------------------------------------------------------------------===//562 563 564def KCACHE : InstFlag<"printKCache">;565 566class ALU_CLAUSE<bits<4> inst, string OpName> : R600WrapperInst <(outs),567(ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,568KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,569i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,570i32imm:$COUNT, i32imm:$Enabled),571!strconcat(OpName, " $COUNT, @$ADDR, "572"KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),573[] >, CF_ALU_WORD0, CF_ALU_WORD1 {574 field bits<64> Inst;575 576 let CF_INST = inst;577 let ALT_CONST = 0;578 let WHOLE_QUAD_MODE = 0;579 let BARRIER = 1;580 let isCodeGenOnly = 1;581 let UseNamedOperandTable = 1;582 583 let Inst{31-0} = Word0;584 let Inst{63-32} = Word1;585}586 587class CF_WORD0_R600 {588 field bits<32> Word0;589 590 bits<32> ADDR;591 592 let Word0 = ADDR;593}594 595class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : R600WrapperInst <(outs),596ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {597 field bits<64> Inst;598 bits<4> CNT;599 600 let CF_INST = inst;601 let BARRIER = 1;602 let CF_CONST = 0;603 let VALID_PIXEL_MODE = 0;604 let COND = 0;605 let COUNT = CNT{2-0};606 let CALL_COUNT = 0;607 let COUNT_3 = CNT{3};608 let END_OF_PROGRAM = 0;609 let WHOLE_QUAD_MODE = 0;610 611 let Inst{31-0} = Word0;612 let Inst{63-32} = Word1;613}614 615class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : R600WrapperInst <(outs),616ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {617 field bits<64> Inst;618 619 let CF_INST = inst;620 let BARRIER = 1;621 let JUMPTABLE_SEL = 0;622 let CF_CONST = 0;623 let VALID_PIXEL_MODE = 0;624 let COND = 0;625 let END_OF_PROGRAM = 0;626 627 let Inst{31-0} = Word0;628 let Inst{63-32} = Word1;629}630 631def CF_ALU : ALU_CLAUSE<8, "ALU">;632def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;633def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">;634def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">;635def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">;636def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">;637 638def FETCH_CLAUSE : R600WrapperInst <(outs),639(ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {640 field bits<8> Inst;641 bits<8> addr;642 let Inst = addr;643 let isCodeGenOnly = 1;644}645 646def ALU_CLAUSE : R600WrapperInst <(outs),647(ins i32imm:$addr), "ALU clause starting at $addr:", [] > {648 field bits<8> Inst;649 bits<8> addr;650 let Inst = addr;651 let isCodeGenOnly = 1;652}653 654def LITERALS : R600WrapperInst <(outs),655(ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {656 let isCodeGenOnly = 1;657 658 field bits<64> Inst;659 bits<32> literal1;660 bits<32> literal2;661 662 let Inst{31-0} = literal1;663 let Inst{63-32} = literal2;664}665 666def PAD : R600WrapperInst <(outs), (ins), "PAD", [] > {667 field bits<64> Inst;668}669 670//===----------------------------------------------------------------------===//671// Common Instructions R600, R700, Evergreen, Cayman672//===----------------------------------------------------------------------===//673 674let isCodeGenOnly = 1, isPseudo = 1 in {675 676let Namespace = "R600", usesCustomInserter = 1 in {677 678class FABS <RegisterClass rc> : AMDGPUShaderInst <679 (outs rc:$dst),680 (ins rc:$src0),681 "FABS $dst, $src0",682 [(set f32:$dst, (fabs f32:$src0))]683>;684 685class FNEG <RegisterClass rc> : AMDGPUShaderInst <686 (outs rc:$dst),687 (ins rc:$src0),688 "FNEG $dst, $src0",689 [(set f32:$dst, (fneg f32:$src0))]690>;691 692} // usesCustomInserter = 1693 694multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,695 ComplexPattern addrPat> {696let UseNamedOperandTable = 1 in {697 698 def RegisterLoad : AMDGPUShaderInst <699 (outs dstClass:$dst),700 (ins addrClass:$addr, i32imm:$chan),701 "RegisterLoad $dst, $addr",702 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]703 > {704 let isRegisterLoad = 1;705 }706 707 def RegisterStore : AMDGPUShaderInst <708 (outs),709 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),710 "RegisterStore $val, $addr",711 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]712 > {713 let isRegisterStore = 1;714 }715}716}717 718} // End isCodeGenOnly = 1, isPseudo = 1719 720 721def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;722// Non-IEEE MUL: 0 * anything = 0723def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE">;724def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;725// TODO: Do these actually match the regular fmin/fmax behavior?726def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax_legacy>;727def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin_legacy>;728// According to https://msdn.microsoft.com/en-us/library/windows/desktop/cc308050%28v=vs.85%29.aspx729// DX10 min/max returns the other operand if one is NaN,730// this matches http://llvm.org/docs/LangRef.html#llvm-minnum-intrinsic731def MAX_DX10 : R600_2OP_Helper <0x5, "MAX_DX10", fmaxnum>;732def MIN_DX10 : R600_2OP_Helper <0x6, "MIN_DX10", fminnum>;733 734// For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,735// so some of the instruction names don't match the asm string.736// XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.737def SETE : R600_2OP <738 0x08, "SETE",739 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))]740>;741 742def SGT : R600_2OP <743 0x09, "SETGT",744 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))]745>;746 747def SGE : R600_2OP <748 0xA, "SETGE",749 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))]750>;751 752def SNE : R600_2OP <753 0xB, "SETNE",754 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))]755>;756 757def SETE_DX10 : R600_2OP <758 0xC, "SETE_DX10",759 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))]760>;761 762def SETGT_DX10 : R600_2OP <763 0xD, "SETGT_DX10",764 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))]765>;766 767def SETGE_DX10 : R600_2OP <768 0xE, "SETGE_DX10",769 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))]770>;771 772// FIXME: This should probably be COND_ONE773def SETNE_DX10 : R600_2OP <774 0xF, "SETNE_DX10",775 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE_NE))]776>;777 778// FIXME: Need combine for AMDGPUfract779def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;780def TRUNC : R600_1OP_Helper <0x11, "TRUNC", ftrunc>;781def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;782def RNDNE : R600_1OP_Helper <0x13, "RNDNE", froundeven>;783def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;784 785def MOV : R600_1OP <0x19, "MOV", []>;786 787 788// This is a hack to get rid of DUMMY_CHAIN nodes.789// Most DUMMY_CHAINs should be eliminated during legalization, but undef790// values can sneak in some to selection.791let isPseudo = 1, isCodeGenOnly = 1 in {792def DUMMY_CHAIN : R600WrapperInst <793 (outs),794 (ins),795 "DUMMY_CHAIN",796 [(R600dummy_chain)]797>;798} // end let isPseudo = 1, isCodeGenOnly = 1799 800 801let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {802 803class MOV_IMM <Operand immType> : R600WrapperInst <804 (outs R600_Reg32:$dst),805 (ins immType:$imm),806 "",807 []808> {809 let Namespace = "R600";810}811 812} // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1813 814def MOV_IMM_I32 : MOV_IMM<i32imm>;815def : R600Pat <816 (imm:$val),817 (MOV_IMM_I32 imm:$val)818>;819 820def MOV_IMM_GLOBAL_ADDR : MOV_IMM<i32imm>;821def : R600Pat <822 (AMDGPUconstdata_ptr tglobaladdr:$addr),823 (MOV_IMM_GLOBAL_ADDR tglobaladdr:$addr)824>;825 826 827def MOV_IMM_F32 : MOV_IMM<f32imm>;828def : R600Pat <829 (fpimm:$val),830 (MOV_IMM_F32 fpimm:$val)831>;832 833def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;834def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;835def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;836def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;837 838let hasSideEffects = 1 in {839 840def KILLGT : R600_2OP <0x2D, "KILLGT", []>;841 842} // end hasSideEffects843 844def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;845def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;846def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;847def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;848def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;849def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;850def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", smax>;851def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", smin>;852def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", umax>;853def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", umin>;854 855def SETE_INT : R600_2OP <856 0x3A, "SETE_INT",857 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]858>;859 860def SETGT_INT : R600_2OP <861 0x3B, "SETGT_INT",862 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]863>;864 865def SETGE_INT : R600_2OP <866 0x3C, "SETGE_INT",867 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]868>;869 870def SETNE_INT : R600_2OP <871 0x3D, "SETNE_INT",872 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]873>;874 875def SETGT_UINT : R600_2OP <876 0x3E, "SETGT_UINT",877 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]878>;879 880def SETGE_UINT : R600_2OP <881 0x3F, "SETGE_UINT",882 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]883>;884 885def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;886def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;887def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;888def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;889 890def CNDE_INT : R600_3OP <891 0x1C, "CNDE_INT",892 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]893>;894 895def CNDGE_INT : R600_3OP <896 0x1E, "CNDGE_INT",897 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))]898>;899 900def CNDGT_INT : R600_3OP <901 0x1D, "CNDGT_INT",902 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))]903>;904 905//===----------------------------------------------------------------------===//906// Texture instructions907//===----------------------------------------------------------------------===//908 909let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {910 911class R600_TEX <bits<11> inst, string opName> :912 InstR600 <(outs R600_Reg128:$DST_GPR),913 (ins R600_Reg128:$SRC_GPR,914 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw,915 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz,916 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,917 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,918 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,919 CT:$COORD_TYPE_W),920 !strconcat(" ", opName,921 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "922 "$SRC_GPR.$srcx$srcy$srcz$srcw "923 "RID:$RESOURCE_ID SID:$SAMPLER_ID "924 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),925 [],926 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {927 let Inst{31-0} = Word0;928 let Inst{63-32} = Word1;929 930 let TEX_INST = inst{4-0};931 let SRC_REL = 0;932 let DST_REL = 0;933 let LOD_BIAS = 0;934 935 let INST_MOD = 0;936 let FETCH_WHOLE_QUAD = 0;937 let ALT_CONST = 0;938 let SAMPLER_INDEX_MODE = 0;939 let RESOURCE_INDEX_MODE = 0;940 941 let TEXInst = 1;942}943 944} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0945 946 947 948def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">;949def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">;950def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">;951def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">;952def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">;953def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">;954def TEX_LD : R600_TEX <0x03, "TEX_LD">;955def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> {956 let INST_MOD = 1;957}958def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">;959def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">;960def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">;961def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">;962def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;963def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;964def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;965 966defm : TexPattern<0, TEX_SAMPLE>;967defm : TexPattern<1, TEX_SAMPLE_C>;968defm : TexPattern<2, TEX_SAMPLE_L>;969defm : TexPattern<3, TEX_SAMPLE_C_L>;970defm : TexPattern<4, TEX_SAMPLE_LB>;971defm : TexPattern<5, TEX_SAMPLE_C_LB>;972defm : TexPattern<6, TEX_LD, v4i32>;973defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;974defm : TexPattern<8, TEX_GET_GRADIENTS_H>;975defm : TexPattern<9, TEX_GET_GRADIENTS_V>;976defm : TexPattern<10, TEX_LDPTR, v4i32>;977 978//===----------------------------------------------------------------------===//979// Helper classes for common instructions980//===----------------------------------------------------------------------===//981 982class MUL_LIT_Common <bits<5> inst> : R600_3OP <983 inst, "MUL_LIT",984 []985>;986 987class MULADD_Common <bits<5> inst> : R600_3OP <988 inst, "MULADD",989 []990>;991 992class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <993 inst, "MULADD_IEEE",994 [(set f32:$dst, (any_fmad f32:$src0, f32:$src1, f32:$src2))]995>;996 997class FMA_Common <bits<5> inst> : R600_3OP <998 inst, "FMA",999 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU1000>1001{1002 let OtherPredicates = [FMA];1003}1004 1005class CNDE_Common <bits<5> inst> : R600_3OP <1006 inst, "CNDE",1007 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))]1008>;1009 1010class CNDGT_Common <bits<5> inst> : R600_3OP <1011 inst, "CNDGT",1012 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))]1013> {1014 let Itinerary = VecALU;1015}1016 1017class CNDGE_Common <bits<5> inst> : R600_3OP <1018 inst, "CNDGE",1019 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))]1020> {1021 let Itinerary = VecALU;1022}1023 1024 1025let isCodeGenOnly = 1, isPseudo = 1, Namespace = "R600" in {1026class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins1027// Slot X1028 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X,1029 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X,1030 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X,1031 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X,1032 R600_Pred:$pred_sel_X,1033// Slot Y1034 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y,1035 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y,1036 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y,1037 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y,1038 R600_Pred:$pred_sel_Y,1039// Slot Z1040 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z,1041 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z,1042 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z,1043 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z,1044 R600_Pred:$pred_sel_Z,1045// Slot W1046 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W,1047 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W,1048 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W,1049 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W,1050 R600_Pred:$pred_sel_W,1051 LITERAL:$literal0, LITERAL:$literal1),1052 "",1053 pattern,1054 AnyALU> {1055 1056 let UseNamedOperandTable = 1;1057 1058}1059}1060 1061def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT41062 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X,1063 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y,1064 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z,1065 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>;1066 1067 1068class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>;1069 1070 1071let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {1072multiclass CUBE_Common <bits<11> inst> {1073 1074 def _pseudo : InstR600 <1075 (outs R600_Reg128:$dst),1076 (ins R600_Reg128:$src0),1077 "CUBE $dst $src0",1078 [(set v4f32:$dst, (int_r600_cube v4f32:$src0))],1079 VecALU1080 > {1081 let isPseudo = 1;1082 let UseNamedOperandTable = 1;1083 }1084 1085 def _real : R600_2OP <inst, "CUBE", []>;1086}1087} // End mayLoad = 0, mayStore = 0, hasSideEffects = 01088 1089class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <1090 inst, "EXP_IEEE", AMDGPUexp1091> {1092 let Itinerary = TransALU;1093}1094 1095class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <1096 inst, "FLT_TO_INT", fp_to_sint1097> {1098 let Itinerary = TransALU;1099}1100 1101class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <1102 inst, "INT_TO_FLT", sint_to_fp1103> {1104 let Itinerary = TransALU;1105}1106 1107class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <1108 inst, "FLT_TO_UINT", fp_to_uint1109> {1110 let Itinerary = TransALU;1111}1112 1113class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <1114 inst, "UINT_TO_FLT", uint_to_fp1115> {1116 let Itinerary = TransALU;1117}1118 1119class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <1120 inst, "LOG_CLAMPED", []1121>;1122 1123class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <1124 inst, "LOG_IEEE", AMDGPUlog1125> {1126 let Itinerary = TransALU;1127}1128 1129class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;1130class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;1131class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;1132class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <1133 inst, "MULHI_INT", mulhs> {1134 let Itinerary = TransALU;1135}1136 1137class MULHI_INT24_Common <bits<11> inst> : R600_2OP_Helper <1138 inst, "MULHI_INT24", AMDGPUmulhi_i24> {1139 let Itinerary = VecALU;1140}1141 1142class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <1143 inst, "MULHI", mulhu> {1144 let Itinerary = TransALU;1145}1146 1147class MULHI_UINT24_Common <bits<11> inst> : R600_2OP_Helper <1148 inst, "MULHI_UINT24", AMDGPUmulhi_u24> {1149 let Itinerary = VecALU;1150}1151 1152class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <1153 inst, "MULLO_INT", mul> {1154 let Itinerary = TransALU;1155}1156class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {1157 let Itinerary = TransALU;1158}1159 1160class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <1161 inst, "RECIP_CLAMPED", []1162> {1163 let Itinerary = TransALU;1164}1165 1166class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <1167 inst, "RECIP_IEEE", [(set f32:$dst, (AMDGPUrcp f32:$src0))]1168> {1169 let Itinerary = TransALU;1170}1171 1172class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <1173 inst, "RECIP_UINT", AMDGPUurecip1174> {1175 let Itinerary = TransALU;1176}1177 1178// Clamped to maximum.1179class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <1180 inst, "RECIPSQRT_CLAMPED", AMDGPUrsq_clamp1181> {1182 let Itinerary = TransALU;1183}1184 1185class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP_Helper <1186 inst, "RECIPSQRT_IEEE", AMDGPUrsq> {1187 let Itinerary = TransALU;1188}1189 1190// TODO: There is also RECIPSQRT_FF which clamps to zero.1191 1192class SIN_Common <bits<11> inst> : R600_1OP <1193 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{1194 let Trig = 1;1195 let Itinerary = TransALU;1196}1197 1198class COS_Common <bits<11> inst> : R600_1OP <1199 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> {1200 let Trig = 1;1201 let Itinerary = TransALU;1202}1203 1204def FABS_R600 : FABS<R600_Reg32>;1205def FNEG_R600 : FNEG<R600_Reg32>;1206 1207//===----------------------------------------------------------------------===//1208// Helper patterns for complex intrinsics1209//===----------------------------------------------------------------------===//1210 1211// FIXME: Should be predicated on unsafe fp math.1212multiclass DIV_Common <InstR600 recip_ieee> {1213def : R600Pat<1214 (fdiv f32:$src0, f32:$src1),1215 (MUL_IEEE $src0, (recip_ieee $src1))1216>;1217 1218def : RcpPat<recip_ieee, f32>;1219}1220 1221class SqrtPat<Instruction RsqInst, Instruction RecipInst> : R600Pat <1222 (fsqrt f32:$src),1223 (RecipInst (RsqInst $src))1224>;1225 1226//===----------------------------------------------------------------------===//1227// R600 / R700 Instructions1228//===----------------------------------------------------------------------===//1229 1230let Predicates = [isR600] in {1231 1232 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;1233 def MULADD_r600 : MULADD_Common<0x10>;1234 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;1235 def CNDE_r600 : CNDE_Common<0x18>;1236 def CNDGT_r600 : CNDGT_Common<0x19>;1237 def CNDGE_r600 : CNDGE_Common<0x1A>;1238 def DOT4_r600 : DOT4_Common<0x50>;1239 defm CUBE_r600 : CUBE_Common<0x52>;1240 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;1241 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;1242 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;1243 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;1244 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;1245 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;1246 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;1247 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;1248 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;1249 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;1250 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;1251 def SIN_r600 : SIN_Common<0x6E>;1252 def COS_r600 : COS_Common<0x6F>;1253 def ASHR_r600 : ASHR_Common<0x70>;1254 def LSHR_r600 : LSHR_Common<0x71>;1255 def LSHL_r600 : LSHL_Common<0x72>;1256 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;1257 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;1258 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;1259 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;1260 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;1261 1262 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;1263 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;1264 1265 def : SqrtPat<RECIPSQRT_IEEE_r600, RECIP_IEEE_r600>;1266 1267 def R600_ExportSwz : ExportSwzInst {1268 let Word1{20-17} = 0; // BURST_COUNT1269 let Word1{21} = eop;1270 let Word1{22} = 0; // VALID_PIXEL_MODE1271 let Word1{30-23} = inst;1272 let Word1{31} = 1; // BARRIER1273 }1274 defm : ExportPattern<R600_ExportSwz, 39>;1275 1276 def R600_ExportBuf : ExportBufInst {1277 let Word1{20-17} = 0; // BURST_COUNT1278 let Word1{21} = eop;1279 let Word1{22} = 0; // VALID_PIXEL_MODE1280 let Word1{30-23} = inst;1281 let Word1{31} = 1; // BARRIER1282 }1283 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;1284 1285 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT),1286 "TEX $CNT @$ADDR"> {1287 let POP_COUNT = 0;1288 }1289 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT),1290 "VTX $CNT @$ADDR"> {1291 let POP_COUNT = 0;1292 }1293 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),1294 "LOOP_START_DX10 @$ADDR"> {1295 let POP_COUNT = 0;1296 let CNT = 0;1297 }1298 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {1299 let POP_COUNT = 0;1300 let CNT = 0;1301 }1302 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),1303 "LOOP_BREAK @$ADDR"> {1304 let POP_COUNT = 0;1305 let CNT = 0;1306 }1307 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),1308 "CONTINUE @$ADDR"> {1309 let POP_COUNT = 0;1310 let CNT = 0;1311 }1312 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),1313 "JUMP @$ADDR POP:$POP_COUNT"> {1314 let CNT = 0;1315 }1316 def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR),1317 "PUSH_ELSE @$ADDR"> {1318 let CNT = 0;1319 let POP_COUNT = 0; // FIXME?1320 }1321 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),1322 "ELSE @$ADDR POP:$POP_COUNT"> {1323 let CNT = 0;1324 }1325 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {1326 let ADDR = 0;1327 let CNT = 0;1328 let POP_COUNT = 0;1329 }1330 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),1331 "POP @$ADDR POP:$POP_COUNT"> {1332 let CNT = 0;1333 }1334 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {1335 let CNT = 0;1336 let POP_COUNT = 0;1337 let ADDR = 0;1338 let END_OF_PROGRAM = 1;1339 }1340 1341}1342 1343 1344//===----------------------------------------------------------------------===//1345// Register loads and stores - for indirect addressing1346//===----------------------------------------------------------------------===//1347 1348let Namespace = "R600" in {1349defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;1350}1351 1352// Hardcode channel to 01353// NOTE: LSHR is not available here. LSHR is per family instruction1354def : R600Pat <1355 (i32 (load_private ADDRIndirect:$addr) ),1356 (R600_RegisterLoad FRAMEri:$addr, (i32 0))1357>;1358def : R600Pat <1359 (store_private i32:$val, ADDRIndirect:$addr),1360 (R600_RegisterStore i32:$val, FRAMEri:$addr, (i32 0))1361>;1362 1363 1364//===----------------------------------------------------------------------===//1365// Pseudo instructions1366//===----------------------------------------------------------------------===//1367 1368let isPseudo = 1 in {1369 1370def PRED_X : InstR600 <1371 (outs R600_Predicate_Bit:$dst),1372 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),1373 "", [], NullALU> {1374 let FlagOperandIdx = 3;1375}1376 1377let isTerminator = 1, isBranch = 1 in {1378def JUMP_COND : InstR600 <1379 (outs),1380 (ins brtarget:$target, R600_Predicate_Bit:$p),1381 "JUMP $target ($p)",1382 [], AnyALU1383 >;1384 1385def JUMP : InstR600 <1386 (outs),1387 (ins brtarget:$target),1388 "JUMP $target",1389 [], AnyALU1390 >1391{1392 let isPredicable = 1;1393 let isBarrier = 1;1394}1395 1396} // End isTerminator = 1, isBranch = 11397 1398let usesCustomInserter = 1 in {1399 1400let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {1401 1402def MASK_WRITE : InstR600 <1403 (outs),1404 (ins R600_Reg32:$src),1405 "MASK_WRITE $src",1406 [],1407 NullALU1408>;1409 1410} // End mayLoad = 0, mayStore = 0, hasSideEffects = 11411 1412 1413def TXD: InstR600 <1414 (outs R600_Reg128:$dst),1415 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,1416 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),1417 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", [],1418 NullALU > {1419 let TEXInst = 1;1420}1421 1422def TXD_SHADOW: InstR600 <1423 (outs R600_Reg128:$dst),1424 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,1425 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),1426 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",1427 [], NullALU> {1428 let TEXInst = 1;1429}1430} // End isPseudo = 11431} // End usesCustomInserter = 11432 1433 1434//===----------------------------------------------------------------------===//1435// Constant Buffer Addressing Support1436//===----------------------------------------------------------------------===//1437 1438let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "R600" in {1439def CONST_COPY : Instruction {1440 let OutOperandList = (outs R600_Reg32:$dst);1441 let InOperandList = (ins i32imm:$src);1442 let Pattern =1443 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];1444 let AsmString = "CONST_COPY";1445 let hasSideEffects = 0;1446 let isAsCheapAsAMove = 1;1447 let Itinerary = NullALU;1448}1449} // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"1450 1451def TEX_VTX_CONSTBUF :1452 InstR600ISA <(outs R600_Reg128:$dst_gpr), (ins (MEMxi $src_gpr, $src_index):$src, i32imm:$buffer_id), "VTX_READ_eg $dst_gpr, $src",1453 [(set v4i32:$dst_gpr, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$src, (i32 imm:$buffer_id)))]>,1454 VTX_WORD1_GPR, VTX_WORD0_eg {1455 1456 let VC_INST = 0;1457 let FETCH_TYPE = 2;1458 let FETCH_WHOLE_QUAD = 0;1459 let SRC_REL = 0;1460 let SRC_SEL_X = 0;1461 let DST_REL = 0;1462 let USE_CONST_FIELDS = 0;1463 let NUM_FORMAT_ALL = 2;1464 let FORMAT_COMP_ALL = 1;1465 let SRF_MODE_ALL = 1;1466 let MEGA_FETCH_COUNT = 16;1467 let DST_SEL_X = 0;1468 let DST_SEL_Y = 1;1469 let DST_SEL_Z = 2;1470 let DST_SEL_W = 3;1471 let DATA_FORMAT = 35;1472 1473 let Inst{31-0} = Word0;1474 let Inst{63-32} = Word1;1475 1476// LLVM can only encode 64-bit instructions, so these fields are manually1477// encoded in R600CodeEmitter1478//1479// bits<16> OFFSET;1480// bits<2> ENDIAN_SWAP = 0;1481// bits<1> CONST_BUF_NO_STRIDE = 0;1482// bits<1> MEGA_FETCH = 0;1483// bits<1> ALT_CONST = 0;1484// bits<2> BUFFER_INDEX_MODE = 0;1485 1486 1487 1488// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding1489// is done in R600CodeEmitter1490//1491// Inst{79-64} = OFFSET;1492// Inst{81-80} = ENDIAN_SWAP;1493// Inst{82} = CONST_BUF_NO_STRIDE;1494// Inst{83} = MEGA_FETCH;1495// Inst{84} = ALT_CONST;1496// Inst{86-85} = BUFFER_INDEX_MODE;1497// Inst{95-86} = 0; Reserved1498 1499// VTX_WORD3 (Padding)1500//1501// Inst{127-96} = 0;1502 let VTXInst = 1;1503}1504 1505def TEX_VTX_TEXBUF:1506 InstR600ISA <(outs R600_Reg128:$dst_gpr), (ins (MEMxi $src_gpr, $src_index):$src, i32imm:$buffer_id), "TEX_VTX_EXPLICIT_READ $dst_gpr, $src">,1507VTX_WORD1_GPR, VTX_WORD0_eg {1508 1509let VC_INST = 0;1510let FETCH_TYPE = 2;1511let FETCH_WHOLE_QUAD = 0;1512let SRC_REL = 0;1513let SRC_SEL_X = 0;1514let DST_REL = 0;1515let USE_CONST_FIELDS = 1;1516let NUM_FORMAT_ALL = 0;1517let FORMAT_COMP_ALL = 0;1518let SRF_MODE_ALL = 1;1519let MEGA_FETCH_COUNT = 16;1520let DST_SEL_X = 0;1521let DST_SEL_Y = 1;1522let DST_SEL_Z = 2;1523let DST_SEL_W = 3;1524let DATA_FORMAT = 0;1525 1526let Inst{31-0} = Word0;1527let Inst{63-32} = Word1;1528 1529// LLVM can only encode 64-bit instructions, so these fields are manually1530// encoded in R600CodeEmitter1531//1532// bits<16> OFFSET;1533// bits<2> ENDIAN_SWAP = 0;1534// bits<1> CONST_BUF_NO_STRIDE = 0;1535// bits<1> MEGA_FETCH = 0;1536// bits<1> ALT_CONST = 0;1537// bits<2> BUFFER_INDEX_MODE = 0;1538 1539 1540 1541// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding1542// is done in R600CodeEmitter1543//1544// Inst{79-64} = OFFSET;1545// Inst{81-80} = ENDIAN_SWAP;1546// Inst{82} = CONST_BUF_NO_STRIDE;1547// Inst{83} = MEGA_FETCH;1548// Inst{84} = ALT_CONST;1549// Inst{86-85} = BUFFER_INDEX_MODE;1550// Inst{95-86} = 0; Reserved1551 1552// VTX_WORD3 (Padding)1553//1554// Inst{127-96} = 0;1555 let VTXInst = 1;1556}1557 1558//===---------------------------------------------------------------------===//1559// Flow and Program control Instructions1560//===---------------------------------------------------------------------===//1561 1562multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> {1563 def _i32 : ILFormat<(outs),1564 (ins brtarget:$target, rci:$src0),1565 "; i32 Pseudo branch instruction",1566 [(Op bb:$target, (i32 rci:$src0))]>;1567 def _f32 : ILFormat<(outs),1568 (ins brtarget:$target, rcf:$src0),1569 "; f32 Pseudo branch instruction",1570 [(Op bb:$target, (f32 rcf:$src0))]>;1571}1572 1573// Only scalar types should generate flow control1574multiclass BranchInstr<string name> {1575 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src),1576 !strconcat(name, " $src"), []>;1577 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src),1578 !strconcat(name, " $src"), []>;1579}1580// Only scalar types should generate flow control1581multiclass BranchInstr2<string name> {1582 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1),1583 !strconcat(name, " $src0, $src1"), []>;1584 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1),1585 !strconcat(name, " $src0, $src1"), []>;1586}1587 1588//===---------------------------------------------------------------------===//1589// Custom Inserter for Branches and returns, this eventually will be a1590// separate pass1591//===---------------------------------------------------------------------===//1592let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1,1593 Namespace = "R600" in {1594 def BRANCH : ILFormat<(outs), (ins brtarget:$target),1595 "; Pseudo unconditional branch instruction",1596 [(br bb:$target)]>;1597 defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>;1598}1599 1600//===----------------------------------------------------------------------===//1601// Branch Instructions1602//===----------------------------------------------------------------------===//1603 1604def IF_PREDICATE_SET : ILFormat<(outs), (ins R600_Reg32:$src),1605 "IF_PREDICATE_SET $src", []>;1606 1607let isTerminator=1 in {1608 def BREAK : ILFormat< (outs), (ins),1609 "BREAK", []>;1610 def CONTINUE : ILFormat< (outs), (ins),1611 "CONTINUE", []>;1612 def DEFAULT : ILFormat< (outs), (ins),1613 "DEFAULT", []>;1614 def ELSE : ILFormat< (outs), (ins),1615 "ELSE", []>;1616 def ENDSWITCH : ILFormat< (outs), (ins),1617 "ENDSWITCH", []>;1618 def ENDMAIN : ILFormat< (outs), (ins),1619 "ENDMAIN", []>;1620 def END : ILFormat< (outs), (ins),1621 "END", []>;1622 def ENDFUNC : ILFormat< (outs), (ins),1623 "ENDFUNC", []>;1624 def ENDIF : ILFormat< (outs), (ins),1625 "ENDIF", []>;1626 def WHILELOOP : ILFormat< (outs), (ins),1627 "WHILE", []>;1628 def ENDLOOP : ILFormat< (outs), (ins),1629 "ENDLOOP", []>;1630 def FUNC : ILFormat< (outs), (ins),1631 "FUNC", []>;1632 def RETDYN : ILFormat< (outs), (ins),1633 "RET_DYN", []>;1634 // This opcode has custom swizzle pattern encoded in Swizzle Encoder1635 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;1636 // This opcode has custom swizzle pattern encoded in Swizzle Encoder1637 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;1638 // This opcode has custom swizzle pattern encoded in Swizzle Encoder1639 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;1640 // This opcode has custom swizzle pattern encoded in Swizzle Encoder1641 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;1642 // This opcode has custom swizzle pattern encoded in Swizzle Encoder1643 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;1644 // This opcode has custom swizzle pattern encoded in Swizzle Encoder1645 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;1646 defm IFC : BranchInstr2<"IFC">;1647 defm BREAKC : BranchInstr2<"BREAKC">;1648 defm CONTINUEC : BranchInstr2<"CONTINUEC">;1649}1650 1651//===----------------------------------------------------------------------===//1652// Indirect addressing pseudo instructions1653//===----------------------------------------------------------------------===//1654 1655let isPseudo = 1 in {1656 1657class ExtractVertical <RegisterClass vec_rc> : InstR600 <1658 (outs R600_Reg32:$dst),1659 (ins vec_rc:$vec, R600_Reg32:$index), "",1660 [],1661 AnyALU1662>;1663 1664let Constraints = "$dst = $vec" in {1665 1666class InsertVertical <RegisterClass vec_rc> : InstR600 <1667 (outs vec_rc:$dst),1668 (ins vec_rc:$vec, R600_Reg32:$value, R600_Reg32:$index), "",1669 [],1670 AnyALU1671>;1672 1673} // End Constraints = "$dst = $vec"1674 1675} // End isPseudo = 11676 1677def R600_EXTRACT_ELT_V2 : ExtractVertical <R600_Reg64Vertical>;1678def R600_EXTRACT_ELT_V4 : ExtractVertical <R600_Reg128Vertical>;1679 1680def R600_INSERT_ELT_V2 : InsertVertical <R600_Reg64Vertical>;1681def R600_INSERT_ELT_V4 : InsertVertical <R600_Reg128Vertical>;1682 1683class ExtractVerticalPat <Instruction inst, ValueType vec_ty,1684 ValueType scalar_ty> : R600Pat <1685 (scalar_ty (extractelt vec_ty:$vec, i32:$index)),1686 (inst $vec, $index)1687>;1688 1689def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2i32, i32>;1690def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>;1691def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4i32, i32>;1692def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>;1693 1694class InsertVerticalPat <Instruction inst, ValueType vec_ty,1695 ValueType scalar_ty> : R600Pat <1696 (vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)),1697 (inst $vec, $value, $index)1698>;1699 1700def : InsertVerticalPat <R600_INSERT_ELT_V2, v2i32, i32>;1701def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>;1702def : InsertVerticalPat <R600_INSERT_ELT_V4, v4i32, i32>;1703def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>;1704 1705//===----------------------------------------------------------------------===//1706// ISel Patterns1707//===----------------------------------------------------------------------===//1708 1709let SubtargetPredicate = isR600toCayman in {1710 1711// CND*_INT Patterns for f32 True / False values1712 1713class CND_INT_f32 <InstR600 cnd, CondCode cc> : R600Pat <1714 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),1715 (cnd $src0, $src1, $src2)1716>;1717 1718def : CND_INT_f32 <CNDE_INT, SETEQ>;1719def : CND_INT_f32 <CNDGT_INT, SETGT>;1720def : CND_INT_f32 <CNDGE_INT, SETGE>;1721 1722//CNDGE_INT extra pattern1723def : R600Pat <1724 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT),1725 (CNDGE_INT $src0, $src1, $src2)1726>;1727 1728// KIL Patterns1729def KIL : R600Pat <1730 (int_r600_kill f32:$src0),1731 (MASK_WRITE (KILLGT (f32 ZERO), $src0))1732>;1733 1734def : Extract_Element <f32, v4f32, 0, sub0>;1735def : Extract_Element <f32, v4f32, 1, sub1>;1736def : Extract_Element <f32, v4f32, 2, sub2>;1737def : Extract_Element <f32, v4f32, 3, sub3>;1738 1739def : Insert_Element <f32, v4f32, 0, sub0>;1740def : Insert_Element <f32, v4f32, 1, sub1>;1741def : Insert_Element <f32, v4f32, 2, sub2>;1742def : Insert_Element <f32, v4f32, 3, sub3>;1743 1744def : Extract_Element <i32, v4i32, 0, sub0>;1745def : Extract_Element <i32, v4i32, 1, sub1>;1746def : Extract_Element <i32, v4i32, 2, sub2>;1747def : Extract_Element <i32, v4i32, 3, sub3>;1748 1749def : Insert_Element <i32, v4i32, 0, sub0>;1750def : Insert_Element <i32, v4i32, 1, sub1>;1751def : Insert_Element <i32, v4i32, 2, sub2>;1752def : Insert_Element <i32, v4i32, 3, sub3>;1753 1754def : Extract_Element <f32, v2f32, 0, sub0>;1755def : Extract_Element <f32, v2f32, 1, sub1>;1756 1757def : Insert_Element <f32, v2f32, 0, sub0>;1758def : Insert_Element <f32, v2f32, 1, sub1>;1759 1760def : Extract_Element <i32, v2i32, 0, sub0>;1761def : Extract_Element <i32, v2i32, 1, sub1>;1762 1763def : Insert_Element <i32, v2i32, 0, sub0>;1764def : Insert_Element <i32, v2i32, 1, sub1>;1765 1766// bitconvert patterns1767 1768def : BitConvert <i32, f32, R600_Reg32>;1769def : BitConvert <f32, i32, R600_Reg32>;1770def : BitConvert <v2f32, v2i32, R600_Reg64>;1771def : BitConvert <v2i32, v2f32, R600_Reg64>;1772def : BitConvert <v4f32, v4i32, R600_Reg128>;1773def : BitConvert <v4i32, v4f32, R600_Reg128>;1774 1775// DWORDADDR pattern1776def : DwordAddrPat <i32, R600_Reg32>;1777 1778} // End SubtargetPredicate = isR600toCayman1779 1780def getLDSNoRetOp : InstrMapping {1781 let FilterClass = "R600_LDS_1A1D";1782 let RowFields = ["BaseOp"];1783 let ColFields = ["usesCustomInserter"];1784 let KeyCol = ["1"];1785 let ValueCols = [["0"]];1786}1787