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1//===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9/// \file10/// R600 Machine Scheduler interface11//12//===----------------------------------------------------------------------===//13 14#ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H15#define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H16 17#include "llvm/CodeGen/MachineScheduler.h"18#include <vector>19 20namespace llvm {21 22class R600InstrInfo;23struct R600RegisterInfo;24 25class R600SchedStrategy final : public MachineSchedStrategy {26 const ScheduleDAGMILive *DAG = nullptr;27 const R600InstrInfo *TII = nullptr;28 const R600RegisterInfo *TRI = nullptr;29 MachineRegisterInfo *MRI = nullptr;30 31 enum InstKind {32 IDAlu,33 IDFetch,34 IDOther,35 IDLast36 };37 38 enum AluKind {39 AluAny,40 AluT_X,41 AluT_Y,42 AluT_Z,43 AluT_W,44 AluT_XYZW,45 AluPredX,46 AluTrans,47 AluDiscarded, // LLVM Instructions that are going to be eliminated48 AluLast49 };50 51 std::vector<SUnit *> Available[IDLast], Pending[IDLast];52 std::vector<SUnit *> AvailableAlus[AluLast];53 std::vector<SUnit *> PhysicalRegCopy;54 55 InstKind CurInstKind;56 int CurEmitted;57 InstKind NextInstKind;58 59 unsigned AluInstCount;60 unsigned FetchInstCount;61 62 int InstKindLimit[IDLast];63 64 int OccupiedSlotsMask;65 66public:67 R600SchedStrategy() = default;68 ~R600SchedStrategy() override = default;69 70 void initialize(ScheduleDAGMI *dag) override;71 SUnit *pickNode(bool &IsTopNode) override;72 void schedNode(SUnit *SU, bool IsTopNode) override;73 void releaseTopNode(SUnit *SU) override;74 void releaseBottomNode(SUnit *SU) override;75 76private:77 std::vector<MachineInstr *> InstructionsGroupCandidate;78 bool VLIW5;79 80 int getInstKind(SUnit *SU);81 bool regBelongsToClass(Register Reg, const TargetRegisterClass *RC) const;82 AluKind getAluKind(SUnit *SU) const;83 void LoadAlu();84 unsigned AvailablesAluCount() const;85 SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);86 void PrepareNextSlot();87 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);88 89 void AssignSlot(MachineInstr *MI, unsigned Slot);90 SUnit* pickAlu();91 SUnit* pickOther(int QID);92 void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);93};94 95} // end namespace llvm96 97#endif // LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H98