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1 2class R600Reg <string name, bits<16> encoding> : Register<name> {3 let Namespace = "AMDGPU";4 let HWEncoding = encoding;5}6 7class R600RegWithChan <string name, bits<9> sel, string chan> :8 Register <name> {9 10 field bits<2> chan_encoding = !if(!eq(chan, "X"), 0,11 !if(!eq(chan, "Y"), 1,12 !if(!eq(chan, "Z"), 2,13 !if(!eq(chan, "W"), 3, 0))));14 let HWEncoding{8-0} = sel;15 let HWEncoding{10-9} = chan_encoding;16 let Namespace = "AMDGPU";17}18 19class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :20 RegisterWithSubRegs<n, subregs> {21 field bits<2> chan_encoding = 0;22 let Namespace = "AMDGPU";23 let SubRegIndices = [sub0, sub1, sub2, sub3];24 let HWEncoding{8-0} = encoding{8-0};25 let HWEncoding{10-9} = chan_encoding;26}27 28class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :29 RegisterWithSubRegs<n, subregs> {30 field bits<2> chan_encoding = 0;31 let Namespace = "AMDGPU";32 let SubRegIndices = [sub0, sub1];33 let HWEncoding = encoding;34 let HWEncoding{8-0} = encoding{8-0};35 let HWEncoding{10-9} = chan_encoding;36}37 38class R600Reg_64Vertical<int lo, int hi, string chan> : R600Reg_64 <39 "V"#lo#hi#"_"#chan,40 [!cast<Register>("T"#lo#"_"#chan), !cast<Register>("T"#hi#"_"#chan)],41 lo42>;43 44foreach Index = 0-127 in {45 foreach Chan = [ "X", "Y", "Z", "W" ] in {46 // 32-bit Temporary Registers47 def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;48 49 // Indirect addressing offset registers50 def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan,51 Index, Chan>;52 }53 // 128-bit Temporary Registers54 def T#Index#_XYZW : R600Reg_128 <"T"#Index#"",55 [!cast<Register>("T"#Index#"_X"),56 !cast<Register>("T"#Index#"_Y"),57 !cast<Register>("T"#Index#"_Z"),58 !cast<Register>("T"#Index#"_W")],59 Index>;60 61 def T#Index#_XY : R600Reg_64 <"T"#Index#"",62 [!cast<Register>("T"#Index#"_X"),63 !cast<Register>("T"#Index#"_Y")],64 Index>;65}66 67foreach Chan = [ "X", "Y", "Z", "W"] in {68 69 let chan_encoding = !if(!eq(Chan, "X"), 0,70 !if(!eq(Chan, "Y"), 1,71 !if(!eq(Chan, "Z"), 2,72 !if(!eq(Chan, "W"), 3, 0)))) in {73 def V0123_#Chan : R600Reg_128 <"V0123_"#Chan,74 [!cast<Register>("T0_"#Chan),75 !cast<Register>("T1_"#Chan),76 !cast<Register>("T2_"#Chan),77 !cast<Register>("T3_"#Chan)],78 0>;79 def V01_#Chan : R600Reg_64Vertical<0, 1, Chan>;80 def V23_#Chan : R600Reg_64Vertical<2, 3, Chan>;81 }82}83 84 85// KCACHE_BANK086foreach Index = 159-128 in {87 foreach Chan = [ "X", "Y", "Z", "W" ] in {88 // 32-bit Temporary Registers89 def KC0_#Index#_#Chan : R600RegWithChan <"KC0["#!add(Index,-128)#"]."#Chan, Index, Chan>;90 }91 // 128-bit Temporary Registers92 def KC0_#Index#_XYZW : R600Reg_128 <"KC0["#!add(Index, -128)#"].XYZW",93 [!cast<Register>("KC0_"#Index#"_X"),94 !cast<Register>("KC0_"#Index#"_Y"),95 !cast<Register>("KC0_"#Index#"_Z"),96 !cast<Register>("KC0_"#Index#"_W")],97 Index>;98}99 100// KCACHE_BANK1101foreach Index = 191-160 in {102 foreach Chan = [ "X", "Y", "Z", "W" ] in {103 // 32-bit Temporary Registers104 def KC1_#Index#_#Chan : R600RegWithChan <"KC1["#!add(Index,-160)#"]."#Chan, Index, Chan>;105 }106 // 128-bit Temporary Registers107 def KC1_#Index#_XYZW : R600Reg_128 <"KC1["#!add(Index, -160)#"].XYZW",108 [!cast<Register>("KC1_"#Index#"_X"),109 !cast<Register>("KC1_"#Index#"_Y"),110 !cast<Register>("KC1_"#Index#"_Z"),111 !cast<Register>("KC1_"#Index#"_W")],112 Index>;113}114 115 116// Array Base Register holding input in FS117foreach Index = 448-480 in {118 def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>;119}120 121 122// Special Registers123 124def OQA : R600Reg<"OQA", 219>;125def OQB : R600Reg<"OQB", 220>;126def OQAP : R600Reg<"OQAP", 221>;127def OQBP : R600Reg<"OQAP", 222>;128def LDS_DIRECT_A : R600Reg<"LDS_DIRECT_A", 223>;129def LDS_DIRECT_B : R600Reg<"LDS_DIRECT_B", 224>;130def ZERO : R600Reg<"0.0", 248>;131def ONE : R600Reg<"1.0", 249>;132def NEG_ONE : R600Reg<"-1.0", 249>;133def ONE_INT : R600Reg<"1", 250>;134def HALF : R600Reg<"0.5", 252>;135def NEG_HALF : R600Reg<"-0.5", 252>;136def ALU_LITERAL_X : R600RegWithChan<"literal.x", 253, "X">;137def ALU_LITERAL_Y : R600RegWithChan<"literal.y", 253, "Y">;138def ALU_LITERAL_Z : R600RegWithChan<"literal.z", 253, "Z">;139def ALU_LITERAL_W : R600RegWithChan<"literal.w", 253, "W">;140def PV_X : R600RegWithChan<"PV.X", 254, "X">;141def PV_Y : R600RegWithChan<"PV.Y", 254, "Y">;142def PV_Z : R600RegWithChan<"PV.Z", 254, "Z">;143def PV_W : R600RegWithChan<"PV.W", 254, "W">;144def PS: R600Reg<"PS", 255>;145def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;146def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;147def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;148def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;149def AR_X : R600Reg<"AR.x", 0>;150def INDIRECT_BASE_ADDR : R600Reg <"INDIRECT_BASE_ADDR", 0>;151 152def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,153 (add (sequence "ArrayBase%u", 448, 480))> {154 let Weight = 0;155}156// special registers for ALU src operands157// const buffer reference, SRCx_SEL contains index158def ALU_CONST : R600Reg<"CBuf", 0>;159// interpolation param reference, SRCx_SEL contains index160def ALU_PARAM : R600Reg<"Param", 0>;161 162let Weight = 0 in {163let isAllocatable = 0 in {164 165def R600_Addr : RegisterClass <"AMDGPU", [i32], 32, (add (sequence "Addr%u_X", 0, 127))>;166 167// We only use Addr_[YZW] for vertical vectors.168// FIXME if we add more vertical vector registers we will need to ad more169// registers to these classes.170def R600_Addr_Y : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Y)>;171def R600_Addr_Z : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Z)>;172def R600_Addr_W : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_W)>;173 174def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,175 (add OQA, OQB, OQAP, OQBP, LDS_DIRECT_A, LDS_DIRECT_B)>;176 177def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,178 (add (sequence "KC0_%u_X", 128, 159))>;179 180def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,181 (add (sequence "KC0_%u_Y", 128, 159))>;182 183def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,184 (add (sequence "KC0_%u_Z", 128, 159))>;185 186def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,187 (add (sequence "KC0_%u_W", 128, 159))>;188 189def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,190 (interleave R600_KC0_X, R600_KC0_Y,191 R600_KC0_Z, R600_KC0_W)>;192 193def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,194 (add (sequence "KC1_%u_X", 160, 191))>;195 196def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,197 (add (sequence "KC1_%u_Y", 160, 191))>;198 199def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,200 (add (sequence "KC1_%u_Z", 160, 191))>;201 202def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,203 (add (sequence "KC1_%u_W", 160, 191))>;204 205def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32,206 (interleave R600_KC1_X, R600_KC1_Y,207 R600_KC1_Z, R600_KC1_W)>;208 209} // End isAllocatable = 0210 211def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,212 (add (sequence "T%u_X", 0, 127), AR_X)>;213 214def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,215 (add (sequence "T%u_Y", 0, 127))>;216 217def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32,218 (add (sequence "T%u_Z", 0, 127))>;219 220def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32,221 (add (sequence "T%u_W", 0, 127))>;222 223def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,224 (interleave R600_TReg32_X, R600_TReg32_Y,225 R600_TReg32_Z, R600_TReg32_W)>;226 227def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add228 R600_TReg32,229 R600_ArrayBase,230 R600_Addr,231 R600_KC0, R600_KC1,232 ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF,233 ALU_CONST, ALU_PARAM, OQAP, INDIRECT_BASE_ADDR234 )>;235 236def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add237 PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>;238 239def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add240 PREDICATE_BIT)>;241 242def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,243 (add (sequence "T%u_XYZW", 0, 127))> {244 let CopyCost = -1;245}246 247def R600_Reg128Vertical : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,248 (add V0123_W, V0123_Z, V0123_Y, V0123_X)249>;250 251def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32, i64, f64], 64,252 (add (sequence "T%u_XY", 0, 63))>;253 254def R600_Reg64Vertical : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,255 (add V01_X, V01_Y, V01_Z, V01_W,256 V23_X, V23_Y, V23_Z, V23_W)>;257} // End let Weight = 0258