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1//=====-- R600Subtarget.h - Define Subtarget for AMDGPU R600 ----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//==-----------------------------------------------------------------------===//8//9/// \file10/// AMDGPU R600 specific subclass of TargetSubtarget.11//12//===----------------------------------------------------------------------===//13 14#ifndef LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H15#define LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H16 17#include "AMDGPUSubtarget.h"18#include "R600FrameLowering.h"19#include "R600ISelLowering.h"20#include "R600InstrInfo.h"21#include "Utils/AMDGPUBaseInfo.h"22 23#define GET_SUBTARGETINFO_HEADER24#include "R600GenSubtargetInfo.inc"25 26namespace llvm {27 28class R600Subtarget final : public R600GenSubtargetInfo,29 public AMDGPUSubtarget {30private:31 R600InstrInfo InstrInfo;32 R600FrameLowering FrameLowering;33 bool FMA = false;34 bool CaymanISA = false;35 bool CFALUBug = false;36 bool HasVertexCache = false;37 bool R600ALUInst = false;38 bool FP64 = false;39 short TexVTXClauseSize = 0;40 Generation Gen = R600;41 R600TargetLowering TLInfo;42 InstrItineraryData InstrItins;43 std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;44 45public:46 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,47 const TargetMachine &TM);48 49 ~R600Subtarget() override;50 51 const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }52 53 const R600FrameLowering *getFrameLowering() const override {54 return &FrameLowering;55 }56 57 const R600TargetLowering *getTargetLowering() const override {58 return &TLInfo;59 }60 61 const R600RegisterInfo *getRegisterInfo() const override {62 return &InstrInfo.getRegisterInfo();63 }64 65 const InstrItineraryData *getInstrItineraryData() const override {66 return &InstrItins;67 }68 69 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;70 71 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);72 73 Generation getGeneration() const {74 return Gen;75 }76 77 Align getStackAlignment() const { return Align(4); }78 79 R600Subtarget &initializeSubtargetDependencies(const Triple &TT,80 StringRef GPU, StringRef FS);81 82 bool hasBFE() const {83 return (getGeneration() >= EVERGREEN);84 }85 86 bool hasBFI() const {87 return (getGeneration() >= EVERGREEN);88 }89 90 bool hasBCNT(unsigned Size) const {91 if (Size == 32)92 return (getGeneration() >= EVERGREEN);93 94 return false;95 }96 97 bool hasBORROW() const {98 return (getGeneration() >= EVERGREEN);99 }100 101 bool hasCARRY() const {102 return (getGeneration() >= EVERGREEN);103 }104 105 bool hasCaymanISA() const {106 return CaymanISA;107 }108 109 bool hasFFBL() const {110 return (getGeneration() >= EVERGREEN);111 }112 113 bool hasFFBH() const {114 return (getGeneration() >= EVERGREEN);115 }116 117 bool hasFMA() const { return FMA; }118 119 bool hasCFAluBug() const { return CFALUBug; }120 121 bool hasVertexCache() const { return HasVertexCache; }122 123 short getTexVTXClauseSize() const { return TexVTXClauseSize; }124 125 bool enableMachineScheduler() const override {126 return true;127 }128 129 bool enableSubRegLiveness() const override {130 return true;131 }132 133 /// \returns Maximum number of work groups per compute unit supported by the134 /// subtarget and limited by given \p FlatWorkGroupSize.135 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {136 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);137 }138 139 /// \returns Minimum flat work group size supported by the subtarget.140 unsigned getMinFlatWorkGroupSize() const override {141 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);142 }143 144 /// \returns Maximum flat work group size supported by the subtarget.145 unsigned getMaxFlatWorkGroupSize() const override {146 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);147 }148 149 /// \returns Number of waves per execution unit required to support the given150 /// \p FlatWorkGroupSize.151 unsigned152 getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override {153 return AMDGPU::IsaInfo::getWavesPerEUForWorkGroup(this, FlatWorkGroupSize);154 }155 156 /// \returns Minimum number of waves per execution unit supported by the157 /// subtarget.158 unsigned getMinWavesPerEU() const override {159 return AMDGPU::IsaInfo::getMinWavesPerEU(this);160 }161 162 bool requiresDisjointEarlyClobberAndUndef() const override {163 // AMDGPU doesn't care if early-clobber and undef operands are allocated164 // to the same register.165 return false;166 }167};168 169} // end namespace llvm170 171#endif // LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H172